Spiral transient voltage suppressor and method of manufacturing transient voltage supressor

Abstract

This invention discloses a transient voltage suppressor, comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; a channel formed in the epitaxial layer, the channel having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent segments, the channel having a third doping different from the first doping and the second doping; and a metal layer formed on the top of the channel and contained within the width W of the channel.

Description

Technical Field

[0001] This invention generally relates to integrated circuits, and more specifically to helical wells and terminal structures for transient voltage suppressors or Zener diode devices that provide increased power handling capabilities. Prior Technology

[0002] Transient voltage suppressors, such as Zener diodes, are typically low-power devices. Summary of the Invention

[0003] This invention discloses a transient voltage suppressor, comprising an electrode and a substrate disposed on the electrode. The substrate has a first doping, and an epitaxial layer disposed on the substrate has a second doping different from the first doping. A channel is formed in the epitaxial layer, the channel having a width W, a length L, and a plurality of curved regions, and the channel forming a plurality of adjacent segments. The channel has a third doping different from the first and second doping. A metal layer is formed on the top of the channel and contained within the width W of the channel.

[0004] Other systems, methods, features, and advantages of the present invention will become apparent or obvious to those skilled in the art upon examination of the following drawings and detailed description. The present invention is intended to include all such additional systems, methods, features, and advantages within the scope of this specification and protected by the appended claims. Simple Explanation of the Diagram

[0005] The following figures provide a better understanding of the invention. Components in the figures are drawn to scale, but the focus is on clearly illustrating the principles of the invention. Furthermore, in the figures, the same reference numerals are used throughout several views to denote corresponding parts, and in the figures:

[0006] [Figure 1] is a diagram of a device with a long joint edge according to a specific example of the present invention;

[0007] [Figure 2] is a diagram of a device with a medium-sized contact edge according to a specific example of the present invention;

[0008] [Figure 3] is a diagram of a device with a mating edge according to a specific example of the present invention;

[0009] Figures 4A to 4E are diagrams illustrating stages in the integrated circuit manufacturing process according to specific embodiments of the present invention; and

[0010] [Figure 5] shows the algorithm for the integrated circuit manufacturing process according to a specific example of the present invention. Implementation

[0011] Throughout the description below, the same reference numerals are used to label the same parts in this specification and the drawings. The drawings may be drawn to scale, and for clarity and simplicity, some components may be shown in a general or schematic form and identified by commercial markings.

[0012] This invention relates to low-voltage, high-power transient voltage suppressors, Zener diodes, or other suitable device architectures, such as for applications where the device power rating is 500 watts or greater. The invention provides a device with low capacitance and low leakage current due to the use of low-level doping. In contrast, typical transient voltage suppressor designs use high doping concentrations in the substrate and rely on grain size to control the device power rating.

[0013] By using a long, curved structure to provide long edges to the device, this invention allows the device to handle greater power, in addition to using lower doping levels. In one example, this invention uses cylindrical curvature to avoid the problems caused by prior art spherical curvature architectures. The cylindrical curvature architecture provides constant curvature, allowing the device to treat bends as straight ends. By providing a large ratio of curvature radius to silicon penetration depth, uniform collapse characteristics are provided.

[0014] Furthermore, this invention utilizes control of the α coefficient to facilitate collapse propagation. As the device according to the invention heats up, the collapse increases and propagates with temperature. At low voltage and high concentration, the device operates in Zener mode, and as the device heats up, the collapse voltage decreases, resulting in localized hot spots. At high voltage and low concentration, the device operates in burst mode, and as the device heats up, the collapse voltage level increases, thus providing a smoothing effect on the propagation of localized hot spots. For use with power transient voltage suppressors, Zener diodes are acceptable at low voltages and low power, but burst diodes are better suited for high power operation.

[0015] To achieve these objectives, the present invention utilizes a helical contact region. The use of helical geometry allows for constant distances from edge to edge and from segment to segment, which helps minimize localized heating. The helical geometry also eliminates sharp corners that could cause localized collapse. The long edge path of the helical design allows for support of high-power applications. Collapse control is achieved by controlling the ratio of electrode contact curvature to electrode width, so that the current regions slightly overlap when the device is in Zener collapse mode.

[0016] For silicon devices, the substrate can be doped using phosphorus, arsenic, antimony, or other suitable N++ materials at the N++ doping level. Next, the epitaxial layer can be formed using phosphorus, arsenic, antimony, or other suitable N+ doping materials at the N+ doping level. Electrodes with P+ doping levels can then be formed using boron, aluminum, or other suitable P+ materials. A shielding oxide layer is then formed to reduce defect formation, followed by a photoresist layer to implant P+ electrode doping. The device is then annealed to activate the dopant, and a passivation oxide layer such as semi-insulating polycrystalline silicon (SIPOS) or doped silicon oxide can be formed. The photoresist layer is then coated and etched to form metal contacts and a metal substrate, such as using a barrier metallization process utilizing titanium, nickel, silver, or other suitable materials.

[0017] Low-voltage, high-power (>500 W) transient voltage suppressors can be fabricated using high-concentration dopant, resulting in high capacitance and high leakage. In the case of low-voltage Zener diodes, voltage control can be achieved through junction curvature, allowing for lower-concentration epitaxial layers that provide lower capacitance and leakage. One drawback of Zener structures is that edge collapse results in low-power transient capability because the collapse is confined to the curvature region, which is smaller compared to the grain area. This invention provides long junction edges, which create a larger collapse region and higher power handling capability.

[0018] [picture] [1] A figure for a device 100 having a long contact edge, according to a specific example of an embodiment of the present invention. The device 100 may be manufactured using silicon, germanium, gallium arsenide, metal oxide semiconductor processes and materials, or other suitable methods.

[0019] Device 100 includes a metal layer 102 formed on top of a suitable doped region, such as a P+ doped region forming a channel in an N+ epitaxial layer 114 above an N++ substrate or other suitable device architecture. Metal layer 102 has a thickness "W", a length "L" substantially greater than that thickness, and includes bends 104, 106, 108, and 110, terminating at bend 112. The distance "S" between adjacent metal layers and their associated underlying doped regions is constant at all adjacent locations, within predetermined manufacturing tolerances selected based on device application, voltage, power, and other design constraints. Typically, higher tolerances are required for applications demanding higher voltage or higher power ratings. The use of a helical geometry in device 100 provides constant distances from edge to edge and from segment to segment of metal layer 102, which helps minimize localized heating. Localized collapse is reduced or minimized because sharp corners are avoided. The long edge paths of device 100 allow for operation at higher power.

[0020] [picture] [2] A figure is shown for a specific example of a device 200 having a medium contact edge according to an embodiment of the present invention. The device 200 may be manufactured using silicon, germanium, gallium arsenide, metal oxide semiconductor processes and materials, or other suitable methods.

[0021] Device 200 includes a metal layer 202 formed on top of a suitable doped region, such as a P+ doped region forming a channel in an N+ epitaxial layer 210 above an N++ substrate or other suitable device architecture. Metal layer 202 has a thickness "W", a length "L" substantially greater than the thickness "W" but shorter than the length "L" of metal layer 102 of device 100, and includes bends 204 and 206, terminating at bend 208. The distance "S" between adjacent metal layers and their associated underlying doped regions is constant at all locations, within predetermined manufacturing tolerances selected based on device application, voltage, power, and other design constraints. Typically, higher tolerances are required for applications demanding higher voltage or higher power ratings. The use of a helical geometry in device 200 provides constant distances from edge to edge and from segment to segment of metal layer 202, which helps minimize localized heating. Localized collapse is reduced or minimized because sharp corners are avoided. The long edge path of device 200 allows for operation at higher power.

[0022] [picture] [3] A figure is shown for a specific example of a device 300 having a contact edge according to an embodiment of the present invention. The device 300 may be manufactured using silicon, germanium, gallium arsenide, metal oxide semiconductor processes and materials, or other suitable methods.

[0023] Device 300 includes a metal layer 302 formed on top of a suitable doped region, such as a P+ doped region forming a channel in an N+ epitaxial layer 310 above an N++ substrate or other suitable device architecture. Metal layer 302 has a thickness "W", a length "L" substantially greater than the thickness "W" but less than the length "L" of device 200, and includes bends 304, 306, and 308. The distance "S" between adjacent metal layers and their associated underlying doped regions is constant at all locations, within predetermined manufacturing tolerances selected based on device application, voltage, power, and other design constraints. Typically, higher tolerances are required for applications demanding higher voltage or higher power ratings. The use of the spiral geometry of device 300 provides constant distances from edge to edge and from segment to segment of metal layer 302, which helps minimize localized heating. Localized collapse is reduced or minimized because sharp corners are avoided. The long edge paths of device 300 allow for operation at higher power.

[0024] Figures 4A to 4E are diagrams illustrating stages in an integrated circuit manufacturing process according to specific embodiments of the present invention. In Figure 4A, an N++ doped semiconductor material layer 402 is typically formed from a material wafer, which is grown from a crystal into an ingot that is then sliced. These ingots can be formed from N++ doped semiconductor material or from undoped material, and can be part of a manufacturing process at a designed doping level, such as by vapor phase epitaxy or other suitable doping methods.

[0025] exist [picture] In [4B], an N+ doped semiconductor epitaxial layer 404 is formed on top of the N++ layer 402. In one specific example, the N+ doped semiconductor layer 404 can be formed in the existing N++ layer 402 by sealing the N++ layer 402 substrate with a thin, lightly doped silicon film (such as a thin silicon film about 2 μm thick or other suitable thickness) and then growing the N+ doped semiconductor epitaxial layer 404 by controlling the dopant level in the reaction chamber. The thin Si seal can be sacrificed to prevent self-doping during the epitaxial growth process. Similarly, other suitable processes can be used or alternatively.

[0026] exist [picture] In [4C], a shielding oxide layer 406 is formed on top of the N+ layer 404. In one specific example, the shielding oxide layer 406 may be formed in an existing N+ layer 404 by exposing the N+ layer 404 to an oxidant or by other suitable means.

[0027] exist [picture] In [4D], P+ wells 408 and 410 are formed in an N+-doped semiconductor epitaxial layer 404. In one specific example, P+ wells 408 and 410 have a width "W" and can be formed by first depositing a photoresist layer, then etching the photoresist after applying a mask, and curing the photoresist with a suitable light source so that it can be removed with a first chemical agent to form a pattern that exposes the surface of the shielding oxide layer 406. P+ material can then be implanted using a vapor phase epitaxy process, ion beam implantation, or other suitable process. The device can then be annealed to activate the P+ dopant.

[0028] exist [picture] In [4E], metal contacts 412, 414, and 416 are formed. In one specific example, metal contacts 412 and 414 may be formed by depositing a layer of photoresist, patterning it using a mask, and then curing the photoresist using a suitable light source. The cured photoresist is then removed with a chemical agent to form the pattern for metal contacts 412 and 414, or other suitable processes may be used or alternatively. Metal contacts 412 and 414 may then be formed on the top of device 400 and metal contact 416 on the bottom of device 400 using vapor deposition, ion beam implantation, or other suitable processes such as titanium, nickel, silver, other suitable metals, or suitable combinations of metals. The device may then be subjected to quality control checks and tests to ensure that it functions as designed.

[0029] [picture] [5] An algorithm 500 for an integrated circuit manufacturing process according to a specific example of the present invention. Algorithm 500 may be implemented in conjunction with a programmable semiconductor wafer manufacturing controller or in other suitable manner.

[0030] Algorithm 500 begins at step 502, where an N++-doped substrate is positioned within a semiconductor wafer fabrication assembly. In one specific instance, the substrate may be formed from N++-doped material grown into an ingot and sliced. The neutral substrate material may be N++-doped by vapor deposition, or alternatively, other suitable processes may be used. The algorithm continues to step 504.

[0031] In step 504, an N+ epitaxial layer is formed on top of the N++ substrate layer. In one specific example, the N+ epitaxial layer can be formed in the existing N++ layer 402 by sealing the N++ layer 402 substrate with a thin, lightly doped silicon film (such as a thin silicon film about 2 μm thick or other suitable thickness) and then growing an N+ doped semiconductor material epitaxial layer by controlling the dopant level in the reaction chamber. The thin Si seal can be sacrificed to prevent self-doping during the epitaxial growth process. Alternatively, other suitable processes can be used. The algorithm then continues to step 506.

[0032] In step 506, a shielding oxide layer is formed on the top surface of the N+ epitaxial layer to protect the N+ epitaxial layer from defects caused by subsequent processing steps. The algorithm then proceeds to step 508.

[0033] In step 508, a photoresist layer is formed to produce a pattern or design for P+ implementation. In one specific instance, the photoresist layer may be formed and then exposed to light using a mask to cure the photoresist layer. The cured photoresist layer may then be removed with a suitable chemical to expose the pattern or design, or alternatively, other suitable processes may be used. The algorithm then proceeds to step 510.

[0034] In step 510, the cured photoresist layer is etched to remove the photoresist from the location where it was implanted into the P+ layer. The algorithm then continues to step 512.

[0035] At step 512, a P+ layer is implanted, for example by exposing the wafer to a predetermined level of vapor-form P+ material using ion beam implantation or other suitable methods. In one specific instance, the concentration and exposure time of the vapor deposition process can be controlled to produce a P+ layer with predetermined thickness and width parameters, or other suitable processes may be used alternatively. The algorithm then proceeds to step 514.

[0036] In step 514, the wafer is annealed to activate the implanted P+ dopant. In one specific instance, the wafer may be transferred to an annealing chamber or other suitable location where the temperature is controlled to allow the annealing process to take place. The algorithm then proceeds to step 516.

[0037] In step 516, a passivation oxide layer, such as an N-type SIPOS layer or other suitable passivation oxide layer, is formed. The algorithm then continues to step 518.

[0038] In step 518, a photoresist layer is deposited, and a mask is used to form a pattern for metal contact deposition. The photoresist layer can be cured after the mask has been deployed to form areas that can be subsequently etched. The algorithm then continues to step 520.

[0039] In step 520, the photoresist layer is etched to remove the cured photoresist from the predetermined area to allow the formation of metal contacts. The algorithm then proceeds to step 522.

[0040] In step 522, metal contacts with the P+ layer and the N++ substrate layer are formed by vapor deposition or other suitable processes. The device is then subjected to quality control testing, packaging, and other suitable post-manufacturing processing.

[0041] In operation, Algorithm 500 allows for the fabrication of helical transient voltage suppressors, Zener diodes, or other suitable devices that provide high power handling capabilities. Although Algorithm 500 is shown as a flowchart, those skilled in the art will recognize that it can also be implemented on one or more different processors using object-oriented programming, state diagrams, ladder diagrams, or other suitable methods.

[0042] In a specific embodiment of the present invention, a transient voltage suppressor is disclosed, comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; a channel formed in the epitaxial layer, the channel having a width W, a length L, and a plurality of curved regions, the channel forming a plurality of adjacent segments, the channel having a third doping different from the first doping and the second doping; and a metal layer formed on the top of the channel and contained within the width W of the channel. In other specific embodiments of the transient voltage suppressor, the first doping is N++ doping, the second doping is N+ doping, the third doping is P+ doping, the channel forms a closed loop, the channel extends spirally for more than 360 degrees from the center point, the channel extends spirally for more than 180 degrees from the center point, the channel extends spirally for more than 90 degrees from the center point, and the channel maintains a constant distance from edge to edge in the adjacent segments.

[0043] In another specific example, a method of manufacturing a transient voltage suppressor includes: forming a substrate having a first doping; forming an epitaxial layer on the substrate having a second doping different from the first doping; forming a channel in the epitaxial layer having a width W, a length L, and a plurality of curved regions, the channel having a plurality of adjacent segments, the channel having a third doping different from the first and second doping; and forming a metal layer on top of the channel, the metal layer being contained within the width W of the channel. In other specific examples, the method includes the first doping being N++, the second doping being N+, the third doping being P+, the channel forming a closed loop, the channel extending helically from a center point for more than 360 degrees, the channel extending helically from a center point for more than 180 degrees, the channel extending helically from a center point for more than 90 degrees, and the channel maintaining a constant distance from edge to edge in adjacent segments.

[0044] As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. It should further be understood that the terms “comprises and / or comprising” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. As used herein, phrases such as “between X and Y” and “about X and Y” should be interpreted as including both X and Y. As used herein, phrases such as “between about X and Y” mean “between about X and about Y”. As used herein, phrases such as “from about X to Y” mean “from about X to about Y”.

[0045] As used herein, "hardware" may include discrete components, integrated circuits, application-specific integrated circuits, field-programmable gate arrays, or other suitable combinations of hardware. As used herein, "software" may include one or more objects, agents, threads, code areas, subroutines, individual software applications, two or more code areas, or other suitable software structures operating in two or more software applications, on one or more processors (wherein processors include one or more microcomputers or other suitable data processing units, memory devices, input / output devices, displays, data input devices such as keyboards or mice, peripheral devices such as printers and speakers, associated drivers, control cards, power supplies, network devices, docking station devices, or other suitable devices operating together with processors or other devices under the control of a software system), or other suitable software structures. In one exemplary specific example, software may include one or more code areas or other suitable software structures operating in a general software application such as an operating system, and one or more code areas or other suitable software structures operating in a specific software application. As used herein, the term "couple" and its related terms, such as "couples / coupled," can include physical connections (such as copper wires), virtual connections (such as randomly assigned memory locations via data memory devices), logical connections (such as logic gates via semiconductor devices), other suitable connections, or suitable combinations of such connections. The term "data" can mean suitable structures for using, communicating, or storing data, such as data fields, data buffers, data messages having data values ​​and transmitter / receiver address data, control messages having data values, and one or more operators that cause a receiving system or component to perform functions using the data, or other suitable hardware or software components for the electronic processing of data.

[0046] Generally speaking, a software system is a system that operates on a processor to perform predetermined functions in response to predetermined data fields. A software system typically involves a human programmer generating source code for an algorithm, which is then compiled into a machine language algorithm that has the functionality of the source code algorithm and linked to specific input / output devices, dynamic link libraries, and other specific hardware and software components of the processor, thus transforming the processor from a general-purpose processor into a special-purpose processor. This well-known procedure for implementing the algorithm using the processor should not require interpretation by someone with ordinary knowledge of the art. For example, a system can be defined by the functions it performs and the data fields on which those functions are performed. As used herein, a NAME system (where NAME is typically the name of the general function performed by the system) refers to a software system configured to operate on a processor and perform the disclosed functions on disclosed data fields. The system can receive one or more data inputs, such as data fields or user-entered data, control the data in response to user prompts or other suitable information, and determine the appropriate action based on an algorithm, such as continuing to the next algorithm step when data is received, repeating prompts when no data is received, performing mathematical operations on two data fields, classifying or displaying data fields, or performing other suitable well-known algorithmic functions. Unless a specific algorithm is disclosed, any suitable algorithm known to those skilled in the art for performing functions using associated data fields is considered to be within the scope of this invention. For example, a messaging system that generates a message including a sender address field, a receiver address field, and a message field will encompass software operating on the processor. This software can obtain the sender address field, receiver address field, and message field from a suitable system or device (such as a buffer device or buffer system) of the processor; it can assemble the sender address field, receiver address field, and message field into a suitable electronic message format (such as an email message, a TCP / IP message, or any other suitable message format having sender address field, receiver address field, and message field); and it can transmit the electronic message using the processor's electronic messaging system and device via a communication medium (such as a network). Those skilled in the art will be able to provide specific code for a particular application based on the foregoing disclosure, which is intended to illustrate exemplary specific examples of the invention and is not intended to teach those without ordinary knowledge of the art (such as those unfamiliar with programming or processors using suitable programming languages). The specific algorithm used to perform the function may be provided in the form of a flowchart or in other suitable format, wherein the data fields and associated functions may be illustrated in an illustrative sequence of operations, wherein the sequence may be reconfigured as appropriate and is not intended to be restrictive unless explicitly stated otherwise.

[0047] It should be emphasized that the specific examples described above are merely possible implementation examples. Many variations and modifications can be made to the above specific examples without departing from the principles of the invention. All such modifications and variations are intended to be included within the scope of the invention herein and are protected by the following claims.

[0048] [ ] 100: Device 102: Metal layer 104: Curved area 106: Curved area 108: Curved area 110: Curved area 112: Curved area 114: N+ epitaxial layer 200: Device 202: Metal layer 204: Curved area 206: Curved area 208: Curved Area 210:N+ epitaxial layer 300: Device 302: Metallic layer 304: Bending area 306: Curved area 308: Curve Area 310:N+ epitaxial layer 400: Device 402: N++ doped semiconductor material layer 404: N+ doped semiconductor material epitaxial layer 406: Shielding oxide layer 408:P+ well 410:P+well 412:Metal contact 414:Metal contact 416:Metal contact 500:Algorithm 502: Steps 504: Steps 506: Steps 508: Steps 510: Steps 512: Steps 514: Steps 516: Steps 518: Steps 520: Steps 522: Steps S: Distance W: Width / Thickness

Claims

1. A transient voltage suppressor comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; a channel formed in the epitaxial layer, the channel having a width W, a length L and a plurality of cylindrical bends, the channel having a third doping different from the first doping and the second doping; and a metal layer having a plurality of bends forming a closed loop and formed on the top of the channel and contained within the width W and the length L of the channel.

2. A transient voltage suppressor as claimed in claim 1, wherein the first doping is N++ doping.

3. A transient voltage suppressor as claimed in claim 1, wherein the second doping is N+ doping.

4. A transient voltage suppressor as claimed in claim 1, wherein the third doping is P+ doping.

5. A transient voltage suppressor as described in claim 1, wherein the channel forms a single closed loop.

6. A transient voltage suppressor as requested in item 1, wherein the channel extends in a spiral shape greater than 360 degrees from the center point.

7. A transient voltage suppressor as requested in item 1, wherein the channel extends in a spiral shape greater than 180 degrees from the center point.

8. A transient voltage suppressor as requested in item 1, wherein the channel extends in a spiral shape greater than 90 degrees from the center point.

9. A transient voltage suppressor as claimed in claim 1, wherein the channel maintains a constant edge-to-edge distance in adjacent segments.

10. A method of manufacturing a transient voltage suppressor, comprising: forming a substrate having a first dopant; forming an epitaxial layer on the substrate, the epitaxial layer having a second dopant different from the first dopant; forming a channel in the epitaxial layer, the channel having a width W, a length L, and a plurality of cylindrical curved regions forming a closed loop, the channel having a third dopant different from the first dopant and the second dopant; and forming a metal layer having a plurality of curved regions and a closed loop shape on the top of the channel, the metal layer being contained within the width W and the length L of the channel.

11. The method of request item 10, wherein the first dopant is an N++ dopant.

12. The method of claim 10, wherein the second dopant is an N+ dopant.

13. The method of claim 10, wherein the third dopant is a P+ dopant.

14. The method of request item 10, wherein the channel forms a single closed loop.

15. The method of request item 10, wherein the channel extends in a spiral shape greater than 360 degrees from the center point.

16. The method of request item 10, wherein the channel extends in a spiral shape greater than 180 degrees from the center point.

17. The method of request item 10, wherein the channel extends in a spiral shape greater than 90 degrees from the center point.

18. The method of claim 10, wherein the channel maintains a constant distance from edge to edge in adjacent segments.

19. A transient voltage suppressor comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; a continuous parallel channel formed in the epitaxial layer, the parallel channel having a width W, a length L, a plurality of parallel regions and a plurality of curved regions, the parallel channel having a plurality of adjacent segments to form a closed loop, the parallel channel having a third doping different from the first doping and the second doping; and a metal layer formed on top of the parallel channel and contained within the width W of the parallel channel.

20. A transient voltage suppressor as claimed in claim 19, wherein the first doping is N++ doping.

21. A transient voltage suppressor as claimed in claim 19, wherein the second doping is N+ doping.

22. A transient voltage suppressor as claimed in claim 19, wherein the third doping is P+ doping.

23. A transient voltage suppressor as claimed in claim 19, wherein the parallel channel extends in a spiral shape greater than 360 degrees from the center point.

24. A transient voltage suppressor as claimed in claim 19, wherein the parallel channel extends in a spiral shape greater than 180 degrees from the center point.

25. A transient voltage suppressor as claimed in claim 19, wherein the parallel channel extends in a spiral shape greater than 90 degrees from the center point.

26. The transient voltage suppressor of claim 19, wherein the parallel channel maintains a constant edge-to-edge distance in adjacent segments.

27. A transient voltage suppressor comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; and a parallel channel formed in the epitaxial layer, the parallel channel having a width W, a length L, a plurality of parallel regions and a plurality of curved regions, the parallel channel having a plurality of adjacent segments to form a closed helical loop, the parallel channel having a third doping different from the first doping and the second doping.

28. A transient voltage suppressor as claimed in claim 27, wherein the first doping is N++ doping.

29. A transient voltage suppressor as claimed in claim 27, wherein the second doping is N+ doping.

30. A transient voltage suppressor as claimed in claim 27, wherein the third doping is P+ doping.

31. The transient voltage suppressor of claim 27, wherein the parallel channel extends in a spiral shape greater than 360 degrees from the center point.

32. The transient voltage suppressor of claim 27, wherein the parallel channel extends in a spiral shape greater than 180 degrees from the center point.

33. A transient voltage suppressor as claimed in claim 27, wherein the parallel channel extends in a spiral shape greater than 90 degrees from the center point.

34. The transient voltage suppressor of claim 27, wherein the parallel channel maintains a constant distance from edge to edge in an adjacent segment.

35. A transient voltage suppressor comprising: an electrode; a substrate disposed on the electrode, the substrate having a first doping; an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping different from the first doping; and a parallel channel formed in the epitaxial layer, the parallel channel having a width W, a length L, a plurality of parallel regions, and a plurality of curved regions, the parallel channel having a first segment and turning 180 degrees to form a second segment adjacent to the first segment to form a closed helical loop, the parallel channel having a third doping different from the first doping and the second doping.

36. The transient voltage suppressor of claim 35 further includes a metal layer disposed on top of the parallel channel and contained within the width W of the parallel channel.

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