Multi-channel voltage sensing circuit for pixel compensation

Abstract

A multi-channel voltage sensing circuit for pixel compensation includes: a plurality of channel circuits configured for the plurality of channels; and a first virtual channel circuit and a second virtual channel circuit configured among the plurality of channel circuits, wherein some channel circuits are interposed between the first virtual channel circuit and the second virtual channel circuit, wherein the first virtual channel circuit and the second virtual channel circuit receive a first reference voltage at a fixed voltage level and provide electrical coupling with adjacent channel circuits.

Description

Technical Field

[0001] Various implementations generally relate to compensating for pixels of a display panel, and more specifically, to a multi-channel voltage sensing circuit for pixel compensation, which is improved to give the multi-channel circuit for sensing pixel signals of the display panel consistent sensing characteristics. Prior Technology

[0002] The display system includes a display panel, a driver, and a timing controller.

[0003] The driver converts digital display data provided by the timing controller into analog source drive signals and then supplies these source drive signals to the display panel. The driver is configured on a single chip.

[0004] The number of drivers to be configured in the display system can be determined by considering the size and resolution of the display panel.

[0005] The display panel can be configured as an OLED panel. An OLED panel consists of pixels configured as OLEDs. In this case, there may be deviations in the electrical characteristics between the pixels of the display panel. These characteristic deviations should be corrected.

[0006] The display system should be configured to display the desired image by correcting for characteristic deviations between pixels.

[0007] For this purpose, the driver may include circuitry for sensing pixel characteristics. Therefore, the driver can be configured to sense pixel characteristics by reading out the pixel signal of the pixel, generate compensation data corresponding to the pixel signal, and provide the compensation data to a timing controller.

[0008] The timing controller can have the function of providing display data, which is obtained by compensating for characteristic deviations between pixels using compensation data from the driver.

[0009] The display data that compensates for pixel characteristics by sensing pixel signals as described above can be limited to panel compensation.

[0010] The driver includes internal circuitry, which includes channel circuitry, amplifier circuitry, and an analog-to-digital converter. Each of the internal circuits can have its own gain and offset values, and these gain and offset values ​​can vary for each channel processing the pixel signal.

[0011] The gain and offset values ​​of each element in the internal circuitry of the driver can vary with changes in power supply voltage or temperature.

[0012] Therefore, based on the differences in gain and offset values ​​for each channel, even the same pixel signal can be converted into different compensation data.

[0013] The driver can be configured to sense internal characteristics through internal circuitry, generate compensation data corresponding to the internal characteristics, and provide the compensation data to the timing controller.

[0014] The timing controller can have the function of compensating for display data based on pixel characteristics by excluding internal characteristics. When compensating for display data based on pixel characteristics by excluding internal characteristics as described above for the internal characteristics of the sensor driver, the exclusion of internal characteristics can be limited to internal compensation.

[0015] The driver can provide compensation data for internal compensation and panel compensation at different timings, and the timing controller can use the compensation data to compensate for the display data.

[0016] The driver has multiple channels for reading out pixel signals and is configured to include channel circuitry for each channel.

[0017] The driver can be configured to drive different ranges of channel circuitry depending on the channel mode. For illustration, assume the driver has 240 channels for reading pixel signals.

[0018] For example, the driver can be configured to operate in a channel mode selected between a first channel mode and a second channel mode, in which pixel signals are read out by means of 240 channels (i.e., all channels), and in which pixel signals are read out by means of some of the 240 channels in the second channel mode.

[0019] In the second channel mode, the driver can be configured such that some of the 240 channel circuits arranged in a row (e.g., 120 channel circuits) read out pixel signals. The remaining channel circuits may not read out pixel signals and may not be electrically connected to the pixels of the display panel.

[0020] The channel circuits located at both ends of the 120 channel circuits that read out pixel signals and are arranged in a row are configured in adjacent positions, where they can be electrically coupled to the channel circuits that do not read out pixel signals. The channel circuits that do not read out pixel signals are in an electrically floating state.

[0021] Therefore, the channel circuits at both ends of the channel circuit that reads out pixel signals and is arranged in a row are coupled to adjacent channel circuits that do not read out pixel signals and are in an electrically unstable state. Consequently, the channel circuits at both ends are electrically coupled to adjacent channel circuits in an electrically unstable state, and due to this coupling, the channel circuits at both ends may have unstable and varying internal offset values. Therefore, the channel circuits at both ends differ significantly from other channel circuits that read out pixel signals and are arranged in a row in terms of pixel signal sensing performance.

[0022] Therefore, for the reasons mentioned above, it is difficult for the channel circuits of drivers that form multiple channels to have consistent sensing characteristics, and as a result, it may be difficult to accurately perform compensation for pixel characteristic compensation display data. Summary of the Invention

[0023] Various implementations are designed to ensure that multi-channel circuitry can have consistent sensing characteristics and to ensure the reliability of compensation display data for pixel characteristics.

[0024] In one embodiment, the multi-channel voltage sensing circuit for pixel compensation may include: a plurality of channel circuits configured for the plurality of channels; and a first virtual channel circuit and a second virtual channel circuit configured among the plurality of channel circuits, wherein some channel circuits are inserted between the first virtual channel circuit and the second virtual channel circuit, wherein the first virtual channel circuit and the second virtual channel circuit receive a first reference voltage at a fixed voltage level and provide electrical coupling with adjacent channel circuits.

[0025] In one embodiment, the multi-channel voltage sensing circuit for pixel compensation may include: a plurality of channel circuits arranged for the plurality of channels; and a virtual channel circuit disposed among the plurality of channel circuits, wherein the virtual channel circuit receives a first reference voltage at a fixed voltage level and provides electrical coupling with adjacent channel circuits.

[0026] This disclosure configures a virtual channel circuit to be positioned between each of its readout unselected channel circuits and each of its readout selected channel circuits.

[0027] Therefore, when the channel circuit is electrically coupled to the virtual channel circuit at both ends of the selected channel circuit, the offset value of the internal circuit can be stabilized.

[0028] As a result, the readout of the selected channel circuit can have consistent sensing characteristics and can ensure the reliability of the display data for pixel characteristic compensation. Simple Explanation of the Diagram

[0029] Figure 1 is a circuit diagram illustrating a multi-channel voltage sensing circuit for pixel compensation according to an embodiment of the present disclosure, configured for a first channel mode.

[0030] Figure 2 is a circuit diagram illustrating a multi-channel voltage sensing circuit for pixel compensation according to an embodiment of the present disclosure, configured for a second channel mode.

[0031] Figure 3 is a detailed circuit diagram showing some of the channel circuitry.

[0032] Figure 4 is a graph illustrating the characteristics of the offset value of a general voltage sensing circuit used in the first channel mode.

[0033] Figure 5 is a graph illustrating the characteristics of the offset value of a general voltage sensing circuit used in the second channel mode.

[0034] Figure 6 is a graph illustrating the characteristics of the offset value of the voltage sensing circuit according to an embodiment of the present disclosure for the first channel mode.

[0035] Figure 7 is a graph illustrating the characteristics of the offset value of the voltage sensing circuit according to an embodiment of the present disclosure for the second channel mode. Implementation

[0036] A display system may include a display panel, a driver, and a timing controller.

[0037] Figure 1 is a circuit diagram for explaining embodiments of the present disclosure, and a display panel 10 and a driver 20 are shown in Figure 1 for the purpose of explaining embodiments of the present disclosure.

[0038] Display panel 10 can be exemplified as a panel in which pixels (not shown) are configured by OLEDs. Pixels can be formed in a matrix structure on display panel 10.

[0039] The driver 20 provides a source drive signal (not shown) to the display panel 10, and the pixels of the display panel 10 emit light in response to the source drive signal. An image represented by display data can be displayed by the light emission of the pixels.

[0040] In the detailed description of this disclosure, illustrations and descriptions of the configuration of the driver 20 providing source drive signals to the display panel 10 and the detailed configuration of the driver 20 internally will be omitted.

[0041] Each pixel in the display panel 10 is configured to output a pixel signal corresponding to the pixel characteristics via a sensing line SL1.

[0042] Figure 1 shows that the display panel 10 has 240 channels for outputting pixel signals, and the pixel signals are output via sensing lines SL1 for multiple channels.

[0043] The display panel 10 is interfaced with the driver 20 to have multiple channels for outputting pixel signals. That is, it can be understood that the sensing line SL1 of the display panel 10 is electrically connected one-to-one to the sensing line SL2 of the driver 20.

[0044] The driver 20 has sensing lines SL2 corresponding to multiple channels and is configured to read out pixel signals through the sensing lines SL2 respectively. Figure 1 shows that the sensing lines SL2 of the driver 20 are electrically connected to the sensing lines SL1 of the display panel 10 in a one-to-one manner through a total of 240 channels. As shown in Figure 1, the mode in which the total of 240 channels is configured to read out pixel signals can be defined as a first channel mode.

[0045] The pixel signals of the display panel 10 can be provided to the driver 20 through the electrical connection between the sensing line SL2 and the sensing line SL1.

[0046] The driver 20 is configured to read out pixel signals of pixels through multiple channels and generate and output compensation data ADC_CODE corresponding to the read-out pixel signals.

[0047] Multiple drivers 20 can be configured in a display panel 10. The number of drivers 20 configured in the display panel 10 can be determined according to the size and resolution of the display panel 10. For ease of explanation, an embodiment of this disclosure shows one driver 20 configured in the display panel 10.

[0048] The driver 20 can be manufactured as a semiconductor wafer. For example, terminals TL for forming multiple channels can be formed in a row on one side of the driver 20. It can be understood that the terminals TL are electrically connected one-to-one to the sensing lines SL2 in the driver 20.

[0049] Figure 1 shows that the driver 20 includes a selection circuit 30, multiple channel circuits SH1 to SH240, a virtual channel circuit DM, an amplifier 40, an analog-to-digital converter 50, and a bias unit 60.

[0050] In driver 20, sensing line SL2 is connected to multiple channel circuits SH1 to SH240 via selection circuit 30.

[0051] Multiple channel circuits SH1 to SH240 can be arranged in a row parallel to the terminals TL forming the multiple channels. In other words, the multiple channel circuits SH1 to SH240 can be formed to be arranged in a row relative to the multiple channels and adjacent to each other. Each of the multiple channel circuits SH1 to SH240 is configured to read the pixel signal of each pixel of the display panel 10 via a corresponding sensing line SL2, or receive the second reference voltage Vref2 from the selection circuit 30, and output a sensing voltage corresponding to the pixel signal or the second reference voltage Vref2.

[0052] In Figure 1, multiple channel circuits SH1 to SH240 are configured to correspond one-to-one with multiple channels. However, this is only an example, and the multiple channel circuits SH1 to SH240 are not limited to a one-to-one correspondence with multiple channels.

[0053] Each of the multiple channel circuits SH1 to SH240 can be configured to include a sample and hold circuit that samples and holds a sensed voltage corresponding to the difference between the input and the internal reference voltage, and its detailed configuration will be described later with reference to FIG3.

[0054] The driver 20 in Figure 1 includes two virtual channel circuits DM. The two virtual channel circuits DM are configured at different locations within the plurality of channel circuits SH1 to SH240. As a more detailed example, the two virtual channel circuits DM are positioned between the plurality of channel circuits SH1 to SH240, and some channel circuits SH61 to SH180 are interposed between the two virtual channel circuits DM. That is, one of the virtual channel circuits DM is positioned between channel circuits SH60 and SH61, and the other virtual channel circuit DM is positioned between channel circuits SH180 and SH181.

[0055] The virtual channel circuit DM can receive a first reference voltage Vref1 at a fixed voltage level and can provide electrical coupling to adjacent channel circuits. Unlike the multiple channel circuits SH1 to SH240, each of the virtual channel circuits DM does not output a sensed voltage.

[0056] For example, each of the virtual channel circuits DM is configured to maintain a charging voltage corresponding to the first reference voltage Vref1. That is, each of the virtual channel circuits DM can provide electrical coupling by acting as a coupling capacitor charged corresponding to the first reference voltage Vref1.

[0057] More specifically, each of the virtual channel circuits DM can be configured to charge a voltage corresponding to the difference between a first reference voltage Vref1 and a predetermined internal reference voltage. For this purpose, each of the virtual channel circuits DM can be configured to include a sample-and-hold circuit that samples and holds the sensed voltage corresponding to the difference between the input and the internal reference voltage, and its detailed configuration will be described later with reference to FIG3.

[0058] The selection circuit 30 is configured to selectively provide a second reference voltage Vref2 to the sensing line SL2. For this purpose, the selection circuit 30 is configured to include a plurality of switches SW that switch between the sensing line SL2 and the voltage line providing the second reference voltage Vref2. The plurality of switches SW are configured to correspond one-to-one with the sensing line SL2. The switching on and off of the plurality of switches SW can be controlled simultaneously, sequentially, or per group by switch control signals (not shown). For example, this disclosure will be described as the plurality of switches SW being switched on and off sequentially.

[0059] When the multiple switches SW of the selection circuit 30 are sequentially turned on, the second reference voltage Vref2 is sequentially supplied to the sensing line SL2, and the second reference voltage Vref2 of the sensing line SL2 is sequentially applied to the multiple channel circuits SH1 to SH240. On the other hand, when the multiple switches SW of the selection circuit 30 are turned off, the second reference voltage Vref2 stops being supplied to the multiple channel circuits SH1 to SH240 via the sensing line SL2.

[0060] The driver 20 in Figure 1 includes an amplifier 40, an analog-to-digital converter 50, and a bias unit 60.

[0061] Amplifier 40 can be configured by a circuit that receives the sensed voltage from the output of each of the multiple channel circuits SH1 to SH240, amplifies the sensed voltage, and outputs the amplified voltage. Since amplifier 40 can be designed differently to amplify the sensed voltage and output the amplified voltage according to the manufacturer's purpose, a detailed description thereof will be omitted.

[0062] The analog-to-digital converter 50 is configured to output digital compensation data ADC_CODE obtained by means of the output of the analog-to-digital converter amplifier 40. Since the analog-to-digital converter 50 can be designed to have various configurations for the output of the analog-to-digital converter amplifier 40 according to the manufacturer's purpose, detailed descriptions thereof will be omitted. For example, the analog-to-digital converter 50 can be configured to integrate the input sensed voltage, convert the digital code corresponding to the integrated voltage into compensation data ADC_CODE, and output the compensation data ADC_CODE.

[0063] The bias unit 60 can be configured to provide the bias voltage or bias current required for the operation of the amplifier 40 and the analog-to-digital converter 50. Since the bias unit 60 can also be designed differently to provide the bias voltage or bias current required by the amplifier 40 and the analog-to-digital converter 50 depending on the manufacturer's purpose, a detailed description of it will be omitted.

[0064] In the embodiment of FIG1 above, the voltage sensing circuit can be understood to include multiple channel circuits SH1 to SH240 and a virtual channel circuit DM. Furthermore, in the embodiment of FIG1, it can be understood that the voltage sensing circuit also includes at least one of a selection circuit 30, an amplifier 40, and an analog-to-digital converter 50.

[0065] The embodiment shown in Figure 1 illustrates a configuration in a first channel mode, in which pixel signals are read out by means of 240 channels (i.e., all channels).

[0066] In the first channel mode described above, all 240 channels of the driver 20 are electrically connected to the sensing line SL1 of the display panel 10, and the driver 20 reads out the pixel signal through the 240 channels.

[0067] In contrast, the embodiments of this disclosure can be configured as shown in FIG2 for a second channel mode. The second channel mode can be defined as a mode in which pixel signals are read out by means of some of the 240 channels.

[0068] Figure 2 shows the driver 20 configured such that some of the 240 channel circuits SH1 to SH240 arranged in a row for multiple channels (e.g., 120 channel circuits SH61 to SH180) read out pixel signals. The 120 selected channel circuits SH61 to SH180 that read out occupy a portion of a continuous area of ​​the region where the 240 channel circuits SH1 to SH240 are arranged in a row.

[0069] In the second channel mode described above, 120 channel circuits SH61 to SH180, which are some of the 240 channels of driver 20, are electrically connected to the sensing line SL1 of display panel 10, and driver 20 reads out pixel signals by reading out the selected 120 channels. It can be understood that an interface is not formed between display panel 10 and driver 20 for reading out the remaining unselected channels.

[0070] The difference between Figure 2 and Figure 1 lies in the channel area where the display panel 10 and the driver 20 are mated; the rest of the configuration is the same. Therefore, a detailed description of the configuration and operation of Figure 2 will be omitted.

[0071] The configuration of the multiple channel circuits SH1 to SH240 and the virtual channel circuit DM configured in Figures 1 and 2 can be understood by referring to Figure 3. Figure 3 shows that the channel circuits SH60 to SH181 are arranged in a row in an area where the multiple channel circuits SH1 to SH240 are arranged in a row.

[0072] In Figure 3, Vin60, Vin61, Vin180, and Vin181 represent the pixel signals read out via the sensing line SL2, Vrefs represent the internal reference voltage, and dV60, dV61, dV180, and dV181 represent the sensing voltages corresponding to the differences between the pixel signals Vin60, Vin61, Vin180, and Vin181 and the internal reference voltage Vrefs.

[0073] The channel circuit SH60 includes a capacitor circuit, one end of which is applied with a predetermined internal reference voltage Vrefs, and the other end is applied with a readout pixel signal Vin60. The capacitor circuit in the channel circuit SH60 is configured to charge and output a sensing voltage dV60 corresponding to the difference between the internal reference voltage Vrefs and the pixel signal Vin60.

[0074] More specifically, the capacitor circuit of the channel circuit SH60 includes a pair of capacitors connected in series via a ground node. In this pair of capacitors, one capacitor is configured to form one end of the capacitor circuit, is applied with an internal reference voltage Vrefs, and is charged with a voltage corresponding to the internal reference voltage Vrefs; the other capacitor is configured to form the other end of the capacitor circuit, is applied with a pixel signal Vin60, and is charged with a voltage corresponding to the pixel signal Vin60. With this configuration, the capacitor circuit of the channel circuit SH60 can charge and output a sensing voltage dV60 corresponding to the difference between the charging voltages of the two capacitors.

[0075] Since the configuration and operation of other channel circuits SH61, SH180 and SH181 can be understood by referring to the channel circuit SH60 described above, their description will be omitted.

[0076] The virtual channel circuit DM includes a capacitor circuit with a predetermined internal reference voltage Vrefs applied to one end and a first reference voltage Vref1 applied to the other end. The capacitor circuit configured in the virtual channel circuit DM is configured to store a charging voltage corresponding to the difference between the internal reference voltage Vrefs and the first reference voltage Vref1.

[0077] More specifically, the capacitor circuit of the virtual channel circuit DM includes a pair of capacitors connected in series via a ground node. In this pair of capacitors, one capacitor is configured to form one end of the capacitor circuit, is applied an internal reference voltage Vrefs, and is charged with a voltage corresponding to the internal reference voltage Vrefs; the other capacitor is configured to form the other end of the capacitor circuit, is applied a first reference voltage Vref1, and is charged with a voltage corresponding to the first reference voltage Vref1. In other words, it can be understood that the capacitor circuit of the virtual channel circuit DM stores a charging voltage corresponding to the difference between the charging voltages in the two capacitors.

[0078] In the above description, the first reference voltage Vref1 and the internal reference voltage Vrefs can be set to have the same voltage level.

[0079] In embodiments of this disclosure, driver 20 can be configured to output compensation data ADC_CODE for internal compensation and then output compensation data ADC_CODE for panel compensation.

[0080] For internal compensation, the driver 20 is operated to use the second reference voltage Vref2 to obtain the value of the second reference voltage Vref2 changed by the characteristics of the internal circuit, and outputs the compensation data ADC_CODE corresponding to the value.

[0081] When the mode for performing internal compensation is limited to the first mode, the driver 20 sequentially provides the second reference voltage Vref2 of the same voltage level to the channels configured with multiple channels, and outputs compensation data ADC_CODE determined by the characteristics of the internal circuitry, which includes channel circuitry corresponding to each channel, amplifier 40 and analog-to-digital converter 50.

[0082] Therefore, in the first mode, the selection circuit 30 is sequentially turned on, and each of the multiple channel circuits SH1 to SH240 receives the second reference voltage Vref2 via the sensing line SL2, and outputs a sensing voltage corresponding to the difference between the second reference voltage Vref2 and the internal reference voltage Vrefs. The sensing voltage can be output as compensation data ADC_CODE via amplifier 40 and analog-to-digital converter 50.

[0083] For panel compensation, the driver 20 is operated to read the pixel signal and output the compensation data ADC_CODE corresponding to the pixel signal.

[0084] When the mode used to perform panel compensation is limited to the second mode, the driver 20 reads the pixel signals of the channels configured with multiple channels and outputs compensation data ADC_CODE corresponding to the pixel signals of each channel.

[0085] Therefore, in the second mode, the selection circuit 30 is disconnected, and each of the multiple channel circuits SH1 to SH240 reads the pixel signal via the sensing line SL2 and outputs a sensing voltage corresponding to the difference between the pixel signal and the internal reference voltage Vrefs. The sensing voltage can be output as compensation data ADC_CODE via amplifier 40 and analog-to-digital converter 50.

[0086] The operation of driver 20 for the aforementioned internal compensation and panel compensation can be applied in the same manner to the first channel mode of FIG1 and the second channel mode of FIG2.

[0087] When performing operations for internal compensation and panel compensation, each of the multiple channel circuits SH1 to SH240 of driver 20 should read out the pixel signal and output a sensing voltage with the same offset value. Furthermore, by maintaining a consistent offset value, the multiple channel circuits SH1 to SH240 should have consistent sensing characteristics.

[0088] Figure 4 is a graph illustrating the characteristics of the offset values ​​of multiple channel circuits SH1 to SH240 when the virtual channel circuit DM is not configured and the display panel 10 and driver 20 are docked to correspond to the first channel mode shown in Figure 1. In Figure 4, a) corresponds to internal compensation, and b) corresponds to panel compensation.

[0089] As shown in Figures 4a) and 4b), when the display panel 10 and the driver 20 are docked in the first channel mode, the multiple channel circuits SH1 to SH240 maintain stable offset values ​​(offset voltages). That is, the reliability of the compensation for the pixel characteristics used to display data can be ensured.

[0090] Figure 5 is a graph illustrating the characteristics of the offset values ​​of multiple channel circuits SH61 to SH180 when the virtual channel circuit DM is not configured and the display panel 10 and driver 20 are docked to correspond to the second channel mode shown in Figure 2. In Figure 5, a) corresponds to internal compensation, and b) corresponds to panel compensation.

[0091] As shown in Figure 5a), when the display panel 10 and the driver 20 are docked in the second channel mode, the multiple channel circuits SH61 to SH180 maintain a stable offset value (offset voltage) for internal compensation. However, for panel compensation, as shown in Figure 5b), the multiple channel circuits SH61 to SH180 do not maintain a consistent and stable offset value (offset voltage).

[0092] More specifically, the offset values ​​of channel circuits SH61 and SH180 located at both ends of the 120 channel circuits SH61 to SH180 differ significantly from the offset values ​​of the other channel circuits SH62 to SH179, which are arranged in a row to read out pixel signals. Therefore, channel circuits SH61 and SH180 differ greatly from the other channel circuits SH62 to SH179 in their performance of compensating for pixel characteristics, resulting in difficulty in ensuring the reliability of pixel characteristic compensation used for display data.

[0093] In panel compensation where the virtual channel circuit DM is not configured, channel circuits SH61 and SH180 are configured in adjacent positions that can form an electrical coupling relationship with other channel circuits SH60 and SH181, whose readouts are not selected.

[0094] Therefore, channel circuits SH61 and SH180 may be affected by the electrical instability of adjacent channel circuits SH60 and SH181 that do not read out pixel signals, and may have unstable changes in internal offset values. That is, as shown in Figure 5b), in panel compensation, channel circuits SH61 and SH180 have significant differences in performance compared to other channel circuits SH62 to SH179 in compensating for pixel characteristics.

[0095] This disclosure is implemented as described above by including a virtual channel circuit DM to stabilize the offset values ​​of channel circuits SH61 and SH180 located at both ends of channel circuits SH61 to SH180 in a second channel mode.

[0096] Figure 6 is a graph illustrating the characteristics of the offset values ​​of multiple channel circuits SH1 to SH240 when the virtual channel circuit DM is configured and the display panel 10 and driver 20 are docked to correspond to the first channel mode shown in Figure 1. In Figure 6, a) corresponds to internal compensation, and b) corresponds to panel compensation.

[0097] When the display panel 10 and driver 20 are docked in the first channel mode as shown in FIG1, as shown in FIG6a) and b), the multiple channel circuits SH1 to SH240 maintain stable offset values ​​(offset voltages) in both internal compensation and panel compensation. That is, the reliability of the compensation for the pixel characteristics used to display data can be ensured.

[0098] Figure 7 is a graph illustrating the characteristics of the offset values ​​of multiple channel circuits SH61 to SH180 when the virtual channel circuit DM is configured and the display panel 10 and driver 20 are docked to correspond to the second channel mode shown in Figure 2. In Figure 7, a) corresponds to internal compensation, and b) corresponds to panel compensation.

[0099] When the virtual channel circuit DM is configured and the display panel 10 and driver 20 are docked to correspond to the second channel mode as shown in FIG2, the multiple channel circuits SH61 to SH180 maintain a stable offset value (offset voltage) for internal compensation as shown in FIG7a), and maintain a stable offset value (offset voltage) for panel compensation as shown in FIG7b).

[0100] More specifically, in embodiments of this disclosure, a virtual channel circuit DM electrically coupled to the channel circuits SH61 and SH180 located at both ends of the 120 channel circuits SH61 to SH180 is configured to be adjacent to the channel circuits SH61 and SH180, and the 120 channel circuits SH61 to SH180 are arranged in a row for readout.

[0101] The virtual channel circuit DM receives a first reference voltage Vref1 and has a charging voltage corresponding to the first reference voltage Vref1. Therefore, the virtual channel circuit DM acts as a coupling capacitor, which prevents the channel circuits SH61 and SH180 from being affected by the floating and electrically unstable channel circuits SH60 and SH181, and maintains a stable charging voltage in the channel circuits SH61 and SH180.

[0102] Therefore, channel circuits SH61 and SH180 can have the same or similar offset values ​​as the other channel circuits SH62 to SH179. In other words, channel circuits SH61 and SH180 do not differ significantly from the other channel circuits SH62 to SH179 in terms of performance in compensating for pixel characteristics.

[0103] Therefore, in embodiments of this disclosure, for internal compensation and panel compensation in either the first channel mode or the second channel mode, the channel circuits selected to read out the pixel signals can maintain completely consistent and stable offset values ​​(offset voltages). As a result, regardless of the first or second channel mode, all channel circuits SH1 to SH240 can always have consistent pixel characteristic compensation performance, and the reliability of pixel characteristic compensation for display data can be ensured.

[0104] 10: Display Panel 20: Drive 30: Selection Circuit 40: Amplifier 50: Analog to Digital Converter 60: Bias unit ADC: Analog to Digital Converter ADC_CODE: Compensation data DM: Virtual Channel Circuit dV60: Sensing voltage dV61: Sensing voltage dV180: Sensing voltage dV181: Sensing voltage SH1: Channel Circuit SH2: Channel Circuit SH59: Channel Circuit SH60: Channel Circuit SH61: Channel Circuit SH62: Channel Circuit SH179: Channel Circuit SH180: Channel Circuit SH181: Channel Circuit SH182: Channel Circuit SH239: Channel Circuit SH240: Channel Circuit SL1: Sensing line SL2: Sensing line SW: Switch TL: terminal Vin60: Pixel signal Vin61: Pixel signal Vin180: Pixel signal Vin181: Pixel signal Vref1: First reference voltage Vref2: Second reference voltage Vrefs: Internal reference voltage

Claims

1. A multi-channel voltage sensing circuit for pixel compensation, comprising: A plurality of channel circuits are provided for multiple channels, the plurality of channel circuits including a first channel circuit, a second channel circuit, a third channel circuit, and a fourth channel circuit, wherein the second channel circuit is adjacent to the first channel circuit, and the fourth channel circuit is adjacent to the third channel circuit; and a first virtual channel circuit and a second virtual channel circuit are disposed between the plurality of channel circuits, and some channel circuits are interposed between the first virtual channel circuit and the second virtual channel circuit, wherein the first virtual channel circuit is disposed between the first channel circuit and the second channel circuit, and the second virtual channel circuit is disposed between the third channel circuit and the fourth channel circuit, wherein the first virtual channel circuit and the second virtual channel circuit receive a first reference voltage at a fixed voltage level and provide electrical coupling with adjacent channel circuits; the first virtual channel circuit provides electrical coupling with the first channel circuit and the second channel circuit, and the second virtual channel circuit provides electrical coupling with the third channel circuit and the fourth channel circuit.

2. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the first virtual channel circuit and the second virtual channel circuit maintains a charging voltage corresponding to the first reference voltage.

3. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the first virtual channel circuit and the second virtual channel circuit acts as a coupling capacitor corresponding to the charging of the first reference voltage to provide the electrical coupling.

4. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the first virtual channel circuit and the second virtual channel circuit is charged with a voltage corresponding to the difference between the first reference voltage and a predetermined internal reference voltage.

5. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the first virtual channel circuit and the second virtual channel circuit includes a capacitor circuit having one end to which a predetermined internal reference voltage is applied and another end to which the first reference voltage is applied, and the capacitor circuit is charged and stored with a voltage corresponding to the difference between the first reference voltage and the internal reference voltage.

6. The multi-channel voltage sensing circuit according to claim 5, wherein, The first reference voltage and the internal reference voltage are set to have the same voltage level.

7. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the plurality of channel circuits is connected to a sensing line for reading out pixel signals and outputs a sensing voltage corresponding to the difference between the pixel signal and a predetermined internal reference voltage, and each of the first virtual channel circuit and the second virtual channel circuit is charged with a voltage corresponding to the difference between the first reference voltage and the internal reference voltage.

8. The multi-channel voltage sensing circuit according to claim 6 further includes: A selection circuit is configured to selectively provide a second reference voltage to a sensing line, wherein when the selection circuit is turned on in a first mode, each of the plurality of channel circuits receives the second reference voltage via the sensing line and outputs a sensing voltage corresponding to the difference between the second reference voltage and the internal reference voltage, and wherein when the selection circuit is turned off in a second mode, each of the plurality of channel circuits receives a pixel signal via the sensing line and outputs the sensing voltage corresponding to the difference between the pixel signal and the internal reference voltage.

9. The multi-channel voltage sensing circuit according to claim 8, further comprising: An amplifier is configured to receive and amplify the sensed voltage of the plurality of channel circuits; And an analog-to-digital converter, configured to output digital compensation data obtained by means of the output of the amplifier via the analog-to-digital converter.

10. The multi-channel voltage sensing circuit according to claim 1, wherein, Each of the plurality of channel circuits, the first virtual channel circuit, and the second virtual channel circuit includes a sample and hold circuit that samples and holds a sense voltage corresponding to the difference between the input and an internal reference voltage.

11. The multi-channel voltage sensing circuit according to claim 1, wherein, The selected channel circuit among the plurality of channel circuits and the first virtual channel circuit and the second virtual channel circuit is connected to the display panel via a sensing line for reading out pixel signals, and the first virtual channel circuit and the second virtual channel circuit are electrically coupled to the adjacent channel circuit that receives the pixel signals.

12. The multi-channel voltage sensing circuit according to claim 1, wherein, The multiple channels are arranged in a row for the multiple channels.

13. A multi-channel voltage sensing circuit for pixel compensation, comprising: Multiple channel circuits are arranged for multiple channels, the multiple channel circuits including a first channel circuit and a second channel circuit adjacent to the first channel circuit; A virtual channel circuit is disposed between the first channel circuit and the second channel circuit, wherein the virtual channel circuit receives a first reference voltage at a fixed voltage level and provides electrical coupling with the adjacent channel circuit, and provides electrical coupling with the first channel circuit and the second channel circuit.

14. The multi-channel voltage sensing circuit according to claim 13, wherein, The virtual channel circuit acts as a coupling capacitor corresponding to the charging of the first reference voltage to provide the electrical coupling.

15. The multi-channel voltage sensing circuit according to claim 13, wherein, The virtual channel circuit includes a capacitor circuit having one end to which a predetermined internal reference voltage is applied and another end to which the first reference voltage is applied, and the capacitor circuit is charged and stored with a voltage corresponding to the difference between the first reference voltage and the internal reference voltage.

16. The multi-channel voltage sensing circuit according to claim 13, wherein, Each of the plurality of channel circuits is connected to a sensing line for reading out pixel signals and outputs a sensing voltage corresponding to the difference between the pixel signal and a predetermined internal reference voltage, and the virtual channel circuit is charged with a voltage corresponding to the difference between the first reference voltage and the internal reference voltage.

17. The multi-channel voltage sensing circuit according to claim 13, wherein, Each of the plurality of channel circuits and the virtual channel circuit includes a sample and hold circuit that samples and holds a sense voltage corresponding to the difference between the input and an internal reference voltage.

18. The multi-channel voltage sensing circuit according to claim 13, wherein, The multiple channel circuits are arranged in a row for the multiple channels.

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