Method and apparatus for performing block interleaving for data transmission

Abstract

An apparatus includes: an encoder configured to encode source data and generate a codeword consisting of a plurality of bits; and an interleaver configured to perform block-based interleaving of the codeword including a plurality of sub-blocks, wherein the interleaver is configured to: generate a first reference input index of a first reference sub-block among the sub-blocks; generate a first input index of a first sub-block among the sub-blocks based on the first reference input index, the first sub-block being arranged adjacent to a first reference sub-block in a first direction; and store bits corresponding to the first reference sub-block and the first sub-block in internal memory according to the first reference input index and the first input index, respectively.

Description

Technical Field

[0001] The present invention relates to an interleaving method, and more specifically to a method and apparatus for performing block interleaving for data transmission. [Cross-reference to related applications]

[0002] This application is based on and claims priority over Korean Patent Application No. 10-2021-0018534, filed on February 9, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Prior Technology

[0003] With the increasing data throughput required to be processed in short periods of time in data transceiver systems, the importance of data processing speed and / or efficiency of exemplary embodiments of the devices in the system has been emphasized. Furthermore, although the power consumed by data processing and data transmission in the system continues to increase, the amount of available power supplies is limited. Therefore, efficiency in power usage within the devices of the system is also advantageous.

[0004] In various data transmission systems, interleavers are inevitably used for data transfer. Interleavers can transform clustered errors into random errors, thus improving error correction performance. Recently, interleavers have been implemented to perform block interleaving with right-angled isosceles triangles. However, according to previous methods, the computational complexity for interleaving is higher, and therefore, inefficiencies in terms of power consumption and / or hardware area complexity may become problems. Summary of the Invention

[0005] The present invention provides a method and apparatus for performing block interleaving to reduce hardware area complexity and / or provide improved power efficiency.

[0006] According to a concept of the present invention, an apparatus is provided, the apparatus comprising: an encoder configured to generate a codeword consisting of a plurality of bits by encoding source data; and an interleaver configured to perform block-based interleaving of the codeword including a plurality of sub-blocks, wherein the interleaver is configured to: generate a first reference input index of a first reference sub-block among the sub-blocks; generate a first input index of a first sub-block among the sub-blocks based on the first reference input index, the first sub-block being arranged adjacent to the first reference sub-block in a first direction; and store bits corresponding to the first reference sub-block and the first sub-block in internal memory according to the first reference input index and the first input index, respectively.

[0007] According to another aspect of the present invention, a block-based interleaving method is provided, the block-based interleaving method comprising multiple sub-blocks and performed on codewords composed of multiple bits, the block-based interleaving method comprising: generating a first reference input index of a first reference sub-block among the sub-blocks; generating a first input index of the first sub-block among the sub-blocks based on the first reference input index, the first sub-block being arranged adjacent to the first reference sub-block in a first direction; and storing bits corresponding to the first reference sub-block and the first sub-block.

[0008] According to another aspect of the present invention, an apparatus is provided, the apparatus comprising: a memory; a processor configured to encode source data and generate a codeword consisting of a plurality of bits and configured to perform block-based interleaving of the codeword including a plurality of sub-blocks; and integrated circuitry configured to output data including the interleaved codeword via a predetermined or otherwise desired channel, wherein the processor is further configured to: generate a first input index of a first sub-block, the first sub-block corresponding to a first row, based on an order relationship between first sub-blocks among the sub-blocks; store bits corresponding to the first sub-block in the memory; and output the bits stored in the memory according to a first output index of the first sub-block. Simple Explanation of the Diagram

[0009] Exemplary embodiments of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG1 is a block diagram of an electronic system according to an exemplary embodiment.

[0010] Figure 2 is a flowchart of the block interleaving operation of the interleaver according to an exemplary embodiment.

[0011] Figure 3 is a diagram of a comparative embodiment of an exemplary embodiment.

[0012] Figure 4 is a diagram of a block according to an exemplary embodiment.

[0013] Figure 5 is a flowchart of an operation method of an interleaver according to an exemplary embodiment.

[0014] Figure 6 is a diagram showing the sequential relationship between the first sub-block and the second sub-block arranged in the same row according to an exemplary embodiment.

[0015] Figures 7A and 7B are detailed diagrams of the operation of the interleaver according to an exemplary embodiment.

[0016] Figure 8A is a block diagram of the components of an interleaver according to an exemplary embodiment, and Figure 8B is a diagram of the output of the interleaver shown in Figure 8A.

[0017] Figure 9 is a flowchart of the block interleaving operation of the interleaver according to an exemplary embodiment.

[0018] Figure 10 is a detailed diagram of the operation of the interleaver according to an exemplary embodiment.

[0019] Figure 11 is a diagram of a block according to an exemplary embodiment.

[0020] Figure 12 is a diagram illustrating an embodiment for generating the input index of the p-1th sub-block shown in Figure 11.

[0021] Figure 13 is a block diagram of a communication system according to an exemplary embodiment.

[0022] Figure 14 is a block diagram of a system according to an exemplary embodiment.

[0023] Figure 15 is a block diagram of a processor according to an exemplary embodiment. Implementation

[0024] In the following sections, exemplary embodiments of the present invention are described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram of an electronic system 1 according to an exemplary embodiment. As shown in Figure 1, the transmitter 10 and the receiver 20 can communicate with each other via a channel 30.

[0026] According to exemplary embodiments, electronic system 1 may include any communication system that defines a communication protocol between transmitter 10 and receiver 20. In some exemplary embodiments, channel 30 may include a wireless channel using radio resources, and electronic system 1 may include a wireless communication system. For example, electronic system 1 may include: a wireless communication system using a cellular network, such as a 5th generation wireless (5G) new radio (NR) system, a long term evolution (LTE) system, an LTE-advanced system, a code division multiple access (CDMA) system, or a global system for mobile communication (GSM); a wireless personal area network (WPAN) system; or any other wireless communication system. Additionally, in some exemplary embodiments, channel 30 may include a wired channel using electrical signals and / or optical signals, and electronic system 1 may include a wired communication system.

[0027] In another exemplary embodiment, electronic system 1 may include a memory system or an image processing system. In some exemplary embodiments, channel 30 may include a wired channel using electrical signals and / or optical signals, and each of transmitter 10 and receiver 20 may correspond to a controller, memory device, or imaging device. However, examples of electronic system 1 implementing the inventive concept are not limited thereto. The inventive concept can be widely implemented in various electronic systems that transmit and receive data via a predetermined or alternatively desired channel. Hereinafter, electronic system 1 will be described primarily based on wireless communication systems (especially 5G NR systems using cellular networks). However, it should be understood that exemplary embodiments of the inventive concept are not limited thereto.

[0028] When electronic system 1 is a wireless communication system using a cellular network, each of transmitter 10 and receiver 20 can be a base station (BS) or user equipment (UE). When transmitter 10 is a BS and receiver 20 is a UE, a downlink can be formed in channel 30. Conversely, when transmitter 10 is a UE and receiver 20 is a BS, an uplink can be formed in channel 30. Additionally, when both transmitter 10 and receiver 20 are UEs, a sidelink can be formed in channel 30. Transmitter 10 can operate as a receiver receiving signals via channel 30, and receiver 20 can operate as a transmitter transmitting signals via channel 30.

[0029] A BS generally refers to a fixed station that communicates with a UE and / or another BS, and can exchange data and control information with the UE and / or the other BS through communication. For example, a BS can be called a Node B, Evolved Node B (eNB), Next Generation Node B (gNB), sector, site, base transceiver system (BTS), access point (AP), relay node, remote radio head (RRH), radio unit (RU), small cell, etc. In this specification, BS or cell can be interpreted as having the following combined meaning: This combined meaning indicates one or more areas or functions covered by the base station controller (BSC) in a CDMA system, a node B in a wideband code division multiple access (WCDMA) system, an eNB in ​​an LTE system, a gNB in ​​a 5G system, a sector (site), etc., and can encompass all different coverage areas, such as mega-cell, macro-cell, micro-cell, pico-cell, femto-cell, relay node, RRH, RU, small cell communication range, etc. UE can be fixed or mobile, and can refer to any device capable of transmitting and receiving data and / or control information by communicating with the BS. For example, UE can also be referred to as a terminal, terminal equipment, mobile station (MS), mobile terminal (MT), user terminal (UT), subscriber station (SS), wireless device, handheld device, etc.

[0030] The wireless communication network between the UE and BS can support communication between multiple users by sharing available network resources. For example, in a wireless communication network, information can be transmitted using various multiple access methods such as CDMA, frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), orthogonal frequency division multiple (OFDM)-FDMA, OFDM-TDMA, and OFDM-CDMA.

[0031] Transmitter 10 can transmit signals via channel 30, and receiver 20 can receive signals via channel 30. Electronic system 1 can define channel coding. Therefore, transmitter 10 can transmit coded signals via channel 30, and receiver 20 can decode signals received via channel 30. For example, electronic system 1 can define channel coding based on polar code (or polar sign), Reed-Solomon code, convolutional code, etc.

[0032] As shown in Figure 1, transmitter 10 may include encoder 12 for channel encoding, and receiver 20 may include decoder (not shown). Encoder 12 may encode source data SD and generate codeword CW. Codeword CW may include error correcting code (ECC) for correcting bit errors caused by noise, interference, etc., generated from channel 30. Transmitter 10 may include interleaver 100, which is configured to perform block-based interleaving on codeword CW. In addition to channel encoding by encoder 12, interleaver 100 may perform interleaving on codeword CW to additionally improve data reliability. In some exemplary embodiments, encoder 12 and interleaver 100 may be integrated into a circuit included in a processor (not shown). In some exemplary embodiments, the processor may perform channel encoding and interleaving according to the exemplary embodiments.

[0033] According to an exemplary embodiment, interleaver 100 can perform block-based interleaving of codeword CW, including multiple sub-blocks. According to an exemplary embodiment, the blocks may have shapes where the length of the sides varies depending on the columns and rows. For example, blocks may have various shapes, such as right-angled isosceles triangles, trapezoids, etc. Hereinafter, exemplary embodiments of the inventive concept are illustrated based on blocks having the shape of right-angled isosceles triangles. However, it should be understood that the exemplary embodiments are not limited thereto.

[0034] According to an exemplary embodiment, interleaving 100 can perform interleaving by dividing a block into sub-blocks and the size of the sub-blocks can be configured. For example, interleaving 100 can configure the size of the sub-blocks based on the operating conditions of the transmitter 10. The operating conditions may be related to the power status (or battery status) of the transmitter 10, the amount of data to be transmitted to the receiver 20, etc. According to an exemplary embodiment, a sub-block can be configured to have a length of 2n bits in a first direction (n is an integer equal to or greater than 1) and a length of 1 bit in a second direction intersecting the first direction. However, this is only an exemplary embodiment. The inventive concept is not limited to this, and the sub-blocks can be configured to have various sizes to form a predetermined or alternatively desired relationship between the sub-blocks. Depending on the shape of the block, the block may further include sub-blocks with a different size than the sub-blocks with a length of 2n bits in the first direction (n is an integer equal to or greater than 1) and a length of 1 bit in the second direction intersecting the first direction. The method for generating input and output indices for sub-blocks of different sizes will be described in detail below with reference to Figures 11 and 12.

[0035] Interleaver 100 can write bits of codeword CW in consecutive columns of a block from left to right and read bits of codeword CW in consecutive rows of a block from top to bottom. Hereinafter, the direction from top to bottom may be referred to as the first direction or row direction, and the direction from left to right may be referred to as the second direction or column direction. In some exemplary embodiments, the first and second directions may vary depending on the implementation of the block or interleaving method.

[0036] To write bits of codeword CW, interleaver 100 can generate input indices (or input addresses) for each bit. Additionally, to read bits of codeword CW from a block, interleaver 100 can generate output indices (or output addresses) for each bit. That is, interleaver 100 can write bits of codeword CW into a block according to the generated input indices and read bits of codeword CW from the block according to the generated output indices. The block can correspond to the virtual space of the interleaver 100's internal memory. Therefore, writing and reading to a block can represent writing and reading to internal memory.

[0037] According to an exemplary embodiment, interpolator 100 can generate a first reference input index for a first reference sub-block in the first row of a block, and can generate a first input index for at least one first sub-block based on the first reference input index, the at least one first sub-block being arranged together with the first reference sub-block in a first direction. The input index of a sub-block may include a plurality of input indices corresponding to bits written into the sub-block. According to an exemplary embodiment, interpolator 100 can configure the size of the sub-block such that the first reference input index and the first input index can form an inter-sequential relationship. Hereinafter, the inter-sequential relationship between sub-blocks may refer to the inter-sequential relationship between the input indices corresponding to the sub-blocks. According to an exemplary embodiment, interpolator 100 can generate the first input index by performing simple addition, subtraction, and shifting using the first reference input index.

[0038] According to an exemplary embodiment, interleaver 100 can generate a second reference input index for a second reference sub-block in a second row of a block, and can generate a second input index for at least one second sub-block based on the second reference input index, the at least one second sub-block being arranged together with the second reference sub-block in a first direction.

[0039] According to another exemplary embodiment, interleaving unit 100 may use a previously generated first reference input index or first input index to generate a second input index for the at least one second sub-block in the second row of the block. The first sub-block arranged in the first row and the second sub-block arranged in the second row may form a predetermined or alternatively desired relationship. Interleaving unit 100 may generate the second input index based on the first reference input index or first input index by taking this relationship into account.

[0040] Interleaver 100 can consider predetermined or alternatively desired relationships between sub-blocks and can generate input indices for all sub-blocks through simple calculation, as described above according to the exemplary embodiment. Interleaver 100 can write bits of codeword CW into internal memory based on the generated input indices. Interleaver 100 can generate output indices for the sub-blocks and can read bits of codeword CW from internal memory based on the output indices to output interleaved codeword I_CW.

[0041] In some exemplary embodiments, after performing additional interleaving on the sub-blocks in addition to the block interleaving described above, the interleaved codeword I_CW can be transmitted to the receiver 20 via channel 30.

[0042] The interleaver 100 according to the exemplary embodiment can utilize the relationships between sub-blocks and generate input indices for interleaving through simple calculations, thus simplifying the hardware design of the interleaver 100 and enabling efficient power utilization. Therefore, the overall performance of the transmitter 10 can be improved.

[0043] According to an exemplary embodiment, receiver 20 may further include a de-interleaver (not shown) and can be used to rearrange the interleaved codewords I_CW to their original order. In some exemplary embodiments, the de-interleaver may also implement the inventive concept of the interleaver 100 described above. Therefore, the de-interleaver can perform de-interleaving by simple calculation. In addition, receiver 20 may further include a decoder (not shown) and can be used to decode the de-interleaved codewords into source data.

[0044] Additionally, transmitter 10 may further include a deinterleaver (not shown) for deinterleaving signals received from the outside and a decoder (not shown) for decoding the deinterleaved signals. For example, the deinterleaver may be configured to perform a deinterleaving operation corresponding to the operation of interleaver 100.

[0045] Figure 2 is a flowchart of the block interleaving operation of the interleaver according to an exemplary embodiment.

[0046] Referring to Figure 2, in operation S100, the interleaver can configure the size of the sub-blocks included in the block. For example, the interleaver can adaptively configure the size of the sub-blocks according to the operating conditions of the device. The interleaver can configure the size of the sub-blocks to have a length of 2n bits in a first direction (n is an integer equal to or greater than 1) and a length of 1 bit in a second direction intersecting the first direction.

[0047] In operation S110, the interleaver can generate reference input and output indices for reference sub-blocks in the first row of the block. In the following text, input and output indices include both input and output indices.

[0048] In operation S120, the interleaver can generate input and output indices for sub-blocks arranged in the first row of the block, based on reference input and output indices, wherein the sub-blocks are parallel to the reference sub-blocks in a first direction. For example, the interleaver can generate input indices based on the reference input indices according to the order relationship between the reference sub-blocks and the sub-blocks. Additionally, the interleaver can generate output indices for the sub-blocks in the same manner. In operation S120, the interleaver can use the methods described in operation S120 to generate input and output indices for sub-blocks in rows other than the first row of the block.

[0049] In operation S130, the interleaver can perform block-based interleaving using the generated input and output indices. According to an exemplary embodiment, the interleaver can write bits of a codeword into internal memory according to the input index of the generated sub-block and can read bits of a codeword from internal memory according to the output index of the generated sub-block. In this way, the interleaver can perform block-based interleaving.

[0050] Figure 3 is a diagram of a comparative embodiment of an exemplary embodiment of the present invention. Figure 3 shows an example compared with the exemplary embodiment. It is obvious that the concept of the present invention should not be construed as limited to the example shown in Figure 3.

[0051] Referring to Figure 3, the block BLK can have the shape of a right-angled isosceles triangle.

[0052] The length T of the edge of block BLK can be configured based on [Equation 1].

[0053]

[0054] The codeword written into block BLK can consist of E bits. The minimum value among those satisfying [Equation 1] can be the length T of one edge of block BLK. For example, the length T of one edge of block BLK can correspond to a length of 8 bits. Null data is written into the part of block BLK indicated as N, and the number D of null data can correspond to [Equation 2].

[0055] [Equation 2] D = T × (T + 1) / 2 - E

[0056] Block BLK may include a first part P1 to a third part P3, and the length T2 of the edge to the second part P2 may be configured based on [Equation 3].

[0057]

[0058] The minimum value among those satisfying [Equation 3] can be the length T2 of the edge to the second part P2. For example, the length T2 can correspond to a length of 4 bits.

[0059] The length T1 of the edge to the first part P1 can be configured based on [Equation 4].

[0060] [Equation 4] T1 = T2 × (T2 + 1) - D

[0061] In a comparative embodiment, when the input and output indices are generated in the first part P1, the interleaver can use the following algorithm.

[0062]

[0063] The numbers 0 to 36 written in block BLK indicate the input index of the bits of the codeword written in block BLK. As described in the algorithm above, the bits of the codeword can be written into consecutive columns of block BLK from left to right according to the input index, and the bits of the codeword in consecutive rows of block BLK can be read from top to bottom according to the output index.

[0064] In a comparative embodiment, the interleaver must perform complex calculations (e.g., multiplication and division) to generate the input index in the first part P1. Therefore, the hardware complexity and / or power consumption of the interleaver may increase.

[0065] Figure 4 is a diagram of block BLK according to an exemplary embodiment. In the following text, block BLK is an example to aid in understanding the concept of the invention. Only one or more sub-blocks SB1 to SB6 are shown, and exemplary embodiments of the concept of the invention can be implemented using blocks of various shapes other than the block BLK shown in Figure 4.

[0066] Referring to Figure 4, block BLK may include first sub-block SB1 to sixth sub-block SB6. Block BLK may have the shape of a right-angled isosceles triangle, and the length of one side may correspond to the length of T bits.

[0067] According to an exemplary embodiment, the first sub-block SB1 to the sixth sub-block SB6 may have a length of 2n bits less than T in the first direction D1 (or row direction) and a length of 1 bit in the second direction D2 (or column direction).

[0068] According to an exemplary embodiment, the interleaver can generate input indices for a first sub-block SB1 to a third sub-block SB3 corresponding to the first row. For example, the interleaver can select the first sub-block SB1 as a reference sub-block and can use the input index of the first sub-block SB1 to generate the input index of the second sub-block SB2 and the input index of the third sub-block SB3. That is, the first sub-block SB1 and the second sub-block SB2 can form a sequential relationship. In addition, the first sub-block SB1 and the third sub-block SB3 can form a sequential relationship. In some exemplary embodiments, the interleaver can use the input index of the first sub-block SB1 to generate the input index of the second sub-block SB2 and the input index of the third sub-block SB3 in parallel. For this purpose, the interleaver can include at least two interleaver circuits. The interleaver can use the input index of the first sub-block SB1 to generate the input index of the second sub-block SB2 and the input index of the third sub-block SB3 by using addition, subtraction, and shifting. The number of bits written to the first subblock SB1 through the sixth subblock SB6 is 2n, and therefore the shift calculation used to generate the input index can replace multiplication.

[0069] According to an exemplary embodiment, the interleaver can generate input indices for the fourth sub-block SB4 to the sixth sub-block SB6 corresponding to the second row. For example, the interleaver can select the fourth sub-block SB4 as a reference sub-block and can use the input index of the fourth sub-block SB4 to generate the input index of the fifth sub-block SB5 and the sixth sub-block SB6. That is, the fourth sub-block SB4 and the fifth sub-block SB5 can form a mutual sequential relationship. In addition, the fourth sub-block SB4 and the sixth sub-block SB6 can form a mutual sequential relationship.

[0070] As another example, the interleaver can use the input indices of the first sub-blocks SB1 to SB3 to generate the input indices of the fourth sub-blocks SB4 to SB6. For instance, the interleaver can generate the input index of the fourth sub-block SB4 by adding a predetermined or alternatively desired constant to the input index of the first sub-block SB1. The interleaver can generate the input index of the fifth sub-block SB5 by adding a predetermined or alternatively desired constant to the input index of the second sub-block SB2. Furthermore, the interleaver can generate the input index of the sixth sub-block SB6 by adding a predetermined or alternatively desired constant to the input index of the third sub-block SB3. The constant can be determined based on the distance difference between the sub-blocks. For example, when generating the input index of the sub-block corresponding to the second row based on the input index of the sub-block corresponding to the first row, the constant can be determined to be 1, and when generating the input index of the sub-block corresponding to the third row based on the input index of the sub-block corresponding to the first row, the constant can be determined to be 2. To generate the input indices of sub-blocks for other rows, the interleaver can pre-store the input indices of the sub-blocks of rows (which are references to other rows) in internal memory and can read the input indices from internal memory as needed.

[0071] The interleaver according to the exemplary embodiment can generate input indices for the remaining sub-blocks (not shown) using the same method as described above. Additionally, the interleaver can perform block-based interleaving using internal memory by generating output indices for the sub-blocks.

[0072] Figure 5 is a flowchart of an operation method of an interleaver according to an exemplary embodiment.

[0073] Referring to Figure 5, in operation S200, the interleaver can set k (k is an integer equal to or greater than 1) to 1, and in operation S210, the interleaver can generate reference input and output indices for the reference sub-block of the k-th row of the block. In operation S220, the interleaver can generate input and output indices for the sub-blocks of the k-th row of the block. According to an exemplary embodiment, the interleaver can generate input indices for sub-blocks based on the reference input index of the reference sub-block of the k-th row, the sub-blocks being arranged together with the reference sub-block in a first direction. The k-th row of the block may include the reference sub-block and multiple sub-blocks. In some exemplary embodiments, in operation S220, the interleaver can use the reference input index of the reference sub-block to generate input indices for the multiple sub-blocks. In some exemplary embodiments, the interleaver can use the reference input index of the reference sub-block to perform the generation of input indices for the multiple sub-blocks in parallel. For example, the interleaver can use reference input indices to generate the input indices of the first sub-block in row k and the second sub-block in row k in parallel.

[0074] In operation S230, the interleaver determines whether the k-th row is the last row of the block. If the k-th row is not the last row of the block in operation S230 (NO), operation S240 can then be executed, in which the interleaver counts up to k. Then, operation S210 can be executed next. Figure 5 illustrates the generation of input and output indices for sub-blocks of a block based on row sequence. However, it is not limited to this, and the interleaver can generate input and output indices corresponding to each row in parallel.

[0075] Otherwise, if the k-th row in operation S240 is the last row of the block (YES), operation S250 can be performed subsequently, in which the interleaver can use the input and output indices of the sub-blocks of the resulting block to perform interleaving.

[0076] Figure 6 is a diagram illustrating the order relationship between a first sub-block SB1 and a second sub-block SB2 arranged in the same row according to an exemplary embodiment. It is assumed that the first sub-block SB1 and the second sub-block SB2 shown in Figure 6 correspond to the first sub-block SB1 and the second sub-block SB2 of block BLK shown in Figure 4. However, the exemplary embodiments illustrated with reference to Figure 6 are merely for the purpose of aiding understanding the concept of the invention, and the concept of the invention is not limited thereto. The concept of the invention can be implemented by applying different order relationships between the first sub-block SB1 and the second sub-block SB2, which are formed based on the shape of the blocks and sub-blocks, the method of interleaving, etc.

[0077] Referring to Figure 6, the first sub-block SB1 may include first elements a1 to eighth elements a8 arranged in the first direction D1 (or row direction), and the second sub-block SB2 may include ninth elements a9 to sixteenth elements a16 arranged in the first direction D1 (or row direction). Elements may represent virtual space, in which a bit is written according to an input index or a bit is read from the virtual space according to an output index. In the following, the relationship between the first sub-block SB1 and the second sub-block SB2 is described based on the input index, and the input index of an element may represent the input index of the bit corresponding to that element.

[0078] The relationship between the input indices corresponding to the first elements a1 to a8 in the first sub-block SB1 and the ninth elements a9 to a16 in the second sub-block SB2 is the same as shown in Figure 6. That is, the input index of the first element a1 may differ from the input index of the second element a2, and the difference corresponds to the length T of an edge of the block BLK shown in Figure 4. The input index of the second element a2 may differ from the input index of the third element a3, and the difference corresponds to the length T-1. That is, the input indices of the first element a1 to the sixteenth element a16 may have the following order relationship [Equation 5].

[0079]

[0080] The input indices an_II of the first element a1 to the sixteenth element a16 can have a difference sequence. The difference bk is an equal difference sequence, and the sum Sn of the differences bk can be added to the initial input index a1_II.

[0081] Assuming T=21 and tolerance(d)=1, the relationship between the first element a1 to the eighth element a8 of the first sub-block SB1 and the ninth element a9 to the sixteenth element a16 of the second sub-block SB2 corresponds to [Equation 6].

[0082] [Equation 6] a(n+8)_II_SB2=an_II_SB1+21×8-28-(n-1)×8

[0083] That is, the input index a(n+8)_II_SB2 of the ninth element a9 to the sixteenth element a16 of the second sub-block SB2 and the input index an_II_SB1 of the first element a1 to the eighth element a8 of the first sub-block SB1 can have the order relationship as shown in [Equation 6].

[0084] According to an exemplary embodiment, the interleaver can generate the input index an_II_SB1 of the first sub-block SB1, and then generate the input index a(n+8)_II_SB2 of the second sub-block SB2 based on [Equation 6] by considering the relationship between the first sub-block SB1 and the second sub-block SB2. In [Equation 6], since the first sub-block SB1 and the second sub-block SB2 consist of 2n elements, multiplication can be replaced by shifting. Therefore, the interleaver can generate the input index a(n+8)_II_SB2 of the second sub-block SB2 by performing simple addition, subtraction, and shifting based on [Equation 6].

[0085] Figures 7A and 7B are detailed diagrams of the operation of the interleaver according to exemplary embodiments. The exemplary embodiments shown in Figures 7A and 7B are based on the exemplary embodiments shown in Figures 4 to 6.

[0086] Referring to Figure 7A, the input index an_II_SB1 of the first element a1 to the eighth element a8 of the first sub-block SB1 can be generated based on Equation 5 shown in Figure 6 and can have values ​​0, 21, 41, 60, 78, 95, 111, and 126. The input index a(n+8)_II_SB2 of the ninth element a9 to the sixteenth element a16 of the second sub-block SB2 can be generated based on Equation 6 shown in Figure 6 and based on the input index an_II_SB1 of the first element a1 to the eighth element a8 and can have values ​​140, 153, 165, 176, 186, 195, 203, and 210.

[0087] The relationship between the first element a1 to the eighth element a8 of the first sub-block SB1 and the seventeenth element a17 to the twenty-first element a21 of the third sub-block SB3 corresponds to the following [Equation 7].

[0088] [Equation 7] a(n+16)_II_SB3=an_II_SB1+21×16-120-(n-1)×8

[0089] That is, the input indices a(n+16)_II_SB3 of the seventeenth element a17 to the twenty-first element a21 of the third sub-block SB3 and the input indices an_II_SB1 of the first element a1 to the eighth element a8 of the first sub-block SB1 can have the order relationship as shown in [Equation 7]. Empty (N) data can be written to the remaining areas of the third sub-block SB3, and this state is not described.

[0090] The input index a(n+16)_II_SB3 of the seventeenth element a17 to the twenty-first element a21 of the third subblock SB3 can be generated based on the input index of the first element a1 to the fifth element a5 based on [Equation 7] and can have values ​​216, 221, 225, 228, 230.

[0091] According to an exemplary embodiment, the interleaver can perform the generation of the input index of the second sub-block SB2 and the generation of the input index of the third sub-block SB3 in parallel. A detailed exemplary embodiment for this configuration will be described below with reference to FIG8A.

[0092] Referring further to Figure 7B, the input indices of the 22nd element a22 to the 29th element a29 in the fourth sub-block SB4 can have values ​​1, 22, 42, 61, 79, 95, 111, and 127. The input indices of the 30th element a30 to the 37th element a37 in the fifth sub-block SB5 can be generated based on the input indices of the 22nd element a22 to the 29th element a29, as shown in Figure 6 [Equation 6], and can have values ​​141, 154, 166, 177, 187, 196, 204, and 211.

[0093] The input indices of the thirty-eighth element a38 to the forty-second element a42 of the sixth subblock SB6 can be generated based on the input indices of the twenty-second element a22 to the twenty-sixth element a26, and can have values ​​217, 222, 226, 229, 231, based on [Equation 7].

[0094] FIG8A is a block diagram of the components of interoperator 100 according to an exemplary embodiment, and FIG8B is a diagram of the output of interoperator 100 shown in FIG8A.

[0095] Referring to Figure 8A, the interleaver 100 may include a first interleaver circuit 110, a second interleaver circuit 120, and / or an output buffer 130. Each of the first interleaver circuit 110 and the second interleaver circuit 120 can receive a codeword CW and can perform interleaverating operations on bits of the codeword CW allocated to the first interleaver circuit 110 and the second interleaver circuit 120 in parallel. For example, further referring to Figure 7A, the first interleaver circuit 110 can generate the input index of a second sub-block SB2, and the second interleaver circuit 120 can generate the input index of a third sub-block SB3 in parallel. Each of the first interleaver circuit 110 and the second interleaver circuit 120 can provide the interleaver result to the output buffer 130 in the same time interval. The output buffer 130 can output the interleaver result stored corresponding to a predetermined or alternatively desired timing as the interleaved codeword I_CW.

[0096] Referring further to FIG8B, a portion of the first interpolation result for the bits of the codeword CW corresponding to the xth sub-block SBx from the first interpolation circuit 110 and a portion of the second interpolation result for the bits of the codeword CW corresponding to the (x+1)th sub-block SB(x+1) from the second interpolation circuit 120 may be simultaneously stored in the output buffer 130. In some exemplary embodiments, depending on the size of the output buffer 130, the entire second interpolation result may be stored in the output buffer 130 simultaneously with the first interpolation result.

[0097] With this configuration and operation of the interleaver 100, block-based interleaving operations can be performed quickly and the interleaving performance can be improved.

[0098] Figure 9 is a flowchart of the block interleaving operation of the interleaver according to an exemplary embodiment.

[0099] Referring to Figure 9, in operation S300, the interleaver can generate and store the input and output indices of the sub-blocks in the reference row. In operation S310, the interleaver can use the stored input and output indices to generate the input and output indices of the sub-blocks in other rows. For example, a predetermined or alternatively desired relationship can be formed between the sub-blocks in the reference row and the sub-blocks in other rows, and by taking this relationship into account, the interleaver can generate the input indices of the sub-blocks in other rows by adding a predetermined or alternatively desired constant to the stored input indices. The interleaver can generate the output indices of the sub-blocks based on the algorithm illustrated with reference to Figure 3. In operation S320, the interleaver can perform interleaving using the generated input and output indices.

[0100] Figure 10 is a detailed diagram of the operation of the interleaver according to an exemplary embodiment. The exemplary embodiment shown in Figure 10 is based on the exemplary embodiments shown in Figures 4 and 9.

[0101] Referring to Figure 10, the interleaver can generate the input indices of the first sub-block SB1 to the third sub-block SB3 as described above with reference to Figure 7A, and can use the generated input indices of the first sub-block SB1 to the third sub-block SB3 to generate the input indices of the fourth sub-block SB4 to the sixth sub-block SB6.

[0102] According to an exemplary embodiment, the relationship between the input index of the first sub-block SB1 arranged in the first row of block BLK (FIG. 4) and the input index of the fourth sub-block SB4 arranged in the second row of block BLK is the same as that in Equation 8, wherein the fourth sub-block SB4 is adjacent to the first sub-block SB1 in the second direction.

[0103] [Equation 8] a(n+21)_II_SB4=an_II_SB1+c

[0104] The constant c can be determined based on the mutual distance between the first sub-block SB1 and the fourth sub-block SB4 in the second direction, and as shown in Figure 10, the constant c can have a value of 1. Based on this configuration, for example, the constant c can have a value of 2 in the relationship between the first sub-block SB1 and the seventh sub-block (not shown) arranged in the third row of block BLK, which is parallel to the first sub-block SB1 in the second direction.

[0105] The above relationships may also include the relationship between the second sub-block SB2 and the fifth sub-block SB5, which are arranged parallel to each other in the second direction, and the relationship between the third sub-block SB3 and the sixth sub-block SB6.

[0106] The interleaver can configure the first row as the reference row, generate input indices for the first sub-blocks SB1 to SB3 of the reference row, and store the generated input indices in internal memory. The interleaver can then use the stored input indices to generate input indices for the remaining sub-blocks, including the fourth sub-blocks SB4 to SB6.

[0107] The interleaver according to the exemplary embodiment can quickly generate the input indices of the remaining sub-blocks by performing simple calculations using the input indices of the sub-blocks of the reference row. Therefore, power consumption can be reduced or minimized, and interleaving performance can be improved.

[0108] Figure 11 is a diagram of a block BLK according to an exemplary embodiment. In the following text, patterns identical to those shown in Figure 4 are not described.

[0109] Referring to Figure 11, block BLK may further include a (p-1)th sub-block SB(p-1) and a p-th sub-block SBp. In some exemplary embodiments, p is an integer equal to or greater than 7. Due to the shape limitations of block BLK, the (p-1)th sub-block SB(p-1) and the p-th sub-block SBp may have different sizes than the first sub-block SB1 to the sixth sub-block SB6. The (p-1)th sub-block SB(p-1) and the p-th sub-block SBp may be configured to have various sizes depending on the shape of block BLK. In addition, block BLK may further include other sub-blocks (not shown) with different sizes than the first sub-block SB1 to the sixth sub-block SB6.

[0110] According to an exemplary embodiment, the interleaver can generate the input index of the (p-1)th sub-block SB(p-1) and the input index of the pth sub-block SBp based on the exemplary embodiments illustrated with reference to FIG9 and FIG10. A detailed exemplary embodiment of this state is described below with reference to FIG12.

[0111] Figure 12 is a diagram of an exemplary embodiment for generating the input index of the (p-1)th sub-block SB(p-1) shown in Figure 11.

[0112] Referring to Figure 12, the (p-1)th subblock SB(p-1) may have a length of 4 bits in the first direction and a length of 2 bits in the second direction, and may be arranged to extend from the (p-1)th row of block BLK to the pth row. The (p-1)th subblock SB(p-1) may include 8 elements am to a(m+7).

[0113] According to an exemplary embodiment, the interleaver can use the input index of the first sub-block SB1 in the reference row to generate the input index of the (p-1)th sub-block SB(p-1). For example, in the relationship between the elements am to a(m+3) of the first sub-block SB1 and the (p-1)th sub-block SB(p-1) in the (p-1)th row, the constant c in [Equation 8] shown in FIG10 may have the value p-2. Additionally, in the relationship between the elements a(m+4) to a(m+7) of the first sub-block SB1 and the (p-1)th sub-block SB(p-1) in the pth row, the constant c in [Equation 8] shown in FIG10 may have the value p-1.

[0114] Based on this relationship, the interleaver can generate the input index of the (p-1)th sub-block SB(p-1) by adding each constant to the input index of the first sub-block SB1. The interleaver can generate input indices with values ​​p-2, p+19, p+58, and p+76 corresponding to elements am to a(m+3) in the (p-1)th row, and input indices with values ​​p-1, p+20, p+59, and p+77 corresponding to elements a(m+4) to a(m+7) in the pth row. In some exemplary embodiments, the sub-block corresponding to the input index used to generate the input index of the (p-1)th sub-block SB(p-1) may not be limited to the sub-blocks of the reference row and may vary. For example, the input index of the (p-1)th sub-block SB(p-1) can be generated using the input index of a sub-block (not shown) arranged in the (p-2)th row.

[0115] The interleaver can use the same method described above to generate the input index of the p-th sub-block SBp, which has a different size from the first sub-block SB1 to the sixth sub-block SB6.

[0116] The interleaver according to the exemplary embodiment can utilize relationships between sub-blocks of different sizes and can quickly generate input indices through simple calculations. Therefore, power consumption can be reduced or minimized, and interleaving performance can be improved.

[0117] Figure 13 is a block diagram of a communication system 1000 according to an exemplary embodiment.

[0118] Referring to Figure 13, the communication system 1000 may include a terminal 1100 and a BS 1200. The terminal 1100 may include a wireless communication device and may be mobile. The terminal 1100 may communicate with the BS 1200 via a downlink channel DL and an uplink channel UL to transmit data and control information to and receive data and control information from the BS 1200.

[0119] The interleaving method according to the exemplary embodiment can be used for transmission of the physical sidelink control channel (PSCCH) of the uplink channel UL. Furthermore, when the communication system 1000 supports vehicle-to-everything (V2X) communication, the interleaving method can be used for transmission from the physical sidelink control channel (PSCCH) to another terminal (not shown). However, this is only an exemplary embodiment. The inventive concept is not limited thereto and can be applied to various other control channels.

[0120] Terminal 1100 may include multiple antennas AT, radio frequency (RF) integrated circuit 1110, baseband integrated circuit 1120, and / or processor 1130. The terminal 1100 according to the exemplary embodiment shown in FIG13 is merely an example. Terminal 1100 is not limited thereto and may include more or fewer components than those shown. Furthermore, in some exemplary embodiments, the RF integrated circuit 1110 and the baseband integrated circuit 1120 may be implemented as a single integrated circuit.

[0121] The RF integrated circuit 1110 can perform signal band conversion, signal amplification, etc., for transmitting and receiving signals via a radio channel using the plurality of antennas AT. For example, the RF integrated circuit 1110 can perform uplink conversion on the baseband signal received from the baseband integrated circuit 1120 to generate an RF band signal, can transmit the RF band signal via the antenna AT, and can perform downlink conversion on the RF band signal received via the antenna AT. For example, the RF integrated circuit 1110 may include a transmit filter, a receive filter, an amplifier, a mixer, an oscillator, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), etc. In addition, the RF integrated circuit 1110 may further include multiple RF chains (not shown) and can perform beamforming using the antenna AT. For beamforming, the RF integrated circuit 1110 can adjust the phase and amplitude of each signal transmitted and received via the antenna AT. In addition, the RF integrated circuit 1110 can perform multi-input multi-output (MIMO) operation and can receive multiple layers while performing MIMO operation.

[0122] The baseband integrated circuit 1120 can perform the conversion between the baseband signal and the bit stream according to the system's physical hierarchy standard. For example, the baseband integrated circuit 1120 can generate complex symbols by encoding and modulating the transmitted bit stream during data transmission. In addition, the baseband integrated circuit 1120 can reconstruct the received bit stream by demodulating and decoding the baseband signal provided by the RF integrated circuit 1110 during data reception.

[0123] RF integrated circuit 1110 and baseband integrated circuit 1120 can transmit and receive signals as described above. RF integrated circuit 1110 and baseband integrated circuit 1120 can also be referred to as a transmitter, receiver, transceiver, or communicator. Furthermore, at least one of RF integrated circuit 1110 and baseband integrated circuit 1120 may include multiple communication modules for supporting various wireless access technologies. Additionally, at least one of RF integrated circuit 1110 and baseband integrated circuit 1120 may include different communication modules for processing signals in different frequency bands. For example, different wireless access technologies may include NR technology, LTE technology, etc. Furthermore, different frequency bands may include ultra-high frequency bands, millimeter bands, etc. Terminal 1100 can communicate with BS 1200 using RF integrated circuit 1110 and baseband integrated circuit 1120.

[0124] Processor 1130 controls the general operation of terminal 1100. According to an exemplary embodiment, processor 1130 may include interpolator 1132 that performs interpolation according to an exemplary embodiment of the present invention. Interpolator 1132 may generate input and output indices for sub-blocks by performing simple calculations using the order relationships between sub-blocks of a block. Interpolator 1132 may configure the size of the sub-blocks to satisfy the order relationships.

[0125] According to an exemplary embodiment, since the hardware of the interleaver 1132 is simplified and the power consumption is reduced or minimized, the burden on the processor 1130 due to interleavering can be reduced and the performance of the processor 1130 can be improved.

[0126] The processor 1130 can encode a predetermined or alternatively desired control channel, interleave the codewords generated as a result of the encoding using the interleaver 1132, and then transmit the interleaved codewords to the BS 1200 or another terminal (not shown) using the RF integrated circuit 1110 and the baseband integrated circuit 1120.

[0127] Figure 14 is a block diagram of a memory system 2000 and a host system 2300 according to an exemplary embodiment. As shown in Figure 14, the memory system 2000 and the host system 2300 can communicate with each other via an interface 2400, and the memory system 2000 may include a memory controller 2100 and a memory device 2200.

[0128] Interface 2400 may use electrical signals and / or optical signals, and may include, for example, but not limited to, Serial Advanced Technology Attachment (SATA) interfaces, SATA Express (SATAe) interfaces, Serial Attached Small Computer System (SAS) interfaces, Small Computer System Interface (SCSI) interfaces, Universal Serial Bus (USB) interfaces, or combinations thereof. Host system 2300 and memory controller 2100 may include a serializer / deserializer (SerDes) for serial communication.

[0129] In some exemplary embodiments, the memory system 2000 may be removably coupled to the host system 2300 for communication with the host system 2300. The memory device 2200 may include volatile or non-volatile memory, and the memory system 2000 may also be referred to as a storage system. For example, the memory system 2000 may be implemented as a solid-state drive or solid-state disk (SSD), embedded SSD (eSSD), multimedia card (MMC), embedded MMC (eMMC), etc., but is not limited thereto. The memory controller 2100 may control the memory device 2200 in response to requests received from the host system 2300 via the interface 2400.

[0130] An interleaving device (not shown) performing interleaving according to an exemplary embodiment of the present invention may be implemented in the form of an ADC included in each of the memory controller 2100, the memory device 2200, and the host system 2300. For example, the memory controller 2100, the memory device 2200, and the host system 2300 may use the interleaving device according to an exemplary embodiment of the present invention to interleave predetermined or alternatively desired codewords or predetermined or alternatively desired data including ECC, and may transmit the interleaved codewords or data.

[0131] Figure 15 is a block diagram of a processor 3000 according to an exemplary embodiment. In some exemplary embodiments, the interleaver 100 shown in Figure 1 may be included in the processor 3000 shown in Figure 15.

[0132] As shown in Figure 15, the processor 3000 may include an application-specific integrated circuit (ASIC) 3051, an application-specific instruction set processor (ASIP) 3053, memory 3055, a main processor 3057, and main memory 3059. In some exemplary embodiments, two or more of the ASIC 3051, ASIP 3053, and main processor 3057 may communicate with each other. Furthermore, in some exemplary embodiments, at least two of the ASIC 3051, ASIP 3053, memory 3055, main processor 3057, and main memory 3059 may be embedded in a single semiconductor wafer.

[0133] ASIP 3053 may be a customized integrated circuit for a specific purpose, supporting and executing application-specific instruction sets. Memory 3055 may communicate with ASIP 3053, may be a non-temporary storage device, and may include the plurality of instructions executed by ASIP 3053. For example, memory 3055 may include, but is not limited to, predetermined or alternatively desired tangible memory (accessible by ASIP 3053), such as random-access memory (RAM), read-only memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof. In some exemplary embodiments, memory 3055 may store an input index for a reference subblock, which is used to generate input indices for other subblocks.

[0134] The main processor 3057 can control the processor 3000 by executing multiple instructions. For example, the main processor 3057 can control the ASIC 3051 and ASIP 3053. The main memory 3059 can communicate with the main processor 3057 and may include predetermined or alternatively desired tangible memory accessible by the main processor 3057. In some exemplary embodiments, the main memory 3059 may include a non-temporary storage device and may store multiple instructions executed by the main processor 3057.

[0135] Interleaving according to an exemplary embodiment can be performed by at least one of the components included in the processor 3000 shown in FIG. 15. For example, one or more operations of the interleaver 100 shown in FIG. 1 can be implemented by the plurality of instructions stored in memory 3055. ASIP 3053 can perform the one or more interleaving operations by executing the plurality of instructions stored in memory 3055. In some exemplary embodiments, at least one of the interleaving operations can be performed by a hardware block designed by logic synthesis or the like. In some exemplary embodiments, at least one of the interleaving operations can be implemented by the plurality of instructions stored in main memory 3059. Main processor 3057 can perform at least one of the interleaving operations by executing the plurality of instructions stored in main memory 3059.

[0136] One or more of the elements or functional blocks disclosed above may be included or implemented in, for example, one or more of the following processing circuitry systems: hardware, including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0137] Although the concept of the invention has been specifically shown and illustrated with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the following claims.

[0138] 1: Electronic System

[0139] 10: Transmitter

[0140] 12: Encoder

[0141] 20: Receiver

[0142] 30: Channel

[0143] 100, 1132: Interchange

[0144] 110: First interleaving circuit

[0145] 120: Second interleaving circuit

[0146] 130: Output buffer

[0147] 1000: Communication System

[0148] 1100: Terminal

[0149] 1110: Radio Frequency (RF) Integrated Circuits

[0150] 1120: Fundamental frequency integrated circuit

[0151] 1130, 3000: Processors

[0152] 1200: Base Station (BS)

[0153] 2000: Memory System

[0154] 2100: Memory controller

[0155] 2200: Memory Device

[0156] 2300: Host System

[0157] 2400: Interface

[0158] 3051: Application-Specific Integrated Circuit (ASIC)

[0159] 3053: Application Special Set Instruction Processor (ASIP)

[0160] 3055: Memory

[0161] 3057: Main Processor

[0162] 3059: Main Memory

[0163] AT: Antenna

[0164] a1: First element

[0165] a2: Second element

[0166] a3: Third Element

[0167] a4: The fourth element

[0168] a5: The Fifth Element

[0169] a6: The Sixth Element

[0170] a7: The Seventh Element

[0171] a8: The Eighth Element

[0172] a9: The Ninth Element

[0173] a10: The Tenth Element

[0174] a11: The Eleventh Element

[0175] a12: The twelfth element

[0176] a13: The Thirteenth Element

[0177] a14: The Fourteenth Element

[0178] a15: The Fifteenth Element

[0179] a16: The Sixteenth Element

[0180] a17: The Seventeenth Element

[0181] a18: The Eighteenth Element

[0182] a19: The Nineteenth Element

[0183] a20: The twentieth element

[0184] a21: The Twenty-First Element

[0185] a22: The Twenty-Second Element

[0186] a23: The Twenty-Third Element

[0187] a24: The Twenty-Fourth Element

[0188] a25: The Twenty-Fifth Element

[0189] a26: The Twenty-Sixth Element

[0190] a27: The Twenty-Seventh Element

[0191] a28: The Twenty-Eighth Element

[0192] a29: The Twenty-Ninth Element

[0193] a30: The Thirtieth Element

[0194] a31: The Thirty-First Element

[0195] a32: The Thirty-Second Element

[0196] a33: The Thirty-Third Element

[0197] a34: The Thirty-Fourth Element

[0198] a35: The Thirty-Fifth Element

[0199] a36: The Thirty-Sixth Element

[0200] a37: The Thirty-Seventh Element

[0201] a38: The Thirty-Eighth Element

[0202] a39: The Thirty-Ninth Element

[0203] a40: The Fortieth Element

[0204] a41: The Forty-First Element

[0205] a42: The Forty-Second Element

[0206] am, a(m+1), a(m+2), a(m+3), a(m+4), a(m+5), a(m+6), a(m+7): elements

[0207] BLK: Block

[0208] CW: Code

[0209] D1: First Direction

[0210] D2: Second Direction

[0211] DL: Downlink Channel

[0212] I_CW: Interleaved codeword

[0213] N: empty data

[0214] P1: Part 1

[0215] P2: Part Two

[0216] P3: Part Three

[0217] S100, S110, S120, S130, S200, S210, S220, S230, S240, S250, S300, S310, S320: Operation

[0218] SB1: First sub-block / sub-block

[0219] SB2: Second sub-block / sub-block

[0220] SB3: Third sub-block / sub-block

[0221] SB4: Fourth sub-block / sub-block

[0222] SB5: Fifth sub-block / sub-block

[0223] SB6: Sixth Sub-block / Sub-block

[0224] SBp: p-th sub-block

[0225] SB(p-1): The (p-1)th sub-block

[0226] SBx: The xth sub-block

[0227] SB(x+1): The (x+1)th sub-block

[0228] SD: Source Material

[0229] T, T-1, T1, T2: Length

[0230] UL: Uplink Channel

Claims

1. An apparatus for performing block interleaving, comprising: An encoder is configured to generate codewords consisting of multiple bits by encoding source data; And an interleaver configured to perform block-based interleaving of the codeword comprising a plurality of sub-blocks, wherein the interleaver is configured to: generate a first reference input index of a first reference sub-block among the plurality of sub-blocks; generate a first input index of a first sub-block among the plurality of sub-blocks based on the first reference input index, the first sub-block being arranged adjacent to the first reference sub-block in a first direction; and store bits corresponding to the first reference sub-block and the first sub-block in internal memory according to the first reference input index and the first input index, respectively, wherein the blocks have the shape of right-angled isosceles triangles, and wherein the interleaver is further configured to generate the first input index based on the first reference input index by performing addition, subtraction, and bit shifting operations based on the order relationship between the first reference sub-block and the first sub-block.

2. The device as claimed in claim 1, wherein the block has a shape in which the length of the side varies with the column and row.

3. The device as claimed in claim 1, wherein the first reference sub-block and the first sub-block have a length of (n is an integer equal to or greater than 1) bits in the first direction and a length of 1 bit in a second direction intersecting the first direction.

4. The device as claimed in claim 1, wherein the interpolator is further configured to generate an output index of the first reference subblock and an output index of the first subblock, and output the bits corresponding to the first reference subblock and the first subblock from the internal memory according to the output index.

5. The device as claimed in claim 1, wherein the interpolator is further configured to: generate a second reference input index for a second reference sub-block among the plurality of sub-blocks, the second reference sub-block being adjacent to the first reference sub-block in a second direction intersecting the first direction; generate a second input index for a second sub-block among the plurality of sub-blocks based on the second reference input index, the second sub-block being arranged parallel to the second reference sub-block in the first direction; and store bits corresponding to the second reference sub-block and the second sub-block in the internal memory according to the second reference input index and the second input index, respectively.

6. The device as claimed in claim 1, wherein the interpolator is further configured to generate a second input index of a second sub-block among the plurality of sub-blocks based on the first reference input index, the second sub-block being arranged adjacent to the first sub-block in the first direction.

7. The device as claimed in claim 6, wherein the interleaver is further configured to perform the generation of the first input index and the generation of the second input index in parallel.

8. The device as claimed in claim 7 further includes an output buffer, wherein the interpolator is further configured to store the interpolation result for the first sub-block and the interpolation result for the second sub-block in the same time segment in the output buffer.

9. The device as claimed in claim 1, wherein the interpolator is further configured to use the first input index to generate a second input index for a second sub-block, the second sub-block being arranged adjacent to the first sub-block in a second direction intersecting the first direction.

10. The device as claimed in claim 7, wherein the interpolator is further configured to generate the second input index by adding a constant corresponding to the distance between the first sub-block and the second sub-block to the first input index.

11. A block-based interleaving method, comprising multiple sub-blocks and performed on codewords consisting of multiple bits, the method comprising: Generate a first reference input index for the first reference sub-block among the plurality of sub-blocks; A first input index is generated for a first sub-block among the plurality of sub-blocks based on the first reference input index, the first sub-block being arranged adjacent to the first reference sub-block in a first direction; and bits corresponding to the first reference sub-block and the first sub-block are stored, wherein generating the first input index includes generating the first input index based on the first reference input index by performing addition, subtraction and bit shifting operations based on the order relationship between the first reference sub-block and the first sub-block.

12. The block-based interleaving method as described in claim 11 further includes using the first input index to generate a second input index for a second sub-block, the second sub-block being arranged adjacent to the first sub-block in a second direction intersecting the first direction.

13. An apparatus for performing block interleaving, comprising: Memory; processor, configured to encode source data and generate codewords consisting of multiple bits; The processor performs block-based interleaving of the codeword, comprising multiple sub-blocks; and an integrated circuit configured to output data comprising the interleaved codeword via a predetermined or alternatively desired channel, wherein the processor is further configured to: generate a first input index for a first sub-block corresponding to a first row based on the sequential relationship between first sub-blocks among the multiple sub-blocks; store bits corresponding to the first sub-block in the memory; and output the bits stored in the memory according to a first output index of the first sub-block, wherein the processor is further configured to generate the first input index based on a reference input index of a reference sub-block among the first sub-blocks by addition, subtraction, and shifting.

14. The device as claimed in claim 13, wherein the processor is further configured to use the first input index to generate a second input index for a second sub-block among the plurality of sub-blocks, the second sub-block corresponding to the second row.

15. The device as claimed in claim 14, wherein the processor is further configured to generate the second input index by adding a constant corresponding to the distance difference in the column direction between the first sub-block and the second sub-block to the first input index.

16. The device as claimed in claim 13, wherein the first sub-block has a length of one bit in the row direction (n is an integer equal to or greater than 1) and a length of one bit in the column direction.

Images