Multi-tier semiconductor structure and method of fabricating the same

Abstract

This disclosure provides a multilayer semiconductor structure. For example, the multilayer semiconductor structure may include: a first semiconductor device layer containing a first semiconductor device; a first signal wiring structure formed above the first semiconductor device layer and electrically connected to the first semiconductor device layer; an insulating layer formed above the first signal wiring structure; a second semiconductor device layer formed above the insulating layer, containing a second semiconductor device; a second signal wiring structure formed above the second semiconductor device layer and electrically connected to the second semiconductor device layer; and an interlayer window formed vertically through the insulating layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device layer, the second semiconductor device layer, and the interlayer window may be formed in a single-crystal configuration.

Description

Technical Field

[0001] [Cross-reference to related applications] This application claims priority under the patent law to the following: U.S. Provisional Patent Application No. 63 / 151,166, filed February 19, 2021, entitled "Inverted top-tier FET for multi-tier gate-on-gate 3Di"; and U.S. Non-Provisional Patent Application No. 17 / 542,024, filed December 3, 2021, entitled "Inverted top-tier FET for multi-tier gate-on-gate 3Di", the entire contents of which are incorporated herein by reference.

[0002] This disclosure is generally related to microelectronic components including semiconductor devices, transistors, and integrated circuits, including microfabrication methods. Prior Technology

[0003] In the fabrication of semiconductor devices (especially at the microscale), various manufacturing processes are performed, such as film deposition, photomask etching, patterning, material etching and removal, and doping. These processes are repeatedly performed to form the desired semiconductor device device on a substrate. Historically, in the case of microfabrication, transistors were produced in a plane with wiring / metallization formed on the active element plane, and thus characterized as 2D fabrication or two-dimensional (2D) circuits. Miniaturization efforts have greatly increased the number of transistors per unit area in 2D circuits, allowing the integration of heterogeneous functional circuits (such as logic and memory circuits) on the same semiconductor substrate. However, as miniaturization has entered the single-nanometer semiconductor device manufacturing node, 2D miniaturization efforts have encountered greater challenges. Semiconductor device manufacturers have shown a desire for three-dimensional (3D) semiconductor circuits, in which multiple transistors are stacked on top of each other as another method for further miniaturization of integrated circuits (ICs). Summary of the Invention

[0004] This disclosure provides a multilayer semiconductor structure. For example, the multilayer semiconductor structure may include: a first semiconductor device layer, comprising a first semiconductor device; a first signal wiring structure, formed above the first semiconductor device layer and electrically connected to the first semiconductor device layer; an insulating layer, formed above the first signal wiring structure; in one embodiment, the insulating layer may include a silicon-on-insulator (SoI) layer; a second semiconductor device layer, formed above the insulating layer, comprising a second semiconductor device; a second signal wiring structure, formed above the second semiconductor device layer and electrically connected to the second semiconductor device layer; and an interlayer window, formed vertically through the insulating layer, electrically connecting the second signal wiring structure to the first signal wiring structure. In one embodiment, the first semiconductor device layer, the second semiconductor device layer, and the interlayer window may be formed in a single-crystal manner.

[0005] For example, the interlayer window may be formed in a diffusion interruption region that vertically isolates adjacent second semiconductor devices. As another example, the second semiconductor device layer may include a pseudo-polysilicon, and the interlayer window may be aligned with the pseudo-polysilicon.

[0006] In one embodiment, the multilayer semiconductor structure further includes a substrate, wherein the first semiconductor device layer may be formed on the substrate. For example, the multilayer semiconductor structure may further include a first power rail embedded in the substrate and electrically connected to the first semiconductor device layer. As another example, the multilayer semiconductor structure may further include a second power rail formed on the second semiconductor device layer and electrically connected to the second semiconductor device layer.

[0007] In one embodiment, the first semiconductor device may be stacked perpendicularly to each other, and / or the second semiconductor device may be stacked perpendicularly to each other. For example, the second semiconductor device may include a field-effect transistor (FET).

[0008] In one embodiment, the multilayer semiconductor structure may further include a contact that is vertically formed to electrically connect the second semiconductor device layer to the second signal wiring structure. In another embodiment, the multilayer semiconductor structure may further include a contact that is vertically formed through the insulating layer to electrically connect the second semiconductor device layer to the first signal wiring structure. For example, the contact may include a gate contact that electrically connects a gate region of one of the second semiconductor devices in the second semiconductor device layer to the first signal wiring structure. As another example, the contact may include a source / drain contact that electrically connects a source / drain region of one of the second semiconductor devices in the second semiconductor device layer to the first signal wiring structure.

[0009] This disclosure further provides a method for fabricating a multilayer semiconductor structure. For example, the method may include: forming a first semiconductor device layer, the first semiconductor device layer including a first semiconductor device. The method may include forming a first signal wiring structure over the first semiconductor device layer and electrically connecting the first signal wiring structure to the first semiconductor device layer, and forming an insulating layer over the first signal wiring structure. In one embodiment, the insulating layer may include a SoI layer. The method may further include forming a second semiconductor device layer over the insulating layer, the second semiconductor device layer including a second semiconductor device. The method may further include forming a second signal wiring structure over the second semiconductor device layer and electrically connecting the second signal wiring structure to the second semiconductor device layer, and forming an interlayer window perpendicularly through the insulating layer to electrically connect the second signal wiring structure to the first signal wiring structure. In one embodiment, the first semiconductor device layer, the second semiconductor device layer, and the interlayer window are formed in a single-crystal configuration.

[0010] In one embodiment, the step of forming an interlayer window may include: forming an interlayer window in a diffusion interruption region that vertically isolates the adjacent layers of the second semiconductor device. For example, the second semiconductor device layer may include a pseudo-polysilicon, and the interlayer window is aligned with the pseudo-polysilicon.

[0011] In one embodiment, the method may further include forming a contact perpendicularly through the insulating layer to electrically connect the second semiconductor device layer to the first signal wiring structure.

[0012] It should be understood that this "Summary of the Invention" section does not specify all embodiments and / or less novel aspects of the present disclosure or the scope of the invention claims. Rather, this "Summary of the Invention" only provides a preliminary discussion of different embodiments and novel aspects compared to conventional technology. For additional details and / or possible perspectives regarding the present disclosure and embodiments, please refer to the "Implementation Methods" section below, which discusses them in further detail, and the corresponding illustrations of the present disclosure. Simple Explanation of the Diagram

[0013] Various embodiments of this disclosure, presented as examples, will be described in detail with reference to the accompanying drawings, wherein like numbers refer to like elements, and wherein:

[0014] Figure 1 shows a simplified cross-sectional view of the semiconductor segment;

[0015] Figure 2 shows a semiconductor structure comprising two semiconductor segments fabricated in face-to-face 3D integrated circuit (3Di);

[0016] Figure 3 shows a semiconductor structure comprising two semiconductor segments fabricated face-to-face using 3Di.

[0017] Figure 4 shows a semiconductor structure comprising two semiconductor segments manufactured using a sequential 3Di process;

[0018] Figure 5 shows a semiconductor structure comprising two semiconductor segments fabricated using a sequential 3Di process;

[0019] Figure 6a shows a cross-sectional view of an exemplary multilayer semiconductor structure 600 of Figure 6b according to some embodiments of the present disclosure;

[0020] Figure 6b shows a perspective view of a semiconductor structure according to some embodiments of the present disclosure;

[0021] Figures 7a and 7b show a top view and a bottom view (or layout diagram) of an exemplary multilayer semiconductor structure of Figure 7c according to some embodiments of the present disclosure;

[0022] Figure 7c shows a perspective view of a semiconductor structure according to several embodiments of the present disclosure;

[0023] Figures 8a to 8d respectively show cross-sectional views of the semiconductor devices shown in Figures 7a to 7c along lines 8a-8a', 8b-8b', and 8d-8d' of Figures 7a and 7b according to several embodiments of the present disclosure; and

[0024] Figure 9 is a flowchart illustrating an exemplary method for manufacturing a multilayer semiconductor structure according to several embodiments of the present disclosure. Implementation

[0025] The term "illustrative" is used herein to mean "as an example, instance, or illustration." Any embodiment of construction, process, design, technology, etc., specified herein as illustrative is not necessarily considered preferred or advantageous over other such embodiments. Specific qualities or suitability of examples indicated herein as illustrative are neither specified nor inferred.

[0026] Furthermore, spatial relative terms such as "below," "below," "down," "above," "upper," and similar terms may be used herein for ease of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. These spatial relative terms are intended to encompass different orientations of the device (or apparatus) in use or operation, other than those shown in the figures. The device (or apparatus) may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative narrators used herein may be interpreted similarly accordingly.

[0027] The order in which the different steps discussed herein are presented has been shown for clarity. Generally, these steps can be performed in any suitable order. Furthermore, although each of the different features, techniques, configurations, etc., may be discussed in different places within this disclosure, each of these concepts can be implemented independently of or in combination with each other. Therefore, the invention can be practiced or examined in many different ways.

[0028] As described in previous technical sections, semiconductor device manufacturers have shown a strong desire for three-dimensional (3D) semiconductor circuits, in which multiple transistors are stacked on top of each other as an alternative to traditional 2D miniaturization for ICs. 3D integrated circuits (3Di), the vertical stacking of multiple semiconductor devices, aim to overcome the limitations of 2D miniaturization by increasing transistor density in terms of volume rather than area. While device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, its application to random logic design systems is fundamentally more challenging. 3D integrated circuits for logic chips (such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), FPGAs (Field Programmable Gate Arrays), and SoCs (System-on-a-Chip)) are primarily pursued in two ways: heterogeneous stacking and more homogeneous stacking.

[0029] Heterogeneous stacking utilizes wafer / wafer stacking and silicon layer window (TSV) technology, as revealed in process architectures for 3D sequential stacking of planes and FinFET technology (Anne VanDooren, presented at IMEC PTW 2018, Spring). For example, in this 3D stacking approach, two wafers can be designed and manufactured to be optimized for different specific tasks; for instance, one may contain chemical and biological sensors, while the other may contain nanodevices and microelectromechanical systems (MEMS) devices. TSVs can be used to integrate these two different functional wafers to build a stacked SoC. Detailed information on heterogeneous stacking is available in: Heterogeneous Stacking Blueprint, 2019 Edition, published October 2019 at http: / / eps.ieee.org / hir.

[0030] Homogeneous stacking uses wafer bonding processes to overcome the density loss associated with micron-sized TSVs used in heterogeneous stacking. For example, a substrate wafer can be processed to form devices such as n-type metal-oxide-semiconductor (nMOS) and p-type MOS (pMOS), as well as several layers of metallization / wiring, and then a thinned silicon-on-insulator (SOI) layer can be positioned on top of the substrate wafer and bonded to the top of the substrate wafer by oxide-oxide bonds to form a complete structure.

[0031] Figure 1 shows a simplified cross-sectional view of semiconductor segment 100. A substrate (or wafer) 110, such as a silicon or SiGe substrate, may be provided. A semiconductor device layer (or semiconductor device layer) 150 may be disposed on the front side 110a of the substrate 110. For example, the semiconductor device layer 150 may include one or more semiconductor devices, such as field-effect transistors (FETs), which form functional circuits, such as logic circuits or memory circuits. Furthermore, these FETs may be n-type or p-type FETs arranged along the front side 110a or stacked perpendicularly to each other along the thickness direction of the substrate 110.

[0032] One or more power rails 120 may be embedded in the substrate 110 and electrically connected to the semiconductor device layer 150 via a TSV (e.g., nanoscale) 140 to provide, for example, low-voltage (Vss) and high-voltage (VDD) power delivery from the PDN 130 to the semiconductor device layer 150. The PDN 130 may be formed on the back side 110b of the substrate 110.

[0033] A signal wiring structure (or wiring layer) 160 may be disposed above the semiconductor device layer 150 and used to electrically connect the semiconductor device layer 150 to, for example, another semiconductor device layer (not shown) disposed above the wiring layer 160. The wiring layer 160 may include one or more wiring layers (or wiring hierarchy), each wiring layer including one or more wiring tracks extending along the front side 110a of the substrate 110. Typically, the wiring tracks in a wiring layer are arranged in a direction perpendicular to the direction of the wiring tracks in adjacent wiring layers. For example, the wiring layer 160 may include three wiring layers 1601, 1602, and 1603, and wiring layer 1601 may include seven wiring tracks 1601a to 1601g, which extend in a direction perpendicular to the wiring tracks in wiring layer 1602 along the front side 110a of the substrate 110 (e.g., perpendicular to the plane of the drawing page).

[0034] Figure 2 illustrates a semiconductor structure 200 comprising two semiconductor segments fabricated in face-to-face 3D integrated circuit (3Di), i.e., a multilayer stack of semiconductor devices with high-density interlayer wiring for efficient logic-to-memory or logic-to-logic connections. Figure 2 illustrates the end result pursued by this disclosure. The two semiconductor segments can be constructed separately, and each semiconductor segment may include a power distribution element, a semiconductor device (such as a FET), and a signal wiring structure. For example, semiconductor structure 200 may include the two semiconductor segments 100 shown in Figure 1, stacked perpendicularly to each other by inverting one, and each semiconductor segment 100 may include a power distribution element (e.g., power rail 120, PDN 130, and TSV 140), a semiconductor device (e.g., semiconductor device layer 150), and a signal wiring structure (e.g., signal wiring structure 160). In face-to-face 3Di fabrication, the two separately constructed semiconductor segments 100 are carefully aligned with each other and joined face-to-face at a bonding location (not shown). Typically, one of the semiconductor segments 100 may include a TSV leading to a bump (not shown) disposed on top of the semiconductor segment 100 for connecting the semiconductor structure 200 to its package, as detailed here: https: / / spectrum.ieee.org / tech-talk / semiconductors / processors / globalfoundries-arm-close-in-on-3d-chip-integration.

[0035] Figure 3 illustrates a semiconductor structure 300 comprising two semiconductor segments fabricated using face-to-face 3Di. It can be seen that face-to-face bonding may require relatively high (or thick) wire stacks (i.e., a large number of wiring layers) to gradually increase the wiring pitch to the larger value required to meet the coverage requirements of face-to-face bonding (e.g., 12 wiring layers fan out to a 1 μm pitch). In the process, this gradual expansion results in a significant increase in usable area, which defeats the initial purpose of face-to-face 3Di in terms of density gain. Therefore, this face-to-face 3Di approach is not a true single-crystal integrated circuit because independently processed wafers or wafer segments are stacked on top of each other, and it does not provide a true miniaturization solution for semiconductor manufacturing.

[0036] To achieve coverage tolerance compatible with dense interlayer wiring, sequential 3Di (also known by some as monocrystalline 3Di) is required.

[0037] Figure 4 illustrates a semiconductor structure 400 comprising two semiconductor segments fabricated using a sequential 3Di process. In a sequential 3Di process, a complete bottom layer 410 (which may resemble semiconductor segment 100) can be built initially. Then, a silicon-on-insulator (SoI) layer 490 can be bonded to the top of the bottom layer 410. Finally, a top layer 420 can be built on the SoI layer 490, which may also include power dividers, semiconductor devices (e.g., FETs), and signal wiring structures. For example, in the sequential 3Di process CoolCube™ pioneered by CEA-Leti (more information can be found at https: / / en.wikipedia.org / wiki / Three-dimensional_integrated_circuit), the complete bottom layer 410 can be built under a thermal budget of up to 1000 °C, followed by the bonding of the SoI layer 490 to the top of the bottom layer 410, and finally, the top layer 420 can be built on top of the SoI layer 490 under a different thermal budget (far below 1000 °C, e.g., 500 °C). This lower thermal budget ensures that the performance of the bottom layer 410 and the inherent performance of the top layer 420 are not compromised during the fabrication of the top layer 420. A key advantage of this continuous 3Di process is the near-perfect alignment between the top layer 420 and the existing bottom layer 410. This can be achieved through lithography alignment of the thinned SoI layer 490.

[0038] Figure 5 illustrates a semiconductor structure 500 comprising two semiconductor segments fabricated using a sequential 3Di process, such as the bottom layer 410 and top layer 420 shown in Figure 4. As illustrated, a challenge in sequential 3Di processes is the interconnection between the top layer 420 and the bottom layer 410, such as 510 and 520. For example, laterally connecting top layer signals to interlayer perforation windows would result in space blockage on top layer 420 and a reduction in achievable device density. Therefore, interconnection density directly competes with the device density of top layer 420.

[0039] This disclosure relates to dense 3Di, particularly gate-on-gate (GoG) 3Di, and more specifically to GoG 3Di implemented in sequential (also known as single-crystal) 3Di with dense nanoscale connectivity (as opposed to micrometer-scale connectivity that can be achieved using face-to-face bonding). The embodiments described herein can also be applied to inverted transistor architectures configured to utilize the dense connectivity in sequential 3Di. This is beneficial because the semiconductor industry is shifting towards 3Di, and the terminology is becoming more widely known.

[0040] The techniques described in this paper include a top semiconductor device layer and a standard cell architecture that achieves dense interlayer connectivity by using a combination of bottom contacts and a single-crystal interlayer window (MIV) that passes through the diffusion interruption region to route all pin contacts to a wiring layer below the top semiconductor device layer, while maintaining a dense top semiconductor device layer placement.

[0041] Figure 6a shows a cross-sectional view of an exemplary multilayer semiconductor structure 600, while Figure 6b is a perspective view showing only the top layer of the semiconductor structure 600 according to some embodiments of the present disclosure. In one embodiment, the semiconductor structure 600 may include a substrate 610 (or wafer) (not visible in Figure 6b). For example, the substrate 610 may be a silicon or SiGe substrate. A first semiconductor device layer 651 may be disposed on the front side 610a of the substrate 610. For example, the first semiconductor device layer 651 may include one or more semiconductor devices, such as field-effect transistors (FETs), forming functional circuitry (e.g., logic circuitry or memory circuitry). Furthermore, these FETs may be n-type or p-type FETs (e.g., NMOS and PMOS) arranged along the front side 610a or stacked perpendicularly to each other along the thickness direction of the substrate 610.

[0042] One or more first power rails 621 may be embedded in the substrate 610 and electrically connected to the first semiconductor device layer 651 via a first TSV (e.g., nanometer-scale) 641 to provide low-voltage (Vss) and high-voltage (VDD) power delivery, for example, from the first PDN 631 to the first semiconductor device layer 651. The first PDN 631 may be formed on the back side 610b of the substrate 610.

[0043] A first signal wiring structure (or first wiring layer) 661 may be disposed above the first semiconductor device layer 651 and is used to electrically connect the first semiconductor device layer 651 to, for example, another semiconductor device layer (e.g., a second semiconductor device layer 652) disposed above the first wiring layer 661, or another signal wiring structure (e.g., a second signal wiring structure (or second wiring layer) 662). Similar to the wiring layer 160 shown in FIG1, the first wiring layer 661 may further include one or more wiring layers (or wiring hierarchy), each wiring layer including one or more wiring tracks extending along the front side 610a of the substrate 610. For example, the first wiring layer 661 may include five wiring layers, while the topmost, middle, and bottommost layers may include seven, six, and seven wiring tracks, respectively. Typically, the wiring tracks in a wiring layer will extend in a direction perpendicular to the direction of the wiring tracks in adjacent wiring layers. For example, the wiring track in the top wiring layer can extend in a direction (e.g., perpendicular to the plane of the drawing page) that is perpendicular to the direction of the wiring track in the wiring layer directly below the top wiring layer along the front side 610a of the substrate 610.

[0044] An insulating layer (or SoI layer) 690 (indicated by an arrow but not shown for simplicity) may be formed on top of and bonded to the top of the first wiring layer 661. For example, the insulating layer 690 may comprise a thermally oxidized silicon (SiO2) layer.

[0045] A second semiconductor device layer 652 may be deposited and formed over the front side 690a of an insulating layer (or SoI layer) 690. For example, the second semiconductor device layer 652 may include one or more semiconductor devices, such as FETs, forming functional circuitry, such as logic circuitry or memory circuitry. Furthermore, these FETs may be n-type or p-type FETs arranged along the front side 690a of the insulating layer 690 or stacked perpendicularly to each other along the thickness direction of the insulating layer 690. For example, these FETs may form standard cells, such as XOR or NAND logic cells, and include a plurality of lower p-type FETs and a plurality of upper n-type FETs stacked perpendicularly above the lower p-type FETs to form complementary FETs (CFETs). Adjacent CFETs may be isolated by a diffusion interruption region 653 (indicated by an arrow but not shown for simplicity), which provides space through which a single-crystal interlayer via (MIV) 670 (described later) may pass. For example, the diffusion interruption region 653 may include a double diffusion interruption (DDB) or a single diffusion interruption (SDB). As another example, these FETs can be gate-all-around (GAA) or GAA nanosheet (GAA NS) FETs, which have a source / drain region S / D, a gate region G, and a channel (or nanochannel) region CH entirely surrounded by the gate region G. Note that for convenience, the description here focuses on CFET and GAA devices, but it is understood that the techniques described here can be applied to other 3D device architectures.

[0046] A second signal wiring structure (or second wiring layer) 662 may be disposed above the second semiconductor device layer 652 and used to electrically connect the second semiconductor device layer 652 to, for example, another semiconductor device layer (e.g., the first semiconductor device layer 651) and another signal wiring structure (e.g., the first signal wiring structure 661). Similar to the wiring layer 160 shown in FIG1, the second wiring layer 662 may include one or more wiring layers (or wiring levels), each wiring layer including one or more wiring tracks extending along the front side 690a of the insulating layer 690. For example, the second wiring layer 662 may include a wiring layer, and the wiring layer may include two wiring tracks 662a and 662b.

[0047] One or more second power rails 622 may be formed above the second semiconductor device layer 652 and electrically connected to the second semiconductor device layer 652 via a second TSV (e.g., nanometer-scale) 642 to provide low-voltage (Vss) and high-voltage (VDD) power delivery from the second PDN 632 to the second semiconductor device layer 652, for example. Therefore, the second semiconductor device layer 652 may include an inverted top-layer FET of an exemplary multilayer semiconductor structure 600.

[0048] One or more single-crystal interlayer vias (MIVs) 670 can be formed to electrically connect the second wiring layer 662 to the first wiring layer 661. For example, the MIV 670 can be aligned with a dummy polysilicon and formed vertically through the diffusion interruption region 653 and the insulating layer 690 to electrically connect the second wiring layer 662 to the first wiring layer 661 without laterally transmitting the top-layer signal to the interlayer via.

[0049] In addition, one or more contacts may be formed to electrically connect the second semiconductor device layer 652 to the first wiring layer 661. For example, the contacts may include one or more bottom gate contacts 680, which are formed vertically through the insulating layer 690 to electrically connect the gate region G of the lower FET of the second semiconductor device layer 652 to the outside (e.g., the first wiring layer 661).

[0050] As illustrated in the example of Figure 6b, the top layer of semiconductor structure 600 is shown, illustrating a wiring layer above the device plane (e.g., a second wiring layer 662) and another wiring layer below the device plane (e.g., a first wiring layer 661). This wiring layer (first wiring layer 661) represents the top of the bottom layer of semiconductor structure 600. These two layers are represented in Figures 7a and 7b as a top view (or layout schematic) of the illustrative top layer semiconductor structure 700 of Figure 7c, which is a perspective view of semiconductor structure 700 according to some embodiments of this disclosure. In one embodiment, semiconductor structure 700 may include first to third gate-on-gate logic units 701 to 703, each logic unit including top and bottom semiconductor device layers TP and BM. For example, the top and bottom semiconductor device layers TP and BM may respectively include a plurality of upper n-type FETs and a lower p-type FETs of the second semiconductor device layer 652 of semiconductor structure 600. Each of the top and bottom semiconductor device layers TP and BM may include a plurality of source / drain (S / D) rails, arranged alternately with a plurality of gate (G) rails to form a plurality of FETs. These FETs can be p-type FETs or n-type FETs. For example, the FETs in the bottom semiconductor device layer BM can be p-type and the FETs in the top semiconductor device layer can be n-type to form a CFET. Each cell boundary can be formed by first and second top power tracks 731 and 732, and left and right polysilicon gate tracks 741 and 742.

[0051] As shown in Figures 7c and 7a, which illustrate a top view of the top semiconductor device layer TP of the semiconductor structure 700, the top power contact 780 can electrically connect the top semiconductor device layer TP of the first logic unit 701 to the second top power track 732 via the region interconnect 785, the top gate contact 781 can electrically connect the gate region G of the top semiconductor device layer TP of the second logic unit 702 to the first top wiring track 762a, and the top source / drain contact 782 can electrically connect the source / drain region S / D of the top semiconductor device layer TP of the third logic unit 703 to the second top wiring track 762b via the region interconnect 786. In one embodiment, the top power contact 780, the top gate contact 781, and the top source / drain contact 782 may all be formed perpendicularly along the thickness direction of the semiconductor structure 700, and are further described in: U.S. Provisional Application No. 63 / 085583, entitled "Connections from Buried Interconnects to Device Terminals in Multiple Stacked Devices Structures", filed on September 30, 2020, the entire contents of which are incorporated herein by reference.

[0052] Figures 7a, 7c, and 7b show a bottom view of the bottom semiconductor device layer BM of the semiconductor structure 700. A single-crystal interlayer window (MIV) 770 can be vertically formed through the insulating layer 790 (not visible in Figure 7c for clarity) to electrically connect the third top wiring track 762c to the third bottom wiring track 761c. Bottom source / drain contacts 783 can electrically connect the source / drain regions S / D of the bottom semiconductor device layer BM of the first logic unit 701 to the first bottom wiring track 761a, and bottom gate contacts 784 can electrically connect the gate region G of the bottom semiconductor device layer BM of the second logic unit 702 to the second bottom wiring track 761b. The first to third bottom wiring tracks 761a to 761c can be collectively referred to as the bottom wiring layer (or the first wiring layer), and the first to third top wiring tracks 762a to 762c can be collectively referred to as the top wiring layer (or the second wiring layer). In one embodiment, the MIV 770, bottom source / drain contact 783, and bottom gate contact 784 may all be formed perpendicularly through the insulating layer 790 along the thickness direction of the semiconductor structure 700. For example, the MIV 770 may be self-aligned with a virtual polysilicon gate (e.g., the left polysilicon gate track 741 of the first logic cell 701) and formed through a diffusion interruption region 753 that isolates adjacent CFETs.

[0053] Figures 8a to 8d are cross-sectional views of a semiconductor structure 700 along lines 8a-8a', 8b-8b', 8c-8c', and 8d-8d' of some embodiments of the present disclosure. All pins (i.e., the wiring structures to which inter-layer signal routing (first wiring layer 661) is connected) can terminate below the top and bottom semiconductor device layers TP and BM of the semiconductor structure 700. For example, as shown in Figure 8a, a top pin A0 above the top semiconductor device layer TP can be connected to the top semiconductor device layer TP of the semiconductor structure 700 and routed through MIV 770 to the corresponding bottom pin A0 below the bottom semiconductor device layer BM, and as shown in Figure 8d, top pins A1 and B0 above the top semiconductor device layer TP can be connected to the top semiconductor device layer TP of the semiconductor structure 700 and routed through MIV 771 and 772 to the corresponding bottom pins A1 and B0 below the bottom semiconductor device layer BM, respectively. As another example, as shown in Figures 8b and 8c, the bottom pins C0 and Y can be directly connected to the bottom semiconductor device layer BM of the semiconductor structure 700 via the bottom source / drain contact 783 and the bottom gate contact 784, respectively. Figure 8b further shows that the gate dielectric material can be deposited on the channel region CH of the semiconductor device in the top and bottom semiconductor device layers TP and BM by selective deposition. For example, an intermediate layer IL and a high-k layer HK can be sequentially formed on the channel region CH. Figure 8b further shows a metal layer ML that can be deposited on the high-k layer HK. For example, the metal layer ML can include TiN, TaN, or TiAl.

[0054] Figure 9 is a flowchart illustrating an exemplary method 900 for manufacturing a multilayer semiconductor structure according to some embodiments of the present disclosure. In one embodiment, some steps of the exemplary method 900 shown may be performed simultaneously or in a different order than shown, may be replaced by other method steps, or may be omitted. Additional method steps may also be performed as needed. In another embodiment, the exemplary method 900 may correspond to the multilayer semiconductor structures 600 and 700 shown in Figures 6a, 6b, 7a to 7c, and 8a to 8d.

[0055] In step S910, a first semiconductor device layer including a first semiconductor device can be provided. For example, the first semiconductor device layer may include the first semiconductor device layer 651 of the semiconductor structure 600 shown in FIG. 6a. In one embodiment, the first semiconductor device layer may be formed above the front side of the substrate and receive power supplied by a PDN disposed on the back side of the substrate via power rails buried in the substrate. For example, the first semiconductor device layer 651 may be formed above the front side 610a of the substrate 610 and receive power supplied by a first PDN 631 disposed on the back side 610b of the substrate 610 via a first power rail 621 buried in the substrate 610, as shown in FIG. 6a. The first semiconductor device may include a FET, which may be n-type or p-type and arranged along the front side 610a of the substrate 610 or stacked perpendicularly to each other along the thickness direction of the substrate 610.

[0056] In step S920, a first signal wiring structure (or a first wiring layer) may be formed above and electrically connected to the first semiconductor device layer. For example, the first wiring layer 661 may be formed on and electrically connected to the first semiconductor device layer 651, as shown in FIG6a.

[0057] In step S930, an insulating layer (or SoI layer) may be formed above the first signal wiring structure. For example, insulating layer 690 may be formed above the first signal wiring structure 661, as shown in FIG6a. As another example, insulating layer 790 may be formed above the first to third bottom wiring tracks 761a to 761c, as shown in FIG7c.

[0058] In step S940, a second semiconductor device layer including a second semiconductor device can be formed over the insulating layer. For example, the second semiconductor device layer may include a second semiconductor device layer 652 of semiconductor structure 600 formed over insulating layer 690, as shown in Figures 6a and 6b. As another example, the second semiconductor device layer may include top and bottom semiconductor device layers TP and BM of semiconductor structure 700 formed over insulating layer 790, as shown in Figure 7c. The second semiconductor device layer can only be processed and constructed when a second wafer of fresh Si is bonded to the first semiconductor device layer. In one embodiment, a second power rail may be formed over the second semiconductor device layer and provide power from the PDN to the second semiconductor device layer. For example, a second power rail 622 may be formed over the second semiconductor device layer 652 and electrically connect the second semiconductor device layer 652 to the second PDN 632 through a second TSV (e.g., nanometer-scale) 642 to provide low-voltage (Vss) and high-voltage (VDD) power delivery, for example, from the second PDN 632 to the second semiconductor device layer 652, as shown in Figure 6a. The second semiconductor device may include FETs, which may be n-type or p-type and are arranged along the front side 690a of the insulating layer 690 or stacked perpendicularly to each other along the thickness direction of the insulating layer 690.

[0059] In step S950, a second signal wiring structure (or a second wiring layer) may be formed above the second semiconductor device layer and electrically connected to the second semiconductor device layer. For example, the second wiring layer 662 may be formed above the second semiconductor device layer 652 of the semiconductor structure 600 and electrically connected to the second semiconductor device layer 652 of the semiconductor structure 600, as shown in FIG6a. As another example, the first to third top wiring tracks 762a to 762c may be formed above the top and bottom semiconductor device layers TP and BM of the semiconductor structure 700 and electrically connected to the top and bottom semiconductor device layers TP and BM of the semiconductor structure 700, as shown in FIG7c.

[0060] In step S960, an interlayer interposer window may be formed vertically through the insulating layer to electrically connect the second signal wiring structure to the first signal wiring structure. For example, a single-crystal interlayer interposer window (MIV) 670 may be formed vertically through the insulating layer 690 to electrically connect the second wiring layer 662 to the first wiring layer 661, as shown in Figures 6a and 6b. As another example, a single-crystal interlayer interposer window (MIV) 770 may be formed vertically through the insulating layer 790 to electrically connect the third top wiring track 762c to the third bottom wiring track 761c, as shown in Figures 7a to 7c and 8a. In one embodiment, the interlayer interposer window may be formed in a diffusion interruption region that vertically isolates adjacent second semiconductor devices. For example, as shown in Figure 6b, MIV 670 may be formed in a diffusion interruption region 653, which isolates adjacent semiconductor devices (e.g., CFETs) of the semiconductor structure 600. As another example, as shown in FIG7c, MIV 770 may be formed in a diffusion interruption region 753, which vertically isolates adjacent semiconductor devices (e.g., CEFT) of the top and bottom semiconductor device layers TP and BM of the semiconductor structure 700. In another embodiment, the second semiconductor device layer may include dummy polysilicon, and the interlayer interlayer window may be aligned with the dummy polysilicon. For example, the top semiconductor device layer TP may include a left polysilicon gate track 741, and MIV 770 may be aligned with the left polysilicon gate track 741, as shown in FIG7a. In one embodiment, bottom source / drain contacts (e.g., bottom source / drain contacts 783) and bottom gate contacts (e.g., bottom gate contacts 784) may be formed to electrically connect the source / drain regions and gate regions of the bottom semiconductor device layer of the second semiconductor device layer to bottom wiring tracks (e.g., first and second bottom wiring tracks 761a and 761b), respectively. For example, the bottom source / drain contacts and the bottom gate contacts can be formed vertically through the insulating layer 790.

[0061] In the foregoing description, specific details have been set forth, such as the specific geometry of a processing system and the description of the various components and processes used herein. However, it should be understood that the techniques described herein can be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes and not for limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding. Furthermore, embodiments may be practiced without such specific details. Components having substantially the same functional structure are labeled with similar reference characters, and therefore any redundant descriptions may be omitted.

[0062] Various techniques have been described as multiple independent operations to aid in understanding the various embodiments. The order of description should not be construed as implying that these operations are necessarily sequential. Indeed, these operations do not need to be performed in the order presented. The operations may be performed in an order different from that of the embodiments described. Various additional operations may be performed, and / or the operations may be omitted in additional embodiments.

[0063] As used herein, "substrate" or "target substrate" generally refers to an object processed according to the present invention. The substrate may contain any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a substrate structure, such as a semiconductor wafer, a photomask, or a dielectric layer, such as a thin film, on or covering a substrate structure. Therefore, the substrate is not limited to any particular substrate structure, underlying or overlying dielectric layer, patterned or unpatterned; rather, the substrate is considered to include any such dielectric layer or substrate structure, and any combination of dielectric layers and / or substrate structures. This section on embodiments may refer to specific types of substrates, but this is for illustrative purposes only.

[0064] Those skilled in the art will understand that many changes can be made to the operation of the techniques explained above while still achieving the same objectives as the present invention. Such changes are intended to be included within the scope of this disclosure. Thus, the above description of the embodiments of this disclosure is not intended to be limiting. Rather, any limitation on the embodiments of this disclosure is presented within the scope of the following claims.

[0065] 100: Semiconductor segment 110:Substrate 110a: Front 110b: Back 120: Power Rail 130: Power Distribution Network (PDN) 140:TSV 150: Semiconductor device layer 160: Signal routing structure (routing layer) 200: Semiconductor Structure 300: Semiconductor Structure 400: Semiconductor Structure 410: Bottom layer 420: Top Floor 490: Silicon on Insulator (SoI) Layer 500: Semiconductor Structure 510: Connection 520: Connection 600: Semiconductor Structure 610:Substrate 610a: Front 610b: Back 621: First power rail 622: Second power rail 631: First PDN 632: Second PDN 641:TSV 642:TSV 651: First semiconductor device layer 652: Second semiconductor device layer 653: Diffusion Interruption Region 661: First signal wiring structure (first wiring layer) 662: Second signal routing structure (second routing layer) 662a~662b: Wiring Tracks 670: Interlayer Window (MIV) for Single Crystal Layers 680: Bottom gate pole contact 690: Insulation layer 690a: Front 700: Semiconductor Structure 701~703: Logic Units 731~732: Power Tracks 741: Left polycrystalline silicon gate track 742: Right polycrystalline silicon gate track 753: Diffusion Interruption Region 761a~761c: Bottom wiring track 762a~762c: Top wiring track 770~772: Interlayer Window (MIV) for Single Crystal Layers 780: Top power contact 781: Top gate contact 782: Top source / drain junction 783: Bottom source / drain junction 784: Bottom gate contact 785: Regional Interconnection 786: Regional Interconnection 790: Insulation layer 900: Method 1601~1603: Wiring Layer 1601a~1601g: Wiring Track S910~S960: Steps

Claims

1. A multilayer semiconductor structure comprising: a first semiconductor device layer including a first semiconductor device; a first signal wiring structure formed above the first semiconductor device layer and electrically connected to the first semiconductor device layer; an insulating layer formed above the first signal wiring structure; a second semiconductor device layer formed above the insulating layer, the second semiconductor device layer including a second semiconductor device; a second signal wiring structure formed above the second semiconductor device layer and electrically connected to the second semiconductor device layer; a second power rail formed above the second semiconductor device layer and electrically connected to the second semiconductor device layer; and an interlayer window vertically formed through the insulating layer and electrically connecting the second signal wiring structure to the first signal wiring structure, wherein the interlayer window has two opposite ends that are in direct contact with the second signal wiring structure and the first signal wiring structure, the interlayer window is electrically connected to the lower surface of the second signal wiring structure in a region located above the second semiconductor device layer, and the second power rail does not horizontally overlap with the region.

2. The multilayer semiconductor structure of claim 1, wherein the interlayer window is formed in a diffusion interruption region that vertically isolates the adjacent second semiconductor devices.

3. The multilayer semiconductor structure of claim 2, wherein the second semiconductor device layer includes a dummy polysilicon, and the interlayer window system is aligned with the dummy polysilicon.

4. The multilayer semiconductor structure of claim 1 further includes a substrate, wherein the first semiconductor device layer is formed on the substrate.

5. The multilayer semiconductor structure of claim 4 further includes a first power rail embedded in the substrate and electrically connected to the first semiconductor device layer.

6. The multilayer semiconductor structure of claim 1, wherein the first semiconductor devices are stacked perpendicularly to each other, and / or the second semiconductor devices are stacked perpendicularly to each other.

7. The multilayer semiconductor structure of claim 6, wherein the second semiconductor device includes a field-effect transistor (FET).

8. The multilayer semiconductor structure of claim 1, wherein the first semiconductor device layer, the second semiconductor device layer, and the interlayer window are formed monolithically.

9. The multilayer semiconductor structure of claim 1 further includes a contact that is vertically formed to electrically connect the second semiconductor device layer to the second signal wiring structure.

10. The multilayer semiconductor structure of claim 1 further includes a contact that is formed vertically through the insulating layer to electrically connect the second semiconductor device layer to the first signal wiring structure.

11. The multilayer semiconductor structure of claim 10, wherein the contact includes a gate contact electrically connecting a gate region of one of the second semiconductor devices of the second semiconductor device layer to the first signal wiring structure.

12. The multilayer semiconductor structure of claim 10, wherein the contact includes a source / drain contact that electrically connects a source / drain region of one of the second semiconductor devices of the second semiconductor device layer to the first signal wiring structure.

13. The multilayer semiconductor structure of claim 1, wherein the insulating layer comprises a silicon-on-insulator (SoI) layer.

14. A method of manufacturing a multilayer semiconductor structure, comprising: forming a first semiconductor device layer, the first semiconductor device layer including a first semiconductor device; forming a first signal wiring structure above the first semiconductor device layer and electrically connecting the first signal wiring structure to the first semiconductor device layer; forming an insulating layer above the first signal wiring structure; forming a second semiconductor device layer above the insulating layer, the second semiconductor device layer including a second semiconductor device; forming a second signal wiring structure above the second semiconductor device layer and electrically connecting the second signal wiring structure to the second semiconductor device layer; and forming an interlayer window perpendicularly passing through the insulating layer to electrically connect the second signal wiring structure to the first signal wiring structure, wherein the interlayer window has two opposite ends that are in direct contact with the second signal wiring structure and the first signal wiring structure respectively, and the interlayer window is electrically connected to a lower surface of the second signal wiring structure in a region located above the second semiconductor device layer; and forming a second power rail above the second semiconductor device layer and electrically connecting the second power rail to the second semiconductor device layer. The second power rail does not overlap horizontally with the region.

15. The method of manufacturing a multilayer semiconductor structure as claimed in claim 14, wherein the step of forming an interlayer window comprises: forming an interlayer window in a diffusion interruption region, the diffusion interruption region vertically isolating the adjacent of the second semiconductor device.

16. The method of manufacturing a multilayer semiconductor structure as claimed in claim 15, wherein the second semiconductor device layer includes a dummy polysilicon, and the interlayer window is aligned with the dummy polysilicon.

17. The method of manufacturing a multilayer semiconductor structure as claimed in claim 14, wherein the first semiconductor device layer, the second semiconductor device layer, and the interlayer window are formed in a single crystal.

18. The method of manufacturing a multilayer semiconductor structure as claimed in claim 14, further comprising forming a contact perpendicularly through the insulating layer to electrically connect the second semiconductor device layer to the first signal wiring structure.

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