Semiconductor device

Abstract

A semiconductor device includes: an active pattern disposed on a substrate; a source / drain pattern disposed on the active pattern; a channel pattern configured to connect to the source / drain pattern; a gate electrode configured to extend in a first direction and intersect the channel pattern; and a first spacer disposed on a side surface of the gate electrode. The first spacer includes a gate portion disposed on the side surface of the active pattern and below the source / drain pattern. The source / drain pattern includes a body portion and a neck portion located between the body portion and the active pattern. The body portion includes a crystalline surface configured to extend obliquely from the neck portion. The crystalline surface is configured to be spaced apart from the uppermost portion of the gate portion.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor (FET) and a method for manufacturing the same. [Cross-reference to related applications]

[0002] This application claims priority to Korean Patent Application No. 10-2021-0112180, filed on August 25, 2021, with the Korean Intellectual Property Office, the entire contents of which are hereby incorporated herein by reference. Prior Technology

[0003] Semiconductor devices can include integrated circuits containing metal-oxide-semiconductor (MOS) field-effect transistors (FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOSFETs are being actively scaled down. MOSFET scaling down can lead to a degradation in the operating properties of semiconductor devices. Various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0004] A semiconductor device and a method for manufacturing a semiconductor device having improved electrical and reliability characteristics are provided.

[0005] Additional states will be described in part in the following description, and these additional states will become apparent in part from this description, or may be learned by practicing the embodiments provided.

[0006] According to the present disclosure, a semiconductor device may include: an active pattern disposed on a substrate; a source / drain pattern disposed on the active pattern; a channel pattern configured to connect to the source / drain pattern; a gate electrode configured to extend in a first direction and intersect the channel pattern; and a first spacer disposed on a side surface of the gate electrode. The first spacer may include a gate portion disposed on the side surface of the active pattern and below the source / drain pattern. The source / drain pattern may include a body portion and a neck portion located between the body portion and the active pattern. The body portion may include a crystal surface configured to extend obliquely from the neck portion. The crystal surface may be configured to be spaced apart from the uppermost portion of the gate portion.

[0007] According to the present disclosure, a semiconductor device may include: an active pattern disposed on a substrate; a source / drain pattern disposed on the active pattern; a channel pattern configured to connect to the source / drain pattern; a gate electrode configured to extend in a first direction and intersect the channel pattern; a first spacer disposed on the active pattern; and a second spacer disposed on the source / drain pattern. The source / drain pattern may include a body portion and a neck portion located between the body portion and the active pattern. The body portion may include a crystalline surface configured to extend obliquely from the neck portion. A top surface of the neck portion may be exposed between the crystalline surface and the first spacer. The second spacer may be configured to cover the top surface of the neck portion.

[0008] According to the present disclosure, a semiconductor device may include: a first active pattern and a second active pattern, respectively disposed in the p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (MOSFET) region and the n-type MOSFET (PMOSFET) region of a substrate. On a MOSFET (NMOSFET) region; a device isolation layer configured to fill a trench between a first active pattern and a second active pattern; a first source / drain pattern and a second source / drain pattern, respectively disposed on the first active pattern and the second active pattern; a first channel pattern disposed on the first active pattern and configured to connect to the first source / drain pattern; a second channel pattern disposed on the second active pattern and configured to connect to the second source / drain pattern, wherein the first channel pattern includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern configured to be stacked sequentially at a distance from each other, and wherein the second channel pattern includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth semiconductor pattern configured to be stacked sequentially at a distance from each other; a gate electrode configured to extend from a first region on the first channel pattern to a second region on the second channel pattern, the gate electrode being... The system comprises: a gate insulating layer disposed between a channel pattern and a gate electrode; a spacer disposed on a side surface of the gate electrode; a gate cap pattern disposed on a top surface of the gate electrode; a first interlayer insulating layer disposed on the gate cap pattern; an active contact configured to penetrate the first interlayer insulating layer and coupled to at least one of a first source / drain pattern and a second source / drain pattern; a gate contact configured to penetrate the first interlayer insulating layer and coupled to the gate electrode; a second interlayer insulating layer disposed on the first interlayer insulating layer; a first metal layer disposed in the second interlayer insulating layer, the first metal layer including a first interconnect configured to be electrically connected to the active contact and the gate contact; a third interlayer insulating layer disposed on the second interlayer insulating layer; and a second metal layer disposed in the third interlayer insulating layer. The second metal layer may include a second interconnect configured to be electrically connected to the first interconnect. The spacer may include a first spacer and a second spacer disposed on the first spacer. The dielectric constant of the first spacer may be less than that of the second spacer. The first spacer may be configured to extend from a side surface of a first active pattern to a side surface of a second active pattern while covering the top surface of the isolation layer of the covering device. The second spacer may be configured to extend along the first spacer from a first source / drain pattern to a second source / drain pattern.

[0009] According to the present disclosure, a method of manufacturing a semiconductor device may include: alternately stacking a sacrificial layer and an active layer on a substrate; forming a stacked pattern on an active pattern by patterning the sacrificial layer and the active layer; forming a sacrificial pattern that intersects with the stacked pattern; forming a first spacer on the sacrificial pattern; forming a groove by etching the stacked pattern, the groove being located on one side of the sacrificial pattern; using the first spacer as an etching mask; forming a source / drain pattern in the groove; forming an oxide layer on the surface of the source / drain pattern by selectively oxidizing the surface of the source / drain pattern; removing the first spacer; and forming a second spacer. Simple Explanation of the Diagram

[0010] The above and other features, characteristics, and advantages of the specific embodiments disclosed herein will become apparent from the following description in conjunction with the accompanying drawings, wherein: Figures 1, 2 and 3 are diagrams illustrating the logic cells of a semiconductor device according to an embodiment. Figure 4 is a plan view illustrating a semiconductor device according to an embodiment. Figures 5A, 5B, 5C and 5D are cross-sectional views taken along lines A-A', B-B', C-C' and D-D' of Figure 4, respectively, according to the embodiment. Figure 6A is an enlarged cross-sectional view showing part "L" of Figure 5C according to an embodiment. Figure 6B is a top view taken at plane M-M' of Figure 5A and plane N-N' of Figure 5B according to an embodiment. Figures 7A, 7B, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 15D, 16A, 16B, 16C, 16D, 17A, 17B, 17C, and 17D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. Figures 18A and 18B are cross-sectional views showing a portion "L" of Figure 10C according to an embodiment. Figures 19 and 20 are cross-sectional views showing a portion of a semiconductor device according to an embodiment (e.g., portion L of Figure 5C). Figure 21 is a cross-sectional view taken along line C-C' of Figure 4 to show a semiconductor device according to an embodiment. Figures 22A, 22B, 23A and 23B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. Figures 24A, 24B, 24C and 24D are cross-sectional views of a semiconductor device according to an embodiment, taken along lines A-A', B-B', C-C' and D-D' of Figure 4, respectively. Implementation

[0011] Various embodiments of the concept of the invention are illustrated below with reference to the accompanying drawings. The embodiments described herein are exemplary, and therefore the concept of the invention is not limited thereto, but can be achieved in various other forms. When expressions such as "at least one of..." appear before a series of elements, they modify the entire series of elements rather than individual elements within the series. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this specification, a pattern signal may refer to a signal having a periodically repeating waveform.

[0012] Figures 1, 2 and 3 are diagrams illustrating the logic cells of a semiconductor device according to an embodiment.

[0013] Referring to Figure 1, a single-height SHC cell can be provided. Specifically, a first power line M1_R1 and a second power line M1_R2 can be provided on the substrate 100. The first power line M1_R1 can be a conductive path for receiving a drain voltage VDD (e.g., a power supply voltage). The second power line M1_R2 can be a conductive path for receiving a source voltage VSS (e.g., a ground voltage).

[0014] A single-height SHC cell can be defined between a first power line M1_R1 and a second power line M1_R2. A single-height SHC cell may include a p-type metal-oxide-semiconductor (MOS) field-effect transistor (FET) (MOSFET) (PMOSFET) region PR and an N-type MOSFET (NMOSFET) region NR. In other words, a single-height SHC cell may have a complementary metal-oxide-semiconductor (CMOS) structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0015] Each of the PMOSFET region PR and the NMOSFET region NR may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as a first height HE1. The first height HE1 may be substantially equal to the distance (e.g., pitch) between the first power line M1_R1 and the second power line M1_R2.

[0016] A single-height SHC can constitute a single logic cell. A logic cell can refer to a logic device configured to perform a specific function (such as AND, OR, XOR, XNOR, inverter, etc.). In other words, a logic cell can include transistors that constitute the logic device and interconnections that connect the transistors to each other.

[0017] Referring to Figure 2, a dual-height cell DHC can be provided. Specifically, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 can be provided on the substrate 100. The first power line M1_R1 can be disposed between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 can be a conductive path for which a drain voltage VDD is provided.

[0018] The dual-height cell DHC can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height cell DHC may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2.

[0019] The first NMOSFET region NR1 may be adjacent to the second power line M1_R2. The second NMOSFET region NR2 may be adjacent to the third power line M1_R3. The first PMOSFET region PR1 and the second PMOSFET region PR2 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be located between the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0020] The length of the dual-height cell DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be approximately twice the first height HE1 in Figure 1. The first PMOSFET region PR1 and the second PMOSFET region PR2 of the dual-height cell DHC can be combined to serve as a single PMOSFET region.

[0021] Therefore, the channel size of the p-type MOS (PMOS) transistor in a dual-height cell DHC can be larger than the channel size of the PMOS transistor in a single-height cell SHC as illustrated in Figure 1. For example, the channel size of the PMOS transistor in a dual-height cell DHC can be approximately twice the channel size of the PMOS transistor in a single-height cell SHC. In this case, the dual-height cell DHC can operate at a faster speed than the single-height cell SHC. In an embodiment, the dual-height cell DHC shown in Figure 2 can be defined as a multi-height cell. A multi-height cell can include a three-height cell whose cell height is approximately three times the cell height of a single-height cell SHC.

[0022] Referring to Figure 3, a first single-height cell SHC1, a second single-height cell SHC2, and a double-height cell DHC can be two-dimensionally disposed on the substrate 100. The first single-height cell SHC1 can be disposed between the first power line M1_R1 and the second power line M1_R2. The second single-height cell SHC2 can be disposed between the first power line M1_R1 and the third power line M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0023] The dual-height cell DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height cell DHC can be adjacent to the first single-height cell SHC1 and the second single-height cell SHC2 in the second direction D2.

[0024] The segmentation structure DB can be disposed between the first single-height cell SHC1 and the dual-height cell DHC, and between the second single-height cell SHC2 and the dual-height cell DHC. The active region of the dual-height cell DHC can be electrically isolated from the active regions of each of the first single-height cell SHC1 and the second single-height cell SHC2 by means of the segmentation structure DB.

[0025] Figure 4 is a plan view illustrating a semiconductor device according to an embodiment. Figures 5A, 5B, 5C, and 5D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 4, respectively, according to an embodiment. Figure 6A is an enlarged cross-sectional view showing a portion "L" of Figure 5C according to an embodiment. Figure 6B is a top plan view taken along plane M-M' of Figure 5A and plane N-N' of Figure 5B, according to an embodiment. Figures 4 and 5A to 5D illustrate examples of the detailed structures of the first single-height cell SHC1 and the second single-height cell SHC2 of Figure 3.

[0026] Referring to Figures 4 and 5A to 5D, a first single-height cell SHC1 and a second single-height cell SHC2 may be disposed on the substrate 100. Logic transistors constituting a logic circuit may be disposed on each of the first single-height cell SHC1 and the second single-height cell SHC2. The substrate 100 may be a semiconductor substrate formed of or containing silicon (Si), germanium (Ge), silicon-germanium (SiGe), compound semiconductor materials, etc. In an embodiment, the substrate 100 may be a silicon wafer.

[0027] The substrate 100 may include a first PMOSFET region PR1, a second PMOSFET region PR2, a first NMOSFET region NR1, and a second NMOSFET region NR2. Each of the first PMOSFET region PR1, the second PMOSFET region PR2, the first NMOSFET region NR1, and the second NMOSFET region NR2 may extend in a second direction D2. The first single-height cell SHC1 may include the first NMOSFET region NR1 and the first PMOSFET region PR1, and the second single-height cell SHC2 may include the second PMOSFET region PR2 and the second NMOSFET region NR2.

[0028] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed in the upper portion of the substrate 100. The first active pattern AP1 may be disposed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 may be disposed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. Each of the first active pattern AP1 and the second active pattern AP2 may be a vertically projecting portion of the substrate 100.

[0029] A device isolation layer ST can be provided to fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described below.

[0030] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2 and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3 may be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0031] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or contain at least one of Si, Ge, or SiGe. In an embodiment, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or contain crystalline Si.

[0032] Multiple first source / drain patterns SD1 can be disposed on the first active pattern AP1. Multiple first grooves RS1 can be formed in the upper portion of the first active pattern AP1. The first source / drain patterns SD1 can be disposed in the first grooves RS1 respectively. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be sandwiched between each pair of first source / drain patterns SD1. In other words, each pair of first source / drain patterns SD1 can be connected to each other by stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3.

[0033] Multiple second source / drain patterns SD2 can be disposed on the second active pattern AP2. Multiple second grooves RS2 can be formed in the upper portion of the second active pattern AP2. The second source / drain patterns SD2 can be disposed in the second grooves RS2 respectively. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be sandwiched between each pair of second source / drain patterns SD2. In other words, each pair of second source / drain patterns SD2 can be interconnected by stacked first semiconductor patterns to third semiconductor patterns SP1, SP2, and SP3.

[0034] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located at substantially the same level as the top surface of the third semiconductor pattern SP3. Alternatively, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be higher than the top surface of the third semiconductor pattern SP3.

[0035] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, the pair of first source / drain patterns SD1 may apply compressive stress to a first channel pattern CH1 located between the pair of first source / drain patterns SD1. The second source / drain pattern SD2 may be formed of or comprise the same semiconductor element (e.g., Si) as the substrate 100.

[0036] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 stacked in sequence. The cross-sectional shape of the first source / drain pattern SD1 in the second direction D2 will be described in more detail with reference to FIG5A.

[0037] The first semiconductor layer SEL1 may cover the inner surface of the first groove RS1. The first semiconductor layer SEL1 may have a decreasing thickness in the upward direction. For example, the thickness of the first semiconductor layer SEL1 measured in the third direction D3 at the bottom horizontal position of the first groove RS1 may be greater than the thickness of the first semiconductor layer SEL1 measured in the second direction D2 at the top horizontal position of the first groove RS1. The first semiconductor layer SEL1 may have a "U" shaped cross-section, which is attributed to the cross-sectional profile of the first groove RS1.

[0038] The second semiconductor layer SEL2 can fill the remaining space of the first groove RS1, excluding the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 can be larger than the volume of the first semiconductor layer SEL1. In other words, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 can be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0039] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be formed of or contain SiGe. Specifically, the first semiconductor layer SEL1 may be configured to have a relatively low Ge concentration. In another embodiment, the first semiconductor layer SEL1 may be configured to contain only Si and no Ge. The Ge concentration of the first semiconductor layer SEL1 may be in the range of about 0% to about 10%.

[0040] The second semiconductor layer SEL2 can be configured to have a relatively high Ge concentration. For example, the Ge concentration of the second semiconductor layer SEL2 can range from about 30% to about 70%. The Ge concentration of the second semiconductor layer SEL2 can be increased towards D3. For instance, the Ge concentration of the second semiconductor layer SEL2 can be about 40% near the first semiconductor layer SEL1, but about 60% at the top level of the second semiconductor layer SEL2.

[0041] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may contain impurities (e.g., boron) to enable the first source / drain pattern SD1 to have p-type conductivity. In an embodiment, the impurity concentration (in percentage (%)) in the second semiconductor layer SEL2 may be greater than the impurity concentration in the first semiconductor layer SEL1.

[0042] The first semiconductor layer SEL1 prevents stacking faults between the substrate 100 and the second semiconductor layer SEL2, and between the first semiconductor pattern to the third semiconductor patterns SP1, SP2, and SP3 and the second semiconductor layer SEL2. Stacking faults can lead to increased channel resistance. Stacking faults are more likely to occur at the bottom of the first recess RS1. Therefore, to prevent stacking faults, the first semiconductor layer SEL1 can be configured to have a relatively large thickness near the bottom of the first recess RS1.

[0043] In a process where the first to third portions PO1, PO2, and PO3 of the gate electrode GE, as described below, are used to replace the sacrificial layer SAL, the first semiconductor layer SEL1 can protect the second semiconductor layer SEL2. For example, the first semiconductor layer SEL1 can prevent the second semiconductor layer SEL2 from being undesirably used for etching with etch material to remove the sacrificial layer SAL.

[0044] Gate electrodes GE1 and GE2 (hereinafter, each gate electrode may also be referred to as GE) may be configured to intersect with the first channel pattern CH1 and the second channel pattern CH2 and extend in a first direction D1. Gate electrodes GE1 and GE2 may be arranged at a first pitch in a second direction D2. Each of gate electrodes GE1 and GE2 may overlap with the first channel pattern CH1 and the second channel pattern CH2 in a perpendicular direction.

[0045] Each gate electrode GE1 and gate electrode GE2 may include a first portion PO1 sandwiched between the active pattern AP1 or the active pattern AP2 and the first semiconductor pattern SP1, a second portion PO2 sandwiched between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 sandwiched between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 located on the third semiconductor pattern SP3.

[0046] Referring to Figure 5A, the first to third portions PO1, PO2, and PO3 of the gate electrode GE on the PMOSFET region PR may have different widths. For example, the maximum width of the third portion PO3 in the second direction D2 may be greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the first portion PO1 in the second direction D2 may be greater than the maximum width of the third portion PO3 in the second direction D2.

[0047] Referring back to FIG5D, the gate electrode GE may be disposed on the top surface TS, bottom surface BS, and opposite side surfaces SW1 and SW2 of each of the first to third semiconductor patterns SP1, SP2, and SP3. That is, the transistor according to the embodiment may be a three-dimensional field-effect transistor (e.g., a multi-bridge channel FET (MBCFET)) or a gate-all-around field-effect transistor (GAAFET) in which the gate electrode GE is disposed three-dimensionally around the channel pattern.

[0048] As an example, the first single-height cell SHC1 may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The first single-height cell SHC1 may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0049] The gate cleaving pattern CT can be disposed on the boundary parallel to the second direction D2 of each of the first single-height cell SHC1 and the second single-height cell SHC2. For example, the gate cleaving pattern CT can be disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The gate cleaving pattern CT can be arranged along the third boundary BD3 with a first pitch. The gate cleaving pattern CT can be arranged along the fourth boundary BD4 with a first pitch. When viewed in a plan view, the gate cleaving pattern CT on the third boundary BD3 and the fourth boundary BD4 can be arranged to overlap with the gate electrode GE, respectively. The gate cleaving pattern CT can be formed of or contain at least one insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof).

[0050] The gate electrode GE on the first single-height cell SHC1 can be separated from the gate electrode GE on the second single-height cell SHC2 by a gate cutting pattern CT. The gate cutting pattern CT can be sandwiched between the gate electrodes GE of the first single-height cell SHC1 and the second single-height cell SHC2, which are aligned with each other in the first direction D1. In other words, the gate electrode GE extending in the first direction D1 can be divided into multiple gate electrodes by the gate cutting pattern CT.

[0051] Referring back to Figure 4, at least one of the gate cleaving patterns CT may be located within the cell rather than on the cell boundary. For example, the gate cleaving pattern CT may be disposed between the second PMOSFET region PR2 and the second NMOSFET region NR2 of the second single-height cell SHC2.

[0052] Referring back to Figures 4 and 5A to 5D, spacers GS can be disposed on opposite side surfaces of the fourth portion PO4 of the gate electrode GE. Spacers GS can extend along the gate electrode GE in the first direction D1. The top surface of spacers GS can be higher than the top surface of the gate electrode GE. The top surface of spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. Spacers GS can be formed of or contain at least one of silicon carbonitride (SiCN), silicon carbonoxynitride (SiCON), or silicon nitride (SiN). In embodiments, spacers GS can be a multilayer structure formed of or containing at least two different materials selected from SiCN, SiCON, and SiN.

[0053] In an embodiment, the spacer GS may include a first spacer GS1 located on the side surface of the gate electrode GE and a second spacer GS2 located on the first spacer GS1. Each of the first spacer GS1 and the second spacer GS2 may be formed of or contain a Si-containing insulating material.

[0054] Specifically, the first spacer GS1 may be formed of or contain a low-k dielectric material (e.g., SiCON) containing Si. Referring to FIG5C, the first spacer GS1 may cover the top surface of the device isolation layer ST and the upper side surface of each of the first active pattern AP1 and the second active pattern AP2. The first spacer GS1 may cover the lower side surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. The portion of the first spacer GS1 covering the lower side surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be defined as the fence portion FEP.

[0055] The second spacer GS2 may be formed of or contain a Si-containing insulating material (e.g., SiN) with good corrosion resistance. The second spacer GS2 may extend from the first spacer GS1 to cover the upper portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. The second spacer GS2 may be used as an etch stop layer in the process of forming the active contact AC, which will be described below.

[0056] The spacers GS on the first PMOSFET region PR1 and the second PMOSFET region PR2 can have substantially the same structure and thickness as the spacers GS on the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0057] Referring back to Figures 4 and 5A to 5D, a gate cap pattern GP may be provided on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE or in the first direction D1. The gate cap pattern GP may be formed of or contain a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. In detail, the gate cap pattern GP may be formed of or contain at least one of silicon oxynitride (SiON), SiCN, SiCON, or SiN.

[0058] A gate insulating layer GI may be sandwiched between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, bottom surface BS, and opposite side surfaces SW1 and SW2 of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST located below the gate electrode GE (e.g., FIG. 5D).

[0059] In embodiments, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of or contain at least one high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide (Hf), hafnium silicon oxide, hafnium zirconium oxide (Zr), hafnium tantalum oxide (Ta), lanthanum oxide (La), zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide (Ti), barium strontium oxide (Sr) titanium, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide (Al), lead scandium tantalum oxide, or lead zinc niobate.

[0060] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric properties and a paraelectric layer exhibiting paraelectric properties.

[0061] The ferroelectric layer can have negative capacitance, and the paraelectric layer can have positive capacitance. In the case where two or more capacitors are connected in series and each capacitor has positive capacitance, the total capacitance can be reduced to a value smaller than the capacitance of each individual capacitor. Conversely, in the case where at least one of the capacitors connected in series has negative capacitance, the total capacitance of the series-connected capacitors can have a positive value and can be greater than the absolute value of each individual capacitor.

[0062] In the case where a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers can increase. Due to this increase in total capacitance, the transistor including the ferroelectric layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0063] The ferroelectric layer may possess ferroelectric properties. The ferroelectric layer may be formed of or contain at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, hafnium zirconium oxide may be zirconium oxide doped with Zr. Alternatively, hafnium zirconium oxide may be a compound composed of Hf, Zr, and / or oxygen (O).

[0064] The ferroelectric layer may further contain dopants. For example, dopants may include at least one of Al, Ti, niobium (Nb), La, yttrium (Y), magnesium (Mg), Si, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), thorium (Gd), Ge, scandium (Sc), Sr, and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material contained in the ferroelectric layer.

[0065] In cases where the ferroelectric layer comprises hafnium oxide, the dopant in the ferroelectric layer may include at least one of, for example, Gd, Si, Zr, Al and / or Y.

[0066] In the case where the dopant is Al, the Al content in the ferroelectric layer can range from about 3% to about 8% (atomic percentage). Here, the dopant content (e.g., Al atoms) can be the ratio of the number of Al atoms to the number of Hf atoms and Al atoms.

[0067] When the dopant is Si, the Si content in the ferroelectric layer can range from about 2% to about 10%. When the dopant is Y, the Y content in the ferroelectric layer can range from about 2% to about 10%. When the dopant is Gd, the Gd content in the ferroelectric layer can range from about 1% to about 7%. When the dopant is Zr, the Zr content in the ferroelectric layer can range from about 50% to about 80%.

[0068] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed of or contain at least one of, for example, silicon oxide and / or a high-dielectric-constant metal oxide. Metal oxides that can be used as paraelectric layers may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the embodiments are not limited to these examples.

[0069] The ferroelectric layer and the paraelectric layer can be formed of the same material or contain the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not have ferroelectric properties. For example, in the case where both the ferroelectric layer and the paraelectric layer contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may be different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0070] Ferroelectric layers can only exhibit ferroelectric properties when their thickness is within a specific range. In embodiments, ferroelectric layers may have a thickness ranging from about 0.5 nanometers to about 10 nanometers, but embodiments are not limited to this example. Since the critical thickness end associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer may also vary depending on the type of ferroelectric material.

[0071] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include multiple ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0072] The gate electrode GE may include a first metal pattern and a second metal pattern located on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work-function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be achieved. For example, the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern or the work-function metal.

[0073] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer made of at least one metallic material selected from the group consisting of Ti, Ta, Al, tungsten (W), molybdenum (Mo), and N. In an embodiment, the first metal pattern may further include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0074] The second metal pattern may be formed of or comprise a metal material with a lower resistance than the first metal pattern. For example, the second metal pattern may comprise at least one metal material selected from the group consisting of W, Al, Ti, and Ta. The fourth portion PO4 of the gate electrode GE may comprise the first metal pattern and the second metal pattern located on the first metal pattern.

[0075] Referring back to Figure 5B, internal spacers IP can be disposed on the first NMOSFET region NR1 and the second NMOSFET region NR2. The internal spacers IP can be respectively sandwiched between the first to third portions PO1, PO2, and PO3 of the gate electrode GE and the second source / drain pattern SD2. The internal spacers IP can be in direct contact with the second source / drain pattern SD2. Each of the first to third portions PO1, PO2, and PO3 of the gate electrode GE can be spaced apart from the second source / drain pattern SD2 by means of the internal spacers IP.

[0076] A first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer insulating layer 110 may have a top surface that is substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the spacer GS. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. In an embodiment, at least one of the first interlayer insulating layer 110 to the fourth interlayer insulating layer 140 may include a silicon oxide layer.

[0077] Each of the first single-height cell SHC1 and the second single-height cell SHC2 may have a pair of segmented structures DB facing each other in the second direction D2 on both sides. For example, the pair of segmented structures DB may be respectively disposed on the first boundary BD1 and the second boundary BD2 of the first single-height cell SHC1. The segmented structures DB may extend in the first direction D1 parallel to the gate electrode GE. The pitch between the segmented structure DB and the gate electrode GE adjacent to the segmented structure DB may be equal to the first pitch.

[0078] The segmentation structure DB can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and extend into the first active pattern AP1 and the second active pattern AP2. The segmentation structure DB can be configured to penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The segmentation structure DB can electrically separate the active region of each of the first single-height cell SHC1 and the second single-height cell SHC2 from the active regions of adjacent cells.

[0079] The active contact AC can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be provided on both sides of the gate electrode GE. When viewed in a plan view, the active contact AC can be a strip pattern extending in the first direction D1.

[0080] The active contact AC can be a self-aligning contact. For example, the active contact AC can be formed using a self-aligning process of the gate cap pattern GP and the spacer GS. In an embodiment, the active contact AC may cover at least a portion of the side surface of the spacer GS. The active contact AC may cover a portion of the top surface of the gate cap pattern GP.

[0081] Silicone patterns SC may be sandwiched between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC may be electrically connected to the source / drain pattern SD1 or the source / drain pattern SD2 via the silicone pattern SC. The silicone pattern SC may be formed of or contain at least one metal silicone material (e.g., titanium silicone, tantalum silicone, tungsten silicone, nickel silicone (Ni), and cobalt silicone (Co)).

[0082] The gate contact GC can be configured to penetrate the second interlayer insulating layer 120 and the gate top cover pattern GP, ​​respectively, and be electrically connected to the gate electrode GE. When viewed in a plan view, the gate contact GC on the first single-height cell SHC1 can be configured to overlap with the first PMOSFET region PR1. In other words, the gate contact GC on the first single-height cell SHC1 can be disposed on the first active pattern AP1 (e.g., FIG. 5A).

[0083] The gate contact GC can be freely disposed on the gate electrode GE, and its position is not restricted in any way. For example, the gate contact GC on the second single-height cell SHC2 can be disposed on the second PMOSFET region PR2, the second NMOSFET region NR2, and the device isolation layer ST that fills the trench TR (e.g., Figure 4).

[0084] In an embodiment, referring to FIG5A, the upper portion of the active contact AC adjacent to the gate contact GC may be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC. In other words, the top surface of the active contact AC adjacent to the gate contact GC may be formed by the upper insulating pattern UIP at a level lower than the bottom surface of the gate contact GC. This prevents the adjacent gate contacts GC and active contacts AC from contacting each other, thereby preventing short circuits between them.

[0085] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or contain at least one metallic material (e.g., Al, copper (Cu), W, Mo, and Co). The barrier pattern BM may be configured to cover the side and bottom surfaces of the conductive pattern FM. In an embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or contain at least one of Ti, Ta, W, Ni, Co, or Pt. The metal nitride layer may be formed of or contain at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0086] A first metal layer M1 may be provided in the third interlayer insulation layer 130. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, a third power line M1_R3, and a first internal interconnect M1_I. The internal interconnects M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1 may extend parallel to each other in the second direction D2.

[0087] Specifically, the first power line M1_R1 and the second power line M1_R2 can be respectively disposed on the third boundary BD3 and the fourth boundary BD4 of the first single-height cell SHC1. The first power line M1_R1 can extend along the third boundary BD3 and in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 and in the second direction D2.

[0088] The first interconnect M1_I of the first metal layer M1 can be arranged on the first direction D1 with a second pitch. The second pitch can be smaller than the first pitch of the gate electrode GE. The line width of each of the first interconnect M1_I can be smaller than the line width of each of the first power line to the third power line M1_R1, M1_R2 and M1_R3.

[0089] The first metal layer M1 may further include a first through-hole VI1. The first through-hole VI1 may be disposed below the internal interconnects M1_R1, M1_R2, M1_R3, and M1_I of the first metal layer M1. The active contact AC and the internal interconnects of the first metal layer M1 may be electrically connected to each other through the first through-hole VI1. The gate contact GC and the internal interconnects of the first metal layer M1 may be electrically connected to each other through the first through-hole VI1.

[0090] The interconnects of the first metal layer M1 and the first via VI1 located beneath the interconnects can be formed by separate processes. For example, the interconnects of the first metal layer M1 and the first via VI1 can be formed independently by a single damascene process. The semiconductor device according to this embodiment can be manufactured using a sub-20 nm process.

[0091] A second metal layer M2 may be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include a plurality of second interconnects M2_I. Each of the second interconnects M2_I in the second metal layer M2 may be a linear pattern or a strip pattern extending in the first direction D1. In other words, the second interconnects M2_I may extend in the first direction D1 and be parallel to each other.

[0092] The second metal layer M2 may further include a second via VI2, which may be disposed below the second interconnect M2_I. The interconnects of the first metal layer M1 and the interconnects of the second metal layer M2 may be electrically connected to each other via the second via VI2. The interconnects of the second metal layer M2 and the second via VI2 located below the interconnects may be formed together by a dual damascene process.

[0093] The interconnects of the first metal layer M1 may be formed of or contain the same or different conductive material as the interconnects of the second metal layer M2. For example, the interconnects of the first metal layer M1 and the interconnects of the second metal layer M2 may be formed of or contain at least one metallic material (e.g., Al, Cu, W, ruthenium (Ru), Mo, and Co). Multiple metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include interconnects serving as routing paths between cells.

[0094] Figure 6A is an enlarged cross-sectional view of a portion "L" of Figure 5C according to an embodiment. The cross-sectional shapes of the first source / drain pattern SD1 and the spacer GS covering the first source / drain pattern SD1 will be described in more detail with reference to Figure 6A. The first source / drain pattern SD1 may be disposed on a first active pattern AP1. More specifically, the first active pattern AP1 may be recessed to define a first groove RS1, and the first source / drain pattern SD1 may be formed in the first groove RS1. The first active pattern AP1 may be a fan-shaped pattern.

[0095] The first source / drain pattern SD1 may include a neck portion NEP and a body portion BDP located on the neck portion NEP. The neck portion NEP may be in direct contact with the first active pattern AP1. The neck portion NEP may be in direct contact with the inner surface of the first groove RS1.

[0096] The first spacer GS1 can directly cover the side surface AP1_S of the first active pattern AP1 and the side surface NEP_S of the neck portion NEP. The first spacer GS1 in FIG6A may include a fence portion FEP. The fence portion FEP can define the neck portion NEP of the first source / drain pattern SD1. The side surface NEP_S of the neck portion NEP and the side surface AP1_S of the first active pattern AP1 can be aligned with each other by means of the fence portion FEP.

[0097] The neck portion NEP may have an exposed top surface NEP_T. For example, the top surface NEP_T of the neck portion NEP may be substantially parallel to the top surface of the substrate 100. The top surface NEP_T of the neck portion NEP may cover the second spacer GS2. The top surface NEP_T of the neck portion NEP may be located at substantially the same level as the uppermost portion FET of the gate portion FEP.

[0098] The body portion BDP of the first source / drain pattern SD1 may protrude vertically from the neck portion NEP. The body portion BDP of the first source / drain pattern SD1 may have a rhomboid shape. For example, the body portion BDP may include a first facet FA1 extending obliquely upward from the neck portion NEP and a second facet FA2 extending upward at a slope opposite to that of the first facet FA1. The first facet FA1 and the second facet FA2 may intersect each other and may define an edge ED. Each of the first facet FA1 and the second facet FA2 may be a {111} crystalline facet of the first source / drain pattern SD1. The first source / drain pattern SD1 may have a maximum width WM at the level of the edge ED in the first direction D1.

[0099] The first facet FA1 of the body portion BDP can be spaced apart from the uppermost FET of the gate portion FEP by a second spacer GS2 sandwiched between the first facet FA1 of the body portion BDP and the uppermost FET of the gate portion FEP. The first facet FA1 can be offset from the uppermost FET of the gate portion FEP by the top surface NEP_T of the neck portion NEP.

[0100] The width of the body portion BDP, which is adjacent to the boundary line between the body portion BDP and the neck portion NEP, may be smaller than the width of the neck portion NEP, which is adjacent to the boundary line. In other words, the width of the first source / drain pattern SD1 in the first direction D1 may change discontinuously near the boundary line between the body portion BDP and the neck portion NEP.

[0101] The second spacer GS2 may cover the body portion BDP of the first spacer GS1 and the first source / drain pattern SD1. The second spacer GS2 may cover the first facet FA1 and the second facet FA2 of the first source / drain pattern SD1. As described above, the second spacer GS2 may cover at least a portion of the neck portion NEP (e.g., the exposed top surface NEP_T of the neck portion NEP).

[0102] The neck portion NEP of the first source / drain pattern SD1 may include a first semiconductor layer SEL1. In an embodiment, the neck portion NEP of the first source / drain pattern SD1 may include a portion of a second semiconductor layer SEL2. The body portion BDP may include the remaining portion of the second semiconductor layer SEL2. However, the embodiment is not limited to this example. In an embodiment, the neck portion NEP may include only the first semiconductor layer SEL1.

[0103] Figure 6B is a top plan view taken at horizontal line M-M' of Figure 5A and horizontal line N-N' of Figure 5B according to an embodiment. The planar shapes of the first source / drain pattern SD1 and the second source / drain pattern SD2, as well as the spacer GS covering the first source / drain pattern SD1 and the second source / drain pattern SD2, will be described in more detail with reference to Figure 6B. Specifically, Figure 6B is a plan view of the semiconductor device obtained at the level of the first semiconductor pattern SP1 when the semiconductor device is planarized to the level of the first semiconductor pattern SP1 of each of the first channel pattern CH1 and the second channel pattern CH2.

[0104] The first source / drain patterns SD1 can be respectively disposed on both sides of the first semiconductor pattern SP1 of the first channel pattern CH1. Each of the opposite side surfaces of the first semiconductor pattern SP1 can be in direct contact with the first semiconductor layer SEL1 of the first source / drain pattern SD1. The first semiconductor pattern SP1 can connect the first source / drain patterns SD1 to each other.

[0105] The second source / drain pattern SD2 can be respectively disposed on both sides of the first semiconductor pattern SP1 of the second channel pattern CH2. The first semiconductor pattern SP1 can connect the second source / drain patterns SD2 to each other.

[0106] The gate electrode GE may be disposed on the first semiconductor pattern SP1. The spacer GS may be disposed on the side surface of the gate electrode GE. The spacer GS may include a first spacer GS1 and a second spacer GS2.

[0107] The first spacer GS1 may cover at least a portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. The second spacer GS2 may extend from the first spacer GS1 to a side surface covering each of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0108] The first source / drain pattern SD1 and the second source / drain pattern SD2, which are adjacent to each other, are spaced apart from each other by a distance SDI in the first direction D1. As semiconductor devices become increasingly integrated, the cell height of logic cells (e.g., HE1 in FIG1) is decreasing. The decrease in cell height can cause a decrease in the distance SDI between the source / drain patterns. Furthermore, the decrease in the distance SDI can increase the risk of process defects where the first source / drain pattern SD1 and the second source / drain pattern SD2 come into contact with each other.

[0109] Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a maximum width WM in the first direction D1. By reducing the maximum width WM of each of the first source / drain pattern SD1 and the second source / drain pattern SD2, the aforementioned distance SDI can be increased.

[0110] According to an embodiment, by performing a selective oxidation process on the first source / drain pattern SD1 and the second source / drain pattern SD2, the maximum width WM of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be reduced. This prevents process defects such as contact between adjacent source / drain patterns, thereby improving device reliability.

[0111] As shown in Figure 6B, according to an embodiment, spacers GS of the same shape can be achieved on both the PMOSFET region and the NMOSFET region. In other words, the spacer GS on the PMOSFET region may include a first spacer GS1 and a second spacer GS2, and the spacer GS on the NMOSFET region may also include the same first spacer GS1 and second spacer GS2 as the first spacer GS1 and second spacer GS2 on the PMOSFET region.

[0112] According to the embodiments, since the spacers GS on the PMOSFET / NMOSFET regions have the same structure, the electrical characteristics of the semiconductor device can be improved. Furthermore, process failures that may occur during the fabrication of spacers GS with the same structure on the PMOSFET / NMOSFET regions can be effectively prevented; for example, un-etch defects (where the second groove RS2 is not formed to a sufficient depth) or pitting failures (where the lower portion of the gate electrode GE penetrates the lower portion of the spacer GS and has a protruding shape) can be prevented. That is, the semiconductor device according to the embodiments can have high reliability.

[0113] Figures 7A, 7B, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 15D, 16A, 16B, 16C, 16D, 17A, 17B, 17C, and 17D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. Specifically, Figures 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 17A are sectional views corresponding to line A-A' in Figure 4. Figures 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, and 17B are sectional views corresponding to line B-B' in Figure 4. Figures 7B, 8B, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, and 17C are sectional views corresponding to line C-C' in Figure 4. Figures 8C, 9D, 15D, 16D, and 17D are sectional views corresponding to line D-D' in Figure 4.

[0114] Referring to Figures 7A and 7B, a substrate 100 is provided, comprising a first PMOSFET region PR1 and a second PMOSFET region PR2, and a first NMOSFET region NR1 and a second NMOSFET region NR2. A sacrificial layer SAL and an active layer ACL may be formed and alternately stacked on the substrate 100. The sacrificial layer SAL may be formed of or contain one of Si, Ge, and SiGe, and the active layer ACL may be formed of or contain the other of Si, Ge, and SiGe.

[0115] For example, the sacrificial layer SAL may be formed of or contain SiGe, and the active layer ACL may be formed of or contain Si. The Ge concentration of each in the sacrificial layer SAL may be in the range of about 10% to about 30%.

[0116] Masking patterns can be formed on the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2, of the substrate 100. The masking patterns can be linear or stripe patterns extending in the second direction D2.

[0117] A patterning process that uses a mask pattern as an etching mask can be implemented to form a trench TR defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 can be formed on each of the first PMOSFET region PR1 and the second PMOSFET region PR2. The second active pattern AP2 can be formed on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0118] A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP may include alternately stacked sacrificial layers SAL and active layers ACL. The stacked pattern STP can be formed by etching the sacrificial layers SAL and ACL, as well as the first active pattern AP1 and the second active pattern AP2, during the patterning process.

[0119] A device isolation layer ST can be formed to fill the trench TR. Specifically, an insulating layer can be formed on the substrate 100 to cover the first active pattern AP1, the second active pattern AP2, and the stacked pattern STP. The device isolation layer ST can be formed by recessing the insulating layer to expose the stacked pattern STP.

[0120] The device isolation layer ST may be formed of or contain at least one insulating material (e.g., silicon oxide). A stacked pattern STP may be positioned above the device isolation layer ST and may be exposed outside the device isolation layer ST. For example, the stacked pattern STP may protrude vertically above the device isolation layer ST.

[0121] Referring to Figures 8A to 8C, sacrificial patterns PP can be formed on substrate 100 to intersect with stacked patterns STP. Each of the sacrificial patterns PP can be a linear or stripe pattern extending in a first direction D1. The sacrificial patterns PP can be arranged at a specific pitch in a second direction D2.

[0122] In detail, the formation of the sacrificial pattern PP may include forming a sacrificial film on the substrate 100, forming a hard mask pattern MP on the sacrificial film, and using the hard mask pattern MP as an etching mask to pattern the sacrificial film. The sacrificial layer may be formed of or contain amorphous Si and / or polycrystalline silicon.

[0123] Spacers GS can be formed on the sacrificial pattern PP. The spacers GS may include a first spacer GS1 and a first disposable spacer DGS1 located on the first spacer GS1. In detail, the formation of the spacers GS may include conformally forming the first spacer GS1 on the substrate 100 and conformally forming the first disposable spacer DGS1 on the first spacer GS1.

[0124] Spacer GS may cover the opposite side surface of the sacrificial pattern PP. Spacer GS may cover the top surface of the device isolation layer ST and the surface of the stacked pattern STP. For example, the first spacer GS1 may be formed of or contain a low-dielectric-constant dielectric material containing Si (e.g., SiCON). The first disposable spacer DGS1 may be formed of or contain SiN.

[0125] Referring to Figures 9A to 9D, a first masking layer MAL1 can be formed on the first NMOSFET region NR1 and the second NMOSFET region NR2 of the substrate 100. As an example, the first masking layer MAL1 may include an amorphous carbon layer. The first masking layer MAL1 can be formed to expose the first PMOSFET region PR1 and the second PMOSFET region PR2.

[0126] A first groove RS1 can be formed by etching a portion of the stacked pattern STP located between sacrificial patterns PP on a first active pattern AP1 using a first mask layer MAL1 as an etching mask. The formation of the first groove RS1 may include etching the stacked pattern STP on the first active pattern AP1 using a hard mask pattern MP and spacers GS as etching masks. The first groove RS1 may be formed between a pair of sacrificial patterns PP.

[0127] During the formation of the first recess RS1, the upper portion of the spacer GS on the first PMOSFET region PR1 and the second PMOSFET region PR2 can be removed or recessed. Specifically, referring to FIG9C, the spacer GS on the first active pattern AP1 can be recessed to have a reduced height.

[0128] Because the spacer GS is recessed, a fence portion FEP can be formed covering the upper side surface of the first active pattern AP1. In one embodiment, the top surface of the fence portion FEP may be higher than the bottom surface of the first groove RS1. In another embodiment, the top surface of the fence portion FEP may be lower than the bottom surface of the first groove RS1. By changing the height of the fence portion FEP, the maximum width WM of the first source / drain pattern SD1 described above with reference to FIG6A can be adjusted. The greater the height of the fence portion FEP, the smaller the maximum width WM of the first source / drain pattern SD1. The smaller the height of the fence portion FEP, the greater the maximum width WM of the first source / drain pattern SD1.

[0129] A first semiconductor pattern to a third semiconductor pattern SP1, SP2 and SP3 can be formed from the active layer ACL on the first active pattern AP1 and sequentially stacked between adjacent first grooves RS1 in the first groove RS1. The first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3 between adjacent first grooves RS1 in the first groove RS1 can constitute a first channel pattern CH1.

[0130] Referring to Figures 10A to 10C, the first masking layer MAL1 can be selectively removed. Next, first source / drain patterns SD1 can be formed in the first groove RS1. Specifically, the first semiconductor layer SEL1 can be formed by performing a first SEG process using the inner surface of the first groove RS1 as a seed layer. The first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 exposed through the first groove RS1, and the substrate 100, can be used as seed layers to grow the first semiconductor layer SEL1. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0131] The first semiconductor layer SEL1 may be formed of or comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. The first semiconductor layer SEL1 may be formed to have a relatively low Ge concentration. In another embodiment, the first semiconductor layer SEL1 may be configured to comprise only Si and not Ge. The Ge concentration of the first semiconductor layer SEL1 may be in the range of about 0% to about 10%.

[0132] A second semiconductor layer SEL2 can be formed by performing a second SEG process on the first semiconductor layer SEL1. The second semiconductor layer SEL2 can be formed to completely fill the first groove RS1. The second semiconductor layer SEL2 can be configured to have a relatively high Ge concentration. As an example, the Ge concentration of the second semiconductor layer SEL2 can be in the range of about 30% to about 70%.

[0133] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can form a first source / drain pattern SD1. During the first and second SEG processes, the first semiconductor layer SEL1 and the second semiconductor layer SEL2 can be doped with impurities in situ. Alternatively, after forming the first source / drain pattern SD1, impurities can be doped into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type). During the first and second SEG processes, no semiconductor layer can be grown because the first NMOSFET region NR1 and the second NMOSFET region NR2 are covered by spacers GS.

[0134] After forming the first source / drain pattern SD1, a selective oxidation process can be performed to selectively oxidize the exposed surfaces of each of the first source / drain patterns SD1. As a result of the selective oxidation of the first source / drain pattern SD1, a first oxide layer OXL1 can be selectively formed on the surface of the first source / drain pattern SD1.

[0135] In one embodiment, the selective oxidation process of the first source / drain pattern SD1 may include a high-temperature thermal process using water vapor (H2O) and hydrogen (H2). In another embodiment, the selective oxidation process may include a plasma process using water vapor (H2O) and H2. The selective oxidation process may oxidize only the first source / drain pattern SD1 without oxidizing the first disposable spacer DGS1.

[0136] Figures 18A and 18B are cross-sectional views showing a portion "L" of Figure 10C according to an embodiment. The selective oxidation process of the first source / drain pattern SD1 will be described in more detail with reference to Figures 18A and 18B.

[0137] Referring to Figure 18A, a first semiconductor layer SEL1 can be formed on a first active pattern AP1 using a first SEG process, and a second semiconductor layer SEL2 can be formed on the first semiconductor layer SEL1 using a second SEG process. The first source / drain pattern SD1 may include a neck portion NEP surrounded by a gate portion FEP and a body portion BDP disposed on the neck portion NEP. The neck portion NEP can be formed during the SEG process by growing the first source / drain pattern SD1 along the gate portion FEP.

[0138] The body portion BDP may include a first facet FA1 as a {111} crystal facet. The first facet FA1 may extend from the uppermost portion FET of the gate portion FEP toward the edge ED. In other words, the first facet FA1 may not be offset from the uppermost portion FET of the gate portion FEP and may be very close to or in contact with the uppermost portion FET. The first source / drain pattern SD1 may have a first maximum width WM1.

[0139] Referring to FIG18B, a selective oxidation process can be performed on the first source / drain pattern SD1 to form a first oxide layer OXL1 on the first facet FA1 and the second facet FA2 of the first source / drain pattern SD1.

[0140] Since a first oxide layer OXL1 is formed as a result of oxidation of the exposed portion of the first source / drain pattern SD1, the size of the first source / drain pattern SD1 can be reduced. For example, each of the first facet FA1 and the second facet FA2 can be... <111> The height of the first source / drain pattern SD1 can be reduced in the direction of the decrease. The first source / drain pattern SD1 can have a second maximum width WM2 that is smaller than the first maximum width WM1.

[0141] Because the first small facet FA1 of the first source / drain pattern SD1 is in <111> The direction decreases, so the neck portion NEP can have a top surface NEP_T covered by the first oxide layer OXL1. The first facet FA1 can be offset from the uppermost portion FET of the gate portion FEP by means of the top surface NEP_T of the neck portion NEP.

[0142] According to an embodiment, the volume and maximum width of the source / drain patterns can be reduced by a selective oxidation process of the source / drain patterns. Since the volume of the source / drain patterns is reduced, the parasitic capacitance between the gate electrode and the source / drain patterns can be reduced, which makes it possible to improve the electrical characteristics of the semiconductor device. Furthermore, as a result of the reduced volume of the source / drain patterns, contact failure between adjacent source / drain patterns is prevented, thus improving the reliability of the semiconductor device and increasing its density.

[0143] Referring to Figures 11A to 11C, the first disposable spacer DGS1 can be selectively removed. Removal of the first disposable spacer DGS1 may include a phosphoric acid strip process for selectively removing the silicon nitride layer.

[0144] Simultaneously, phosphoric acid can be used to etch not only silicon nitride but also semiconductor materials (e.g., SiGe). According to an embodiment, a first oxide layer OXL1 can be formed on the exposed surface of the first source / drain pattern SD1 to protect the first source / drain pattern SD1 during the etching process. Therefore, process defects caused by unintentional etching of the first source / drain pattern SD1 during the removal process of the first disposable spacer DGS1 can be prevented, thereby improving the reliability of the semiconductor device.

[0145] Referring to Figures 12A to 12C, a second disposable spacer DGS2 can be conformally formed on the substrate 100. The second disposable spacer DGS2 can be formed of SiN or contain SiN. The second disposable spacer DGS2 can be formed on the remaining portion of the first spacer GS1, and the first spacer GS1 and the second disposable spacer DGS2 can constitute spacer GS.

[0146] A second masking layer MAL2 may be formed on the first PMOSFET region PR1 and the second PMOSFET region PR2 of the substrate 100. The second masking layer MAL2 may be formed to expose the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0147] The second groove RS2 can be formed by etching a portion of the stacked pattern STP located between sacrificial patterns PP on the second active pattern AP2 using a second masking layer MAL2 as an etching mask. The formation of the second groove RS2 may include etching the stacked pattern STP on the second active pattern AP2 using a hard masking pattern MP and spacers GS as etching masks. The second groove RS2 may be formed between a pair of sacrificial patterns PP.

[0148] During the formation of the second recess RS2, the upper portion of the spacer GS on the first NMOSFET region NR1 and the second NMOSFET region NR2 can be removed or recessed. Specifically, referring to FIG12C, the spacer GS on the second active pattern AP2 can be recessed to have a reduced height.

[0149] Because the spacer GS is recessed, a fence portion FEP can be formed covering the upper side surface of the second active pattern AP2. In one embodiment, the top surface of the fence portion FEP may be higher than the bottom surface of the second groove RS2. In another embodiment, the top surface of the fence portion FEP may be lower than the bottom surface of the second groove RS2. By adjusting the height of the fence portion FEP, the maximum width WM of the second source / drain pattern SD2 described above with reference to FIG6A can be controlled.

[0150] The height of the fence portion FEP on the second active pattern AP2 can be equal to or different from the height of the fence portion FEP on the first active pattern AP1 as described above with reference to FIG9C. The heights of the fence portions FEP on the first active pattern AP1 and the second active pattern AP2 can be adjusted independently.

[0151] The first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3 can be formed from the active layer ACL on the second active pattern AP2 and stacked sequentially between adjacent second grooves RS2 in the second groove RS2. The first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3 between adjacent second grooves RS2 in the second groove RS2 can constitute the second channel pattern CH2.

[0152] Referring to Figures 13A to 13C, the second masking layer MAL2 can be selectively removed. A second source / drain pattern SD2 can be formed in the second recess RS2. Specifically, the second source / drain pattern SD2 can be formed by performing a third SEG process in which the inner surface of the second recess RS2 is used as a seed layer. In an embodiment, the second source / drain pattern SD2 can be formed of or contain the same semiconductor material as the substrate 100 (e.g., Si).

[0153] The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type). During the third SEG process, no semiconductor layer can be grown because the first PMOSFET region PR1 and the second PMOSFET region PR2 are covered by spacers GS. Internal spacers IP can be formed between the second source / drain pattern SD2 and the sacrificial layer SAL, respectively.

[0154] After forming the second source / drain pattern SD2, a selective oxidation process can be performed to selectively oxidize the exposed surfaces of each of the second source / drain patterns SD2. As a result of the selective oxidation of the second source / drain pattern SD2, a second oxide layer OXL2 can be selectively formed on the surface of the second source / drain pattern SD2. In an embodiment, the second oxide layer OXL2 can be formed by a method substantially the same as that described above for the first oxide layer OXL1.

[0155] Referring to Figures 14A to 14C, the second disposable spacer DGS2 can be selectively removed. Removal of the second disposable spacer DGS2 may include a phosphoric acid stripping process for selectively removing the silicon nitride layer. As described above, during the phosphoric acid stripping process, the first source / drain pattern SD1 and the second source / drain pattern SD2 can be protected by the first oxide layer OXL1 and the second oxide layer OXL2, respectively.

[0156] In one embodiment, the first oxide layer OXL1 and the second oxide layer OXL2 may be selectively removed. In another embodiment, the first oxide layer OXL1 and the second oxide layer OXL2 may not be removed or may be retained.

[0157] The second spacer GS2 can be conformally formed on the substrate 100. The second spacer GS2 can be formed on the first spacer GS1 and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first spacer GS1 and the second spacer GS2 can constitute the spacer GS. The second spacer GS2 can be formed of or contain a material with good corrosion resistance (e.g., SiN).

[0158] Each of the aforementioned first disposable spacer DGS1 and second disposable spacer DGS2 can be used as an etching mask in the process of forming the first groove RS1 and the second groove RS2 and can be destroyed during this process. In the case where each of the first disposable spacer DGS1 and the second disposable spacer DGS2 is not removed and is used as spacer GS, the durability of spacer GS may deteriorate, and in this case, process defects may occur in subsequent processes.

[0159] According to an embodiment, after forming the first source / drain pattern SD1 and the second source / drain pattern SD2, a new second spacer GS2 with the same structure can be formed on the substrate 100. Therefore, a spacer GS with high durability can be achieved, preventing process defects in subsequent processes. Furthermore, since spacers GS of the same material and thickness are provided together in both the PMOSFET and NMOSFET regions, the uniformity of the electrical characteristics of the semiconductor device can be improved.

[0160] Referring to Figures 15A to 15D, a first interlayer insulating layer 110 can be formed to cover the hard mask pattern MP and the spacer GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0161] The first interlayer insulating layer 110 can be planarized to expose the top surface of the sacrificial pattern PP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or chemical-mechanical polishing (CMP). During the planarization process, all hard mask patterns MP can be removed. Therefore, the first interlayer insulating layer 110 can have a top surface that is coplanar with the top surface of the sacrificial pattern PP and the top surface of the spacer GS.

[0162] A photolithography process can be performed to selectively open areas of the sacrificial pattern PP. For example, a localized area of ​​the sacrificial pattern PP on the boundary of the first single-height cell SHC1 can be selectively opened. The opened areas of the sacrificial pattern PP can be selectively etched and removed. The gate cleaving pattern CT can be formed by filling the space created by removing the sacrificial pattern PP with an insulating material.

[0163] Referring to Figures 16A to 16D, the exposed sacrificial pattern PP can be selectively removed. As a result of removing the sacrificial pattern PP, an external region ORG (e.g., Figure 16D) can be formed exposing the first channel pattern CH1 and the second channel pattern CH2. The removal of the sacrificial pattern PP may include a wet etching process performed using an etching solution capable of selectively etching polycrystalline silicon.

[0164] The sacrificial layer SAL exposed via the outer region ORG can be selectively removed to form the inner region IRG (e.g., Figure 16D). Specifically, by performing a process that selectively etches the sacrificial layer SAL, the first to third semiconductor patterns SP1, SP2, and SP3 can be preserved while only the sacrificial layer SAL is removed. For materials with relatively high Ge concentrations (e.g., SiGe), an etching process with a high etch rate can be selected. For example, the etching process can have a high etch rate for Si-Ge with a Ge concentration higher than about 10%.

[0165] During the etching process, the sacrificial layer SAL on the first PMOSFET region PR1 and the second PMOSFET region PR2, as well as the first NMOSFET region NR1 and the second NMOSFET region NR2, can be removed. The etching process can be a wet etching process. The etchant material used in the etching process can be selected to quickly remove the sacrificial layer SAL with a relatively high Ge concentration. At the same time, the first source / drain pattern SD1 on the first PMOSFET region PR1 and the second PMOSFET region PR2 can be protected from the etching process by the first semiconductor layer SEL1 with a relatively low Ge concentration.

[0166] Because the sacrificial layer SAL is selectively removed, first semiconductor patterns to third semiconductor patterns SP1, SP2, and SP3 can be left on each of the first active pattern AP1 and the second active pattern AP2. The empty areas formed by removing the sacrificial layer SAL can respectively form first internal regions to third internal regions IRG1, IRG2, and IRG3. Specifically, the first internal region IRG1 can be formed between the active pattern AP1 or the active pattern AP2 and the first semiconductor pattern SP1, the second internal region IRG2 can be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third internal region IRG3 can be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0167] Referring to Figures 17A to 17D, a gate insulating layer GI can be conformally formed on the exposed first to third semiconductor patterns SP1, SP2, and SP3. A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE may include a first portion to a third portion PO1, PO2, and PO3 formed in the first to third inner regions IRG1, IRG2, and IRG3, respectively, and a fourth portion PO4 formed in the outer region ORG.

[0168] The gate electrode GE can be recessed to have a reduced height. During the recess of the gate electrode GE, the upper portion of the gate cut pattern CT can also be slightly recessed. A gate cap pattern GP can be formed on the recessed gate electrode GE.

[0169] Referring back to Figures 4 and 5A to 5D, a second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. The active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0170] A pair of segmented structures DB can be formed on both sides of each of the first single-height cell SHC1 and the second single-height cell SHC2. The segmented structures DB can penetrate the second interlayer insulating layer 120 and the gate electrode GE and can extend into the active pattern AP1 or the active pattern AP2. The segmented structures DB can be formed of or contain an insulating material (e.g., silicon oxide or silicon nitride).

[0171] A third interlayer insulation layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulation layer 130. A fourth interlayer insulation layer 140 may be formed on the third interlayer insulation layer 130. A second metal layer M2 may be formed in the fourth interlayer insulation layer 140.

[0172] Figures 19 and 20 are cross-sectional views showing a portion (e.g., portion L of Figure 5C) of a semiconductor device according to an embodiment. For the sake of precision, the elements described above with reference to Figures 4, 5A to 5D, 6A and 6B may be identified by the same reference numerals without being repeated.

[0173] Referring to Figure 19, the uppermost FET portion of the gate portion FEP of the first spacer GS1 may be located at a level equal to or lower than the bottom surface of the first recess RS1. The neck portion NEP of the first source / drain pattern SD1 may protrude vertically relative to the uppermost FET portion of the gate portion FEP. The side surface NEP_S of the neck portion NEP may not cover the gate portion FEP. The side surface NEP_S of the neck portion NEP may cover the second spacer GS2. The side surface NEP_S of the neck portion NEP and the side surface AP1_S of the first active pattern AP1 may be aligned with each other.

[0174] The first facet FA1 of the body portion BDP can be vertically spaced from the uppermost FET portion of the gate portion FEP. The side surface NEP_S of the neck portion NEP can be exposed between the first facet FA1 of the body portion BDP and the uppermost FET portion of the gate portion FEP. In other words, the first facet FA1 of the body portion BDP can be spaced from the uppermost FET portion of the gate portion FEP by means of the side surface NEP_S of the neck portion NEP.

[0175] The neck portion (NEP) of the first source / drain pattern SD1 may consist only of the first semiconductor layer SEL1. The body portion (BDP) of the first source / drain pattern SD1 may include the second semiconductor layer SEL2 and the upper portion of the first semiconductor layer SEL1.

[0176] In the case where the uppermost FET portion of the gate portion FEP is formed at a level equal to or lower than the bottom surface of the first groove RS1, a selective oxidation process as illustrated with reference to Figures 18A and 18B can be performed on the first source / drain pattern SD1, and in this case, the first source / drain pattern SD1 can have the structure of Figure 19.

[0177] Referring to Figure 20, the first oxide layer OXL1 can be sandwiched between the body portion BDP of the first source / drain pattern SD1 and the second spacer GS2. In other words, the first oxide layer OXL1 can directly cover the first facet FA1 and the second facet FA2 of the body portion BDP. The first oxide layer OXL1 can cover at least a portion of the top surface NEP_T of the neck portion NEP.

[0178] Unlike those illustrated with reference to Figures 14A to 14C, in cases where the process of removing the first oxide layer OXL1 and the second oxide layer OXL2 is not performed or the first oxide layer OXL1 and the second oxide layer OXL2 are not sufficiently removed, the first oxide layer OXL1 of Figure 20 may remain between the first source / drain pattern SD1 and the second spacer GS2.

[0179] Figure 21 is a cross-sectional view taken along line C-C' of Figure 4 to show a semiconductor device according to an embodiment. Referring to Figure 21, the spacer GS may include a first spacer GS1 and a second spacer GS2 located on the first spacer GS1. The first spacer GS1 may directly cover the surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. That is, the first spacer GS1 may not include the gate portion FEP of Figure 5C. The first spacer GS1 may extend from the upper side surface of the first active pattern AP1 and the second active pattern AP2 to the region on the first source / drain pattern SD1 and the second source / drain pattern SD2 without any cut-out portions.

[0180] Figures 22A, 22B, 23A, and 23B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment. Specifically, Figures 22A and 23A are cross-sectional views corresponding to line A-A' in Figure 4. Figures 22B and 23B are cross-sectional views corresponding to line C-C' in Figure 4.

[0181] Referring to Figures 22A and 22B, a first disposable spacer DGS1 and a second disposable spacer DGS2 can be sequentially formed on the sacrificial pattern PP. Unlike the structures illustrated in Figures 8A to 8C, the first spacer GS1 can be omitted. For example, the first disposable spacer DGS1 may be formed of or contain silicon nitride, and the second disposable spacer DGS2 may be formed of or contain silicon nitride.

[0182] Referring to Figures 23A and 23B, a first groove RS1 can be formed. After forming the first groove RS1, a second disposable spacer DGS2 can be selectively removed. The remaining portion of the first disposable spacer DGS1 can form the fence portion FEP.

[0183] Subsequently, a first source / drain pattern SD1 can be formed, a selective oxidation process can be performed on the first source / drain pattern SD1, and the remaining portion of the first disposable spacer DGS1 can be completely removed. The first disposable spacer DGS1 and the second disposable spacer DGS2 can be sequentially formed on the substrate 100.

[0184] The second source / drain pattern SD2 can be formed in the same manner as described above. After completely removing the disposable spacer, the first spacer GS1 and the second spacer GS2 can be sequentially formed on the substrate 100, as shown in FIG21. That is, in the manufacturing method according to this embodiment, by removing the used spacer and forming a new spacer after forming the first source / drain pattern SD1 and the second source / drain pattern SD2, the reliability of the device can be improved.

[0185] Figures 24A, 24B, 24C, and 24D are cross-sectional views of a semiconductor device according to an embodiment, taken along lines A-A', B-B', C-C', and D-D' of Figure 4, respectively. In the following description, for the sake of precision, the elements described above with reference to Figures 4 and 5A through 5D will be identified by the same reference numerals without repetition.

[0186] Referring to Figures 4 and 24A to 24D, the device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 in the upper portion of the substrate 100. The first active pattern AP1 may be defined on each of the first PMOSFET region PR1 and the second PMOSFET region PR2, and the second active pattern AP2 may be defined on each of the first NMOSFET region NR1 and the second NMOSFET region NR2.

[0187] The device isolation layer ST may cover the side surface of the lower portion of each of the first active pattern AP1 and the second active pattern AP2. The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude above the device isolation layer ST (e.g., FIG. 24D).

[0188] The first active pattern AP1 may include a first source / drain pattern SD1 disposed in the upper portion of the first active pattern AP1 and a first channel pattern CH1 disposed between the first source / drain patterns SD1. The second active pattern AP2 may include a second source / drain pattern SD2 disposed in the upper portion of the second active pattern AP2 and a second channel pattern CH2 disposed between the second source / drain patterns SD2.

[0189] Referring back to FIG24D, each of the first channel pattern CH1 and the second channel pattern CH2 may not include the stacked first to third semiconductor patterns SP1, SP2 and SP3 illustrated above with reference to FIGS. 5A to 5D. Each of the first channel pattern CH1 and the second channel pattern CH2 may resemble a single semiconductor pillar protruding above the device isolation layer ST.

[0190] Gate electrodes GE may be disposed on the top surface and opposite side surface of each of the first channel pattern CH1 and the second channel pattern CH2. In other words, the transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., a fin field-effect transistor, FinFET), wherein the gate electrode GE may be configured to surround the channel pattern in three dimensions.

[0191] A first interlayer insulating layer 110 and a second interlayer insulating layer 120 may be disposed on the substrate 100. The active contact AC may be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and be connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate contact GC may be configured to penetrate the second interlayer insulating layer 120 and the gate top cover pattern GP and be connected to the gate electrode GE. The active contact AC and the gate contact GC may be substantially the same as those in the embodiments described above with reference to Figures 4 and 5A to 5D.

[0192] A third interlayer insulating layer 130 may be disposed on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be disposed on the third interlayer insulating layer 130. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140. The first metal layer M1 and the second metal layer M2 may be substantially the same as the first metal layer M1 and the second metal layer M2 in the embodiments described above with reference to Figures 4 and 5A to 5D.

[0193] In the semiconductor device according to the embodiment, since the spacers are formed with the same multilayer structure on the PMOSFET / NMOSFET regions, the electrical characteristics of the semiconductor device can be improved. Furthermore, process failures that may occur during the fabrication of spacers with the same structure on the PMOSFET / NMOSFET regions can be effectively prevented, thereby achieving high reliability of the semiconductor device.

[0194] In detail, according to embodiments, a selective oxidation process can be performed on the source / drain patterns to remove disposable spacers and form new spacers. Therefore, process defects can be prevented and the volume and maximum width of the source / drain patterns can be reduced. Due to the reduced volume of the source / drain patterns, the parasitic capacitance between the gate electrode and the source / drain patterns can be reduced. Due to the reduced maximum width of the source / drain patterns, short-circuit failures where adjacent source / drain patterns contact each other can be prevented. Therefore, the electrical characteristics and reliability of the semiconductor device can be improved, and the integrated density of the semiconductor device can be increased.

[0195] According to some embodiments, a disposable spacer (e.g., SiN) is formed, and an oxide layer is formed to protect the source / drain epitaxial pattern when the disposable spacer is removed. Furthermore, an oxide layer can be formed on the epitaxial pattern to provide an epitaxial pattern with a unique structure. According to some embodiments, the MBCFET includes an embedded silicon-germanium (e-SiGe) epitaxial pattern spaced apart from the spacer, with the spacer's gate located at a level lower than the neck portion of the e-SiGe. The oxide layer is uniquely retained as a surface that directly covers the e-SiGe pattern.

[0196] At least one of the components, elements, modules, or units (collectively referred to as "components" in this paragraph) represented by the blocks in the diagram can be implemented as various numbers of hardware, software, and / or firmware structures to perform the corresponding functions described above. At least one of these components may use direct circuit structures such as memory, processors, logic circuits, lookup tables, etc., which can perform the corresponding functions by controlling one or more microprocessors or other control devices. Furthermore, at least one of these components may be implemented as a portion of a module, program, or code containing one or more executable instructions for performing the specified logical function and executed by one or more microprocessors or other control devices. Additionally, at least one of these components may include, for example, a central processing unit (CPU), a microprocessor, or other processor performing the corresponding function, or may be implemented by, for example, a central processing unit (CPU), a microprocessor, or other processor performing the corresponding function. Two or more of these components may be combined into a single component, which performs all the operations or functions of the combined two or more components. Furthermore, at least some of the functions of at least one of these components can be implemented by another of these components. The functional patterns of the above exemplary embodiments can be implemented by algorithms executed on one or more processors. Furthermore, the components represented by blocks or processing steps can employ any number of related technologies for electronics configuration, signal processing and / or control, data processing, etc.

[0197] Although the disclosed embodiments have been specifically shown and described, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims.

[0198] 100:Substrate 110: First interlayer insulation layer 120: Second interlayer insulation layer 130: Third interlayer insulation layer 140: Fourth interlayer insulation layer AC: Active contact element ACL: Active Layer AP1: First Active Pattern AP1_S: Side surface AP2: Second Active Pattern / Active Pattern BD1: First Boundary BD2: Second Boundary BD3: Third Boundary BD4: The Fourth Boundary BDP: body part BM: Barrier Pattern BS: Bottom surface CH1: First Channel Pattern CH2: Second Channel Pattern CT: Gate Cutting Pattern D1: First Direction D2: Second Direction D3: Third direction DB: Partition Structure DGS1: First Disposable Spacer DGS2: Second Disposable Spacer DHC: Highly Cellular Components ED: Edge FA1: First Minute FA2: Second side FEP: Fence section FET: Topmost part FM: Conductive pattern GC: Gate Contact GE: Gate electrode GE1, GE2: Gate electrodes GI: Gate Insulation Layer GP: Gate top cover pattern GS: Spacer GS1: First spacer GS2: Second spacer HE1: First Height HE2: Second Altitude IP: Internal Spacer IRG: Internal Region IRG1: First Internal Region IRG2: Second Internal Region IRG3: Third Internal Region L: Part M1: First metal layer M1_I: First internal connection / Internal connection M1_R1: First power line / internal connection M1_R2: Second power line / internal connection M1_R3: Third power cable / internal connection M2: Second metal layer M2_I: Second internal connection MAL1: First masking layer MAL2: Second masking layer M-M', N-N': Horizontal MP: Hard Mask Pattern NEP: Neck area NEP_S, SW1, SW2: Side surfaces NEP_T, TS: Top surface NR: N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region NR1: First NMOSFET region NR2: Second NMOSFET region ORG: External Region OXL1: First oxide layer OXL2: Second oxide layer PO1: Part 1 PO2: Part Two PO3: Part Three PO4: Part Four PP: Sacrifice Pattern PR: p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region PR1: First PMOSFET region PR2: Second PMOSFET region RS1: First Groove RS2: Second groove SAL: Sacrificial Layer SC: Silicone Pattern SD1: First source / drain pattern / source / drain pattern SD2: Second source / drain pattern / source / drain pattern SDI: Distance SEL1: First semiconductor layer SEL2: Second semiconductor layer SHC: Single-celled high-density cells SHC1: First high-level cell SHC2: Second high-level cell SP1: First semiconductor pattern SP2: Second semiconductor pattern SP3: Third Semiconductor Pattern ST: Device isolation layer STP: Stacked Pattern TR: Ditch UIP: Upper Insulation Pattern VDD: Drain Voltage VI1: First through hole VI2: Second through hole VSS: Source Voltage W1: First width WM: Maximum Width WM1: First maximum width WM2: Second Maximum Width

Claims

1. A semiconductor device, comprising: Active pattern, set on the substrate; A source / drain pattern is disposed on the active pattern; The channel pattern is configured to connect to the source / drain pattern; The gate electrode is configured to extend in a first direction and intersect the channel pattern; and a first spacer disposed on a side surface of the gate electrode, wherein the first spacer includes a fence portion disposed on a side surface of the active pattern and below the source / drain pattern, wherein the source / drain pattern includes a body portion and a neck portion between the body portion and the active pattern, wherein the body portion includes a crystalline surface configured to extend obliquely from the neck portion, wherein the crystalline surface is configured to be spaced apart from the uppermost portion of the fence portion, and wherein the neck portion includes a first portion and a second portion, the first portion being connected to the body portion, and the top surface of the neck portion at the second portion being exposed between the crystalline surface and the uppermost portion of the fence portion.

2. The semiconductor device of claim 1, further comprising a second spacer disposed on the first spacer, wherein the second spacer is configured to cover the top surface of the crystal surface and the neck portion.

3. The semiconductor device as claimed in claim 1, further comprising: A second spacer is disposed on the first spacer and the source / drain pattern; An oxide layer is disposed between the crystalline surface and the second spacer.

4. The semiconductor device as claimed in claim 3, wherein the oxide layer is configured to directly cover the crystalline surface.

5. The semiconductor device of claim 1, wherein a side surface of the neck portion is configured to align with a side surface of the active pattern, and wherein the fence portion of the first spacer is configured to cover the side surface of the neck portion and the side surface of the active pattern.

6. The semiconductor device of claim 1, wherein the neck portion is configured to project vertically relative to the uppermost portion of the gate portion, wherein the crystal surface is configured to be spaced apart from the uppermost portion of the gate portion, and wherein a side surface of the neck portion is disposed between the crystal surface and the uppermost portion of the gate portion.

7. The semiconductor device of claim 6 further includes a second spacer disposed on the first spacer, wherein the first spacer is configured to cover the side surface of the active pattern, and wherein the second spacer is configured to cover the side surface of the neck portion.

8. The semiconductor device of claim 1, wherein the channel pattern comprises a plurality of semiconductor patterns configured to be stacked and spaced perpendicularly to each other, and wherein the gate electrode is configured to surround each of the plurality of semiconductor patterns.

9. The semiconductor device of claim 1, wherein the neck portion of the source / drain pattern includes a first semiconductor layer, wherein the body portion of the source / drain pattern includes a second semiconductor layer, wherein the germanium concentration of the first semiconductor layer is from about 0% to about 10%, and wherein the germanium concentration of the second semiconductor layer is from about 30% to about 70%.

10. A semiconductor device, comprising: Active pattern, set on the substrate; A source / drain pattern is disposed on the active pattern; The channel pattern is configured to connect to the source / drain pattern; The gate electrode is configured to extend in a first direction and intersect the channel pattern; A first spacer is disposed on the active pattern; and a second spacer disposed on the source / drain pattern, wherein the source / drain pattern includes a body portion and a neck portion between the body portion and the active pattern, wherein the body portion includes a crystalline surface configured to extend obliquely from the neck portion, wherein the neck portion includes a first portion and a second portion, the first portion being connected to the body portion, the top surface of the neck portion at the second portion being exposed between the crystalline surface and the first spacer, and wherein the second spacer is configured to cover the top surface of the neck portion.

11. The semiconductor device of claim 10, wherein the channel pattern comprises a plurality of semiconductor patterns configured to be stacked and spaced perpendicularly to each other, and wherein the gate electrode is configured to surround each of the plurality of semiconductor patterns.

12. The semiconductor device of claim 10, wherein the first spacer includes a fence portion configured to cover a side surface of the neck portion, and wherein the uppermost portion of the fence portion is located at a level equal to or lower than the top surface of the neck portion.

13. The semiconductor device of claim 10, wherein the dielectric constant of the first spacer is less than the dielectric constant of the second spacer.

14. The semiconductor device of claim 10 further includes an oxide layer disposed between the crystalline surface and the second spacer.

15. A semiconductor device, comprising: A first active pattern and a second active pattern are respectively disposed on a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region and an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region of a substrate; a device isolation layer is configured to fill a trench between the first active pattern and the second active pattern; a first source / drain pattern and a second source / drain pattern are respectively disposed on the first active pattern and the second active pattern; a first channel pattern is disposed on the first active pattern and configured to be connected to the first source / drain pattern; a second channel pattern is disposed on the second active pattern and configured to be connected to the second source / drain pattern, wherein the first channel pattern includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern configured to be stacked sequentially and spaced apart from each other, and wherein the second channel pattern includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth semiconductor pattern configured to be stacked sequentially and spaced apart from each other; a gate electrode is configured to extend from a first region on the first channel pattern to a second region on the second channel pattern, and the gate electrode is configured to surround each of the first semiconductor pattern to the sixth semiconductor pattern; A gate insulating layer is disposed between the gate electrode and the first channel pattern and the second channel pattern; A spacer is disposed on the side surface of the gate electrode; a gate top cover pattern is disposed on the top surface of the gate electrode; a first interlayer insulating layer is disposed on the gate top cover pattern; and an active contact is configured to pass through the first interlayer insulating layer and is configured to couple to at least one of the first source / drain pattern and the second source / drain pattern. A gate contact is configured to pass through the first interlayer insulation layer and to be coupled to the gate electrode; A second interlayer insulating layer is disposed on the first interlayer insulating layer; a first metal layer is disposed in the second interlayer insulating layer, the first metal layer including a first interconnect configured to be electrically connected to the active contact and the gate contact; a third interlayer insulating layer is disposed on the second interlayer insulating layer; and a second metal layer is disposed in the third interlayer insulating layer, wherein the second metal layer includes a second interconnect configured to be electrically connected to the first interconnect, wherein the spacer includes a first spacer and a second spacer disposed on the first spacer, wherein the dielectric constant of the first spacer is less than the dielectric constant of the second spacer, wherein the first spacer is configured to extend from the side surface of the first active pattern to the side surface of the second active pattern while covering the top surface of the device isolation layer, wherein the second spacer is configured to extend along the first spacer from the first source / drain pattern to the second source / drain pattern, wherein the first source / drain pattern includes a body portion and a neck portion between the body portion and the first active pattern. The first spacer includes a fence portion configured to cover the side surface of the neck portion, wherein the body portion includes a crystalline surface configured to extend obliquely from the neck portion, and wherein the neck portion includes a first portion and a second portion, the first portion being connected to the body portion, and the top surface of the neck portion at the second portion being exposed between the crystalline surface and the uppermost portion of the fence portion.

16. The semiconductor device of claim 15, wherein the crystalline surface is configured to be spaced apart from the gate portion.

17. The semiconductor device of claim 15, wherein the second spacer is configured to cover the top surface of the neck portion.

18. The semiconductor device of claim 15, wherein the neck portion is configured to project perpendicularly relative to the gate portion, wherein the crystal surface is configured to be spaced apart from the gate portion, and wherein a side surface of the neck portion is disposed between the crystal surface and the gate portion.

19. The semiconductor device of claim 18, wherein the second spacer is configured to cover the side surface of the neck portion.

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