Magnetoresistive random-access memory cell and magnetoresistive random-access memory array including the same

Abstract

This invention provides a magnetoresistive random access memory (MRAM) cell and a MRAM array including the same. The MRAM cell includes a template layer. The template layer includes a binary alloy having an alternating layer lattice structure. The cell further includes a semi-metallic semi-Hausler layer, which includes a semi-metallic semi-Hausler material having a tetragonal lattice structure. The semi-metallic semi-Hausler layer is located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer is different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material. A tunneling barrier is located outside the semi-metallic semi-Hausler layer, and a magnetic layer is located outside the tunneling barrier.

Description

Technical Field

[0001] This invention relates generally to the electrical, electronic and computer fields, and more specifically to magnetoresistive random-access memory (MRAM) and MRAM arrays including the thereof. Prior Technology

[0002] Current MRAMs are three-layer devices employing magnetic tunnel junctions (MTJs). An MRAM typically includes a reference layer magnet, a tunneling barrier, and a storage or free magnetic layer. The magnetic layers can be ferromagnetic or subferromagnetic. Current flows through the device, and resistance is measured. The change in resistance based on the magnetic orientation of the two magnetic layers and the relative change in resistance is called tunnel magnetoresistance (TMR), which is related to spin polarization (i.e., high spin polarization means high TMR). High spin polarization and therefore high TMR are desirable (higher TMR provides a higher on / off ratio). Low switching current is also desirable. In a parallel configuration, the magnetic layers magnetize themselves to align with each other; the resistance is typically lower in this state compared to the antiparallel configuration. In the antiparallel state, the magnetic layers do not magnetize themselves to align with each other; the resistance is typically higher in this state compared to the parallel configuration. The MTJ changes its magnetic state by allowing current to pass through it. The current delivers spin angular momentum, causing the direction of the memory layer torque to switch once the threshold current is exceeded. Because these MRAM devices use spin transfer torque (STT) switching, they are called STT-MRAM. When the magnetization of the electrodes is oriented perpendicular to the layer, the required switching current is lower.

[0003] The current device uses an alloy of cobalt, iron, and boron for the magnetic layers, and these layers are ferromagnetic. Heusler compounds are magnetic intermetallic compounds (full-heusler or simply "heusler") with a face-centered cubic (FCC) crystal structure and an X2YZ composition, where X and Y are transition metals and Z is located in the p block (or group) of the periodic table. Half-heuslers have the composition XYZ. References to one or more heuslers without the term "half" are intended to refer to full-heuslers. Heusler compounds have four interpenetrating FCC sublattices (for the half-heusler compound XYZ, one FCC sublattice remains unoccupied). Summary of the Invention

[0004] The principles of this invention provide techniques for using tetragonal semimetallic haussler compounds in MRAM and the like. In one example, an exemplary magnetoresistive random access memory cell comprises: a template layer comprising a binary alloy having an alternating layer lattice structure; a semimetallic haussler layer comprising a semimetallic haussler material having a tetragonal lattice structure, the semimetallic haussler layer being located outside the template layer, and the in-plane lattice constant of the semimetallic haussler layer being different from the in-plane lattice constant of the cubic semimetallic haussler material; a tunneling barrier located outside the semimetallic haussler layer; and a magnetic layer located outside the tunneling barrier.

[0005] In another embodiment, the magnetoresistive random access memory (MRAM) array of this type of MRAM cell comprises: multiple bit lines and multiple complementary bit lines, forming multiple bit line-complementary bit line pairs; multiple word lines intersecting the multiple bit line pairs at multiple cell locations; and multiple MRAM cells, each located at one of the multiple cell locations. Each MRAM cell is electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under the control of a corresponding word line.

[0006] In another embodiment, a method of operating the array includes: providing the array; applying signals to word lines such that a first subset of the cells stores logic one and a second subset of the cells stores logic zero; and reading the stored logic one and logic zero via the bit lines and complementary bit lines.

[0007] In another embodiment, the method of forming a magnetoresistive random access memory cell includes: providing a template layer comprising a binary alloy having an alternating layer lattice structure and having an in-plane lattice constant of the template layer; epitaxially growing a semi-metallic semi-Hausler layer on the template layer, the semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material, the semi-metallic semi-Hausler layer being grown on the template layer such that the semi-Hausler material has a tetragonal lattice structure and an in-plane lattice constant of the semi-Hausler material, the in-plane lattice constant of the semi-Hausler material being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material and substantially matching the in-plane lattice constant of the template layer; forming a tunneling barrier outside the semi-metallic semi-Hausler layer; and forming a magnetic layer outside the tunneling barrier.

[0008] In another instance, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium. The HDL design structure comprises elements that generate a machine-executable representation of magnetoresistive random access memory units and / or arrays during processing in a computer-aided design system, as described.

[0009] As used herein, "facilitation" includes performing an action, making an action easier, assisting in the implementation of an action, or causing an action to be performed. Therefore, by way of example rather than limitation, instructions executed on a processor can facilitate actions performed by semiconductor processing devices by sending appropriate data or commands to cause or assist in the execution of an action. In cases where the actor performs facilitation actions other than performing an action, the action is still performed by some entity or combination of entities.

[0010] The techniques disclosed herein can provide substantial beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages may not be required in all embodiments. By way of example only and without limitation, one or more embodiments may provide one or more of the following: ▪ MRAM devices, in which the cells exhibit high spin polarization (by using a half-metal with spin polarization of one), and therefore exhibit high TMR and high on / off ratio. ▪ MRAM devices, in which cells exhibit low magnetization and therefore low switching current. ▪ MRAM devices, in which the magnetic layers of the cells exhibit perpendicular magnetic anisotropy (PMA), allow for scaling to a smaller size by using tetragonal semimetallic semi-Hausler compounds (tetragonal crystallization contributes to PMA). ▪ Manufacturing techniques that use an underlying layer (e.g., CoAl) to allow epitaxial growth of tetragonal semimetallic semihausler compounds.

[0011] These and other features and advantages will become apparent from the following detailed description of their illustrative embodiments, which will be read in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0012] The following diagrams are presented by way of example only and are not restrictive, wherein in several views, the same reference numerals (when used) indicate corresponding elements, and wherein: Figure 1 shows the semi-Hausler compound used in the present invention. Figure 2 illustrates the growth of a Haussler compound on a template layer according to the present invention (also illustrating the growth of a semi-Haussler compound on a template layer according to the present invention). Figures 3A, 3B, and 3C present a table of semi-metallic semi-Hausler compounds that can be used in MRAM in tetragonal form according to the present invention. Figures 4 and 5 respectively depict ferromagnetic half-metallic half-Hausler compounds and subferromagnetic half-metallic half-Hausler compounds that can be used in MRAM according to the present invention. The tetragonal unit cells shown in Figures 4 and 5 are rotated 45° about the z-axis relative to the parent cubic structure shown in Figure 1. Figures 6 and 7 depict the density of state (DOS) of the two compounds described in Figures 4 and 5, respectively. Figure 8 reproduces portions of Figures 3A to 3C of the selected list of compounds with strong PMA. Figure 9 illustrates a non-limiting example of a chemical template layer applicable to one or more embodiments. Figure 10 shows a first exemplary MRAM cell according to the present invention. Figure 11 shows a second exemplary MRAM cell according to the present invention. Figure 12 shows an MRAM cell array according to the present invention. Figure 13 shows a flowchart of a method for manufacturing a sample according to the present invention. Figure 14 depicts a computer system applicable to implementing one or more forms and / or elements of the present invention. Figure 15 is a flowchart of the design process used for semiconductor design, manufacturing and / or testing. It should be understood that the elements in the drawings are shown for simplicity and clarity. Common but easily understood elements that may be useful or necessary in commercially viable embodiments may not be shown in order in order to facilitate a less obstructed view of the illustrated embodiments. Implementation

[0013] The principles of the invention described herein will be understood in the context of the illustrative embodiments. Furthermore, given the teachings herein, it will be apparent to those skilled in the art that numerous modifications can be made to the illustrated embodiments within the scope of the claims. That is, no limitation is intended or should be inferred regarding the embodiments shown and described herein.

[0014] We have identified tetragonal semi-Hausler compounds as a focus for MRAM applications. Current MRAM devices use magnetic tunneling junctions (MTJs) as storage elements. A simple MTJ is a three-layer structure containing two magnetic layers separated by a tunneling barrier layer. Current MTJs using cobalt-iron-boron (Co / Fe / B) can provide magnetic layers with magnetization perpendicular to the film surface (i.e., exhibiting the desired perpendicular magnetic anisotropy (PMA)). The perpendicular magnetic anisotropy (PMA) of the Co-Fe-B layers arises from the interface between these layers and the tunneling barrier and / or the underlying layer, on which the Co-Fe-B layers are deposited. Therefore, these layers should be made thin enough that the interface PMA overcomes the demagnetization energy caused by the magnetic volume and increases proportionally to the magnetic volume of the Co-Fe-B layers. However, the high torque of these layers requires high switching current. One or more embodiments advantageously provide PMA, but with lower torque and therefore reduced switching current compared to prior art devices.

[0015] The desired magnetic material has a volumetric PMA rather than a surface (interface) PMA, because this allows for scaling the device to smaller sizes (typically smaller diameters). As the device size decreases, the device becomes less thermally stable. However, for devices with volumetric anisotropy, it is advantageously possible to compensate for the decrease in thermal stability by increasing the thickness. The switching current is proportional to the product (Ms V Hk), where Ms is the saturation magnetization, V is the volume, and Hk is the anisotropic field. Unless the increase in Hk outweighs the lower Ms, low-torque (i.e., low-Ms) semi-Hausler compounds require a lower switching current.

[0016] Therefore, for MRAM applications, it is desirable for all magnetic elements to have their torque perpendicular to the layer itself (i.e., magnetization perpendicular to the film plane – PMA caused by the crystal structure). Low magnetization and low switching current are required. We have found that one way to achieve PMA is by using a semi-Hausler compound. Typically, semi-Hausler compounds tend to be cubic. Therefore, the thin film is grown, and the magnetic moment will be located in the plane of the layer. For MTJs used in MRAM applications, it is particularly desirable for the magnetic moment of the magnetic layer to be perpendicular to the layer. The way to induce PMA in a semi-Hausler layer is to modify the compound from a cubic crystal form to a tetragonal crystal form. Instead of making all three unit axis lengths the same, if one of the axes is slightly longer (or shorter), then the magnetization can be perpendicular due to the breaking of crystal symmetry. It is worth noting that since the unit cells of the semi-Hausler materials discussed elsewhere in this paper with respect to Figures 4 and 5 are not simple crystals with only a single element, the parameter c' discussed elsewhere in this paper is relevant (c=a, a simple relationship for cubic crystals, is not suitable for such units with multiple elements). In the case of tetragonal crystals, one of the axes is elongated (or shortened) relative to the cubic crystal case. Figure 1 depicts the state of cubic semi-Hausler compounds and the in-plane lattice constant acub. The volume PMA is required because it is difficult to scale the surface (interface) PMA to small units, and our calculations indicate that the volume PMA can be advantageously scaled to a smaller size. As discussed elsewhere in this paper, in the case of tetragonal crystals, the Z (vertical) axis is "stretched" (and may also shrink in alternative methods) relative to the cubic crystal case. Due to the bulk concentration, magnetization tends to be perpendicular to the film (i.e., along the z-axis). If a semi-Hausler layer is grown on a suitable template layer using a z-axis perpendicular to the (xy) plane, the Hausler layer will have a torque perpendicular to the (xy) plane of the film.

[0017] Half-metallic (HM) magnetic materials are materials with a band gap at Fermi energy EF in one spin channel, thus DOS(spin1, EF) = 0, and a normal metallic DOS: DOS(spin2, EF) > 0 in the other spin channel (DOS = density of states). Theoretically, such materials would produce infinite TMR when used as electrodes in MRAM devices. Unfortunately, all known half-metallic hausler compounds are cubic crystals with zero volume anisotropy (attributed to symmetry); this makes them unsuitable for practical STT-MRAM devices. By using a suitable template layer, the hausler compound can be strained in a plane, which can induce tetragonal crystallinity. Tetragonal crystallinity implies the presence of PMA, indicating suitability for vertical MTJs. If the half-metallicity of the hausler compound allows for in-plane strain stability, the TMR from these vertical MTJs can be high, as desired.

[0018] Further regarding half-metallicity, each material possesses both an up-spin and a down-spin. If a band gap exists in one of the spin channels, then at the Fermi level, if current flows, only one spin electron moves. Half-metals are highly suitable for achieving high TMR. One or more embodiments prepare cubic compounds into tetragonal compounds via epitaxy. The material is deposited on a template layer (in a non-limiting example, a chemical template layer), which forces the in-plane lattice constant to differ from the out-of-plane lattice constant. This results in tetragonal crystallization. One or more embodiments ensure that half-metallicity is still maintained (i.e., a band gap exists in one of the spin channels). We have discovered a variety of semi-metallic Hausler compounds. There are approximately three thousand semi-Hausler compounds. Less than one hundred and fifty of these semi-Hausler compounds are half-metallic. Only a few of these semi-Hausler compounds can be prepared into tetragonal crystals while maintaining their half-metallic properties, resulting in perpendicular magnetic anisotropy, i.e., magnetization perpendicular to the film. These few Haussler compounds are advantageous for use in MRAM and may have high TMR.

[0019] One or more embodiments involve varying the in-plane lattice constants of known half-metallic cubic half-Hausler compounds using different template layers, such that these half-Hausler compounds become tetragonal with non-zero volume anisotropy. The template layer can be, for example, a non-magnetic binary compound (e.g., CoAl with an in-plane lattice constant α = 4.04 Å) and the half-metallic magnetic half-Hausler compound can be, for example, a known ternary compound (e.g., RhCrGe with acub = 4.07 Å, NiMnSi with acub = 3.86 Å, RhFeSn with acub = 4.28 Å, or NiVSn with acub = 4.15 Å). When the ternary compound is epitaxially grown on the CoAl layer, the ternary compound strains. If the variation in the in-plane lattice constant is not significant (e.g., within 5% of the self-balancing cubic lattice constant), our calculations indicate that the half-metallicity may be preserved, at least for some of the half-Hausler compounds. Therefore, using density-functional theory (DFT) calculations, we have identified several tetragonal semi-Hausler compounds that are still semimetallic and exhibit non-zero volume anisotropy. Furthermore, semimetallic semi-Hausler compounds are well-known in this regard. However, to date, all known semimetallic semi-Hausler compounds have exhibited cubic lattice structures and therefore do not exhibit PMA. We have discovered that semimetallic semi-Hausler compounds with tetragonal lattice structures can be obtained by growth on a template layer, thus producing PMA. We have found that growing on a template layer by "extruding" or "stretching" the lattice constant in one direction to obtain the desired tetragonal lattice structure while maintaining semimetallic properties (e.g., "extruding" in x and y and "stretching" in z). Based on our calculations, high TMR is expected for such compounds when the template layer is used as the substrate for epitaxial growth.

[0020] One or more embodiments advantageously fabricate tetragonal semimetallic hausler compounds with non-zero anisotropy by using a substrate (e.g., CoAl) with a different in-plane lattice constant (compared to a cubic form) to achieve volume anisotropy relative to interfacial anisotropy. One or more embodiments use a hausler semimetal compound. In one or more embodiments, the hausler semimetal compound is grown on a general substrate, which may be, for example, a nonmagnetic metal (e.g., CoAl) or a magnetic metal (e.g., cubic Co₂MnSi, which is also a hausler semimetal), and thus, the tetragonal hausler semimetal can serve as the bottom electrode of an MRAM cell. On the other hand, in one or more embodiments, the hausler semimetal compound is grown on a semiconductor barrier (e.g., MgO), and thus, the tetragonal hausler semimetal can serve as the top electrode of an MRAM cell. Refer to Figures 3A, 3B, and 3C. The parameter a_cub is the in-plane cubic lattice constant (also referred to as acub in this paper) applicable to half-metals exhibiting cubic crystal form. If this a_cub value can vary by, for example, + / - 0.3 Å or + / - 10% and the compound still remains half-metallic, then the compound is considered to exhibit robust half-metallicity and may be grown on the template layer to achieve tetragonal crystal form without losing its half-metallicity.

[0021] It is worth noting that a half-metal is a substance that acts as a conductor for electrons with one spin orientation, but as an insulator or semiconductor for electrons with a relatively oriented spin. Half-metals are known to be ferromagnetic (or subferromagnetic). In a half-metal, the valence band for one spin orientation is partially filled, while gaps exist in the density of states for the other spin orientation. This results in conductivity only for electrons in the first spin orientation. In some half-metals, most of the spin channels are conductive, while in others, only a few channels are conductive.

[0022] We have identified nineteen semimetallic hausslers that retain their semimetallic nature when the in-plane lattice constant α varies within 0.50 Å (or 5%) of the corresponding cubic lattice constant acub. These compounds possess extremely stable semimetallic properties that are difficult to be destroyed by variations in the lattice constant within 10% of acub.

[0023] Referring again to Figure 1, consider the state of the chemical template layer. A semi-Hausler compound XYZ, such as Mn₂As, contains alternating layers of Mn-Mn and Mn-As atoms. In Figure 1, shaded atom 101 represents an As atom (main group), shaded atom 103 represents a Mn atom at the Y-position in XYZ (via a tetrahedron coordinated by Z), and shaded atom 105 represents an elemental Mn atom at the X-position in XYZ (via an octahedron coordinated by Z). Mn is a transition metal and As is from a main group of the periodic table. One of the alternating layers contains only transition metal atoms 103, while the other contains both main group element atoms 101 and transition metal atoms 105. Therefore, a seed layer containing a single element with a lattice constant in the lattice-matching plane does not promote the growth of ordered semi-Hausler compounds at low temperatures, such as room temperature. An ideal seed layer contains a binary compound containing both transition and main group elements. Furthermore, this ideal seed layer also possesses an alternating layer structure containing these two different elements. One layer contains only transition metals. The other layer contains only main group metals (the "Z" in XYZ is also a main group metal). These binary compounds have a CsCl-like (cesium chloride-like) structure (where each cesium ion is coordinated by eight chloride ions). Exemplary template layers include CoAl, CoGa, and their analogues.

[0024] Referring now to Figure 2, one or more embodiments employ a CsCl-type chemical templating layer (CTL) 401 (CoAl is an excellent example of a CsCl-type CTL), which promotes the growth of ordered Haussler compounds even at ultrathin thicknesses and at room temperature. "E" can correspond to, for example, Al, and "A" can correspond to, for example, Co. In Figure 2, view 421 is a schematic diagram, while view 423 is a transmission electron microscopy (TEM) image. In the example of Figure 2, a full Haussler compound 403, such as Mn3Sb, is epitaxially grown on top of the CoAl layer 401; however, this example is equally effective for semi-Haussler materials (as previously described, which have an alternating layer structure, one layer containing transition metal atoms and another layer containing transition metals and main group atoms). The in-plane lattice constant of ultrathin (<approximately 25 Å) full Haussler compounds is similar to that of the CoAl CTL. It is possible to strain full-Hausler (or semi-Hausler) materials to varying degrees with appropriate selection of the CTL. We have found that even ternary full-Hausler or semi-Hausler compounds can be sequenced by CTL. As shown, Mn (typically X) is grown on Al and Ge (typically Z) is grown on Co. Note the atomic step 405. Full-Hausler (or semi-Hausler) materials can be strained and therefore employ the in-plane lattice constant of the template material. One or more embodiments apply the lattice constant of the template layer to the Hausler (or semi-Hausler) layer. In view 423, note that CoAl 401 comprises an Al layer 409 and a Co layer 411, and MnSb comprises an MnMn layer 413 and a MnSb layer 415. Note the MgO tunneling barrier 407.

[0025] We detected that 150 cubic semi-Hausler compounds, as claimed in the literature, are theoretically half-metals (HM). As needed, we used both the DFT / Generalized Gradient Approximation (GGA) and the DFT / Local Density Approximation (LDA) methods in our calculations, and found that some of these compounds are indeed HMs, some are not HMs but have large spin polarization, and some are not HMs but have relatively small spin polarization. Specifically, based on the 150 compounds studied, as depicted in Figures 3A, 3B, and 3C, it should be noted that 58 compounds have 100% spin polarization (true half-metals), 51 compounds are ferromagnetic, 25 compounds exhibit PMA, and 19 compounds remain half-metals when the in-plane lattice constant α varies by up to 0.50 Å around the corresponding cubic lattice constant acub. These compounds exhibit extremely stable half-metallic properties, which are difficult to disrupt by lattice constant variations within approximately 10% of acub. In Figures 3A, 3B, and 3C, the first row lists the relevant half-metallic Haussler compounds. Except for seven subferromagnetic compounds: CoCrGe, CoMnGe, MnMnAs, FeCrAs, RuCrAs, CoCrAs, and MnVAs, all compounds presented in Figure 3 are ferromagnetic. The second row lists compounds defined as ac = acub / The ac parameter. If this ac value can vary by, for example, + / - 0.3 Å or + / - 10% and the compound still remains half-metallic, then the compound is considered to exhibit robust half-metallicity and may grow on a template layer to achieve tetragonal crystallization without losing its half-metallicity. The third line shows the total torque mtot. This total torque remains unchanged when the in-plane lattice constant varies within the half-metallic range. The fourth line shows Egap, which is the band gap value. The fifth line lists TC, which is the Curie temperature calculated for the ground-state cubic crystallization structure of the half-metallic half-Hausler. The sixth and seventh lines list amin and amax, which are the minimum and maximum values ​​of the in-plane lattice constant a, where the tetragonal deformed compound is half-metallic (as mentioned above, when a varies between amin and amax, the total magnetic moment of the compound does not change). The eighth line contains whm, which is equal to amax-amin, the width of the half-metallic range. Rows 9 and 10 contain aopt and c'opt, which are the optimal in-plane lattice constant and the corresponding scale-free, dimensionless out-of-plane lattice constant c'opt = copt / (2aopt). These lattice constants provide the maximum volume magnetic anisotropy constant Kv (aminaopt amax) for a in the half-metallic range. Here, copt is the optimal out-of-plane lattice constant c shown in Figure 4. Row 11 shows Kv, which is the volume magnetic anisotropy constant calculated for the optimal lattice constant aopt. The tables shown in Figures 3A, 3B, and 3C only include compounds with PMA (Kv > 0). The last row lists the spin-polarized SP and is 1.00 for all compounds included in Figures 3A, 3B, and 3C because these compounds are half-metals. In Figures 3A, 3B, and 3C, the compounds are ordered by the width of the half-metal range whm. This is because the larger whm and band gap Egap are, the more stable the half-metal properties of the compounds are with respect to various effects (the changes in in-plane and out-of-plane lattice constants, the details of the calculation method, the selected DFT function, the finite temperature effect, impurities, dislocations, etc.).

[0026] We identified fifty-six compounds that remain half-metals when α changes by up to 0.30 Å near acub (all of these compounds are highlighted in the eighth row of Figures 3A to 3C). These compounds exhibit extremely stable half-metallicity, which is difficult to be disrupted by changes in the lattice constant (in all directions) within 10% of acub. Our calculations indicate that most of the promising candidates for electrodes in the MRAM device are NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, RhCrGe, CoCrGe, RhFeSn, NiVSn, RuCrAs, CoCrAs, and CsSrSn, which have 100% spin polarization and anisotropy constant Kv >= 0.19 mJ / m³ at the optimal in-plane lattice constant. The chemical sequence of RhFeGe, RhCrGe, CoCrGe, RhFeSn, NiVSn, RuCrAs, and CoCrAs, which contain transition elements and main group elements, is described in Figure 2. The other listed compounds contain another metal atom, or in some cases two metal atoms, replacing transition metal atoms along with main group element atoms. The chemical template layer should also facilitate chemical sequencing within these sets of compounds.

[0027] It should be understood that Kv is suitable to be greater than zero, and higher values ​​are preferred. Therefore, the table highlights all Kv values ​​≥ 0.19 mJ / m³. In one or more embodiments, the spin polarization SP = 1.

[0028] Referring now to Figures 4 and 5. Figure 4 shows RhFeSn, an example of a ferromagnetic half-metallic half-Hausler. In Figure 4, note the absence of 601, Fe 602, Sn, and Rh. Figure 5 shows CoCrAs, an example of a subferromagnetic half-metallic half-Hausler. In Figure 5, note the absence of 601, Cr 612, As 613, and Co 611. In Figures 4 and 5, the arrows indicate the magnetic moments on individual atoms. The tetragonal unit cells shown in Figures 4 and 5 are rotated 45° about the z-axis relative to the parent cubic structure shown in Figure 1. (Note that only some atoms from Figure 1 are shown in Figures 4 and 5.) The lattice constants acub of the cubic half-Hausler material are shown in Figure 1, and the lattice constants a and c of the tetragonal half-Hausler material are shown in Figure 4. For a cubic crystal structure, the relationship between the in-plane lattice constant *a* shown in Figure 4 and the lattice constant *acub* shown in Figure 1 is: *ac* = *acub* / For the properties of the tetragonal unit cell, we use the size-free parameter c' = c / (2a), which is equal to 1 / of the size-free parameter of the cubic structure. Figures 6 and 7 show the density of states (DOS) of the two compounds described in Figures 4 and 5. For both compounds, a significant small band gap exists at the Fermi level. Figures 6 and 7 plot the DOS in states / eV versus E-EF in eV.

[0029] As mentioned, the tetragonal form can be produced by growth on a suitable template layer. By way of review, in the template concept, a template layer is grown and another layer (e.g., a Haussler or semi-Haussler compound) is grown on top of the template layer. The template essentially means the lattice constant a of the layer grown on the template layer up to the bottom / seed layer. Similar to Poisson's ratio, changing a also changes c; if a shrinks, c increases (and conversely, if a grows, c shrinks). Since the lattice constant a of the semi-metallic semi-Haussler layer is greater than the lattice constant (aTL) of the template layer, the template layer is rotated 45º to match the lattice of the semi-metallic semi-Haussler layer. Referring to Figure 9, we define aTL' as Sqrt(2)*aTL for the following discussion. Consider a semi-metallic semi-Haussler CoCrAs grown on a CoAl template layer. Since a decreases from 3.57 Å in the cubic form to 4.04 Å in the tetragonal form, c decreases. The material attempts to preserve its unit cell volume. Referring again to Figure 2, CoAl has a layered structure. In Haussler compound 403 (also representing semi-Haussler), the all-Mn layer, due to its presence of only transition metals, prefers to grow on the Al of the template layer, while the MnSb layer, due to its presence of main group elements, prefers to grow on Co, and thus acquires ordering in material 403. Atomic steps 405 are inherent to the template layer 401 but do not interfere with the ordering in Haussler material 403 (also representing semi-Haussler).

[0030] Figure 8 shows the semimetallic semi-Hausler compounds with optimal in-plane lattice constants for high PMA. It should be noted that Figure 8 reproduces a portion of the selected list of compounds with strong PMA (Kv ≥ 0.19 mJ / m³) from Figures 3A to 3C; it should also be noted that Figure 8 includes CoCrGe with Kv = 0.2 mJ / m³ due to rounding instead of Kv = 0.19 mJ / m³ listed in Figure 3B. It should be noted that for all these compounds, Eg > 0.4 eV and whm ≥ 0.34 Å, except for RhFeGe with whm = 0.20 Å. Therefore, these compounds exhibit robust semimetallic properties.

[0031] Figure 9 illustrates candidate CTL materials. It should be noted that the in-plane lattice constant aTL of several CTL materials can be tuned across a wide range of values. These aTL values ​​can also be further adjusted using strain induced from the underlying seed layer and / or by variations in the composition from its nominal 1:1 value. In one or more embodiments, different lattice constants can be “mixed and matched.” Further regarding “mixing and matching,” it should be noted that, for example, CoAl has a lattice constant of 2.86 Å, while RuAl has a lattice constant of 2.95 Å. In principle, if a semi-Hausler compound is grown on RuAl, the semi-Hausler compound will attempt to conform to the RuAl lattice constant and will therefore be stretched in a different manner than when grown on CoAl. That is, the degree of tetragonal elongation depends on the substrate on which the tetragonal semi-Hausler material is grown.

[0032] Figure 10 illustrates an embodiment with a semi-metallic semi-Hausler compound as a storage layer 1205. A seed layer 1203 will typically comprise a CTL and is located on a substrate 1201. The substrate 1201 is typically silicon with CMOS circuitry, such as transistors and access lines that allow selection of individual devices. In addition to the novel cells described herein, conventional transistors, access lines, peripheral circuitry, and the like may be used, referring to the discussion in Figure 12 below. The CTL or even multiple CTLs may be grown on a suitable surface, such as, where possible, directly above the substrate, or more typically on a seed layer deposited on the substrate. Non-limiting examples of seed layers include tantalum, tantalum-ruthenium, chromium, manganese, manganese nitride, or the like. The semi-metallic semi-Hausler layer 1205 is located on the CTL and may be formed, for example, by epitaxial growth on the CTL. A polarization enhancement layer 1207 is located outside layer 1205, and layer 1207 (when present) may comprise a thin layer of a magnetic material such as cobalt. A tunneling barrier 1209 is located outside layer 1207 (if present), or otherwise outside layer 1205; barrier 1209 may comprise, for example, MgO, MgAl2O4, or similar materials. Magnetic layer 1211 comprises known cobalt, iron, nickel, or alloys, or may also comprise Hausler or semi-Hausler materials. A synthetic antiferromagnet (SAF) layer 1213 (if present) is located outside layer 1211. Typically, the synthetic antiferromagnetic layer (SAF) comprises a Co / Pt multilayer (not shown) magnetically coupled to an underlying magnetic layer to achieve the desired performance. A thin layer of Ta, Ir, or Ru (approximately several angstroms) (not shown) may typically be inserted between the magnetic layer and the SAF layer. A capping layer 1215 is located outside layer 1213 (if present), or otherwise outside layer 1211. The capping layer may comprise Mo, W, Ta, Pt, Ru, or combinations thereof. In Figure 10, double-headed arrow 1221 indicates a storage layer where magnetization can be changed, while single-headed arrow 1223 indicates a reference layer with constant / fixed magnetization.

[0033] Figure 11 illustrates an embodiment with a semi-metallic, semi-Hausler compound as a reference layer. A seed layer 1303 will typically comprise a CTL and is located on a substrate 1301. A semi-metallic, semi-Hausler layer 1305 is located on the CTL and can be formed, for example, by epitaxial growth on the CTL. A polarization enhancement layer 1307 is located outside layer 1305, depending on the situation. A tunneling barrier 1309 is located outside layer 1307 (if present), otherwise outside layer 1305. A magnetic layer 1311 comprises conventional cobalt, iron, nickel, or an alloy, or may also comprise a Hausler or semi-Hausler material. A capping layer 1313 is located outside layer 1311. In Figure 11, a double-headed arrow 1323 indicates a storage layer where magnetization can be varied, while a single-headed arrow 1321 indicates a reference layer with constant / fixed magnetization. The notes regarding the materials in Figure 10 generally also apply to Figure 11.

[0034] In both Figures 10 and 11, the semi-Hausler layer is typically located on top of the template layer due to epitaxial growth during the manufacturing process.

[0035] We have thus identified forty-five semimetallic haussler compounds that remain semimetallic even when subjected to nearly 10% significant in-plane lattice strain (with strain varying by up to 0.50 Å near acub). These compounds are KCrTe, NaCsP, NaCsAs, CsRbAs, CsRbN, NaKP, CsRbP, KCaGe, RbCrTe, CsBaC, LiSrGe, RbSrGe, KCaSn, KCaSi, NaVSi, RbSrSi, RbSrB, NaCaGe, KSrB, KTaSn, RbTaGe, CsSrSn, CsVS, RbSrC, CsSrC, RbTaSi, KBaB, CoVSb, RbNbSn, RbNbSi, KMgGe, MnMnAs, RbCaB, CsSrGe, CoCrAs, LiBaGe, CoCrSb, NaCaSn, CoCrGe, RhVAs, CsNbSn, CsNbSi, CsNbGe, NiMnSi, and RhCrGe. These compounds exhibit extremely stable semimetallic properties that are difficult to disrupt due to changes in lattice constant (in all directions). Experimentally, such strain can be achieved by epitaxial growth of these compounds on CTLs (such as CoAl).

[0036] Our calculations indicate that the majority of promising electrode candidates for the MRAM device are KCrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn, all of which possess 100% spin polarization and anisotropy constants of Kv >= 0.19 mJ / m³ at the optimal in-plane lattice constant. Twenty-three of these twenty-five compounds are ferromagnetic. Twenty-one of these twenty-five compounds exhibit stable half-metallic properties that are difficult to disrupt by variations in the lattice constant (strain can vary by up to 0.50 Å near acub). Sixteen of these twenty-five compounds have low torque (m = 1.0 µB / form_unit), comparable to that of Mn3Ge (m = 1.0 µB / form_unit, where form_unit represents "formula unit").

[0037] One or more embodiments therefore include an apparatus, which in turn includes a multilayer structure (e.g., Figures 10 and 11). The multilayer structure includes a first layer that is nonmagnetic at room temperature, comprising a binary alloy having a CsCl structure with a target in-plane lattice constant (e.g., CTL of 1203, 1303). It also includes second layers 1205 and 1305 having a semi-metallic semi-Hausler compound whose magnetization is substantially perpendicular to the layers. As those skilled in the art will understand, typically, the magnetization is not fixed, but rather precesses like a spin gyroscope at non-zero temperatures. This can vary depending on temperature. Given this precession, as used herein, perpendicularity refers to the perpendicularity of the time integral / average value of the magnetization path. The time integral / average value of the magnetization path can be, for example, "precisely" perpendicular, perpendicular within = / - 5%, or perpendicular within + / - 10%.

[0038] In some cases, the semimetallic semi-Hausler compound is selected from the group consisting of: RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, and RuCrAs; in some such cases, the semimetallic semi-Hausler layer has a thickness of, for example, less than 5 nanometers. In some such cases, the template layer or chemical template layer for the binary alloy is represented by Al-xEx, where A is a transition metal element and E is a main group element. For example, A contains Co and E contains at least aluminum or gallium and possibly trace amounts of other elements (e.g., Al or Ga; or Al doped with Ga, Ge, Sn or any combination thereof, such as AlSn, AlGe, AlGaGe, AlGaSn, AlGeSn, and AlGaGeSn), and x is in the range of 0.42 to 0.55. In some such cases, tunneling barriers 1209 and 1309 are located in contact with a semi-metallic semi-Hausler layer, and the tunneling barriers may contain, for example, MgO (aluminum magnesium oxide is a suitable substitute for MgO, wherein aluminum magnesium oxide has the form Mg1-zAl2+(2 / 3)zO4, where -0.5 < z < 0.5).

[0039] In one or more embodiments, the semi-metallic semi-Hausler compound is selected from the group consisting of: KcrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn; the semi-metallic semi-Hausler layer has a thickness of, for example, less than 5 nanometers; in some such cases, the template layer or chemical template layer of the binary alloy is represented by Al-xEx, where A is a transition metal element and E is a main group element. For example, A contains Co and E contains at least aluminum or gallium and possibly trace amounts of other elements, and x is in the range of 0.42 to 0.55, as discussed above. In some such cases, tunneling barriers 1209 and 1309 are located in contact with a semi-metallic semi-Hausler layer; the tunneling barriers may contain, for example, MgO (aluminum magnesium oxide is a suitable substitute for MgO).

[0040] It should be noted that the semi-metallic semi-Hausler compound is indicated by a chemical formula, and this does not preclude minor variations from the nominal value by up to several percentage points. The template layer may contain any of the materials listed in Figure 9, but is not limited to those materials.

[0041] Referring now to FIG12, an array of MRAM devices 1202 is shown. Each cell 1202 (e.g., the embodiment of FIG10 or FIG11) is connected to a separate transistor 1204 for controlling read and write operations. Word lines 1206 provide data for writing to cells 1202, while bit lines 1210 and complementary bit lines 1208 read data from cells 1202. In this way, a large memory device array can be implemented on a single chip. Any large number of cells 1202 can be used within the constraints of manufacturing processes and design specifications.

[0042] Writing data to cell 1202 involves passing current through the cell. This current causes the magnetization direction to switch between a parallel state and an antiparallel state, which has the effect of switching between low resistance and high resistance. Since this effect can be used to represent 1s and 0s of digital information, cell 1202 can be used as non-volatile memory. Passing current through cell 1202 in one direction causes the magnetization of free layers 1205 and 1311 to be parallel to the magnetization of reference layers 1211 and 1305, while passing current through cell 1202 in the other direction causes the magnetization of free layers 1205 and 1311 to be antiparallel to the magnetization of reference layers 1211 and 1305. Reading bits stored in cell 1202 involves applying a voltage (lower than the voltage used to write information) to cell 1202 to determine whether the cell provides high resistance ("1") or low resistance ("0") to the current.

[0043] Semiconductor device manufacturing involves various steps in the device patterning process. For example, the fabrication of a semiconductor wafer may begin with multiple device patterns generated by computer-aided design (CAD), followed by an effort to replicate these patterns onto a substrate. The replication process may involve the use of various exposure techniques and a variety of subtractive (etching) and / or additive (deposition) material processing procedures. For example, in photolithography, a photoresist material layer may first be applied on top of a substrate and then selectively exposed according to one or more predetermined device patterns. The portions of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may undergo some variation in their solubility in certain solutions. The photoresist may then be developed in a developing solution, thereby removing the unexposed (in negative resists) or exposed (in positive resists) portions of the resist layer to create a photoresist pattern or photomask. The photoresist pattern or photomask may then be replicated or transferred to the substrate beneath the photoresist pattern.

[0044] Numerous techniques exist available to those skilled in the art for removing material at various stages of semiconductor structure formation. As used herein, these processes are generally referred to as "etching." For example, etching includes techniques such as wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), all well-known techniques for removing selected materials during semiconductor structure formation. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. Etching techniques and applications are well understood by those skilled in the art, and therefore, a more detailed description of such processes is not presented herein.

[0045] Although the overall manufacturing method (involving epitaxial growth of a semi-metallic semi-Hausler material on a template layer) and the resulting structure are novel, certain individual processing steps required to implement the method can utilize known semiconductor manufacturing techniques and processes. These techniques and processes are already familiar to those with ordinary skills in the relevant fields given the teachings herein. Furthermore, the processing steps and one or more of the fabrication processes used to manufacture semiconductor devices are described in numerous readily available publications, including, for example, James D. Plummer et al., *Silicon VLSI Technology: Fundamentals, Practice, and Modeling*, 1st ed., Prentice Hall, 2001, and PH Holloway et al., *Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices*, Cambridge University Press, 2008, all of which are hereby incorporated herein by reference. It is emphasized that although some individual processing steps are described herein, they are merely illustrative, and those skilled in the art will be familiar with several equally suitable alternatives.

[0046] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for ease of interpretation, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure. This does not imply that un-explicitly shown semiconductor layers are omitted in actual integrated circuit devices.

[0047] Based on the discussion to date, it should be understood that, generally speaking, an exemplary magnetoresistive random access memory (MRAM) cell includes a template layer (e.g., a portion of template layer 1203 or template layer 1303) comprising a binary alloy (e.g., binary alloy 401) having an alternating layer lattice structure. The cell also includes a semi-metallic semi-Hausler layer 1205 and a semi-metallic semi-Hausler layer 1305, which comprises a semi-metallic semi-Hausler material (e.g., semi-metallic semi-Hausler material 403) having a tetragonal lattice structure. The semi-metallic semi-Hausler layer is located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer differs from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material. Refer to the discussion in Figures 4 and 5. The cell further includes tunneling barriers 1209 and 1309 outside the semi-metallic semi-Hausler layers, and magnetic layers 1211 and 1311 outside the tunneling barriers. The magnetic layer can be, for example, a conventional material or a Haussler or semi-Haussler material.

[0048] Referring specifically to FIG10, in some cases, the semi-metallic semi-Hausler layer 1205 includes a storage layer and the magnetic layer 1211 includes a reference layer. On the other hand, referring specifically to FIG11, in some cases, the semi-metallic semi-Hausler layer 1305 includes a reference layer and the magnetic layer 1311 includes a storage layer.

[0049] The semi-metallic semi-Hausler compound can be selected from the group consisting of: KCrTe, NaCsP, NaCsAs, CsRbAs, KCaGe, CsBaC, LiSrGe, KCaSn, NaCaGe, KTaSn, RbTaGe, CsSrC, RbTaSi, RbNbSi, CoCrAs, NaCaSn, RhCrGe, LiCaGe, RhFeSn, NiVSn, CsRbN, RhFeGe, CoCrGe, RuCrAs, and CsSrSn. In some cases, the thickness of the semi-metallic semi-Hausler layer is less than 5 nanometers. The exemplary material stack used in Figure 10 can be Si substrate / 50 Å Ta / 3 Å Co20Fe60B20 / 200 Å Mn3N / 300 Å CoAl / 14 Å RhFeGe / 12 Å MgO / 11 Å Co20Fe60B20 / 3 Å Ta / [2.5 Å Co / 5 Å Pt]2 / 5 Å Co / 9 Å Ru / 5 Å Co / 5 Å Pt / [2.5 Å Co / 5 Å Pt]4 / 5 Å Pt / 100 Å Ru. The exemplary material stack used in Figure 11 can be Si substrate / 50 Å Ta / 3 Å Co20Fe60B20 / 200 Å Mn3N / 300 Å CoAl / 25 Å Mn2FeSb / 12 Å MgO / 11 Å Co20Fe60B20 / 100 Å Ru.

[0050] In some cases, the semimetallic semihaussler compound is selected from the group consisting of: RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, and RuCrAs; furthermore, in some cases, the semimetallic semihaussler layer has a thickness of, for example, less than 5 nanometers.

[0051] In one or more embodiments, tunnel barrier 1209 and tunnel barrier 1309 are selected from the group consisting of magnesium oxide and magnesium aluminum oxide.

[0052] In one or more embodiments, the binary alloy of the template layer is represented by Al-xEx, where A is a transition metal element and E is a main group element including at least one of aluminum and gallium, and x is in the range of 0.42 to 0.55.

[0053] In some cases, the alternating layer lattice structure of the template layer contains a cesium chloride structure.

[0054] In some cases, the template layer is nonmagnetic at room temperature (i.e., 20°C).

[0055] In one or more embodiments, the template layer has an in-plane lattice constant, and the in-plane lattice constant of the semi-Hausler material substantially matches the in-plane lattice constant of the template layer. As used herein, the in-plane lattice constant of the semi-Hausler material "substantially matches" the in-plane lattice constant of the template layer when it matches the in-plane lattice constant of the template layer, or when the in-plane lattice constant of the tetragonal semi-Hausler material has moved from the in-plane lattice constant of the cubic semi-Hausler material toward the in-plane lattice constant of the template material. In some cases, the in-plane lattice constant of the semi-Hausler material matches the in-plane lattice constant of the template layer within + / - 10%. In some cases, the in-plane lattice constant of the semi-Hausler material matches the in-plane lattice constant of the template layer within + / - 5%. The semi-metallic semi-Hausler material has, for example, magnetization substantially perpendicular to the semi-metallic semi-Hausler layer.

[0056] In another configuration, referring to FIG12, the magnetoresistive random access memory array includes a plurality of bit lines 1210 forming a plurality of bit line-complementary bit line pairs and a plurality of complementary bit lines 1208. A plurality of word lines 1206 intersect the plurality of bit line pairs at a plurality of cell locations. A plurality of magnetoresistive random access memory cells 1202 are located at each of the plurality of cell locations. Each of the magnetoresistive random access memory cells 1202 is electrically connected to a corresponding bit line 1210 and selectively interconnected to a corresponding complementary bit line 1208 under the control of a corresponding word line 1206 (e.g., each transistor 1204 is a field-effect transistor that is turned on or off by a signal from a word line 1206 applied to its gate, controlling read and write operations and whether the cell is coupled to the complementary bit line).

[0057] As shown in Figure 10 or 11, each cell in a plurality of magnetoresistive random access memories comprises: a template layer comprising a binary alloy having an alternating layer lattice structure; a semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material having a tetragonal lattice structure, the semi-metallic semi-Hausler layer being located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material; a tunneling barrier located outside the semi-metallic semi-Hausler layer; and a magnetic layer located outside the tunneling barrier, all as described elsewhere herein. Typically, a capping layer 1215 or capping layer 1313 of the device indicated in Figures 10 and 11 is connected to bit line 1210, while layer 1203 or layer 1303 is connected to complementary bit line 1208 via an access FET.

[0058] In another state, an exemplary method of operation includes: providing an array such as exactly described; applying a signal to word line 1206 such that a first subset of cell 1202 stores logic one and a second subset of cell 1202 stores logic zero; and reading the stored logic one and logic zero via bit line 1210 and complementary bit line 1208.

[0059] In another example, referring to FIG13, an exemplary method for forming a magnetoresistive random access memory cell (such as in FIG10 or FIG11) includes: according to step 1301, providing a template layer (e.g., template layer 1203 or a portion of template layer 1303, see layer 401 in FIG2). The template layer comprises a binary alloy having an alternating layer lattice structure and having an in-plane lattice constant of the template layer. Another step 1303 includes epitaxially growing a semi-metallic semi-Hausler layer on the template layer (e.g., semi-metallic semi-Hausler layer 1205 or semi-metallic semi-Hausler layer 1305, see layer 403 in FIG2). The semi-metallic semi-Hausler layer comprises a semi-metallic semi-Hausler material. The semi-metallic semi-Hausler layer is grown on the template layer such that the semi-Hausler material has a tetragonal lattice structure and a semi-Hausler in-plane lattice constant that differs from the in-plane lattice constant of a cubic semi-metallic semi-Hausler material. The lattice constant in the semi-Hausler plane substantially matches the lattice constant in the template layer plane. Other steps include step 1305, forming a tunneling barrier (e.g., tunneling barrier 1209 or tunneling barrier 1309, see layer 407 in FIG. 2) outside the semi-metallic semi-Hausler layer; and step 1307, forming magnetic layers 1211 and 1311 outside the tunneling barrier. The method may also include providing and / or forming other elements visible in FIG. 10 and FIG. 11 using techniques readily apparent to those skilled in the art, in accordance with the teachings herein. In accordance with the teachings herein, cells can be integrated into an array by simultaneously forming multiple cells and interconnecting the cells in a manner readily apparent to those skilled in the art using wires, transistors, and peripheral circuitry.

[0060] Those skilled in the art will understand that the exemplary structures described above can be in their original form (i.e., a single wafer having multiple unpackaged wafers), distributed as bare dies in a packaged form, or incorporated as part of an intermediate or final product benefiting from tetragonal semimetallic semihaussler compounds in MRAM and the like.

[0061] The integrated circuits of the form according to the invention can be used in virtually any application and / or electronic system, wherein tetragonal semimetallic semihaussler compounds of MRAM and the like will be advantageous. In view of the teachings provided herein, those skilled in the art will be able to grasp other implementations and applications of the embodiments disclosed herein.

[0062] Some embodiments or elements thereof of the present invention may be implemented in the form of a device comprising memory and at least one processor coupled to the memory and operable to perform exemplary method steps. Figure 14 depicts a computer system suitable for implementing one or more embodiments and / or elements of the present invention; it is referred to herein as a cloud computing node but also represents a server, general-purpose computer, etc., which may be located in the cloud or locally. It should be noted that such computers may control semiconductor design and / or manufacturing, and / or may use, for example, memory cells / arrays as described herein.

[0063] Within cloud computing node 10, there exists a computer system / server 12 that can operate alongside a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, simplified client computers, complex client computers, handheld or laptop computer devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

[0064] Computer system / server 12 can be described within the general context of computer system executable instructions (such as program modules) that may be executed by the computer system. Generally, program modules may contain routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system / server 12 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules may reside on both local computer system storage media and remote computer system storage media, which include memory storage devices.

[0065] As shown in Figure 14, the computer system / server 12 in the cloud computing node 10 is shown in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, system memory 28, and a bus 18 that couples various system components including system memory 28 to the processor 16.

[0066] Bus 18 represents one or more of several types of bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor local buses that use any of a variety of bus architectures. By way of example and without limitation, such architectures include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0067] Computer system / server 12 typically contains a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, and includes both volatile and non-volatile media, and both removable and non-removable media.

[0068] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. For example only, storage system 34 may be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown and commonly referred to as a "hard drive") to non-removable, non-volatile magnetic media. Although not shown, a disk drive may be provided for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks") to removable, non-volatile magnetic disks, and an optical drive may be provided for reading from and writing to removable, non-volatile optical disks (such as CD-ROMs, DVD-ROMs, or other optical media). In such cases, each may be connected to bus 18 via one or more data media interfaces. As will be further described below, memory 28 may contain at least one program product of a collection (e.g., at least one) of program modules configured to perform embodiments of the present invention.

[0069] By way of example and not limitation, a program / utility 40 having at least one set of program modules 42, along with an operating system, one or more applications, other program modules, and program data, may be stored in memory 28. Each of the operating system, one or more applications, other program modules, and program data, or a combination thereof, may include an implementation of a network connectivity environment. Program modules 42 typically perform the functions and / or methods of embodiments of the invention as described herein.

[0070] Computer system / server 12 may also communicate with one or more external devices 14, such as a keyboard, indicator device, display 24, etc.; one or more devices that enable a user to interact with computer system / server 12; and / or any device that enables computer system / server 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may occur via input / output (I / O) interface 22. Additionally, computer system / server 12 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via network adapter 20. As depicted, network adapter 20 communicates with other components of computer system / server 12 via bus 18. It should be understood that, although not shown, other hardware and / or software components may be used in conjunction with computer system / server 12. Examples include, but are not limited to: microcode, device drivers, redundant processing units and external disk drive arrays, RAID systems, tape drives and data archiving storage systems, etc.

[0071] Therefore, one or more embodiments may utilize software running on a general-purpose computer or workbench (e.g., for semiconductor design and / or manufacturing). Referring to FIG14, such implementations may employ, for example, a processor 16, memory 28, and input / output interfaces 22 to a display 24 and external devices 14 (such as a keyboard, indexing device), or the like. As used herein, the term "processor" is intended to include any processing device, such as a processing device including a central processing unit (CPU) and / or other forms of processing circuitry. Furthermore, the term "processor" may refer to more than one individual processor. The term "memory" is intended to include memory associated with a processor or CPU, such as random access memory (RAM) 30, read-only memory (ROM), fixed memory devices (e.g., hard disk drive 34), removable memory devices (e.g., floppy disks), flash memory, and the like. Furthermore, as used herein, the term "input / output interface" is intended to encompass interfaces for inputting data into the processing unit (e.g., a mouse) and interfaces for providing results associated with the processing unit (e.g., a printer). The processor 16, memory 28, and input / output interface 22 may be interconnected, for example, via bus 18, which is part of the data processing unit 12. Suitable interconnections via bus 18 may also be provided to network interface 20, such as a network card, which may be provided for interfacing with a computer network; and media interface, such as a floppy disk or CD-ROM drive, which may be provided for interfacing with media.

[0072] Therefore, as described herein, computer software containing instructions or program code for performing the methods of the present invention may be stored in one or more associated memory devices (e.g., ROM, fixed or removable memory) and, when ready for use, may be partially or completely loaded (e.g., into RAM) and implemented by the CPU. Such software may include, but is not limited to, firmware, resident software, microcode, and the like.

[0073] A data processing system suitable for storing and / or executing code will include at least one processor 16 directly or indirectly coupled to memory element 28 via system bus 18. The memory element may include local memory, mass storage used during the actual implementation of the code, and cache memory 32 that provides temporary storage for at least some code in order to reduce the number of times code must be retrieved from mass storage during implementation.

[0074] Input / output or I / O devices (including but not limited to keyboards, displays, indicator devices and the like) may be coupled to the system directly or via an intervening I / O controller.

[0075] Network adapter 20 can also be coupled to the system to enable the data processing system to connect to other data processing systems or remote printers or storage devices via access to private or public networks. Modems, cable modems, and Ethernet cards are just a few of the currently available types of network adapters.

[0076] As used herein, including within the scope of the claims, "server" includes a physical data processing system (e.g., system 12 as shown in Figure 14) that runs server programs. It should be understood that this physical server may or may not include a display and a keyboard.

[0077] It should be noted that any method described herein may include additional steps of providing different software modules implemented on a computer-readable storage medium; said modules may include any or all suitable elements, such as those depicted in FIG. 15. The method steps may then be implemented using different software modules and / or sub-modules of the system, as described above, which execute on one or more hardware processors (such as hardware processor 16). Furthermore, a computer program product may include a computer-readable storage medium having code adapted to implement one or more method steps described herein, including providing a system with different software modules. In one or more embodiments, the computer-readable storage medium implementing the code and / or design structure is non-transitory.

[0078] In some cases, an example of a user interface that can be used is Hypertext Markup Language (HTML) code served to the browser on the user's computing device by a server or similar entity. HTML is parsed by the browser on the user's computing device to generate a graphical user interface (GUI).

[0079] Indicative design processes for semiconductor design, manufacturing and / or testing

[0080] One or more embodiments utilize computer-aided semiconductor integrated circuit design simulation, testing, placement, and / or fabrication. In this regard, Figure 15 illustrates a block diagram of an exemplary design flow 700 used in, for example, semiconductor IC logic design, simulation, testing, placement, and fabrication. Design flow 700 includes processes, machines, and / or mechanisms for processing design structures or devices to produce logically or otherwise functionally equivalent representations of design structures and / or devices (such as design structures and / or devices that can be analyzed using the techniques disclosed herein or their analogues). Design structures processed and / or produced by design flow 700 may be encoded on a machine-readable storage medium to include data and / or instructions that, when executed or otherwise processed on a data processing system, produce logically, structurally, mechanically, or otherwise functionally equivalent representations of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machines used in IC design processes such as designing, manufacturing, or simulating circuits, components, devices, or systems. For example, the machine may include: a lithography machine, a machine and / or apparatus for producing photomasks (e.g., an electron beam writer), a computer or apparatus for simulating a design structure, any device for manufacturing or testing a process, or any machine for programming a functionally equivalent representation of a design structure into any media (e.g., a machine for programming a programmable gate array).

[0081] Design flow 700 can vary depending on the type of representation being designed. For example, design flow 700 for building application-specific ICs (ASICs) can differ from design flow 700 for designing standard components or from design flow 700 for materializing a design into a programmable array, such as a programmable gate array (PGA) or field programmable gate array (FPGA) provided by Altera® or Xilinx®.

[0082] Figure 15 illustrates several such design structures including an input design structure 720 preferably processed by design process 710. Design structure 720 may be a logic simulation design structure generated and processed by design process 710 to produce a logically equivalent functional representation of a hardware device. Design structure 720 may also or alternatively include data and / or program instructions that, when processed by design process 710, produce a functional representation of the physical structure of a hardware device. Regardless of representing functional and / or structural design features, design structure 720 may be generated using methods such as electronic computer-aided design (ECAD) implemented by a core developer / designer. When coded on a gate array or storage medium or the like, design structure 720 may be accessed and processed by one or more hardware and / or software modules within design process 710 to simulate or otherwise functionally represent electronic components, circuits, electronic or logic modules, devices, apparatuses, or systems. Therefore, design structure 720 may include files or other data structures containing human- and / or machine-readable source code, compiled structures, and computer-executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent circuits or other layers of a hardware logic design. Such data structures may contain hardware description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​(such as Verilog and VHDL) and / or high-level design languages ​​(such as C or C++).

[0083] Design process 710 preferably employs and incorporates design / simulation functional equivalents for synthesizing, translating, or otherwise processing components, circuits, devices, or logic structures to produce a hardware and / or software module that may contain a network connection table 780 containing a design structure such as design structure 720. Network connection table 780 may be a compiled or otherwise processed data structure comprising a list of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., describing connections to other elements and circuits in an integrated circuit design. Network connection table 780 may be synthesized using an iterative process, wherein network connection table 780 is resynthesized one or more times depending on the design specifications and parameters used for the device. As with other design structure types described herein, network connection table 780 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium, such as a magnetic disk or optical disk drive, a programmable gate array, a CF card, or other flash memory. Alternatively, or in an alternative example, the media may be system or cache memory, buffer space, or other suitable memory.

[0084] Design process 710 may include hardware and software modules for processing various input data structure types, including network connection table 780. These data structure types may reside, for example, in library element 730, and include a collection of common components, circuits, and devices for a given manufacturing technology (e.g., different technology nodes: 32nm, 45nm, 90nm, etc.), including models, layouts, and symbolic representations. The data structure types may further include design specifications 740, characterization data 750, verification data 760, design rules 770, and test data files 785, which may include input test patterns, output test results, and other test information. Design process 710 may further include, for example, standard mechanical design processes, such as stress analysis, thermal analysis, mechanical event simulation, and process simulation for operations such as casting, molding, and template forming. Those skilled in the art of mechanical design will understand the range of possible mechanical design tools and applications used in design process 710 without departing from the scope and spirit of the invention. Design process 710 may also include modules for performing standard circuit design processes (such as timing analysis, verification, design rule checking, placement and transfer operations).

[0085] Design process 710 employs and incorporates logical and physical design tools, such as HDL compilers and simulation model building tools, to process design structure 720 along with some or all of the depicted supporting data structures and any additional mechanical design or data (if applicable), to produce a second design structure 790. Design structure 790 resides on storage media or a programmable gate array in a data format used for exchanging information about mechanical devices and structures (e.g., stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format to store or present information about such mechanical design structures). Similar to design structure 720, design structure 790 preferably includes one or more files, data structures, or other computer-coded data or instructions that reside on data storage media and, when processed by an ECAD system, produce one or more logically or otherwise functionally equivalent forms of IC designs or their likenesses. In one embodiment, design structure 790 may include a compiled executable HDL simulation model that functionally simulates the device to be analyzed.

[0086] Design structure 790 may also employ data formats and / or symbol data formats used for exchanging layout data of integrated circuits (e.g., information stored in GDSII (GDS2), GL1, OASIS, mapping files, or any other suitable format for storing such design data structures). Design structure 790 may include information such as symbol data, mapping files, test data files, design content files, manufacturing data, layout parameters, wires, metal content, vias, shapes, data for the manufactured wiring, and any other data required by the manufacturer or other designer / developer to produce the device or structure as described herein (e.g., lib files). Design structure 790 may then proceed to stage 795, where, for example, design structure 790: continues to tape-out, is made public for manufacturing, is made public to a photomask room, is sent to another design room, is sent back to the consumer, etc.

[0087] The embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to constitute a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. In view of the teachings herein, many other embodiments will become apparent to those skilled in the art; utilizing other embodiments and deriving from them allows for structural and logical substitutions and changes without departing from the scope of the invention. It should also be noted that in some alternative embodiments, some steps in the illustrative method may not appear in the order mentioned in the figures. For example, depending on the functionality involved, two blocks shown in a sequential manner may actually be performed substantially simultaneously, or certain steps may sometimes be performed in reverse order. The drawings are also representative only and not to scale. Therefore, this specification and the drawings should be viewed in an illustrative rather than restrictive sense.

[0088] The term "embodiment" used herein, individually and / or collectively, is for convenience only and is not intended to limit the scope of this application to any single embodiment or inventive concept (where more than one embodiment is actually shown). Therefore, although specific embodiments have been shown and described herein, it should be understood that configurations achieving the same purpose may be substituted for the specific embodiments shown; that is, this disclosure is intended to cover any and all adaptations or variations of the various embodiments. In view of the teachings herein, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art.

[0089] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are intended to include the plural forms as well. It should be further understood that the term "comprises / comprising," when used in this specification, designates the presence of stated features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as "bottom," "top," "on," "above," "below," and "under" are used to indicate the relative positioning of elements or structures relative to each other with respect to relative height. If a layer of a structure is described herein as being "above" another layer, it should be understood that there may or may not be an intermediate element or layer between the two specified layers. If a layer is described as being "directly above" another layer, it indicates that the two layers are in direct contact. When terms are used herein and in the claims of the appended claims, "about" means within ±10 percent.

[0090] The corresponding structures, materials, actions, and equivalents of any component or step plus functional element in the following claims are intended to include any structure, material, or action used to perform a function in conjunction with other claimed elements as specifically claimed. Various embodiments have been described for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. Embodiments have been chosen and described to best explain the principles and practical application, and to enable those skilled in the art to understand the various embodiments with respect to various modifications suitable for the intended particular use.

[0091] An abstract is provided to comply with 37 CFR § 1.76(b), requiring that the abstract enable the reader to quickly determine the nature of the technical invention. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing embodiments, it can be seen that various features are grouped together in a single embodiment for the purpose of simplifying the invention. This disclosure method should not be construed as reflecting an intention that the claimed embodiments require more features than explicitly stated in each claim. In fact, as reflected in the appended claims, the claimed subject matter may lie in fewer than all the features of a single embodiment. Therefore, the following claims are hereby incorporated into the embodiments, wherein each claim is, in itself, a separately claimed subject matter.

[0092] In view of the teachings provided herein, those skilled in the art will be able to grasp the technology and other implementations and applications of the disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

[0093] 10: Cloud computing nodes 12: Computer system / server, data processing unit 14: External devices 16: Processing Unit 18: Busbar 20: Network adapter 22: Input / Output Interface 24: Monitor 28: System Memory 30: Random Access Memory 32: Cache memory 34: Storage System 40: Programs / Utilities 42: Program Module 101, 103, 105: Atoms 401: Chemical template layer / CoAl layer 403: Haussler compound 405: Atomic Step 407:MgO tunneling barrier 409: Al layer 411: Co layer 413:MnMn layer 415: MnSb layer 421, 423: Views 601: Vacancy 602:Fe 611:Co 612:Cr 613:As 700: Design Process 710: Design Process 720: Input Design Structure 730: Library Components 740: Design Specifications 750: Specific Data 760: Verification Data 770: Design Rules 780: Network Connection Table 785: Test Data Archive 790: Second Design Structure 795: Stage 1201: Base 1202: Unit 1203: Template Layer 1204: Transistor 1205: Semi-metallic semi-Hausler layer / layer / free layer 1206: Character Line 1207: Polarization Enhancement Layer 1208: Complementary bit line 1209, 1309: tunnel barrier 1210: Bit line 1211: Magnetic layer / reference layer 1213: Antiferromagnetic layer 1215, 1313: Top cover layer 1221, 1323: Double-headed arrows 1223, 1321: Single-headed arrow 1301: Substrate / Steps 1303: Template Layer / Steps 1305: Semi-metallic semi-Hausler layer / step / layer / reference layer 1307: Polarization Enhancement Layer / Steps 1311: Magnetic layer / Free layer X, Y, Z: Position

Claims

1. A magnetoresistive random access memory unit, comprising: Template layer, comprising a binary alloy having an alternating layered lattice structure; A semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material having a tetragonal lattice structure, the semi-metallic semi-Hausler layer being located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material; a tunneling barrier being located outside the semi-metallic semi-Hausler layer. And a magnetic layer, located outside the tunnel barrier.

2. The magnetoresistive random access memory unit as described in claim 1, wherein: The semi-metallic semi-Hausler layer includes a storage layer; and the magnetic layer includes a reference layer.

3. The magnetoresistive random access memory cell as claimed in claim 2, wherein the semi-metallic semi-Hausler material comprises a semi-metallic semi-Hausler compound selected from the group consisting of: RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

4. The magnetoresistive random access memory cell as claimed in claim 3, wherein the thickness of the semi-metallic semi-Hausler layer is less than 5 nanometers.

5. The magnetoresistive random access memory cell as claimed in claim 3, wherein the half-metallic half-Hausler compound is selected from the group consisting of: RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs.

6. The magnetoresistive random access memory cell as claimed in claim 5, wherein the thickness of the semi-metallic semi-Hausler layer is less than 5 nanometers.

7. The magnetoresistive random access memory cell as claimed in claim 2, wherein the tunneling barrier is selected from the group consisting of magnesium oxide and magnesium aluminum oxide.

8. The magnetoresistive random access memory cell as claimed in claim 2, wherein the binary alloy is represented by Al-xEx, wherein A is a transition metal element and E is a main group element including at least one of aluminum and gallium, and x is in the range of 0.42 to 0.

55.

9. The magnetoresistive random access memory unit as described in claim 1, wherein: The semi-metallic semi-Hausler layer includes a reference layer; and the magnetic layer includes a storage layer.

10. The magnetoresistive random access memory cell as claimed in claim 9, wherein the semi-metallic semi-Hausler material comprises a semi-metallic semi-Hausler compound selected from the group consisting of: RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

11. The magnetoresistive random access memory cell as claimed in claim 10, wherein the thickness of the semi-metallic semi-Hausler layer is less than 5 nanometers.

12. The magnetoresistive random access memory cell as claimed in claim 10, wherein the half-metallic half-Hausler compound is selected from the group consisting of: RhCrGe, RhFeSn, CoCrGe, NiVSn, CoCrAs, RhFeGe, or RuCrAs.

13. The magnetoresistive random access memory cell as claimed in claim 12, wherein the thickness of the semi-metallic semi-Hausler layer is less than 5 nanometers.

14. The magnetoresistive random access memory cell as claimed in claim 1, wherein the alternating layer lattice structure of the template layer comprises a cesium chloride structure.

15. The magnetoresistive random access memory cell as claimed in claim 1, wherein the template layer is nonmagnetic at room temperature.

16. The magnetoresistive random access memory unit as claimed in claim 1, wherein: The template layer has an in-plane lattice constant; and the in-plane lattice constant of the semi-Hausler plane is substantially matched with the in-plane lattice constant of the template layer.

17. The magnetoresistive random access memory cell as claimed in claim 16, wherein the semi-metallic semi-Hausler material has a magnetization substantially perpendicular to the semi-metallic semi-Hausler material.

18. A magnetoresistive random access memory array, comprising: Multiple bit lines and multiple complementary bit lines form multiple bit line-complementary bit line pairs; Multiple word lines intersect with multiple bit line-complementary bit line pairs at multiple cell locations; multiple magnetoresistive random access memory (MRMemory) cells are located at each of the multiple cell locations, each of the MRMemory cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under the control of a corresponding word line, each of the multiple MRMemory cells comprising: a template layer comprising a binary alloy having an alternating layer lattice structure; a semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material having a tetragonal lattice structure, the semi-metallic semi-Hausler layer being located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material; a tunneling barrier located outside the semi-metallic semi-Hausler layer; and a magnetic layer located outside the tunneling barrier.

19. A magnetoresistive random access memory array as described in claim 18, wherein: The semi-metallic semi-Hausler layer includes a storage layer; and the magnetic layer includes a reference layer.

20. The magnetoresistive random access memory array as claimed in claim 19, wherein the semi-metallic semi-Hausler material comprises a semi-metallic semi-Hausler compound selected from the group consisting of: RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

21. The magnetoresistive random access memory array as described in claim 18, wherein: The semi-metallic semi-Hausler layer includes a reference layer; and the magnetic layer includes a storage layer.

22. The magnetoresistive random access memory array as claimed in claim 21, wherein the semi-metallic semi-Hausler material comprises a semi-metallic semi-Hausler compound selected from the group consisting of: RhCrGe, RhFeSn, NiVSn, NaCsP, LiCaGe, LiSrGe, NaCaGe, KCaGe, RbTaGe, KCrTe, NaCaSn, KTaSn, KCaSn, RbNbSi, RbTaSi, NaCsAs, CsRbAs, CsBaC, CsSrC, CsRbN, RhFeGe, CoCrGe, RuCrAs, CoCrAs, and CsSrSn.

23. A method for operating a magnetoresistive random access memory array, comprising: A magnetoresistive random access memory (MRAM) array is provided, the array comprising: a plurality of bit lines and a plurality of complementary bit lines forming a plurality of bit line-complementary bit line pairs; a plurality of word lines intersecting the plurality of bit line-complementary bit line pairs at a plurality of cell locations; a plurality of magnetoresistive random access memory cells located at each of the plurality of cell locations, each of the magnetoresistive random access memory cells being electrically connected to a corresponding bit line and selectively interconnected to a corresponding complementary bit line under the control of a corresponding word line, each of the plurality of magnetoresistive random access memory cells comprising: a template layer comprising a binary alloy having an alternating layer lattice structure; a semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material having a tetragonal lattice structure, the semi-metallic semi-Hausler layer being located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material. A tunneling barrier is located outside the semi-metallic semi-Hausler layer; and a magnetic layer is located outside the tunneling barrier; a signal is applied to the word lines to cause a first subset of the cells to store logic one and a second subset of the cells to store logic zero; and the stored logic one and logic zero are read via the word lines and the complementary word lines.

24. A method for forming a magnetoresistive random access memory cell, comprising: A template layer comprising a binary alloy is provided, the binary alloy having an alternating layer lattice structure and having an in-plane lattice constant of the template layer; A semi-metallic semi-Hausler layer is epitaxially grown on a template layer. The semi-metallic semi-Hausler layer comprises a semi-metallic semi-Hausler material. The semi-metallic semi-Hausler layer is grown on the template layer such that the semi-Hausler material has a tetragonal crystal structure and a semi-Hausler in-plane lattice constant. The semi-Hausler in-plane lattice constant is different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material and substantially matches the in-plane lattice constant of the template layer. A tunneling barrier is formed on the exterior of the semi-metallic semi-Hausler layer. A magnetic layer is formed on the exterior of the tunneling barrier.

25. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, the HDL design structure comprising elements that generate a machine-executable representation of a magnetoresistive random access memory unit during processing in a computer-aided design system, wherein, The HDL design structure includes: a template layer comprising a binary alloy with an alternating layer lattice structure; a semi-metallic semi-Hausler layer comprising a semi-metallic semi-Hausler material with a tetragonal lattice structure, the semi-metallic semi-Hausler layer being located outside the template layer, and the in-plane lattice constant of the semi-metallic semi-Hausler layer being different from the in-plane lattice constant of the cubic semi-metallic semi-Hausler material; a tunneling barrier located outside the semi-metallic semi-Hausler layer; and a magnetic layer located outside the tunneling barrier.

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