Circuit probing pad in scribe line structure and a semiconductor device having the same

Abstract

This application provides a dicing structure. The dicing structure includes a die region, a dicing region, and one or more circuit probe pads. The die region is disposed on a semiconductor wafer. The dicing region surrounds the die region. The one or more circuit probe pads are disposed on a first top surface of the die region and a second top surface of the dicing region.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 140,085 (i.e., priority date "April 27, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device, and more particularly to a dicing structure, a semiconductor device, and a method for fabricating a semiconductor wafer thereof. Prior Technology

[0003] When designing DDR4 (Double Data Rate 4) memory chips, circuit probe pads and bonding pads may be located near one edge of the memory chip to improve high-speed electrical characteristics.

[0004] A 2Gb DDR4 DRAM chip using 18nm technology has an area of ​​approximately 8 mm x 8 mm, and hundreds or thousands of identical memory chips can be found on a single semiconductor wafer. However, each memory chip can have numerous probe pads and bonding pads, which can occupy a considerable area within the total area of ​​the memory chip, leading to increased cost and size.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above description of "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a dicing structure. The dicing structure includes a die region, a dicing region, and one or more circuit probe pads. The die region is disposed on a semiconductor wafer. The dicing region surrounds the die region. The one or more circuit probe pads are disposed on a first top surface of the die region and a second top surface of the dicing.

[0007] Another aspect of this disclosure provides a semiconductor device including a plurality of die regions, a dicing region, and a plurality of circuit probe pads. The plurality of die regions are disposed on a semiconductor wafer. The dicing region is disposed between the plurality of die regions. The plurality of circuit probe pads are disposed on a first top surface of the die regions and a second top surface of the dicing region.

[0008] Another aspect of this disclosure provides a method for fabricating a semiconductor wafer. The method includes the following steps: fabricating a grain region on a semiconductor wafer, wherein the grain region is surrounded by a dicing region; and forming a circuit probe pad on a first top surface of the grain region and a second top surface of the dicing region.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When referring to the drawings in conjunction with the embodiments and the scope of the claim, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements, and: Figure 1 is a top view illustrating a semiconductor wafer of some embodiments disclosed herein. Figure 2A is an enlarged top view illustrating the area of ​​the embodiment in Figure 1. Figure 2B is an enlarged view, illustrating the cutting channel structure in Figure 2A. Figures 2C to 2D are cross-sectional views illustrating a semiconductor wafer along line AA' in Figure 2B. Figure 3A is another enlarged top view, illustrating the area of ​​the embodiment in Figure 1. Figure 3B is an enlarged view, illustrating the cutting channel structure in Figure 3A. Figures 3C to 3D are cross-sectional views illustrating a semiconductor wafer along line BB' in Figure 3B. Figure 4A is a top view illustrating the grain region after the cutting process in one embodiment of this disclosure. Figure 4B is a cross-sectional view along line CC' in Figure 4A. Figure 4C is a side view illustrating a semiconductor wafer package according to an embodiment of this disclosure. Figure 5 is a flowchart illustrating a method for fabricating a semiconductor wafer according to an embodiment of this disclosure. Implementation

[0011] The embodiments or examples of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as things that would be commonly done by one of ordinary skill in the art related to the content of this disclosure. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same reference numerals.

[0012] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below can be referred to as the second element, component, region, layer, or part without departing from the teachings of the present invention.

[0013] The phrase "an instance" or "an embodiment" as used in this specification means that a particular feature, structure, or characteristic associated with that instance is included in at least one instance of the invention. Therefore, the phrases "in one instance" or "in one embodiment" appearing throughout this specification do not necessarily refer to the same instance. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances in any suitable manner.

[0014] The terminology used herein is for describing specific embodiments only and is not intended to limit the scope of the invention. As used herein, the singular forms "a," "an," and "the" also include the plural forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprising" and "including," when used in this specification, indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0015] Furthermore, spatial relative terms, such as "below," "under," "down," "above," and "above," are used here for ease of description to describe the relationship between one element or feature and another element(s) shown in the figure. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientations described in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used here can be interpreted accordingly.

[0016] Understandably, when an element is described as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be an intermediate element present. Conversely, when an element is described as "directly connected" or "directly coupled" to another element, there is no intermediate element present. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" vs. "directly between", "adjacent" vs. "directly adjacent", etc.).

[0017] It is understandable that when an element or layer is said to be "formed on" another element or layer, it can be formed directly or indirectly on the other element or layer. That is, for example, an intermediate element or layer may exist. Conversely, when an element or layer is said to be "directly formed on" another element, no intermediate element or layer exists. Other terms used to describe the relationship between elements or layers should be interpreted in a similar way (e.g., "between" vs. "directly between", "adjacent" vs. "directly adjacent", etc.).

[0018] Figure 1 is a top view illustrating a semiconductor wafer 1 of some embodiments disclosed herein.

[0019] As shown in Figure 1, the semiconductor wafer 1 includes a plurality of grain regions 110, each grain region being surrounded by a dicing channel region 121, such that every two adjacent grain regions 110 are separated by the dicing channel region 121. The dicing channel region 121 is a non-functional region on the semiconductor wafer 1. Furthermore, one or more dicing paths can be defined on the dicing channel region 121. In some embodiments, the dicing paths can be from top to bottom and from left to right, or from bottom to top and from right to left, depending on the dicing equipment.

[0020] Specifically, a semiconductor wafer or die (such as an image sensor wafer) is typically fabricated together with hundreds, sometimes thousands, of individual dies on a single semiconductor wafer. The dicing required to separate individual dies from the semiconductor wafer, known as "dicing" or "wafer dicing," can be performed using a die saw (such as a diamond saw). The dicing is carried out along the non-functional regions of the semiconductor material, which are called dicing tracks (i.e., dicing track regions 121), thus separating the die regions 110 on the semiconductor wafer 1.

[0021] Figure 2A is an enlarged top view illustrating region 120 of the embodiment in Figure 1. Please refer to Figure 1 and Figure 2A.

[0022] An enlarged top view of region 120 in Figure 1 is shown in Figure 2A. For example, there are two semiconductor wafers (or dies) 110 in region 120. The two die regions 110 are separated by a dicing region 121, and a dicing path 122 is defined on the dicing region 121. For ease of description, the dicing path 122 may be aligned with the centerline 123 of the dicing region 121. In addition, a plurality of circuit probe pads 231 are disposed on the top surface (not shown in Figure 2A) of the edge region of each of the two die regions 110. For ease of description, the circuit probe pads 231 are disposed on the left edge region of the two die regions 110, as shown in Figure 2A.

[0023] In some embodiments, the functional circuitry may be located under a plurality of circuit probe pads 231, so that during the fabrication or testing of the die region 110, testing can be performed via one or more circuit probes (not shown in FIG. 2A) electrically connected to an external testing device and placed on the plurality of circuit probe pads 231. In some embodiments, the width d of the cut channel region 121 may be from 80 to 100 μm, but this disclosure is not limited thereto.

[0024] Figure 2B is an enlarged view illustrating the cut channel structure 200 in Figure 2A. In some embodiments, the size of each circuit probe pad 231 can be x μm xy μm, where the values ​​of x and y can be 68 and 60, respectively, but this disclosure is not limited thereto. Therefore, the size of each circuit probe pad 231 is sufficient to accommodate the circuit probe pins thereon.

[0025] Figures 2C to 2D are cross-sectional views illustrating semiconductor wafer 1 along line AA' in Figure 2B. Please refer to Figures 2B to 2D.

[0026] As shown in Figure 2C, the circuit probe pad 231 is disposed on the top surface of the left edge region of each die region 110. It should be noted that the margin 232 between the circuit probe pad 231 and the dicing area 121 ensures that the circuit probe pad 231 is not cut out from the semiconductor wafer 1 along with the dicing area 121.

[0027] In some embodiments, after the circuit probe pads 231 are formed on the top surface of the left edge region of each die region 110, the functional circuitry of each die region 110 can be tested via one or more circuit probe pins 240 electrically connected to an external test device and placed on each circuit probe pad 231, as shown in FIG2D. After testing the functional circuitry of each die region 110 on the semiconductor wafer 1, a copper pillar bump (not shown) can be formed on each circuit probe pad 231 to connect the die region 110 to a substrate of a printed circuit board using flip-chip packaging. In some other embodiments, a copper pillar bump (not shown) can be formed on each circuit probe pad 231 before testing the functional circuitry of each die region 110 via one or more circuit probe pins 240.

[0028] In some other embodiments, each die region 110 can be bonded face up to the substrate of a printed circuit board via a wire.

[0029] In the embodiments shown in Figures 2A to 2D, for ease of description, the die region 110 can be, for example, a 2Gb DDR4 die. For example, the 2Gb DDR4 die can have an area of ​​2000 μm x 4000 μm, and the die size of the 2Gb DDR4 die is approximately 8 mm². Furthermore, the circuit probe pads 231 (or bonding pads) can have a size of 60 μm x 68 μm, approximately 0.00408 mm². Moreover, for the die region 110, the total number of circuit probe pads 231 is approximately 200, and the total area of ​​the circuit probe pads 231 is approximately 0.00408 mm² x 200 = 0.816 mm². Therefore, the circuit probe pads 231 can occupy 10.2% of the total area of ​​the die region 110 (i.e., 0.816 / 8 = 10.2%).

[0030] Figure 3A is another enlarged top view illustrating region 120 of the embodiment in Figure 1. Please refer to Figure 1 and Figure 3A.

[0031] Another enlarged top view of region 120 in Figure 1 is shown in Figure 3A. For example, there are two semiconductor wafers (or dies) 110 in region 120. The two die regions 110 are separated by a dicing region 121, and a dicing path 122 is defined on the dicing region 121. Furthermore, a plurality of circuit probe pads 331 are provided on a first top surface of the dicing region 121 and a second top surface of the die region 110. In addition, the first top surface of the dicing region 121 is substantially aligned with the second top surface of the die region 110. In other words, the first top surface of the dicing region 121 and the second top surface of the die region 110 are substantially coplanar.

[0032] For ease of description, a plurality of circuit probe pads 331 are disposed on the left edge region of each die region 110. In some embodiments, a semiconductor wafer package may have input / output pins on one or more of its edges, and a plurality of circuit probe pads 331 may be disposed on two edge regions of each die region 110, such as two adjacent edge regions or two opposite edge regions.

[0033] In some embodiments, a functional circuit may be located under the top surface of each die region 110, on which a circuit probe pad 331 is disposed. Thus, each die region 110 can be tested by one or more circuit probes (not shown in FIG. 3A), which are electrically connected to an external test device and are placed on the plurality of circuit probe pads 331 during the preparation or testing of the die region 110.

[0034] In some embodiments, the width d of the cleavage region 121 between the two grain regions 110 can be between 80 μm and 100 μm, but this disclosure is not limited thereto.

[0035] Figure 3B is an enlarged view illustrating the dicing structure 300 in Figure 3A. In some embodiments, the size of each circuit probe pad 331 can be x μm xy μm, where the values ​​of x and y can be 68 and 60, respectively. Therefore, the size of each circuit probe pad 331 is sufficient to accommodate the circuit probe pins thereon (not shown in Figure 3B). In some embodiments, the center 3311 of each circuit probe pad 331 can be located on the left edge 1102 between the dicing region 121 and the left edge 1102 of the right-side die region 110. Therefore, there is a safe margin between the centerline 123 of the dicing region 121 and the right side of the left edge of the die region 110. Thus, when the semiconductor wafer 1 is diced on the dicing region to separate each die region 110, the die region 110 will not be damaged.

[0036] In some other embodiments, the center 3311 of each circuit probe pad 331 may be located to the left (i.e., farther from the grain region 110) or to the right (i.e., closer to the grain region 110) of the center line 123 of the dicing region 121, depending on fabrication requirements or design trade-offs. For example, when the center 3311 of each circuit probe pad 331 is located to the left of the center line 123 of the dicing region 121, it indicates that the center 3311 of each circuit probe pad 331 is positioned away from the grain region 110 according to the center line 123 of the dicing region 121. Furthermore, when the center 3311 of each circuit probe pad 331 is located to the right of the center line 123 of the dicing region 121, it indicates that the center 3311 of each circuit probe pad 331 is positioned closer to the grain region 110 according to the center line 123 of the dicing region 121. In other words, the proportion of each circuit probe pad 331 disposed on the top surface of the dicing region 121 can be changed according to fabrication requirements.

[0037] For example, when the center 3311 of each circuit probe pad 331 is located to the left of the center line 123 of the dicing zone 121, most of each circuit probe pad 331, along with the dicing zone 121, is cut out from the semiconductor wafer 1, but the contact area between each circuit probe pad 331 and the functional circuitry of the die region 110 is small. When the center 3311 of each circuit probe pad 331 is located to the right of the center line 123 of the dicing zone 121, a portion of each circuit probe pad 331, along with the dicing zone 121, is cut out from the semiconductor wafer 1, but the contact area between each circuit probe pad 331 and the functional circuitry of the die region 110 is larger. Therefore, the manufacturer can find an appropriate proportion of each circuit probe pad 331 disposed on the upper surface of the dicing zone to reduce the overall area of ​​each die region 110 (or semiconductor package) and facilitate testing of the functional circuitry of each die region 110.

[0038] In some embodiments, when the center 3311 of each circuit probe pad 331 is located to the left of the center line 123 of the dicing zone 121, after testing the functional circuitry of the die region 110, most of each circuit probe pad 331, together with a portion of the dicing zone 121, is cut out from the semiconductor wafer 1.

[0039] It should be noted that the top surfaces of the dicing region 121 and the grain region 110 in Figure 3B can be substantially flat and can be regarded as the common top surface of the semiconductor wafer 1.

[0040] Figures 3C to 3D are cross-sectional views illustrating semiconductor wafer 1 along line BB' in Figure 3B. Please refer to Figures 3B to 3D.

[0041] As shown in Figure 3C, a circuit probe pad 331 is disposed on the top surface of the dicing zone 121. It should be noted that there is a safety margin between the center line 123 of the dicing zone 121 and the left edge of the right-side die region 110. Therefore, when the semiconductor wafer 1 is diced on the dicing zone to separate each die region 110, the die region 110 will not be damaged.

[0042] In some embodiments, after the circuit probe pad 331 is formed on the top surface of the semiconductor wafer 1, the functional circuit of each die region 110 can be tested by one or more circuit probe pins 340 that are electrically connected to an external test device and placed on each circuit probe pad 331, as shown in FIG3D.

[0043] Based on the embodiments in Figures 3A to 3D, the dicing structure can be built step by step. For example, a circuit probe pad 331 is formed on the top surface of the dicing region 121. After the functional circuitry of each die region 110 is tested, a portion of the circuit probe pad 331, along with a portion of the dicing region 121, is cut out from the semiconductor wafer 1, thus significantly reducing the size of the die region 110 (or semiconductor wafer package).

[0044] In the embodiments shown in Figures 3A to 3D, for ease of description, a 2Gb DDR4 chip is used as an example. For instance, the size of a 2Gb DDR4 die can be 2000 μm x 4000 μm, and the size of a 2Gb DDR4 chip is approximately 8 mm². Furthermore, the size of the circuit probe pad 331 can be 60 μm x 68 μm, which is approximately 0.00408 mm². It should be noted that the circuit probe pad 331 is disposed on the common top surface between the dicing region 121 and the die region 110, and a portion of the area of ​​the circuit probe pad 331 will be included in the overall area of ​​the die region 110. The circuit probe pad 331 is substantially rectangular.

[0045] Assuming that during the dicing process, half of each circuit probe pad 331 is cut out from the semiconductor wafer 1, this indicates that the other half of each circuit probe pad 331 can still remain on the top surface of each die region 110. Therefore, using the dicing channel structure 300 described in the embodiments of Figures 3A to 3D can reduce the overall area of ​​the circuit probe pads 331 by 50% and the overall area of ​​each die region 110 can be reduced by 5% compared to the dicing channel structure 200 in the embodiments of Figures 2A to 2D. In other words, the dicing channel structure 300 shown in Figures 3A to 3D can significantly reduce the overall area of ​​the die region 110 (or semiconductor package).

[0046] Figure 4A is a top view 400A, illustrating the die region 110 after the dicing process in one embodiment of this disclosure. Figure 4B is a cross-sectional view 400B along line CC' in Figure 4A. Figure 4C is a side view 400C, illustrating a semiconductor wafer package in one embodiment of this disclosure. Please refer to Figures 3A and 4A through 4C.

[0047] After the dicing region 121 in FIG. 3A is cut to separate the die region 110, FIG. 4A shows a top view of the cut die region 110. For example, the cut area 410 of the dicing region 121 may be uneven, and a portion of the circuit probe pad 331 in FIG. 3A may be cut out from the semiconductor wafer 1. As shown in FIG. 4A, the cut area 410 surrounds the die region 110, and the remaining circuit probe pads 331' remain together with the remaining dicing region 121' and the die region 110, as shown in FIG. 4B. A first portion of each of the plurality of remaining circuit probe pads 331' is on the first top surface corresponding to one of the plurality of die regions 110, and a second portion of each of the plurality of remaining circuit probe pads 331' is on the second top surface corresponding to one of the plurality of remaining dicing structures 121'. Since the circuit probe pad 331 will no longer be used after the functional circuit of the die region 110 of the semiconductor wafer 1 has been tested, the circuit probe pad 331 can be cut off from the semiconductor wafer 1 along with the dicing area 121.

[0048] Since the remaining circuit probe pad 331' is still on the top surface of the die region 110, the functional circuitry of the die region 110 will not be affected. Specifically, the component shown in Figure 4B is part of the overall component in the semiconductor wafer package SCP. The die region 110 can be electrically connected to the substrate 460 of a printed circuit board via a wire bond, as shown in Figure 4C.

[0049] For example, as shown in FIG4C, the top surface 1101 of the die region 110 faces upward. Furthermore, the functional circuitry of the die region 110 can be electrically connected from the remaining circuit probe pads 331' (i.e., the remaining portion of the circuit probe pads 331) to bonding pads 456 disposed on a metal connector 462 of a substrate 460 (e.g., a copper foil substrate, CCL) via metal wires 454, and the substrate 460 has one or more solder balls 464 disposed thereon. The functional circuitry of each of the plurality of die regions 110 is electrically connected from the counterpart of the plurality of remaining circuit probe pads 331' to a bonding pad 456 disposed on a metal connector 462 of a corresponding substrate 460 via metal wires 454. For example, the material of the metal wires 454 can be one of aluminum, copper, silver, gold, aluminum alloy, etc., but this disclosure is not limited thereto. The die region 110 and the metal wires 454 are encapsulated by a molding compound 452. In addition, the remaining circuit probe pad 331' can be used as a bonding pad, and in this embodiment, it is electrically connected to the substrate 460 through the metal wire 454.

[0050] Therefore, the components in the cross-sectional view 400C in Figure 4C can be packaged as a semiconductor wafer package SCP, wherein solder ball 464 can be regarded as a physical pad or pin of the semiconductor wafer package SCP.

[0051] Figure 5 is a flowchart illustrating a semiconductor wafer fabrication method 500 according to an embodiment of this disclosure. Please refer to Figure 5 and Figures 3A to 3D.

[0052] In step S510, a grain region 110 is formed on the semiconductor wafer 1, wherein the grain region 110 is surrounded by a dicing region 121. For example, the semiconductor wafer 1 may include hundreds or thousands of identical grain regions 110. These grain regions 110 on the semiconductor wafer 1 are separated by a "dicing" process on the dicing region 121 of the semiconductor wafer 1, wherein each grain region 110 may include functional circuitry, while the dicing region 121 may be a non-functional region.

[0053] In step S512, one or more circuit probe pads 331 are formed on a first top surface of the die region 110 and a second top surface of the dicing region 121. In some embodiments, the size of each circuit probe pad 331 may be 60 μm x 68 μm, but this disclosure is not limited thereto. It should be noted that the first top surface of the die region 110 and the second top surface of the dicing region 121 may be substantially flat, and they can be considered as the common top surface of the semiconductor wafer 1. In other words, the first top surface of the die region 110 and the second top surface of the dicing region 121 are coplanar.

[0054] In step S514, the functional circuitry of the die region 110 is tested by contacting one or more circuit probes 340 with one or more circuit probe pads 331. For example, when a circuit probe 340 electrically connected to an external test device is placed on one or more circuit probe pads 331, the functional circuitry of the die region 110 can be tested.

[0055] In step S516, the semiconductor wafer 1 is cut along the cutting path 122 defined on the dicing region 121. For example, since circuit probe pads 331 are formed on the top surface of the dicing region 121, after testing the functional circuitry of the die region 110, a portion of each circuit probe pad 331, along with a portion of the dicing region 121, is cut out from the semiconductor wafer 1.

[0056] In step S518, the cut die region 110 is bonded to a substrate 460 of a printed circuit board via a wire. For example, the functional circuitry of the die region 110 can be electrically connected via a metal wire 454 from the remaining circuit probe pad 331' to a bonding pad 456 disposed on a metal connector 462 on the substrate 460 (e.g., a copper foil substrate, CCL), and the substrate 460 has one or more solder balls 464 disposed thereon, as shown in FIG4C. For example, the material of the metal wire 454 can be one of aluminum, copper, silver, gold, aluminum alloy, etc., but this disclosure is not limited thereto. The die region 110 and the metal wire 454 are encapsulated by a molding compound 452.

[0057] Based on the embodiment in FIG5, a portion of the circuit probe pad 331, together with a portion of the dicing zone 121, is cut out from the semiconductor wafer 1, so the size of the die region 110 (or semiconductor wafer package) can be significantly reduced.

[0058] Preparation method 500 is merely an example and is not intended to limit the scope of this disclosure to the extent expressly described in the claims. Additional operations may be provided before, during, or after each operation of preparation method 500, and some of these operations may be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, preparation method 500 may include further operations not depicted in FIG. 5.

[0059] One aspect of this disclosure provides a dicing structure. The dicing structure includes a die region, a dicing region, and one or more circuit probe pads. The die region is disposed on a semiconductor wafer. The dicing region surrounds the die region. The one or more circuit probe pads are disposed on a first top surface of the die region and a second top surface of the dicing.

[0060] In some embodiments, the grain region includes a functional circuit, while the dicing region is a non-functional region.

[0061] In some embodiments, a portion of each of the circuit probe pads is electrically connected to the functional circuitry of the grain region.

[0062] In some embodiments, the functional circuit of the die region is tested by one or more circuit probes that are electrically connected to an external test device and placed on the one or more circuit probe pads.

[0063] In some embodiments, the center of each of the circuit probe pads is disposed on a boundary between the grain region and the dicing region.

[0064] In some other embodiments, the center of each of the circuit probe pads is positioned away from the grain region, according to a center line of the cut channel region.

[0065] In some other embodiments, the center of each of the circuit probe pads is positioned closer to the grain region, according to a center line of the cut channel region.

[0066] In some embodiments, a dicing process is performed on the semiconductor wafer along a dicing path defined on the dicing area, a portion of each of the circuit probe pads is cut out from the semiconductor wafer, and a residual dicing structure is formed after the dicing process.

[0067] In some embodiments, the grain region and the remaining dicing structure are packaged into a semiconductor wafer package.

[0068] In some embodiments, the semiconductor wafer package further includes a residual circuit probe pad corresponding to each of the circuit probe pads obtained after the dicing process.

[0069] In some embodiments, the die region is electrically connected to a substrate of a printed circuit board via a wire bonding.

[0070] In some embodiments, the first top surface of the grain region is coplanar with the second top surface of the dicing region.

[0071] Another aspect of this disclosure provides a semiconductor device including a plurality of die regions, a dicing region, and a plurality of circuit probe pads. The plurality of die regions are disposed on a semiconductor wafer. The dicing region is disposed between the plurality of die regions. The plurality of circuit probe pads are disposed on a first top surface of the die regions and a second top surface of the dicing region.

[0072] In some embodiments, each of the die regions includes a functional circuit, and the dicing region is a non-functional region. The functional circuit of each of the die regions is tested by a plurality of circuit probes electrically connected to an external test device and placed on the one or more circuit probe pads.

[0073] In some embodiments, a center of each of the circuit probe pads is disposed on a boundary between each of the grain regions and the dicing region.

[0074] In some other embodiments, the center of each of the circuit probe pads is positioned away from each of the grain regions according to a center line of the cut channel region.

[0075] In some other embodiments, the center of each of the circuit probe pads is positioned closer to each of the grain regions according to a center line of the cut channel region.

[0076] In some embodiments, a dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the dicing area, a portion of each of the circuit probe pads is cut off from the semiconductor wafer, and a residual dicing structure is formed after the dicing process.

[0077] In some embodiments, the grain region and the remaining dicing structure are packaged into a semiconductor wafer package.

[0078] In some embodiments, the semiconductor wafer package further includes a residual circuit probe pad corresponding to each of the circuit probe pads obtained after the dicing process.

[0079] In some embodiments, each of the die regions is electrically connected to a substrate of a printed circuit board via a wire bonding.

[0080] Another aspect of this disclosure provides a method for fabricating a semiconductor wafer. The method includes fabricating a grain region on a semiconductor wafer, wherein the grain region is surrounded by a dicing region; and forming a circuit probe pad on a first top surface of the grain region and a second top surface of the dicing region.

[0081] In some embodiments, the grain region includes a functional circuit, while the dicing region is a non-functional region.

[0082] In some embodiments, a portion of each of the circuit probe pads is electrically connected to the functional circuitry of the grain region.

[0083] In some embodiments, after forming the circuit probe pad on the first top surface of the grain region and the second top surface of the cut channel region, the fabrication method further includes: testing the functional circuit of the grain region by means of a circuit probe electrically connected to an external testing device and placed on the circuit probe pad.

[0084] In some embodiments, the center of each of the circuit probe pads is disposed on a boundary between the grain region and the dicing region.

[0085] In some other embodiments, the center of each of the circuit probe pads is positioned away from the grain region according to a center line of the cut channel region.

[0086] In some other embodiments, the center of each of the circuit probe pads is positioned close to the grain region according to a center line of the cut channel region.

[0087] In some embodiments, after testing the functional circuit of the die region by means of the circuit probe electrically connected to the external test equipment and placed on the circuit probe pad, the fabrication method further includes: performing a dicing process on the semiconductor wafer along a dicing path defined on the dicing area, and forming a residual dicing structure after the dicing process.

[0088] In some embodiments, the preparation method further includes: encapsulating the grain region and the remaining dicing structure into a semiconductor wafer package.

[0089] In some embodiments, the semiconductor wafer package further includes a residual circuit probe pad corresponding to each of the circuit probe pads obtained after the dicing process.

[0090] In some embodiments, each of the die regions is electrically connected to a substrate of a printed circuit board via a wire bonding.

[0091] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined by the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0092] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0093] 1: Semiconductor wafer 110: Grain region 120: Area 121: Cutting Road Area 121': Remaining cutting lane area 122: Cutting Path 200: Cutting channel structure 231: Circuit Probe Pad 232: Balance 300: Cutting track structure 331: Circuit Probe Pad 331': Remaining Circuit Detection Pad 340: Circuit probe 400A: Top View 400B: Sectional View 400C: Side View 410: Incision area 452: Molded Compound 454: Metal wire 456: Bonding Pad 460:Substrate 462: Metal connectors 464: Welding ball 500: Preparation method 1101: Top surface 1102: Left edge 3311: Center 3312: Part AA': line BB':line CC': line d: width S510: Steps S512: Steps S514: Steps S516: Steps S518: Steps SCP: Semiconductor Wafer Packaging

Claims

1. A cutting channel structure, comprising: A plurality of grain regions are disposed on a semiconductor wafer; a dicing zone is disposed between the plurality of grain regions; The wafer comprises a plurality of circuit probe pads disposed on a first top surface of each of the die regions and a second top surface of the dicing region, wherein a portion of each of the plurality of circuit probe pads is electrically connected to a functional circuit of each of the plurality of die regions; wherein the first top surface of each of the die regions and the second top surface of the dicing region are substantially flat and are common top surfaces of the semiconductor wafer; and wherein the circuit probe pads are substantially rectangular, and a center of each circuit probe pad is substantially disposed on a boundary between the die region and the dicing region, such that half of the circuit probe pad is disposed on the die region and the other half of the circuit probe pad is disposed on the dicing region. A dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the dicing area, a portion of each of the circuit probe pads is cut off from the semiconductor wafer, and a plurality of remaining dicing structures and a plurality of remaining circuit probe pads are formed after the dicing process, wherein a first portion of each of the plurality of remaining circuit probe pads is on the first top surface corresponding to one of the plurality of die regions, and a second portion of each of the plurality of remaining circuit probe pads is on the second top surface corresponding to one of the plurality of remaining dicing structures, wherein the functional circuit of each of the plurality of die regions is electrically connected from the counterpart of the plurality of remaining circuit probe pads to bonding pads disposed on a metal connector on a corresponding substrate through metal wires.

2. The cutting channel structure as described in claim 1, wherein the cutting channel area is a non-functional area.

3. The cleavage structure as described in claim 1, wherein the functional circuitry of the die region is tested by one or more circuit probes electrically connected to an external testing device and placed on the one or more circuit probe pads.

4. The dicing structure as described in claim 1, wherein each of the die regions and its corresponding counterpart of the plurality of remaining dicing structures are packaged into a semiconductor wafer package.

5. The dicing structure as described in claim 1, wherein the die region is electrically connected to a substrate of a printed circuit board via a wire bond.

6. A semiconductor element, comprising: A plurality of grain regions are disposed on a semiconductor wafer; a dicing zone is disposed between the plurality of grain regions; The wafer comprises a plurality of circuit probe pads disposed on a first top surface of each of the die regions and a second top surface of the dicing region, wherein a portion of each of the plurality of circuit probe pads is electrically connected to a functional circuit of each of the plurality of die regions; wherein the first top surface of each of the die regions and the second top surface of the dicing region are substantially flat and are common top surfaces of the semiconductor wafer; and wherein each circuit probe pad is substantially rectangular, and a center of each circuit probe pad is substantially disposed on a boundary between each of the plurality of die regions and the dicing region, such that half of the circuit probe pad is disposed on the die region and the other half of the circuit probe pad is disposed on the dicing region. A dicing process is performed on the semiconductor wafer along one or more dicing paths defined on the dicing area, a portion of each of the circuit probe pads is cut off from the semiconductor wafer, and a plurality of remaining dicing structures and a plurality of remaining circuit probe pads are formed after the dicing process. A first portion of each of the plurality of remaining circuit probe pads is on the first top surface corresponding to one of the plurality of die regions, and a second portion of each of the plurality of remaining circuit probe pads is on the second top surface corresponding to one of the plurality of remaining dicing structures. The functional circuit of each of the plurality of die regions is electrically connected from the counterpart of the plurality of remaining circuit probe pads to bonding pads disposed on a metal connector on a corresponding substrate via metal wires.

7. The semiconductor device as described in claim 6, wherein the diced region is a non-functional region.

8. The semiconductor device as claimed in claim 6, wherein the functional circuitry of each of the die regions is tested by a plurality of circuit probes electrically connected to an external test device and placed on the one or more circuit probe pads.

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