Integrated circuit semiconductor device

Abstract

An integrated circuit (IC) semiconductor device includes: a field insulating layer embedded in field trenches disposed spaced apart from each other within a substrate; an active region defined by the field insulating layer; and active fins disposed on the active region and protruding from the surface of the field insulating layer. The field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer, wherein the surface of the first sub-field insulating layer is disposed at a lower level than the surface of the second sub-field insulating layer.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2022-0091319 filed with the Korean Intellectual Property Office on July 22, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0003] This invention relates to an integrated circuit (IC) semiconductor device, and more specifically, to an IC semiconductor device comprising active fins. Prior Technology

[0004] As the integration level of IC semiconductor devices increases, the design rules for the components that make up IC devices have decreased. In IC semiconductor devices that are scaled up to a high degree, it is necessary to increase the height of the active fins. Increasing the height of the active fins can improve the electrical characteristics of IC semiconductor devices, for example, it can improve short-channel effects or current drive capability. Summary of the Invention

[0005] According to an embodiment of the present invention, an integrated circuit semiconductor element includes: a field insulating layer embedded in field trenches disposed spaced apart from each other within a substrate; an active region defined by the field insulating layer; and an active fin disposed on the active region and protruding from the surface of the field insulating layer. The field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer, wherein the surface of the first sub-field insulating layer is disposed at a lower level than the surface of the second sub-field insulating layer.

[0006] According to another embodiment of the invention, an integrated circuit semiconductor element includes: a field insulating layer embedded in field trenches disposed spaced apart from each other within a substrate; an active region defined by the field insulating layer; and active fins disposed on the active region and protruding from the surface of the field insulating layer. The field insulating layer includes a first field insulating layer having a first width. A second field insulating layer has a second width less than the first width. The first field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer. The surface of the first sub-field insulating layer is disposed at a level lower than the surface of the second sub-field insulating layer.

[0007] According to another aspect of the present invention, an integrated circuit semiconductor element includes: a field insulating layer embedded in field trenches disposed spaced apart from each other within a substrate; an active region defined by the field insulating layer; and active fins disposed on the active region and protruding from the surface of the field insulating layer. The field insulating layer includes a first field insulating layer having a first width and a second field insulating layer having a second width less than the first width. The first field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer. The surfaces of the first sub-field insulating layer and the second sub-field insulating layer have concave shapes. Simple Explanation of the Diagram

[0008] The above and other features, characteristics and advantages of certain embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: FIG1 is a layout diagram of an IC semiconductor element according to an embodiment.

[0009] Figure 2 is a partial layout diagram used in the manufacturing method of an IC semiconductor device according to an embodiment.

[0010] Figures 3A to 11D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and an IC semiconductor device manufactured by the method.

[0011] Figure 12 is an enlarged cross-sectional view of an IC semiconductor device according to an embodiment.

[0012] Figures 13A to 18D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and an IC semiconductor device manufactured by the method.

[0013] Figures 19A to 23D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and an IC semiconductor device manufactured by the method.

[0014] Figure 24 shows a system containing IC semiconductor elements according to an embodiment of the present invention.

[0015] Figure 25 shows a memory card containing IC semiconductor elements according to an embodiment of the present invention. Implementation

[0016] In the following detailed description, with reference to the accompanying drawings, embodiments are described in detail. These embodiments may be implemented individually or in combination. Therefore, the invention is not to be construed as being limited to a single embodiment.

[0017] In this specification, unless the context clearly indicates otherwise, the singular form of a component may include the plural form. Enlarged drawings are used in this invention specification to more clearly describe the invention.

[0018] Figure 1 is a layout diagram of an integrated circuit semiconductor element 100 according to an embodiment. In Figure 1, the first direction (X direction) may be the word line direction, the second direction (Y direction) may be the bit line direction, and the third direction (D direction) may be the diagonal direction. The layout of the IC semiconductor element 100 will be described in more detail below, and the invention is not limited to the layout of Figure 1.

[0019] In some embodiments, the IC semiconductor device 100 may include memory elements, such as dynamic random access memory (DRAM) elements. The IC semiconductor device 100 may include a plurality of active regions ACT. The active regions ACT may be defined via field insulating layers (114-1 and 114-2 in Figures 3A to 3D) formed on the substrate 110 of Figures 3A to 3D. The field insulating layer may be an isolation insulating layer for the device. As shown in Figures 1 and 2, as the design rules of the IC semiconductor device 100 decrease, the active regions ACT may be arranged in a diagonal or oblique strip shape.

[0020] Multiple word lines WL extending parallel to each other in the first direction (X direction) across the active region ACT can be located on the active region ACT. Word lines WL can be gate lines. Word lines WL can contain gate electrodes. Word lines WL can be arranged at equal intervals.

[0021] The width of the character line WL or the spacing between character lines WL can be determined based on design rules. Multiple bit lines BL extending parallel to each other in a second direction (Y direction) orthogonal to the character line WL can be placed on the character line WL. Bit lines BL can also be placed at equal intervals. The width of the bit lines BL or the spacing between bit lines BL can be determined according to design rules.

[0022] According to embodiments of the present invention, the IC semiconductor element 100 may include various contact configurations formed on the active region ACT, such as direct contacts DC, embedded contacts BC, landing pads LP, and the like. Here, direct contacts DC may refer to contacts that connect the active region ACT to the bit line BL, and embedded contacts BC may refer to contacts that connect the active region ACT to the lower electrode of a capacitor.

[0023] Generally, in terms of configuration, the contact area between the embedded contact BC and the active region ACT may be extremely small. Therefore, a conductive landing pad LP can be introduced to increase the contact area with the lower electrode of the capacitor and the contact area with the active region ACT. In this embodiment of the invention, the landing pad LP can be disposed between the embedded contact BC and the lower electrode of the capacitor. As described above, by increasing the contact area through the introduction of the landing pad LP, the contact resistance between the active region ACT and the lower electrode of the capacitor can be reduced.

[0024] In the IC semiconductor element 100, the direct contact DC can be disposed at the center of the active region ACT, and the embedded contact BC can be disposed at both ends of the active region ACT. Since the embedded contact BC is disposed at both ends of the active region ACT, the landing pad LP can be configured to be adjacent to both ends of the active region ACT to partially overlap with the embedded contact BC.

[0025] The character lines WL can be embedded in the substrate 110 of the IC semiconductor element 100 and can be configured to span the active region ACT between the direct contact DC or the embedded contact BC. As shown in Figure 1, two character lines WL are configured to span one active region ACT. Since the active region ACT is arranged in a diagonal shape (direction D), the active region ACT can have a predetermined angle of less than 90 degrees with the character lines WL.

[0026] The direct contact DC and the embedded contact BC are symmetrically arranged, and therefore can be arranged on a straight line along the X and Y axes. Unlike the direct contact DC and the embedded contact BC, the landing pad LP can be arranged in a Z-shape L1 in the second direction (Y direction) where the bit line BL extends.

[0027] Furthermore, the landing pads LP along the same line in the Y direction can be configured to overlap with the same side portion of each bit line BL in a first direction (X direction) extending from the character line WL. For example, the landing pads LP of the first line can overlap with the left side of the corresponding bit line BL, and the landing pads LP of the second line can overlap with the right side of the corresponding bit line BL.

[0028] Figure 2 is a partial layout diagram used in a method for manufacturing an IC semiconductor device according to an embodiment. Figure 2 may be a layout diagram that is substantially the same as the layout diagram of Figure 1. The word lines WL, bit lines BL, and contact configurations such as direct contacts DC, embedded contacts BC, and landing pads LP shown in Figure 1 are not illustrated in Figure 2.

[0029] Figure 2 further illustrates the field insulating layer and the hard mask pattern HM. The field insulating layer may include a first field insulating layer 114-1 and a second field insulating layer 114-2. In the plan view, the first field insulating layer 114-1 may be placed in an area with a large distance (or width) between the active regions ACT (116). Compared to the first field insulating layer 114-1 in the plan view, the second field insulating layer 114-2 may be placed in an area with a smaller distance (or width) between the active regions ACT 116.

[0030] The first field insulation layer 114-1 may include a first subfield insulation layer 114A and a second subfield insulation layer 114B. The second field insulation layer 114-2 may include a third subfield insulation layer 114C.

[0031] The hard mask patterns HM can be positioned to extend parallel to each other in a first direction (X direction). The hard mask patterns HM may not overlap with the character lines WL described above with reference to FIG1. ​​The hard mask patterns HM can be configured to extend parallel to each other in the first direction (X direction) between the character lines WL described above with reference to FIG1.

[0032] Figures 3A to 11D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and an IC semiconductor device manufactured by the method.

[0033] Figures 3A to 6A and 8A to 11A are cross-sectional views taken along line A-A' of Figure 2; Figures 3B to 6B and 8B to 11B are cross-sectional views taken along line B-B' of Figure 2; Figures 3C to 6C and 8C to 11C are cross-sectional views taken along line C-C' of Figure 2; and Figures 3D to 6D and 8D to 11D are cross-sectional views taken along line D-D' of Figure 2. Figure 7 is a partially enlarged cross-sectional view of Figure 6B. In the following text, the fourth direction (Z direction) can be a direction perpendicular to the first direction (X direction), the second direction (Y direction), and the third direction (D direction).

[0034] In Figures 3A to 3D, spaced-apart field trenches 112 are formed in the substrate 110, and field insulating layers are formed in the field trenches 112. The field trenches 112 can be trenches used for device isolation. The field trenches 112 are formed by etching the substrate 110 from its surface 110T (or upper surface) into its interior. The field insulating layer can be a device isolation insulating layer. The field insulating layer can be formed by filling the interior of the field trenches 112 with the insulating layer.

[0035] Active regions 116 may be defined by a field insulating layer in the substrate 110. Each active region 116 may have a relatively long island shape, the island shape having a minor axis and a major axis, as illustrated in FIG2. As illustrated in FIG2, the active regions 116 may be positioned in an inclined shape in the diagonal direction (D direction) to have an angle of less than 90 degrees relative to the character line WL extending in the first direction (X direction).

[0036] The substrate 110 may comprise silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. In other embodiments, the substrate 110 may comprise germanium (Ge) or compound semiconductors, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate 110 may comprise conductive regions, such as impurity-doped wells or impurity-doped structures.

[0037] The field insulating layer may include a first field insulating layer 114-1 and a second field insulating layer 114-2. The first field insulating layer 114-1 and the second field insulating layer 114-2 may include the first field insulating layer 114-1 as shown in Figure 3B or Figure 3C. The first field insulating layer 114-1 may include a first sub-field insulating layer 114A and a second sub-field insulating layer 114B.

[0038] The first subfield insulating layer 114A and the second subfield insulating layer 114B may comprise different materials. In some embodiments, the first subfield insulating layer 114A may comprise a material that has higher etch selectivity relative to the hard mask pattern HM than the second subfield insulating layer 114B.

[0039] For example, the first subfield insulating layer 114A may comprise a silicon oxide layer, and the second subfield insulating layer 114B may comprise a silicon nitride layer. However, the configuration of the first field insulating layer 114-1 is not limited to this. For example, the first field insulating layer 114-1 may comprise a multilayer containing a combination of at least three types of insulating layers.

[0040] In Figures 3A and 3D, the second field insulating layer 114-2 may include a third sub-field insulating layer 114C. In some embodiments, the second field insulating layer 114-2 may include a single third sub-field insulating layer 114C. The third sub-field insulating layer 114C may contain the same material as the first sub-field insulating layer 114A. For example, the third sub-field insulating layer 114C may contain a silicon oxide layer.

[0041] A buffer insulating layer 117 is formed on the active region 116 and on the first field insulating layer 114-1 and the second field insulating layer 114-2. The buffer insulating layer 117 may contain the same material as the second field insulating layer 114-2. In Figures 3A to 3D, the buffer insulating layer 117 and the second field insulating layer 114-2 contain the same material, therefore the boundary line between the buffer insulating layer 117 and the second field insulating layer 114-2 is not indicated.

[0042] A hard mask pattern HM is formed on the buffer insulating layer 117. The hard mask pattern HM is formed to define the character lines (WL in FIG1). As described above with reference to FIG2, the hard mask pattern HM does not overlap with the character lines (WL in FIG1), but is configured to extend parallel to each other between the character lines (WL in FIG1) in a first direction (X direction).

[0043] Subsequently, a hard mask pattern HM is used as an etching mask to etch the buffer insulating layer 117 to form a patterned buffer insulating layer 117. The patterned buffer insulating layer 117 can serve as a mask pattern in subsequent processes. In FIG. 3A, the hard mask pattern HM completely covers the patterned buffer insulating layer 117, and in FIG. 3B, the patterned buffer insulating layer 117 is exposed to the outside. In FIG. 3C and FIG. 3D, the hard mask patterns HM are spaced apart from each other on the patterned buffer insulating layer 117.

[0044] In Figures 4A to 4D, a gate trench 118 is formed by etching a patterned buffer insulating layer 117, an active region 116, a first field insulating layer 114-1, and a second field insulating layer 114-2 using a hard mask pattern HM as an etching mask. The gate trench 118 can be a character line trench.

[0045] In Figure 4A, the hard mask pattern HM completely covers the patterned buffer insulating layer 117, and as shown in Figure 4B, the active region 116 and the first field insulating layer 114-1 and the second field insulating layer 114-2 are exposed to the outside. In Figures 4C and 4D, the gate trench 118 is spaced apart from each other in the patterned buffer insulating layer 117 and the active region 116. Furthermore, as shown in Figures 4B and 4C, the gate trench 118 can be formed at a level lower than the level of the surface 110T (or upper surface) of the substrate 110.

[0046] In Figures 5A to 5D, a hard mask pattern HM is used as an etching mask to perform an initial etching of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a first field recessed via 120 and a second field recessed via 122. In some embodiments, the initial etching can be performed as a wet etching method or a dry etching method. The first field recessed via 120 and the second field recessed via 122 can be formed by recess etching the upper portions of the first field insulating layer 114-1 and the second field insulating layer 114-2. The lower surfaces of the first field recessed via 120 and the second field recessed via 122 can be located at a level lower than the surface level of the active region 116.

[0047] As shown in Figure 5B, a first field recess 120 can be formed by etching the first field insulating layer 114-1. As shown in Figures 5B and 5D, a second field recess 122 can be formed by etching the second field insulating layer 114-2.

[0048] In some embodiments, the surface of the first field recess 120 may have a flat shape (e.g., a flat surface), and the surface of the second field recess 122 may have a concave shape (e.g., a concave surface). Furthermore, due to the formation of the first field recess 120 and the second field recess 122, the active region 116 may be more exposed than the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form the first active fin F1.

[0049] In Figures 6A to 6D, a hard mask pattern HM is used as an etching mask to perform a secondary etching of the first field insulating layer 114-1 and the second field insulating layer 114-2, which were initially etched, to form a third field recessed hole 124 and a fourth field recessed hole 126. In some embodiments, the secondary etching can be performed as a wet etching method or a dry etching method. In some embodiments, the secondary etching can be performed as a non-plasma-based dry etching method. In some embodiments, the secondary etching can be performed as a chemical oxide removal (COR) method. The COR method can be a silicon oxide etching method using HF and NH3 gases.

[0050] The third field recess 124 and the fourth field recess 126 can be formed by recess etching the upper portion of the first field insulating layer 114-1 and the second field insulating layer 114-2 during the initial etching. The lower surfaces of the third field recess 124 and the fourth field recess 126 can be located at a level lower than the surface level of the active region 116.

[0051] As shown in Figure 6B, a third field recess 124 can be formed by etching the first subfield insulating layer 114A that was initially etched. As shown in Figures 6B and 6D, a fourth field recess 126 can be formed by etching the second field insulating layer 114-2 (e.g., the third subfield insulating layer 114C) that was initially etched.

[0052] In some embodiments, as illustrated in FIG6B, the surface of the third field recessed aperture 124 may have a concave shape (e.g., a concave surface), and the surface of the fourth field recessed aperture 126 may have a concave shape (e.g., a concave surface). The surface of the third field recessed aperture 124 may be located at a lower level than the surface of the first field recessed aperture 120.

[0053] Furthermore, due to the formation of the third field recess 124 and the fourth field recess 126, the active region 116 can protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form the second active fin F2.

[0054] Here, the relationship between the first field insulating layer 114-1 and the second field insulating layer 114-2, the first field recessed hole 120, the third field recessed hole 124, the fourth field recessed hole 126, the active region 116, and the second active fin F2 is described in more detail with reference to Figures 6B and 7. The enlarged view EN1 in Figure 7 can be a cross-sectional view of a portion of Figure 6B.

[0055] As illustrated in Figures 6B and 7, the first field insulating layer 114-1 may be located in region RG1, which has a large distance between the outermost portions of the second active fins F2 located on the active region 116. The second sub-field insulating layer 114B constituting the first field insulating layer 114-1 may have a first width W1. The first sub-field insulating layer 114A constituting the first field insulating layer 114-1 may have a second width W2, which is smaller than the first width W1. Therefore, the first field insulating layer 114-1 may have a third width W3. In some embodiments, the first width W1, the second width W2, and the third width W3 may be from a few nanometers to tens of nanometers.

[0056] The second field insulating layer 114-2 may be disposed in a region RG2 having a small distance between the outermost portions of the second active fins F2 located on the active region 116. The second field insulating layer 114-2 may include a third sub-field insulating layer 114C. The third sub-field insulating layer 114C constituting the second field insulating layer 114-2 may have a fourth width W4. The fourth width W4 may be greater than the second width W2 and less than the first width W1. In some embodiments, the fourth width W4 may be from a few nanometers to tens of nanometers.

[0057] The surface 120T of the first recessed hole 120 may have a flat shape, such as a flat surface. The surface 124T of the third recessed hole 124 may have a concave shape, such as a concave surface. The surface 126T of the fourth recessed hole 126 may have a concave shape, such as a concave surface.

[0058] In other words, the surface 114AT1 of the first subfield insulating layer 114A may have a concave shape, such as a concave surface. The surface 114BT of the second subfield insulating layer 114B may have a flat shape, such as a flat surface. The surface 114CT1 of the third subfield insulating layer 114C may have a concave shape, such as a concave surface.

[0059] The fourth field recessed aperture 126 may have a first depth d1 from the surface 120T of the first field recessed aperture 120. The third field recessed aperture 124 may have a second depth d2 (less than the first depth d1) from the surface 120T of the first field recessed aperture 120. In some embodiments, the first depth d1 and the second depth d2 may be from a few nanometers to tens of nanometers.

[0060] The active region 116 may protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a second active fin F2. The second active fin F2 and the active region 116 may have the same body. The second active fin F2 may have a first height H1 from the surface 114CT1 of the third sub-field insulating layer 114C to the uppermost end FT1. In the IC semiconductor device described above, the first height H1 of the second active fin F2 can be adjusted by adjusting the first depth d1 of the fourth field recess 126.

[0061] In Figures 8A to 8D, the hard mask pattern HM is removed. Subsequently, a gate insulating layer 132 is formed on the patterned buffer insulating layer 117, the second active fin F2, the active region 116, and the first field insulating layer 114-1 and the second field insulating layer 114-2. As shown in Figure 8B, the gate insulating layer 132 is formed to cover the second active fin F2.

[0062] The gate insulating layer 132 may comprise at least one of the following: a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of a silicon oxide layer. For example, the gate insulating layer 132 may have a dielectric constant of about 10 to about 25.

[0063] In some embodiments, the gate insulating layer 132 may comprise at least one material selected from the following: hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), zirconium oxynitride (ZrOxNy), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiOx), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), and lead scandium tantalum oxide (Pb2ScTaO6). In some embodiments, the gate insulating layer 132 may comprise HfO2, Al2O3, Ta2O3, or TiO2.

[0064] In Figures 9A to 9D, a gate material layer 134 is formed on the gate insulating layer 132. In Figure 9B, the gate material layer 134 can be formed to fully cover the second active fin F2 on the gate insulating layer 132. In Figures 9C and 9D, the gate material layer 134 can be formed to fully cover the active region 116, the patterned buffer insulating layer 117, the first field recess 120, and the fourth field recess 126 on the gate insulating layer 132.

[0065] The gate material layer 134 may comprise a metal layer or a metal nitride layer. In some embodiments, the gate material layer 134 may comprise at least one material selected from Ti, TiN, Ta, TaN, W, WN, TiSiN, and WSiN.

[0066] In Figures 10A to 10D, the gate material layer 134 is etched back to form the gate electrode 138. The gate material layer 134 can be etched back using either wet or dry etching. The gate electrode 138 serves as the character line WL of Figure 1 as described above.

[0067] In Figure 10A, the etchable gate material layer 134, the gate insulating layer 132, and the patterned buffer insulating layer 117 expose the surface (110T or upper surface) of the substrate 110. In Figure 10B, the upper surface of the gate electrode 138 may be located at a lower level than the surface 110T of the substrate 110 in Figure 10A. In Figures 10C and 10D, the gate electrode 138 may be formed at a lower level than the upper surface of the active region 116.

[0068] In Figures 11A to 11D, an embedded insulating layer 140 is formed on the gate electrode 138. The embedded insulating layer 140 may comprise a silicon nitride layer. As illustrated in Figure 11B, the embedded insulating layer 140 is formed on the gate electrode 138 on the second active fin F2. The upper surface 138T of the gate electrode 138 may be located at a level lower than that of the embedded insulating layer 140. Furthermore, the lower surface of the gate electrode 138 (e.g., the active region 116 and the upper surface of the second active fin F2) may have an uneven shape.

[0069] As shown in Figures 11C and 11D, an embedded insulating layer 140 may be formed between the active regions 116 and between the first field insulating layer 114-1 and the second field insulating layer 114-2 and the active regions 116. The upper surface 140T of the embedded insulating layer 140 may be located at the same level as the surface 110T (or upper surface) of the substrate 110. The upper surface 138T of the gate electrode 138 may be located at a lower level than the surface 110T (or upper surface) of the substrate 110. In the manufacturing method of the IC semiconductor device described above, the description of the formation of the source / drain regions is omitted for convenience.

[0070] Using the IC semiconductor device manufacturing method described above, the active region 116, the second active fin F2, the gate insulating layer 132, and the gate electrode 138 can constitute a finFET. The active region 116, the second active fin F2, the gate insulating layer 132, and the gate electrode 138 can also constitute a saddle-shaped finFET with a saddle-shaped fin structure. Furthermore, the active region 116, the second active fin F2, the gate insulating layer 132, and the gate electrode 138 can also constitute a buried channel array transistor (BCAT).

[0071] Figure 12 is an enlarged cross-sectional view EN2 of an IC semiconductor device according to an embodiment. The enlarged cross-sectional view EN2 of Figure 12 may be the same as the enlarged cross-sectional view of Figure 7, except that the fourth field recess 126 has a third depth d3. The enlarged cross-sectional view EN2 of Figure 12 may be a modified example of a portion of Figure 6B. In Figure 12, reference numerals identical to those in Figures 6B and 7 indicate the same components. In Figure 12, descriptions identical to those given above with reference to Figures 6B and 7 are briefly given or omitted.

[0072] The third field recessed aperture 124 may have a second depth d2 (less than the first depth d1) extending from the surface 120T of the first field recessed aperture 120, as described above with reference to Figures 6B and 7. The fourth field recessed aperture 126 may have a third depth d3 (less than the second depth d2) extending from the surface 120T of the first field recessed aperture 120. The third depth d3 may be from a few nanometers to tens of nanometers.

[0073] The third sub-field insulating layer 114C constituting the second field insulating layer 114-2 may have a fourth width W4. The fourth width W4 may be greater than the second width W2 and less than the first width W1. In some embodiments, the fourth width W4 may be a few nanometers to tens of nanometers. The surface 126T of the fourth field recessed aperture 126 may have a concave shape, such as a concave surface. The surface 114CT1 of the third sub-field insulating layer 114C may have a concave shape, such as a concave surface.

[0074] The active region 116 may protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a second active fin F2. The second active fin F2 may have a second height H2 extending from the surface 114AT1 of the first sub-field insulating layer 114A to its uppermost end FT1. In the IC semiconductor device described above, the second height H2 of the second active fin F2 can be adjusted by adjusting the second depth d2 of the third field recess 124.

[0075] Figures 13A to 18D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and the IC semiconductor device manufactured by said method. Figures 13A to 18D are substantially the same as Figures 3A to 11D, except that a protective layer 150 and a protective pattern 152 are further formed during the manufacturing process. In Figures 13A to 18D, reference numerals that are the same as those in Figures 3A to 11D indicate the same parts. In Figures 13A to 18D, descriptions that are the same as those given above with reference to Figures 3A to 11D are briefly given or omitted.

[0076] Figures 13A to 15A, 17A, and 18A are cross-sectional views taken along line A-A' in Figure 2; Figures 13B to 15B, 17B, and 18B are cross-sectional views taken along line B-B' in Figure 2; Figures 13C to 15C, 17C, and 18C are cross-sectional views taken along line C-C' in Figure 2; and Figures 13D to 15D, 17D, and 18D are cross-sectional views taken along line D-D' in Figure 2. Cross-sectional view EN3 in Figure 16 is a partially enlarged cross-sectional view of Figure 15B.

[0077] In Figures 13A to 13D, the processes described above for Figures 3A to 3D and 4A to 4D are performed. Subsequently, a protective layer 150 is formed on the hard mask pattern HM, the patterned buffer insulating layer 117, the active region 116, and the field insulating layers 114-1 and 114-2. The protective layer 150 may comprise a silicon nitride layer.

[0078] In Figure 13A, the protective layer 150 may be formed on the hard mask pattern HM. In Figure 13B, the protective layer 150 is formed in the gate trench (118 in Figure 4B) on the active region 116 and the first field insulating layer 114-1 and the second field insulating layer 114-2.

[0079] In Figures 13C and 13D, a protective layer 150 is formed in the gate trench 118 and on the patterned buffer insulating layer 117, the active region 116, the first field insulating layer 114-1, and the second field insulating layer 114-2.

[0080] Similar to Figures 5A to 5D, in Figures 14A to 14D, a hard mask pattern HM and a protective layer 150 are used as etching masks to initially etch the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a first field recessed hole 120' and a second field recessed hole 122. The hard mask pattern HM is used as an etching mask to initially etch the lower portion of the protective layer 150 to form a protective pattern 152, and the upper portions of the first field insulating layer 114-1 and the second field insulating layer 114-2 are initially etched to form the first field recessed hole 120' and the second field recessed hole 122.

[0081] In some embodiments, the initial etching can be performed as a wet etching method or a dry etching method. A first field recess 120' and a second field recess 122 can be formed by recess etching the upper portions of the first field insulating layer 114-1 and the second field insulating layer 114-2. The lower surfaces of the first field recess 120' and the second field recess 122 can be located at a level lower than the surface level of the active region 116.

[0082] As illustrated in Figure 14B, due to the formation of the first field recess 120' and the second field recess 122, the active region 116 can be more exposed than the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form the first active fin F1. As illustrated in Figure 14D, due to the protective layer (150 in Figure 13D), the second field recess 122 may not be formed in the second field insulating layer 114-2.

[0083] As illustrated in Figures 14C and 14D, when the lower portion of the protective layer 150 is etched using a hard mask pattern HM as an etching mask, etching loss on both sides of the upper portion of the patterned buffer insulating layer 117 and the active region 116 can be prevented. Therefore, subsequent processes (e.g., bit line formation process or capacitor electrode formation process) can be easily performed.

[0084] Similar to Figures 6A to 6D, in Figures 15A to 15D, a hard mask pattern HM and a protective pattern 152 are used as etching masks to perform a second etching on the first field insulating layer 114-1 and the second field insulating layer 114-2, which were etched in the first etching, to form a third field recessed hole 124' and a fourth field recessed hole 126'.

[0085] In some embodiments, the secondary etching can be performed as a wet etching method or a dry etching method. In some embodiments, the secondary etching can be performed as a non-plasma-based dry etching method. In some embodiments, the secondary etching can be performed as a COR method. The COR method can be a silicon oxide etching method using HF and NH3 gases.

[0086] In some embodiments, as illustrated in FIG15B, the third field recess 124' may have the same surface as the first field recess 120'. When forming the third field recess 124', the upper portion of the first sub-field insulating layer 114A may not be etched. Therefore, the surface of the third field recess 124' may have a flat shape, such as a flat surface.

[0087] In some embodiments, unlike FIG. 15B, the surface of the third field recessed aperture 124' may be located at a lower level than the surface of the first field recessed aperture 120', as in the previous embodiments. When forming the third field recessed aperture 124', the upper portion of the first sub-field insulating layer 114A may be etched. Therefore, the surface of the third field recessed aperture 124' may have a concave shape, such as a concave surface.

[0088] As illustrated in FIG15B, a fourth field recessed aperture 126' can be formed by recess etching the upper portion of the initially etched second field insulating layer 114-2 (e.g., the third sub-field insulating layer 114C). The lower surface of the fourth field recessed aperture 126' can be located at a level lower than the surface level of the active region 116. In some embodiments, as illustrated in FIG15B, the surface of the fourth field recessed aperture 126' can have a flat shape, such as a flat surface. The surfaces of the first field recessed aperture 120', the third field recessed aperture 124', and the fourth field recessed aperture 126' can be located at the same level.

[0089] Furthermore, due to the formation of the first field recessed hole 120' and the fourth field recessed hole 126', the active region 116 can protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form the second active fin F2.

[0090] As illustrated in Figures 15C and 15D, when using the hard mask pattern HM and the protective pattern 152 as etching masks to perform secondary etching on the first field insulating layer 114-1 and the second field insulating layer 114-2, etching defects on both sides of the upper portion of the patterned buffer insulating layer 117 and the active region 116 can be prevented. Therefore, subsequent processes, such as bit line formation or capacitor electrode formation, can be easily performed.

[0091] Here, the relationship between the first field insulating layer 114-1 and the second field insulating layer 114-2, the first field recessed hole 120', the third field recessed hole 124', the fourth field recessed hole 126', the active region 116, and the second active fin F2 is described in more detail with reference to Figures 15B and 16. The enlarged cross-sectional view EN3 of Figure 16 can be a cross-sectional view of a portion of Figure 15B. In the enlarged cross-sectional view EN3 of Figure 16, descriptions that are the same as or similar to those given above with reference to Figure 12 are briefly given or omitted.

[0092] As shown in Figures 15B and 16, the surface 120T of the first recessed hole 120' may have a flat shape, for example, a flat surface. The surface 124T' of the third recessed hole 124' may have a flat shape, for example, a flat surface. The surface 126T' of the fourth recessed hole 126' may have a flat shape, for example, a flat surface.

[0093] In other words, the surface 114BT of the second subfield insulating layer 114B and the surface 114AT2 of the first subfield insulating layer 114A may have a flat shape, such as a flat surface. The surface 114CT2 of the third subfield insulating layer 114C may have a flat shape, such as a flat surface. The surfaces of the first field recessed hole 120', the third field recessed hole 124', and the fourth field recessed hole 126' may have the same level.

[0094] The first field recess 120', the third field recess 124', and the fourth field recess 126' may have a fourth depth d4 extending from the uppermost end FT1 of the second active fin F2 to the surface 114BT of the second subfield insulating layer 114B, the surface 114AT2 of the first subfield insulating layer 114A, and the surface 114CT2 of the third subfield insulating layer 114C. In some embodiments, the fourth depth d4 may be from a few nanometers to tens of nanometers.

[0095] The active region 116 may protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a second active fin F2. The second active fin F2 may have a third height H3 extending from the surface 114BT of the second sub-field insulating layer 114B, the surface 114AT2 of the first sub-field insulating layer 114A, and the surface 114CT2 of the third sub-field insulating layer 114C to the uppermost end FT1. The fourth depth d4 and the third height H3 may have the same value.

[0096] In the IC semiconductor device described above, the third height H3 of the second active fin F2 can be adjusted by adjusting the fourth depth d4 of the first field recess 120', the third field recess 124', and the fourth field recess 126'.

[0097] In Figures 17A to 17D, the protective pattern 152 is removed (shown in Figures 14C and 14D). As illustrated in Figures 17C and 17D, the protective pattern 152 formed on the two sidewalls of the patterned buffer insulating layer 117 and the hard mask pattern HM is removed. The protective pattern 152 can be removed using wet etching or dry etching.

[0098] In Figures 18A to 18D, the hard mask pattern HM is removed. Subsequently, similar to Figures 8A to 8D, a gate insulating layer 132 is formed on the patterned buffer insulating layer 117, the second active fin F2, the active region 116, and the first field insulating layer 114-1 and the second field insulating layer 114-2.

[0099] As shown in Figure 18B, a gate insulating layer 132 is formed to cover the second active fin F2. Since the material for forming the gate insulating layer 132 has already been described above, its description is omitted. Subsequently, an IC semiconductor device can be manufactured by performing the manufacturing process described above with reference to Figures 9A to 11D.

[0100] Figures 19A to 23D are cross-sectional views illustrating a method for manufacturing an IC semiconductor device according to an embodiment and an IC semiconductor device manufactured by the method.

[0101] Figures 19A to 23D are substantially the same as Figures 3A to 11D, except that a protective layer 160 and a protective pattern 162 are further formed during the manufacturing process. In Figures 19A to 23D, the same reference numerals as in Figures 3A to 11D indicate the same parts. In Figures 19A to 23D, descriptions identical to those given above with reference to Figures 3A to 11D are given briefly or omitted.

[0102] Figures 19A, 20A, and 22A to 23A are cross-sectional views taken along line A-A' in Figure 2; Figures 19B, 20B, and 22B to 23B are cross-sectional views taken along line B-B' in Figure 2; Figures 19C, 20C, and 22C to 23C are cross-sectional views taken along line C-C' in Figure 2; and Figures 19D, 20D, and 22D to 23D are cross-sectional views taken along line D-D' in Figure 2. Cross-sectional view EN4 in Figure 21 is a partially enlarged cross-sectional view of Figure 20B.

[0103] In Figures 19A to 19D, the processes described above for Figures 3A to 3D, 4A to 4D, and 5A to 5D are performed. Subsequently, a protective layer 160 is formed on the hard mask pattern HM, the patterned buffer insulating layer 117, the active region 116, the first field insulating layer 114-1 and the second field insulating layer 114-2, and the first field recessed via 120 and the second field recessed via 122. The protective layer 160 may comprise a silicon nitride layer.

[0104] In Figure 19A, the protective layer 160 may be formed on the hard mask pattern HM. In Figure 19B, the protective layer 160 is formed on the first field recess 120 and the second field recess 122, the active region 116, and the first field insulating layer 114-1 and the second field insulating layer 114-2.

[0105] In Figures 19C and 19D, a protective layer 160 is formed on the first field recessed hole 120 and the second field recessed hole 122, the patterned buffer insulating layer 117, the active region 116, and the first field insulating layer 114-1 and the second field insulating layer 114-2.

[0106] Similar to Figures 6A to 6D, in Figures 20A to 20D, a hard mask pattern HM and a protective layer 160 are used as etching masks to perform a second etching on the first field insulating layer 114-1 and the second field insulating layer 114-2, which were initially etched, to form deformed first field recessed holes 120", deformed third field recessed holes 124", and deformed fourth field recessed holes 126". The hard mask pattern HM is used as an etching mask to etch the lower portion of the protective layer 160 to form a protective pattern 162, and the upper portion of the first field insulating layer 114-1 and the second field insulating layer 114-2 is etched a second time to form deformed first field recessed holes 120", deformed third field recessed holes 124", and deformed fourth field recessed holes 126".

[0107] In some embodiments, the secondary etching can be performed as a wet etching method or a dry etching method. In some embodiments, the secondary etching can be performed as a non-plasma-based dry etching method. In some embodiments, the secondary etching can be performed as a COR method. The COR method can be a silicon oxide etching method using HF and NH3 gases.

[0108] A deformed first field recess 120", a deformed third field recess 124", and a deformed fourth field recess 126" can be formed by etching the upper portions of the first field insulating layer 114-1 and the second field insulating layer 114-2 during the initial etching. The lower surfaces of the deformed first field recess 120", the deformed third field recess 124", and the deformed fourth field recess 126" can be located at a level lower than the surface level of the active region 116.

[0109] As illustrated in Figure 20B, due to the formation of the deformed first field recess 120", the deformed third field recess 124", and the deformed fourth field recess 126", the active region 116 can be exposed more than the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form the second active fin F2. As illustrated in Figure 19D, due to the protective layer (160 in Figure 19D), the deformed fourth field recess 126" may not be formed in the second field insulating layer 114-2.

[0110] In some embodiments, as illustrated in FIG20B, the deformed first field recessed hole 120" and the deformed third field recessed hole 124" may have the same surface. The surfaces of the deformed first field recessed hole 120" and the deformed third field recessed hole 124" may have a concave shape, such as a concave surface.

[0111] As illustrated in FIG20B, a fourth field recessed aperture 126" can be formed by recess etching the second field insulating layer 114-2 (e.g., the upper portion of the third sub-field insulating layer 114C) during the initial etching. The lower surface of the fourth field recessed aperture 126" can be located at a level lower than the surface level of the active region 116. In some embodiments, as illustrated in FIG20B, the surface of the fourth field recessed aperture 126" can have a concave shape, such as a concave surface. The deformed first field recessed aperture 120", the deformed third field recessed aperture 124" and the deformed fourth field recessed aperture 126" can be located at the same level.

[0112] Furthermore, due to the formation of the deformed first field recess 120", the deformed third field recess 124", and the deformed fourth field recess 126", the active region 116 can protrude from the surface of the field insulating layer 114-1 and the field insulating layer 114-2 to form the second active fin F2.

[0113] As illustrated in Figures 20C and 20D, when the lower portion 164 of the protective layer 160 is etched using a hard mask pattern HM as an etching mask, etching loss on both sides of the patterned buffer insulating layer 117 and the upper portion of the active region 116 can be prevented. Therefore, subsequent processes, such as bit line formation or capacitor electrode formation, can be easily performed.

[0114] Here, the relationship between the first field insulating layer 114-1 and the second field insulating layer 114-2, the deformed first field recessed hole 120", the deformed third field recessed hole 124", the deformed fourth field recessed hole 126", the active region 116, and the second active fin F2 is described in more detail with reference to Figures 20B and 21. The enlarged cross-sectional view EN4 of Figure 21 can be a cross-sectional view of a portion of Figure 20B. In the enlarged cross-sectional view EN4 of Figure 21, descriptions that are the same as or similar to those given above with reference to Figure 7 are briefly given or omitted.

[0115] As shown in Figures 20B and 21, the surface 120T of the deformed first field recessed hole 120" and the surface 124T" of the deformed third field recessed hole 124" have concave shapes, such as concave surfaces. The surface 126T" of the deformed fourth field recessed hole 126" may have a concave shape, such as a concave surface.

[0116] In other words, the surface 114BT2 of the second sub-field insulating layer 114B and the surface 114AT3 of the first sub-field insulating layer 114A may have a concave shape, such as a concave surface. The surface 114CT3 of the third sub-field insulating layer 114C may also have a concave shape, such as a concave surface. The surfaces of the deformed first field recessed hole 120", the deformed third field recessed hole 124", and the deformed fourth field recessed hole 126" may have the same position.

[0117] The deformed first field recessed hole 120", the deformed third field recessed hole 124", and the deformed fourth field recessed hole 126" may have a fifth depth d5 ​​from the uppermost end FT1 of the second active fin F2 to the surface 114BT2 of the second subfield insulating layer 114B and the surface 114CT3 of the third subfield insulating layer 114C-2. In some embodiments, the fifth depth d5 ​​may be a few nanometers to tens of nanometers.

[0118] The active region 116 may protrude from the surfaces of the first field insulating layer 114-1 and the second field insulating layer 114-2 to form a second active fin F2. The second active fin F2 may have a fourth height H4 extending from the surface 114BT2 of the second sub-field insulating layer 114B and the surface 114CT3 of the third sub-field insulating layer 114C-2 to the uppermost end FT1. The fifth depth d5 ​​and the fourth height H4 may have the same value.

[0119] In the IC semiconductor device described above, the fourth height H4 of the second active fin F2 can be adjusted by adjusting the fifth depth d5 ​​of the deformed first field recess 120", the deformed third field recess 124", and the deformed fourth field recess 126".

[0120] In Figures 22A to 22D, the protective pattern 162 is partially removed. As illustrated in Figures 22C and 22D, the protective pattern 162 formed on the upper portions of the two sidewalls of the patterned buffer insulating layer 117 and the hard mask pattern HM is removed. The protective pattern 162 can be partially removed using wet etching or dry etching.

[0121] As shown in Figure 22D, the protective pattern 162' is retained in the second field recess 122 formed in the upper portion of the second field insulating layer 114-2 (e.g., the third sub-field insulating layer 114C). In other words, the protective pattern 162' can be retained on the upper side surface of the active region 116 surrounded by the second field insulating layer 114-2.

[0122] In Figures 23A to 23D, the hard mask pattern HM is removed. Subsequently, similar to Figures 8A to 8D, a gate insulating layer 132 is formed on the patterned buffer insulating layer 117, the second active fin F2, the active region 116, and the first field insulating layer 114-1 and the second field insulating layer 114-2. As shown in Figure 23B, the gate insulating layer 132 is formed to cover the second active fin F2. Since the materials for forming the gate insulating layer 132 have been described above, their description is omitted. Subsequently, an IC semiconductor device can be manufactured by performing the manufacturing process described above with reference to Figures 9A to 11D.

[0123] Figure 24 illustrates a system 1000 incorporating IC semiconductor elements according to an embodiment of the present invention. According to an embodiment of the present invention, system 1000 may include a controller 1010, input / output (I / O) elements 1020, storage elements 1030, and an interface 1040. System 1000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may include a personal digital assistant (PDA), a portable computer, a tablet computer, a wireless telephone, a mobile phone, a digital music player, or a memory card.

[0124] The controller 1010 is configured to control the executable program in the system 1000 and may include a microprocessor, digital signal processor, microcontroller, or similar component. I / O element 1020 can be used to input or output data to the system 1000. The system 1000 can use the I / O element 1020 to connect to external components (e.g., a personal computer or network) and exchange data with them. The I / O element 1020 may include, for example, a keypad, keyboard, or display.

[0125] Storage element 1030 may store program code and / or data for operation of controller 1010, or data processed by controller 1010. Storage element 1030 may include IC semiconductor element 100 according to embodiments of the present invention. Interface 1040 may be a data transmission path between system 1000 and another external component. Controller 1010, I / O element 1020, storage element 1030 and interface 1040 may communicate with each other via bus 1050.

[0126] According to embodiments of the present invention, the system 1000 can be used in, for example, mobile phones, MP3 players, navigation systems, portable multimedia players (PMPs), solid state disks (SSDs), or home appliances.

[0127] Figure 25 shows a memory card 1100 incorporating an IC semiconductor element according to an embodiment of the present invention. The memory card 1100 may include a storage element 1110 and a memory controller 1120. The storage element 1110 may store data. In some embodiments, the storage element 1110 may have non-volatile characteristics, which enable it to retain stored data even when its power is interrupted. The storage element 1110 may include an IC semiconductor element 100 manufactured by the methods described above.

[0128] The memory controller 1120 can read data stored in the storage element 1110 or store data in the storage element 1110 in response to a read / write request from the host 1130. The memory controller 1120 may include an IC semiconductor element 100 manufactured by the method shown above. According to embodiments of the invention, the height of the active fins can be increased by recess etching the field insulating layer between the active fins. Therefore, according to embodiments of the invention, the IC semiconductor element can improve electrical characteristics, such as improved short-channel effect or current drive capability.

[0129] While the invention has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the following claims and their equivalents.

[0130] 100: Integrated circuit semiconductor components

[0131] 110: Base

[0132] 110T: Surface of substrate 110

[0133] 112: Trench

[0134] 114-1: First Field Insulation Layer

[0135] 114-2: Second Field Insulation Layer

[0136] 114A: First subfield insulation layer

[0137] 114AT1, 114AT2, 114AT3: Surface of the first subfield insulating layer 114A

[0138] 114B: Second subfield insulation layer

[0139] 114BT, 114BT2: Surface of the second subfield insulation layer 114B

[0140] 114C, 114C-2: Third subfield insulation layer

[0141] 114CT1, 114CT2, 114CT3: Surface of the third subfield insulating layer 114C

[0142] 116. ACT: Active Zone

[0143] 117: Buffer insulation layer

[0144] 118: Gate trench

[0145] 120, 120': First concave hole

[0146] 120": The first dented hole of deformation

[0147] 120T: Surface of the first recessed hole 120 / Surface of the first recessed hole 120' / Surface of the deformed first recessed hole 120"

[0148] 122: Second-stage concave hole

[0149] 124, 124': Third-stage concave hole

[0150] 124": The third field of the deformed concave hole

[0151] 124T: Surface of the third recessed hole 124

[0152] 124T': Surface of the third recessed hole 124'

[0153] 124T: Surface of the deformed third-field recessed hole 124

[0154] 126, 126': Fourth field concave hole

[0155] 126": Deformed fourth field concave hole

[0156] 126T: Surface of the fourth recessed hole 126

[0157] 126T': Surface of the fourth recessed hole 126'

[0158] 126T: Surface of the deformed fourth field recessed hole 126".

[0159] 132: Gate insulation layer

[0160] 134: Gate material layer

[0161] 138: Gate electrode

[0162] 138T: Upper surface of gate electrode 138

[0163] 140: Embedded insulation layer

[0164] 140T: Upper surface of the embedded insulation layer 140

[0165] 150, 160: Protective layer

[0166] 152, 162, 162': Protective pattern

[0167] 164: Lower portion of protective layer 160

[0168] 1000: System

[0169] 1010: Controller

[0170] 1020: Input / Output Components

[0171] 1030, 1110: Storage elements

[0172] 1040: Interface

[0173] 1050: Busbar

[0174] 1100: Memory Card

[0175] 1120: Memory controller

[0176] 1130: Host

[0177] A-A', B-B', C-C', D-D': lines

[0178] BC: Embedded Contacts

[0179] BL: Bitline

[0180] d1: First depth

[0181] d2: Second depth

[0182] d3: Third depth

[0183] d4: Fourth Depth

[0184] d5: Fifth Depth

[0185] D, X, Y, Z: Direction

[0186] DC: Direct Contact

[0187] EN1: Enlarged View

[0188] EN2: Enlarged cross-sectional view

[0189] EN3, EN4: Cross-sectional view

[0190] F1: First active fin

[0191] F2: Second active fin

[0192] FT1: Top End

[0193] H1: First Height

[0194] H2: Second Altitude

[0195] H3: Third Height

[0196] H4: Fourth Height

[0197] HM: Hard mask pattern

[0198] L1: Z-shaped

[0199] LP: Landing Liner

[0200] RG1, RG2: Zones

[0201] W1: First width

[0202] W2: Second width

[0203] W3: Third width

[0204] W4: Fourth Width

[0205] WL: Character Line

Claims

1. An integrated circuit (IC) semiconductor element, comprising: Field insulation layer, embedded in field trenches that are spaced apart from each other inside the substrate; The active region is defined by the field insulation layer; And an active fin, disposed on the active region and protruding from the surface of the field insulating layer, wherein the field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer, wherein the surface of the first sub-field insulating layer is disposed at a level lower than the surface of the second sub-field insulating layer, and wherein the uppermost end of the active fin is disposed at a level higher than the surface of the second sub-field insulating layer.

2. The IC semiconductor device as claimed in claim 1, wherein the first subfield insulating layer comprises a material having a higher etch selectivity relative to the hard mask pattern than that of the second subfield insulating layer.

3. The IC semiconductor element as claimed in claim 1, wherein: The surface of the first subfield insulating layer has a concave shape, and the surface of the second subfield insulating layer has a flat shape.

4. The IC semiconductor device as claimed in claim 1, wherein the active region and the active fin have the same body.

5. The IC semiconductor device as claimed in claim 1, wherein a gate insulating layer and a gate electrode are sequentially formed on the active fin and the field insulating layer.

6. The IC semiconductor element as claimed in claim 5, wherein: The surfaces of the active fin and the field insulating layer are positioned at a lower level than the surface of the substrate, and the active region, the active fin, the gate insulating layer, and the gate electrode constitute a buried channel array transistor (BCAT).

7. An integrated circuit (IC) semiconductor element, comprising: Field insulation layer, embedded in field trenches that are spaced apart from each other inside the substrate; The active region is defined by the field insulation layer; and active fins, disposed on the active region and protruding from the surface of the field insulating layer, wherein: the field insulating layer includes a first field insulating layer having a first width, a second field insulating layer having a second width less than the first width, the first field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer, the surface of the first sub-field insulating layer is disposed at a level lower than the surface of the second sub-field insulating layer, and wherein the uppermost end of the active fin is disposed at a level higher than the level of the surface of the second sub-field insulating layer.

8. The IC semiconductor device as claimed in claim 7, wherein the first field insulating layer is formed on the substrate in a region between the outermost portions of the active fins where the distance is greater than that of the second field insulating layer.

9. The IC semiconductor element as claimed in claim 7, wherein: The surface of the first subfield insulating layer has a concave shape, and the surface of the second subfield insulating layer has a flat shape.

10. The IC semiconductor device as claimed in claim 9, wherein the surface of the second field insulating layer has a concave shape.

11. The IC semiconductor device as claimed in claim 7, wherein the second field insulating layer comprises a single third sub-field insulating layer.

12. The IC semiconductor device as claimed in claim 11, wherein the surface of the third subfield insulating layer is disposed at a higher level than the surface of the first subfield insulating layer.

13. The IC semiconductor device as claimed in claim 11, wherein the surface of the second field insulating layer is disposed at a lower level than the surface of the first field insulating layer.

14. The IC semiconductor device as claimed in claim 11, wherein the surface of the third subfield insulating layer has a concave shape.

15. An integrated circuit (IC) semiconductor element, comprising: Field insulation layer, embedded in field trenches that are spaced apart from each other inside the substrate; The active region is defined by the field insulation layer; And an active fin, disposed on the active region and protruding from the surface of the field insulating layer, wherein: the field insulating layer includes a first field insulating layer having a first width and a second field insulating layer having a second width less than the first width, the first field insulating layer includes a first sub-field insulating layer and a second sub-field insulating layer, the surfaces of the first sub-field insulating layer and the second sub-field insulating layer have concave shapes, and wherein the uppermost end of the active fin is disposed at a level higher than the level of the surface of the second sub-field insulating layer.

16. The IC semiconductor element as claimed in claim 15, wherein a protective pattern is further formed on two sidewalls of the second field insulating layer in contact with the active region.

17. The IC semiconductor device as claimed in claim 15, wherein the surface of the second field insulating layer has a concave shape.

18. The IC semiconductor device as claimed in claim 15, wherein the surface of the first field insulating layer has the same height as the surface of the second field insulating layer.

19. The IC semiconductor device as claimed in claim 15, wherein the second field insulating layer includes a single third sub-field insulating layer.

20. The IC semiconductor device of claim 15, wherein the active region and the active fin are of the same body, and the active fin is formed by recess etching of the upper portion of the field insulating layer.

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