Method for making an electronic package

Abstract

This application provides an electronic package and a method for manufacturing the electronic package. The electronic package includes a substrate; a plurality of electronic components mounted on the substrate; and a sealing cap for sealing the substrate and the plurality of electronic components, wherein the sealing cap includes an upper surface having a first region and a second region; and wherein the first region has a first roughness, and the second region has a second roughness greater than the first roughness.

Description

Technical Field

[0001] This application generally relates to semiconductor technology, and more specifically, to a semiconductor package and a method for manufacturing an electronic package. Prior Technology

[0002] System-in-Package (SiP) is a functional electronic system or subsystem comprising two or more heterogeneous semiconductor dies, such as logic wafers, memory, integrated passive devices (IPDs), RF filters, sensors, heat sinks, or antennas. Molded underfill (MUF) processes are used to manufacture SiPs that combine underfill and molded semiconductor devices. However, in traditional MUF processes, cracks and breakage frequently occur in the semiconductor package when it is demolded from the mold.

[0003] Therefore, a method is needed to manufacture electronic packages that can increase yield. Summary of the Invention

[0004] One object of this application is to provide a method for manufacturing electronic packages.

[0005] According to one aspect of the embodiments of this application, an electronic package is provided, the electronic package including a substrate; a plurality of electronic components mounted on the substrate; and a sealing cap for sealing the substrate and the plurality of electronic components, wherein the sealing cap includes an upper surface having a first region and a second region; and wherein the first region has a first roughness and the second region has a second roughness greater than the first roughness.

[0006] According to another aspect of the embodiments of this application, an electronic packaging strip is provided, the electronic packaging strip including a plurality of electronic packages, each electronic package including a substrate; a plurality of electronic components mounted on the substrate; and a sealing cap for sealing the substrate and the plurality of electronic components, wherein the sealing cap includes an upper surface having a first region and a second region; and wherein the first region has a first roughness and the second region has a second roughness greater than the first roughness.

[0007] According to one aspect of the present application, a method for manufacturing an electronic package is provided, the method comprising: placing a substrate strip having a plurality of electronic packages on a bottom mold, wherein each electronic package includes a substrate and a plurality of electronic components disposed on the substrate; placing a top mold on the electronic package, wherein the top mold has a molding cavity for receiving the electronic package, and the molding cavity has a molding surface facing the electronic package, and wherein the molding surface has a first molding region and a second molding region, the first molding region having a first roughness, and the second molding region having a second roughness greater than the first roughness; injecting a sealing material into the molding cavity to form a sealing cap encapsulating the substrate and the plurality of electronic components of each electronic package, wherein the sealing cap includes a first region having a first region corresponding to the first molding region and a second molding region; separating each electronic package sealed with the sealing cap from the top mold and the bottom mold; and separating the plurality of electronic packages from each other by segmentation such that each electronic package is sealed by the sealing cap.

[0008] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and not intended to limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Simple Explanation of the Diagram

[0009] The accompanying drawings cited herein form part of the specification. The features shown in the drawings are only illustrations of some embodiments of this application, and not all embodiments of this application, unless otherwise expressly stated in the detailed description, and the reader of the specification should not imply the contrary.

[0010] Figure 1 shows a cross-sectional view of an electronic package 100 according to an embodiment of this application;

[0011] Figure 2 shows a top view of the electronic package strip with multiple electronic packages 100 of Figure 1;

[0012] Figure 3 shows a cross-sectional view of an electronic package 200 according to an embodiment of this application;

[0013] Figures 4A to 4G illustrate the various steps of a method for manufacturing an electronic package according to an embodiment of this application;

[0014] Figure 5 shows a flowchart of an electronic packaging manufacturing method according to an embodiment of this application.

[0015] The same reference numerals will be used throughout the accompanying drawings to denote the same or similar parts. Implementation

[0016] The following detailed description of exemplary embodiments of this application is taken with reference to the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret it in a limiting manner, and the scope of the embodiments of this application is limited only to the appended claims.

[0017] In this application, unless otherwise expressly stated, the singular is used to include the plural. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms such as "including" and "containing" is not restrictive. Furthermore, unless otherwise expressly stated, terms such as "element" or "part" cover elements and parts that include one unit, as well as elements and parts that include more than one subunit. Moreover, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0018] As used herein, spatially relative terms such as “below,” “under,” “above,” “over,” “upper,” “upper side,” “lower side,” “left side,” “right side,” “horizontal,” “vertical,” “side,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the accompanying figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0019] As previously mentioned, semiconductor packages often crack and break when demolded from a mold used in the molding process. The inventors of this application have discovered that the low interface roughness between the semiconductor package and the mold can result in significant force being required to separate the semiconductor package (especially the sealing cap) from the mold, potentially leading to cracking and breakage. Specifically, when the sealing cap is demolded, both ends may detach from the mold, but the middle portion may remain firmly attached, causing cracks or breakage in or near the middle of the package. However, laser marking typically requires a low-roughness sealing surface on the semiconductor package, as a smooth surface improves the resolution of the laser marking. Generally, the surface for laser marking requires a relatively low roughness, such as less than 0.8 μm.

[0020] To address the aforementioned problems, the inventors of this application have conceived of a novel electronic package with a sealing cap having two roughnesses, and a method for manufacturing the electronic package, as described in more detail below.

[0021] Figure 1 shows a cross-sectional view of an electronic package 100 according to an embodiment of this application.

[0022] As shown in Figure 1, the electronic package 100 includes a substrate 101 having an upper surface 101a and a lower surface 101b. In some embodiments, the substrate 101 may be a printed circuit board (PCB) and may include a redistribution structure (RDS) having one or more dielectric layers and one or more conductive layers located between and through the dielectric layers. The conductive layers may define pads, traces, and sockets through which electrical signals or voltages can be distributed horizontally and vertically on the RDS. In some embodiments, the RDS may include a plurality of conductive patterns formed on either or both of the upper and lower surfaces of the substrate 101.

[0023] Multiple electronic components 102 may be disposed on the upper surface 101a of the substrate 101, at least a portion of which are sealed by a sealing cap 105. Furthermore, multiple bumps 104 may be attached to the substrate 101 to facilitate integration of the electronic package 100 with external electronic devices and systems. Specifically, multiple electronic components 102 are mounted on the upper surface 101a of the substrate 101 and sealed by a sealing cap 105. After sealing, the electronic package 100 may be marked with certain information by laser marking. For example, this information may be marked on the upper surface of the sealing cap 105, including specifications and / or manufacturing information of the electronic package 100.

[0024] In this embodiment, the upper surface of the sealing cap 105 has a first region 1051 and a second region 1052. The first region 1051 has a first roughness, and the second region 1052 has a second roughness greater than the first roughness. Having two different roughnesses on the sealing cap 105 offers several advantages. For example, during the MUF process, because the first roughness is lower than the second roughness, the second region with the second roughness is less likely to adhere to the mold than the first region when the sealing cap 105 is demolded. In this way, it is easier to remove the sealing cap 105 and the electronic package 100 from the mold, thus preventing breakage of the electronic package. It should be noted that since the two rough upper surfaces of the sealing cap 105 are designed to address cracking during demolding, these upper surfaces should be formed in a single molding and demolding process, rather than formed separately in two or more molding and demolding processes.

[0025] In some embodiments, as shown in FIG1, the first region 1051 is higher than the second region 1052 relative to the substrate 101, and optionally, the thickness of the sealing cap 105 sealing the first electronic component 102a in the first region 1051 may be greater than the thickness of the sealing cap 105 sealing the second electronic component 102b in the second region 1052. An electronic package with a sealing cap 105 having this thickness variation can further compensate for the warpage effect of the electronic package 100. In some embodiments, the upper surface of the sealing cap 105 may include two or more regions each having its own thickness.

[0026] In some embodiments, the first electronic component 102a and / or the second electronic component 102b may include multiple semiconductor dies, semiconductor devices, and / or discrete devices. For example, the electronic component may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, an RF circuit, a wireless baseband system-on-a-chip (SoC) processor, a sensor, a memory controller, a memory device, a dedicated integrated circuit, etc. The electronic component 102 may also be a passive device, such as a capacitor, inductor, or resistor. In the example shown in FIG1, the first electronic component 102a may include two active devices with larger form factors, while the second electronic component 102b may include three passive devices with smaller form factors, but the scope of this application is not limited thereto. The first electronic component 102a and the second electronic component 102b may be mounted on the upper surface 101a of the substrate 101 using any suitable surface mount technology.

[0027] In some embodiments, the sealing cap 105 is formed by an injection molding process such as MUF (Moisture-Injection Molding) which can reduce or prevent moisture and other contaminants from affecting the functionality and reliability of the electronic package. In some embodiments, the sealing material of the sealing cap 105 may be made of a liquid general molding resin, such as an epoxy resin, but the scope of this application is not limited thereto. In some embodiments, the sealing material is a non-conductive material and provides structural support.

[0028] One or more laser marks may be formed in a first region 1051 on the upper surface of the sealing cap 105, which may have a first roughness of less than 0.8 μm. In some embodiments, the first roughness is in the range of 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, or 0.6 μm to 0.8 μm. In some other embodiments, the first roughness is less than 0.4 μm. In some embodiments, the second roughness is greater than 1.8 μm. Conversely, the second roughness of the second region 1052 is in the range of 1.8 μm to 3.2 μm, 3.2 μm to 6.3 μm, or 6.3 μm to 12.5 μm. In some other embodiments, the second roughness is greater than 12.5 μm.

[0029] In some preferred embodiments, a transition region 106 may be formed on the upper surface of the sealing cap 105 at the boundary between the first region 1051 and the second region 1052. The transition region 106 may be, for example, a circular step, providing a smooth transition from the higher first region 1051 to the lower second region 1052. This smooth transition can reduce or avoid stress concentration at the boundary between the first region 1051 and the second region 1052, thereby reducing the risk of cracking in the transition region.

[0030] Figure 2 shows a top view of an electronic package strip having multiple electronic packages 100 as shown in Figure 1.

[0031] As shown in Figure 2, since the electronic packages are arranged in a row and connected together on the electronic package strip, the sealing cap 105 may include a plurality of first regions 1051 and a plurality of second regions 1052. Each first region 1051 is rectangular, and each second region 1052 is adjacent to and surrounds the first region 1051. In some embodiments, the first and second regions may be arranged in other ways. For example, the first and second regions may intersect each other in an array with multiple rows and columns. It is understood that the arrangement of the first and second regions can be configured by a mold for forming the sealing cap of the electronic package. These integrated electronic packages can then be separated from each other.

[0032] Figure 3 shows a cross-sectional view of an electronic package 200 according to another embodiment of this application.

[0033] As shown in Figure 3, unlike the electronic package 100 shown in Figure 1, the electronic package 200 includes a sealing cap 205 with a generally flat upper surface. The upper surface has a first region 2051 with a first roughness and a second region 2052 with a second roughness greater than the first roughness. In this embodiment, the first region 2051 and the second region 2052 have approximately the same height, meaning the sealing cap 205 has a uniform thickness above the substrate 201.

[0034] It should be noted that although two regions 2051 and 2052 are shown in Figure 3, more regions with their own roughness can be formed on the upper surface of the sealing cap 205. Furthermore, each region can have sub-regions that are not adjacent to each other. For example, when viewed from the top of the electronic package 200, the second region can have a cross shape, and this cross-shaped second region can divide the first region into four sub-regions, each near a corner of the upper surface of the electronic package 200. In some other embodiments, the second region can have a grid shape, which can divide the first region into multiple blocks. Separating the electronic package with such separated or disconnected first regions from the mold is much easier.

[0035] In some embodiments, the first region 2051 may occupy a smaller area on the upper surface of the sealing cap 205 than the second region 2052, as long as the surface area required for laser marking or other similar purposes is sufficient. For example, the first region 2051 may occupy less than 50% of the top surface of the sealing cap 205. In some examples, the first region 2051 may occupy less than 40%, less than 30%, less than 20%, or less than 10% of the upper surface of the sealing cap 205. In some embodiments, the area of ​​the first region 2051 may be less than 5 cm² of the upper surface of the sealing cap 205, or less than 1 cm² of the upper surface of the sealing cap 205, or even smaller.

[0036] Referring to Figures 4A to 4G, various steps of a method for manufacturing an electronic package according to an embodiment of the present invention are illustrated. For example, this method can be used to manufacture the electronic package 100 shown in Figure 1 or the electronic package 200 shown in Figure 3. The method will be described in more detail below with reference to Figures 4A to 4G.

[0037] As shown in Figure 4A, a substrate strip with multiple electronic packages is placed on a bottom mold 306. In some other embodiments, each electronic package may occupy a portion of the substrate strip and may be separated from adjacent electronic packages in a corresponding dividing channel, such as a saw groove, during a subsequent dividing process on the substrate strip. Multiple electronic packages assembled into a strip can be processed simultaneously to improve the production efficiency of the manufacturing process. Each electronic package includes a substrate 301 and multiple electronic components, including a first electronic component 302 and a second electronic component 303.

[0038] The bottom mold 306 may be part of a mold for molding and cooperates with the top mold 307, which is another part of the mold. In embodiments of this application, the bottom mold 306 is generally flat to support an equally flat base strip. In some embodiments, the bottom mold may be a platform of another shape with suitable support and placement for the base strip.

[0039] Subsequently, as shown in Figure 4B, a top mold 307 is positioned above and covers the electronic package, located above the bottom mold 306. The top mold 307 and the base strip form a normally sealed chamber in which the molding process is performed. Specifically, the top mold 307 can be clamped against the bottom mold 306 to prevent relative movement of the base strip between the top mold 307 and the bottom mold 306. In an embodiment, the top mold 307 includes a molding cavity 3071 for receiving the electronic package, and the depth of the molding cavity 3071 should be greater than the height of the electronic package to ensure fluid communication throughout the molding cavity 3071. Specifically, the molding cavity 3071 has a molding surface facing the electronic package. The molding surface has a first molding region 3072 with a first roughness and a second molding region 3073 with a second roughness, wherein the second roughness is greater than the first roughness. For each electronic package, the first molding region 3072 is aligned with a first electronic component 302, and the second molding region 3073 is aligned with a second electronic component 303. Furthermore, the top mold 307 has a first depth in the first molding region 3072, which is greater than the second depth in the second molding region 3073. In some embodiments, the top mold 307 may be an integral structure specifically designed for certain electronic packages. In some other embodiments, the top mold 307 may be an assembly structure that allows for changes in the molding regions 3072 and 3073. Thus, the roughness / depth of the first molding region 3072 and the roughness / depth of the second molding region 3073 can be altered by changing the molding surfaces assembled within the molding cavity 3071, allowing various types of electronic packages conforming to different factor form standards or requirements to be sealed by the top mold 307 without significant modifications to the entire top mold 307.

[0040] In some embodiments, the mold includes a top mold 307 and a bottom mold 306, which may be formed of stainless steel, ceramic, copper, aluminum, or other types of materials. In some embodiments, the design of the mold, including its configuration and layout, can be modified according to the size and number of electronic packages to be housed within the mold.

[0041] Subsequently, as shown in Figure 4C, the sidewall of the top mold 307 is provided with a feed port 309 through which the sealing material 308 can be injected into the molding cavity 3071. Furthermore, the top mold 307 includes vent holes for releasing air during the injection of the sealing material 308. It is understood that the configuration of the feed port and / or vent holes of the top mold 307 can be modified according to some embodiments. Specifically, the sealing material 308 is injected into the molding cavity 3071 through the feed port 309 via a dispenser to seal the substrate 301 and multiple electronic components thereon at appropriate temperature and pressure. Since all electronic packages can be molded simultaneously in a separate molding process, the sealing material 308 injected into the molding cavity 3071 through the feed port 309 can flow and completely fill the molding cavity 3071, as shown in Figure 4D. The sealing material 308 is then baked and cured to form a sealing cap 305 for each electronic package, for example, during a thermosetting process. In this way, the roughness of the upper surface of each sealing cap 305 is substantially equal to the roughness of the corresponding molding surface of the molding cavity 3071, because they adhere tightly to each other during the injection molding process.

[0042] As shown in Figure 4E, the base strips, each covered by an electronic package with a sealing cap 305, can be separated from the mold. Specifically, the top mold 307 also includes an ejector pin 311 inserted into one side of the top mold 307. When the sealing cap 305 is separated from the top mold 307, the ejector pin 311 protrudes from the mold 307 and presses against the edge portion of the base strip. In this way, the electronic package, together with the corresponding sealing cap 305 formed thereon, is pushed away from the top mold 307, thereby demolding it from the top mold 307. In some embodiments, the mold 307 may include two or more ejector pins inserted at both ends or multiple locations of the top mold 307 for simultaneously separating the sealing cap 305 from the top mold 307. For example, the ejector pin 311 may be pressed against a sealing material formed on the base strip rather than against the base strip itself.

[0043] Subsequently, as shown in FIG4F, after separating the substrate 301 from the top mold 307 and the bottom mold 306, a plurality of bumps are formed under each substrate 301 for subsequent semiconductor packaging. In some embodiments, the plurality of bumps 304 may be formed using one or any combination of the following processes: evaporation, electrolytic plating, electroless plating, droplet or screen printing processes.

[0044] Subsequently, the substrate strip with electronic packaging can be divided into individual electronic packages, as shown in Figure 4G. Specifically, for example, the electronic packages can be divided at the dividing channels using a saw blade or laser cutting tool 310. Furthermore, laser markings can be added to the corresponding surfaces of the electronic packages with lower surface roughness, depending on the needs of certain applications.

[0045] Referring to Figure 5, which is a flowchart of a method 400 for manufacturing an electronic package according to an embodiment of this application. As shown in Figure 5, method 400 can begin at block 410 by placing a plurality of electronic packages on a bottom mold. Then, at block 420, a top mold is placed on the electronic packages to form a molding cavity. The molding cavity has a molding surface facing the electronic package, and the molding surface has a first molding region with a first roughness and a second molding region with a second roughness greater than the first roughness. At block 430, a sealing material is injected into the molding cavity of the mold to form a sealing cap on each electronic package. The sealing cap includes an upper surface having a first region and a second region, the first region and the second region corresponding to the first molding region and the second molding region of the molding surface, respectively. At block 440, the electronic packages with corresponding sealing caps are separated from the top mold and the bottom mold. Optionally, the electronic packages can be separated from each other by segmentation, such that each electronic package is sealed to have a sealing cap. Optionally, after forming the sealing cap, an electromagnetic interference shielding layer (EMI) can also be formed on the sealing cap.

[0046] The discussion herein includes numerous illustrative figures illustrating various parts of a semiconductor device and methods of its fabrication. For clarity, these figures do not show all aspects of each example component. Any example device and / or method provided herein may share any or all features with any or all other devices and / or methods provided herein. It will be understood that embodiments described in the context of one device or method are similarly effective for other devices or methods. Similarly, embodiments described in the context of a device are equally effective for a method, and vice versa. Features described in the context of one embodiment may be adapted accordingly to the same or similar features in other embodiments. Features described in the context of one embodiment may be adapted accordingly to other embodiments, even if not explicitly described in those other embodiments. Furthermore, additions and / or combinations and / or substitutions described for a feature in the context of one embodiment may be adapted accordingly to the same or similar features in other embodiments.

[0047] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the embodiments in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended list of exemplary claims.

[0048] 100: Electronic Packaging 101: Base 101a: Upper surface 101b: Lower surface 102: Electronic Components 102a: First electronic component 102b: Second electronic component 104: Bump 105: Sealing cap 1051: Area 1 1052: Second Region 106: Transition Zone 200: Electronic Packaging 201: Base 205: Sealing cap 2051: Area 1 2052: Second Region 301: Base 302: First Electronic Component 303: Second electronic component 304: bump 305: Sealing cap 306: Bottom mold 307: Top mold 3071: Molded cavity 3072: First molding area 3073: Second molding area 308: Sealing material 309: Feed Inlet 310: Laser Cutting Tools 311: Top pin 400: Method 410: Box 420: Box 430: Box 440: Box

Claims

1. A method for manufacturing an electronic package, the method comprising: A substrate strip having multiple electronic packages is placed on a bottom mold, wherein each electronic package includes a substrate and a first electronic component and a second electronic component disposed on the substrate, the first electronic component being higher than the second electronic component; a top mold is placed on the electronic package, wherein the top mold has a molding cavity for receiving the electronic package, the molding cavity having a molding surface facing the electronic package, and wherein the molding surface has a first molding region and a second molding region, the first molding region having a first roughness and the first electronic component being disposed in the first molding region, the second molding region having a second roughness greater than the first roughness and the second electronic component being disposed in the second molding region; a sealing material is injected into the molding cavity to form a sealing cap encapsulating the substrate and the multiple electronic components of each electronic package, wherein the sealing cap includes a first region corresponding to the first molding region and a second region corresponding to the second molding region, the first region being higher than the second region relative to the substrate, and the thickness of the sealing cap sealing the first electronic component in the first region being greater than the thickness of the sealing cap sealing the second electronic component in the second region; each electronic package sealed with the sealing cap is separated from the top mold and the bottom mold; At the dividing channel of the base strip, which is different from the first molding region and the second molding region, the plurality of electronic packages are separated from each other by dividing, such that each electronic package is sealed by a corresponding sealing cap.

2. The method according to request item 1, wherein, The top mold has a first depth in the first molding area, and the first depth is greater than a second depth in the second molding area.

3. The method according to request item 1, wherein, The first roughness is less than 0.8 μm, and the second roughness is greater than 1.8 μm.

4. The method according to request item 1, wherein, The method further includes forming a laser mark in the first region on the upper surface of the sealing cap.

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