Semiconductor device

Abstract

A semiconductor device includes: a substrate having at least one active region defined by an isolation layer; at least one word line extending in a first horizontal direction within the substrate, the at least one word line intersecting the at least one active region; at least one bit line extending in a second horizontal direction orthogonal to the first horizontal direction, the at least one bit line located at a vertical horizontal height higher than the at least one word line; and at least one direct contact electrically connecting the at least one bit line to the at least one active region, the at least one direct contact having a maximum width in a third horizontal direction, the third horizontal direction intersecting each of the first and second horizontal directions at an acute angle.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2022-0116631, filed on September 15, 2022, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

[0003] The embodiments relate to a semiconductor device, and more specifically to a semiconductor device including direct contacts. Prior Technology

[0004] With the rapid development of the electronics industry and the demands of users, electronic devices have become increasingly smaller and lighter. Consequently, the design rules for semiconductor device components have become more stringent due to the need for highly integrated semiconductor devices. This has led to a gradual increase in the difficulty of manufacturing processes that increase the contact area between the conductive patterns constituting the semiconductor device. Summary of the Invention

[0005] According to one embodiment, a semiconductor device is provided, the semiconductor device comprising: a substrate having an active region defined by an isolation layer; a word line extending in a first horizontal direction and intersecting the active region within the substrate; a bit line extending in a second horizontal direction orthogonal to the first horizontal direction at a vertical horizontal height above the word line; and a plurality of direct contacts electrically connecting the bit lines to the active region, wherein each of the plurality of direct contacts has a maximum width in a third horizontal direction intersecting each of the first and second horizontal directions at an acute angle.

[0006] According to another embodiment, a semiconductor device is provided, the semiconductor device comprising: a substrate; an isolation layer defining an active region in the substrate; a word line intersecting the active region in a first horizontal direction while dividing the active region into a first impurity region and a second impurity region; a bit line extending on the substrate in a second horizontal direction orthogonal to the first horizontal direction; and a direct contact electrically connecting the bit line to the first impurity region, wherein the direct contact has a long axis extending in a third horizontal direction intersecting the first and second horizontal directions, and has a shape including a first curve and a second curve intersecting on the long axis.

[0007] According to another embodiment, a semiconductor device is provided, the semiconductor device comprising: a substrate; an isolation layer located in the substrate; an active region including a first impurity region and a second impurity region and defined by the isolation layer, the second impurity regions being separated from each other and the first impurity region being located therebetween; a word line extending in a first horizontal direction within the substrate and intersecting between the first impurity region and the second impurity region; a bit line extending at a vertical horizontal height higher than the word line in a second horizontal direction orthogonal to the first horizontal direction; and a plurality of direct contacts electrically connecting the bit lines to the first impurity region, wherein the direct contacts have a maximum width in a third horizontal direction intersecting each of the first horizontal direction and the second horizontal direction at an acute angle, and the first impurity region has a maximum width in the third horizontal direction. Simple Explanation of the Diagram

[0008] The features will become apparent to those skilled in the art by referring to the accompanying drawings, which illustrate exemplary embodiments in detail. Figure 1A is a layout diagram showing the main components of a semiconductor device according to an embodiment. Figure 1B is a cross-sectional view taken along line I-I' shown in Figure 1A to illustrate a semiconductor device according to an embodiment. Figure 2A is an enlarged layout diagram showing some components of the semiconductor device shown in Figure 1A according to an embodiment. Figure 2B is an enlarged top view of region EX1 shown in Figure 2A. Figures 3A and 3B are enlarged top views showing some components of a semiconductor device according to an embodiment. Figure 4A is a layout diagram showing the main components of a semiconductor device according to some embodiments. Figure 4B is a cross-sectional view taken along line II-II' shown in Figure 4A to illustrate a semiconductor device according to some embodiments. Figures 5A to 13B are top and cross-sectional views of various stages in a method for manufacturing a semiconductor device according to an embodiment. Figure 14 is a block diagram illustrating a system including a semiconductor device according to an embodiment. Implementation

[0009] Figure 1A is a layout diagram showing the main components of a semiconductor device 100 according to an embodiment. Figure 1B is a cross-sectional view taken along line I-I' shown in Figure 1A.

[0010] Referring to FIG1A, a semiconductor device 100 may include a plurality of active regions ACT that extend horizontally in a diagonal direction relative to a first horizontal direction D1 and a second horizontal direction D2 in a top view. In some embodiments, the plurality of active regions ACT may extend in a fourth horizontal direction D4. It should be noted that, hereinafter, "horizontal direction" refers to a direction parallel to the top surface of the substrate, and elements extending horizontally in the "diagonal direction" extend parallel to the top surface of the substrate while extending at an oblique angle relative to either edge of the substrate. "Vertical" direction or horizontal height refers to a direction or distance along a direction normal to or perpendicular to the top surface of the substrate.

[0011] Multiple character lines WL can extend parallel to each other in a first horizontal direction D1 and can intersect with the multiple active regions ACT. Above the multiple character lines WL, multiple bit lines BL can extend parallel to each other in a second horizontal direction D2 that intersects with the first horizontal direction D1.

[0012] The plurality of bit lines BL can be connected to the plurality of active regions ACT via a plurality of direct contacts DC. In some embodiments, a plurality of buried contacts BC can be formed between two adjacent bit lines BL. Each of the plurality of buried contacts BC can extend to the top of either of the two adjacent bit lines BL. In some embodiments, the plurality of buried contacts BC can be arranged in a row in a first horizontal direction D1 and a second horizontal direction D2.

[0013] Multiple landing pads LP can be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP can connect the lower electrode of the capacitor formed on the plurality of bit lines BL to the plurality of active regions ACT. The plurality of landing pads LP can partially overlap with the plurality of buried contacts BC. The semiconductor device 100 will be described in more detail below.

[0014] Referring to FIG1B, the semiconductor device 100 may include a substrate 101, in which the plurality of active regions ACT are defined by an isolation layer 112.

[0015] The substrate 101 may be a silicon (Si) wafer. Alternatively, the substrate 101 may be a wafer containing semiconductor elements (e.g., germanium (Ge)) or compound semiconductors (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). Additionally, the substrate 101 may have a silicon-on-insulator (SOI) structure. Furthermore, the substrate 101 may include conductive regions, such as doped wells or doped structures.

[0016] An isolation layer 112 may be formed in a first trench T1 formed in the substrate 101. The isolation layer 112 may comprise, for example, silicon oxide, silicon nitride, or a combination thereof. In the substrate 101, the active region ACT may be defined by the isolation layer 112.

[0017] The active region ACT can be arranged in a bar shape extending diagonally relative to the first horizontal direction D1 and the second horizontal direction D2. Specifically, the active region ACT can extend in a fourth horizontal direction D4, for example, intersecting the first horizontal direction D1 and the second horizontal direction D2 at an oblique angle. The active region ACT may include a first impurity region SD1 and a second impurity region SD2, the second impurity regions SD2 being separated from each other and with the first impurity region SD1 located between them; for example, the first impurity region SD1 may be located between two second impurity regions SD2 within the same active region ACT. A channel region can be formed between each of the first impurity region SD1 and the second impurity region SD2.

[0018] In the substrate 101, the plurality of character lines WL described above with reference to FIG1A may be embedded. A buffer layer 122 may be formed on the substrate 101. The buffer layer 122 may cover the upper surface of the isolation layer 112. For example, the buffer layer 122 may include a stacked structure composed of a first silicon oxide, a silicon nitride and a second silicon oxide sequentially formed on the substrate 101.

[0019] The plurality of bit lines BL extending parallel to each other in the second horizontal direction D2 may be located on the buffer layer 122. The plurality of bit lines BL may be separated from each other in the first horizontal direction D1. A direct contact DC may be located on a local region of each of the plurality of active regions ACT. Specifically, the direct contact DC may be located on the first impurity region SD1 of each of the plurality of active regions ACT. Each of the plurality of bit lines BL may be connected to the active region ACT via the direct contact DC. The direct contact DC may comprise, for example, tungsten (W), tungsten nitride (WN), cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or combinations thereof. In some embodiments, the direct contact DC may comprise doped polycrystalline silicon. The direct contact DC will be described in more detail below.

[0020] In some embodiments, the lower conductive layer 130 may comprise doped polycrystalline silicon. Each of the intermediate conductive layer 132 and the upper conductive layer 134 may comprise a layer comprising Ti, TiN, titanium silicon nitride (TiSiN), W, WN, tungsten silicon silicide (WSi), tungsten silicon nitride (WSiN), Ru, or combinations thereof. For example, the intermediate conductive layer 132 may comprise a TiN layer and / or a TiSiN layer, and the upper conductive layer 134 may comprise a layer comprising Ti, TiN, W, WN, WSiN, Ru, or combinations thereof. The insulating top cover pattern 136 may comprise silicon nitride. For example, as shown in FIG1B, the lower conductive layer 130, the intermediate conductive layer 132, and the upper conductive layer 134 may be stacked on top of each other to form each of the plurality of bit lines BL.

[0021] In a localized area of ​​substrate 101, a plurality of recessed spaces R1 may be formed in the active region ACT. Each of the plurality of recessed spaces R1 may be filled with a plurality of contact plugs 150. Each of the plurality of contact plugs 150 may have a pillar shape extending from the recessed space R1 in the vertical direction D5. Each of the plurality of contact plugs 150 may contact the active region ACT. The lower end portion of each of the plurality of contact plugs 150 may be located at a horizontal height lower than the upper surface of substrate 101, to be embedded in substrate 101. The plurality of contact plugs 150 may comprise, for example, only metal, metal and metal silicide layers, or doped polycrystalline silicon.

[0022] The plurality of contact plugs 150 may be arranged in a row in a second horizontal direction D2 between adjacent pairs of bit lines BL selected from the plurality of bit lines BL. An insulating fence may be provided between each pair of the plurality of contact plugs 150 arranged in the second horizontal direction D2. The plurality of contact plugs 150 may be insulated from each other by the insulating fence. For example, the insulating fence may comprise silicon nitride. The insulating fence may have a column shape extending on the substrate 101 in the vertical direction D5.

[0023] The plurality of contact plugs 150 may each have a plurality of metal silicate layers 152 and a plurality of overlapping pads LP. Each of the plurality of overlapping pads LP may extend longitudinally in the vertical direction D5 above the contact plug 150. Each of the plurality of overlapping pads LP may be electrically connected to the contact plug 150 via the metal silicate layers 152.

[0024] Each of the plurality of overlapping pads LP may include a conductive barrier layer 154 and a metal layer 156. In some embodiments, the conductive barrier layer 154 may comprise Ti, TiN, or a combination thereof, and the metal layer 156 may comprise W. In a top view, the plurality of overlapping pads LP may have a patterned shape consisting of a plurality of islands. In some embodiments, the metal silicate layer 152 may comprise, for example, cobalt silicate, nickel silicate, or manganese silicate. In some embodiments, the metal silicate layer 152 may be omitted.

[0025] The contact plug 150 and the metal silicate layer 152 can form a buried contact BC. The contact plug 150, the metal silicate layer 152 and the overlapping pad LP sequentially disposed on the substrate 101 can form a contact structure electrically connected to the active region ACT at a position adjacent to the bit line BL in the first horizontal direction D1.

[0026] Each of the plurality of bit lines BL has two (e.g., opposite) sidewalls and a plurality of insulating top cover patterns 136 covering the upper surfaces of the plurality of bit lines BL, respectively, which may be covered by spacer structures SP. A spacer structure SP may be located between one of the plurality of bit lines BL and a plurality of contact plugs 150 arranged in a row in a second horizontal direction D2 adjacent to the one bit line BL. Each of the plurality of spacer structures SP may include an inner spacer 142, an intermediate spacer 146, and an outer spacer 148.

[0027] The inner spacer 142 may contact each of the sidewalls of the bit line BL and the sidewalls of the direct contact DC. The inner spacer 142 may include a portion that contacts the contact plug 150. The inner spacer 142 may contain, for example, silicon nitride.

[0028] Intermediate spacer 146 may be located in a first horizontal direction D1 between inner spacer 142 and outer spacer 148. Intermediate spacer 146 may have a sidewall facing the bit line BL (inner spacer 142 is located between said sidewall and bit line BL) and a sidewall facing the contact plug 150, metal silicate layer 152 and overlap pad LP (outer spacer 148 is located between said sidewall and contact plug 150, metal silicate layer 152 and overlap pad LP). Intermediate spacer 146 may comprise, for example, silicon oxide, an air spacer or a combination thereof.

[0029] The outer spacer 148 can contact the sidewall of each of the contact plug 150, the metal silicate layer 152, and the overlap pad LP. The outer spacer 148 can be separated from the inner spacer 142, with an intermediate spacer 146 located between the outer spacer 148 and the inner spacer 142. In some embodiments, the outer spacer 148 may comprise, for example, silicon nitride.

[0030] The spacer structure SP can extend parallel to the bit line BL in the second horizontal direction D2. The insulating top cover pattern 136 and the spacer structure SP can form an insulating structure covering the upper surface and two sidewalls of the bit line BL.

[0031] A gap-fill pattern 144 may be present between the direct contact DC and the contact plug 150. The gap-fill pattern 144 may be detachable from the direct contact DC, with an inner spacer 142 located between the gap-fill pattern 144 and the direct contact DC. The gap-fill pattern 144 may surround the direct contact DC by covering its sidewalls. The gap-fill pattern 144 may contact the inner spacer 142 and the contact plug 150. In some embodiments, the gap-fill pattern 144 may comprise silicon nitride. The structure including the inner spacer 142 and the gap-fill pattern 144 may be referred to as an insulating pattern IP.

[0032] Although not shown in Figure 1B, multiple capacitors may be located on the multiple overlapping pads LP. The multiple capacitors may include multiple lower electrodes, a capacitor dielectric layer, and a upper electrode. The capacitor dielectric layer may cover the multiple lower electrodes. The upper electrode may cover the capacitor dielectric layer and face the multiple lower electrodes, with the capacitor dielectric layer located between the upper electrode and the multiple lower electrodes.

[0033] Figure 2A is an enlarged layout view of some components of the semiconductor device 100 according to an embodiment. Figure 2B is an enlarged top view of region EX1 shown in Figure 2A. For ease of explanation, only some components are shown in Figures 2A and 2B.

[0034] Referring to Figure 2A, the plurality of character lines WL can extend in a first horizontal direction D1 and can intersect with the plurality of active regions ACT. The active region ACT may include a first impurity region SD1 (e.g., in the center of the active region ACT) and a second impurity region SD2 (e.g., at the edge of the active region ACT), the second impurity region SD2 being separated from each other and the first impurity region SD1 located between them. The character lines WL can divide the active region ACT into the first impurity region SD1 and the second impurity region SD2; for example, two character lines WL can intersect each active region ACT. The first impurity region SD1 and the second impurity region SD2 can be separated from each other and the character lines WL are located between them.

[0035] A direct contact DC can be electrically connected to the first impurity region SD1. Specifically, the direct contact DC can be located on the first impurity region SD1 of each of the plurality of active regions ACT. That is, each of the plurality of bit lines BL can be connected to the first impurity region SD1 via the direct contact DC.

[0036] In some embodiments, the direct contact DC may have a shape that is elongated in the third horizontal direction D3; for example, the direct contact DC may extend longitudinally in the third horizontal direction D3. That is, the direct contact DC may have a maximum width L in the third horizontal direction D3; for example, the direct contact DC may have its longest dimension in the third horizontal direction D3. In some embodiments, a plurality of direct contact DCs may be separated from each other in a diagonal direction intersecting the first horizontal direction D1 and the second horizontal direction D2. For example, the plurality of direct contact DCs may be separated from each other in the third horizontal direction D3 (e.g., in a direction at an oblique or acute angle relative to each of the first horizontal direction D1 and the second horizontal direction D2). As another example, the plurality of direct contact DCs may be separated from each other in a fourth horizontal direction D4. As yet another example, the plurality of direct contact DCs may be separated from each other in another diagonal direction intersecting the third horizontal direction D3 and the fourth horizontal direction D4.

[0037] Referring to Figure 2B, in some embodiments, the third horizontal direction D3 of the direct contact DC having the maximum width may differ from the fourth horizontal direction D4 extending from the active area ACT. For example, the longitudinal direction of the direct contact DC and the longitudinal direction of the active area ACT may differ from each other. Specifically, when each of the third horizontal direction D3 and the fourth horizontal direction D4 intersects the first horizontal direction D1 and the second horizontal direction D2 at an acute angle, the third horizontal direction D3 may intersect the first horizontal direction D1 at an angle smaller than the angle at which the fourth horizontal direction D4 intersects the first horizontal direction D1. For example, as shown in Figure 2B, the third horizontal direction D3 may intersect the first horizontal direction D1 at a first angle θ1, and the fourth horizontal direction D4 may intersect the first horizontal direction D1 at a second angle θ2 larger than the first angle θ1.

[0038] In some embodiments, the third horizontal direction D3 (where the direct contact DC has the maximum width) may be the direction in which the first impurity region SD1 has the maximum width. Specifically, the first impurity region SD1, defined by the character line WL, may have a shape inclined in the fourth horizontal direction D4, similar to the active region ACT, and may have the maximum width in the horizontal direction intersecting the fourth horizontal direction D4. For example, when the first impurity region SD1 has a substantially near-parallelogram shape, the first impurity region SD1 may have the maximum width in the diagonal direction, which may be the third horizontal direction D3 in which the direct contact DC has the maximum width. For example, referring to FIG2B, although the entire active region ACT is inclined at a second angle θ2 relative to the first horizontal direction D1 (i.e., in the fourth horizontal direction D4), both the direct contact DC and the first impurity region SD1 may have a shape in which the maximum width is inclined at a first angle θ1 relative to the first horizontal direction D1 (i.e., in the third horizontal direction D3). For example, as further shown in FIG2B, since the direct contact DC and the first impurity region SD1 have the maximum width in the same direction (e.g., at an angle relative to the edge of the substrate 101), the overlap area between the direct contact DC and the first impurity region SD1 may be increased. For example, the direct contact DC can completely cover the first impurity region SD1 and can overlap with the first impurity region SD1.

[0039] In some embodiments, unlike FIG. 2B, the direction in which the first impurity region SD1 has its maximum width may differ from the direction in which the direct contact DC has its maximum width. For example, the angle at which the direction in which the first impurity region SD1 has its maximum width intersects the first horizontal direction D1 may be smaller than the angle at which it intersects the third horizontal direction D3. As another example, the angle at which the direction in which the first impurity region SD1 has its maximum width intersects the first horizontal direction D1 may be greater than the angle at which it intersects the third horizontal direction D3.

[0040] In some embodiments, the direct contact DC may be arranged to have its maximum width in a third horizontal direction D3, which intersects the first horizontal direction D1 and the second horizontal direction D2. For example, as viewed in a top view, the direct contact DC may have an oval shape having a long axis extending in the third horizontal direction D3.

[0041] Figures 3A and 3B are enlarged top views showing some components of semiconductor devices 100a and 100b according to embodiments.

[0042] Referring to Figure 3A, the direct contact DC may have a shape having a long axis extending in a third horizontal direction D3 and including a first curve CL1 and a second curve CL2 that are recessed relative to the long axis. In some embodiments, the direct contact DC may include the first curve CL1 and the second curve CL2 that intersect each other at two points, and the two intersection points may be two points on the long axis extending in the third horizontal direction D3. That is, the distance between the two intersection points may be the maximum value among the distances between any two points on the first curve CL1 and the second curve CL2.

[0043] In some embodiments, the first curve CL1 and the second curve CL2 may intersect each other at their cusps on the major axis. That is, the direct contact DC may not have a complete oval shape, but rather a twisted shape with two vertices.

[0044] Referring to Figure 3B, the direct contact DC may have a shape having a long axis extending in a third horizontal direction D3 and including first to fourth curves CL1, CL2, CL3, and CL4 that are concave relative to the long axis. In some embodiments, the direct contact DC may have a shape including first to fourth curves CL1, CL2, CL3, and CL4 that intersect each other, and the two intersection points with the largest distance between them may be two points on the long axis extending in the third horizontal direction D3. That is, the maximum distance between the two intersection points may be the maximum value among the distances between any two points on the first to fourth curves CL1, CL2, CL3, and CL4.

[0045] In some embodiments, the first curve CL1 intersects with the second curve CL2, the second curve CL2 with the third curve CL3, the third curve CL3 with the fourth curve CL4, and the fourth curve CL4 with the first curve CL1, respectively, at their respective cusps. That is, the direct contact DC may not have a complete oval shape, but rather a twisted shape with four vertices. In some embodiments, the direct contact DC may have a shape similar to a parallelogram, the parallelogram comprising four sides recessed relative to the center of the parallelogram.

[0046] Figure 4A is a layout diagram showing the main components of a semiconductor device 200 according to some embodiments. Figure 4B is a cross-sectional view taken along line II-II' shown in Figure 4A.

[0047] Referring to Figures 4A and 4B, a semiconductor device 200 with an additional pad 210 is provided. Hereinafter, the differences from the semiconductor device 100 illustrated with reference to Figures 1A and 1B will be primarily described.

[0048] The plurality of active regions ACT can be arranged in a strip shape extending in a fourth horizontal direction D4 intersecting the first horizontal direction D1 and the second horizontal direction D2. For example, as shown in Figures 4A and 4B, the additional pad 210 may have a larger horizontal width than the active region ACT (e.g., in the first horizontal direction D1) and may be located on each of the plurality of active regions ACT. In another example, the additional pad 210 may have a horizontal width no greater than the horizontal width of the active region ACT.

[0049] In some embodiments, a direct contact DC and a pair of contact plugs 150 may be electrically connected to different active regions ACT among the plurality of active regions ACT, the pair of contact plugs 150 facing each other with the direct contact DC located therebetween. That is, the contact plug 150 may be directly connected to an additional pad 210 by forming a contact surface between the contact plug 150 and the additional pad 210, the additional pad 210 having a horizontal width larger than the active region ACT.

[0050] The contact plug 150 and the metal silicate layer 152 can form a buried contact BC. The contact plug 150, the metal silicate layer 152 and the overlapping pad LP sequentially disposed on the substrate 101 can form a contact structure, which is electrically connected to the active region ACT via an additional pad 210 at a position adjacent to the bit line BL in the first horizontal direction D1.

[0051] In some embodiments, the lowest surface of the contact plug 150 may be at a height higher than the lowest surface of the additional pad 210 but lower than the highest surface of the additional pad 210. Additionally, the lowest surface of the contact plug 150 may be at a height higher than the highest surface of the active region ACT but lower than the highest surface of the insulating layer 112. That is, the contact plug 150 may be electrically connected to the active region ACT via the additional pad 210 without direct contact with the active region ACT.

[0052] For example, the additional pad 210 may comprise a single-layer structure formed of doped polycrystalline silicon. In this case, the plurality of contact plugs 150 may be made entirely of doped polycrystalline silicon.

[0053] In another example, the additional pad 210 may comprise a single-layer structure formed of metal. In this case, the plurality of contact plugs 150 may be made entirely of metal.

[0054] In some embodiments, unlike Figures 4A and 4B, the additional pad 210 may have a stacked structure comprising a lower pad containing doped polycrystalline silicon and an upper pad containing metal. Herein, the contact plug 150 may comprise a metal formed of substantially the same material as the upper pad. In some embodiments, the contact plug 150 may be in direct contact with the upper pad, and in this case, the contact plug 150 and the upper pad comprise the same material, and therefore the contact resistance between the contact plug 150 and the upper pad can be very low.

[0055] In some embodiments, the additional pad 210 may further include a metal silicate layer located between the lower pad and the upper pad. Additionally, the contact plug 150 may further include a metal silicate layer along its contact surface with the upper pad.

[0056] In some embodiments, unlike Figures 4A and 4B, the additional pad 210 may have a smaller horizontal width than the active region ACT. In this case, the semiconductor device 200 may include an additional pad 210 disposed on the active region ACT and having a smaller horizontal width than the active region ACT, and additional spacers formed on the two sidewalls of the additional pad 210.

[0057] According to an embodiment, a semiconductor device 100 (or 200) including a direct contact DC having a maximum width in a third horizontal direction D3 can be provided. In this embodiment, by arranging the direct contact DC to have a maximum width in the third horizontal direction D3, the contact area between the direct contact DC and the first impurity region SD1 can be increased. In this embodiment, by arranging the direct contact DC to have a maximum width in the third horizontal direction D3, the electrical connection between the bit line BL and the active region ACT can be improved. Therefore, a semiconductor device with improved performance and reliability can be provided.

[0058] Figures 5A to 13B are top views and cross-sectional views of various stages in the method of manufacturing a semiconductor device 100 according to an embodiment. Specifically, Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A are top views illustrating the method of manufacturing a semiconductor device 100 by showing only some components according to the process sequence. Figures 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, and 13B are cross-sectional views taken along line III-III' shown in Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A to illustrate the method of manufacturing a semiconductor device 100.

[0059] Referring to Figures 5A and 5B, an isolation layer 112 can be formed on substrate 101. Active regions ACT can be defined by the isolation layer 112. An impurity implantation process can be performed on the active regions ACT to form a first impurity region SD1 and a pair of second impurity regions SD2 on each active region ACT. The pair of second impurity regions SD2 can be horizontally separated from each other with a first impurity region SD1 located between them. The first impurity region SD1 and the second impurity region SD2 can be doped to have the same conductivity type (e.g., N-type).

[0060] An insulating layer 113 and a polycrystalline silicon layer 114 may be formed on the substrate 101. The insulating layer 113 may include multiple insulating layers. The insulating layer 113 may include a silicon oxide layer, a silicon nitride layer, or a combination thereof. The polycrystalline silicon layer 114 may include a doped polycrystalline silicon layer. The insulating layer 113 may include the buffer layer 122 shown in FIG. 1B.

[0061] On the polycrystalline silicon layer 114, a target masking layer TM, a first insulating layer IL1, a first masking layer ML1, a second insulating layer IL2, a second masking layer ML2, a third insulating layer IL3, a third masking layer ML3, and a fourth insulating layer IL4 can be formed sequentially. For example, as shown in FIG5B, a stack of alternating masking layers and insulating layers can be formed on the polycrystalline silicon layer 114.

[0062] The target masking layer TM may include a spin-on hard mask (SOH) layer. The target masking layer TM may further include a silicon oxide layer located beneath the SOH layer. The first insulating layer IL1 may include a silicon nitride layer and / or a silicon oxynitride layer. The first masking layer ML1 may include an SOH layer. The second insulating layer IL2 may include a silicon nitride layer and / or a silicon oxynitride layer. The second masking layer ML2 may include an SOH layer. The third insulating layer IL3 may include a silicon nitride layer and / or a silicon oxynitride layer. The third masking layer ML3 may include an SOH layer. The fourth insulating layer IL4 may include a silicon nitride layer and / or a silicon oxynitride layer.

[0063] A first photoresist layer PR1 can be formed on the fourth insulating layer IL4. A first photomask can be used to pattern the first photoresist layer PR1.

[0064] Referring to Figures 6A and 6B, the first opening OP1 can be formed by patterning the fourth insulating layer IL4 and the third masking layer ML3. The first opening OP1 can extend in a horizontal direction parallel to the upper surface of the substrate 101. For example, the first opening OP1 can extend in a first horizontal direction D1, like the character line WL. As another example, the first opening OP1 can extend in a second horizontal direction D2. That is, the first opening OP1 can extend in a direction intersecting with the character line WL. In the specification, although the first horizontal direction D1 or the second horizontal direction D2 is described as the direction in which the first opening OP1 is patterned, this is only illustrative, and the first opening OP1 can also be patterned in another horizontal direction.

[0065] Forming the first opening OP1 may include using a patterned first photoresist layer PR1 on the fourth insulating layer IL4 as an etching mask to pattern the fourth insulating layer IL4 and the third mask layer ML3. The remaining first photoresist layer PR1 may then be removed.

[0066] A first insulating film IF1 may be conformally formed over the front surface (e.g., the upper surface) of substrate 101. The first insulating film IF1 may be formed on the exposed side surfaces of the fourth insulating layer IL4 and the third masking layer ML3. The first insulating film IF1 may define a first opening OP1 together with the third insulating layer IL3; for example, the width of the first opening OP1 between opposing surfaces of the first insulating film IF1 in the second horizontal direction D2 may be L1. The third insulating layer IL3 may be exposed through the first opening OP1. The first insulating film IF1 may include a silicon oxide layer. The first insulating film IF1 may be formed by atomic layer deposition (ALD). After the formation of the first insulating film IF1, a first etch-back process may be performed. By the first etch-back process, the portions of the first insulating film IF1 located on the fourth insulating layer IL4 and the portions of the first insulating film IF1 located on the third insulating layer IL3 may be removed.

[0067] Referring to Figures 7A and 7B, the second opening OP2 can be formed by patterning the third insulating layer IL3 and the second masking layer ML2. The second opening OP2 can extend in a direction parallel to the first opening OP1. That is, the second opening OP2 can extend in a horizontal direction parallel to the upper surface of the substrate 101. For example, the second opening OP2 can extend in the first horizontal direction D1, like the character line WL. As another example, the second opening OP2 can extend in the second horizontal direction D2. That is, the second opening OP2 can extend in a direction intersecting with the character line WL. In embodiments, similar to the first opening OP1, the second opening OP2 can also be patterned in a horizontal direction different from the first horizontal direction D1 and the second horizontal direction D2, but parallel to the first opening OP1.

[0068] In some embodiments, the width of the second opening OP2 may be less than half the width of the first opening OP1. In some embodiments, the width of the second opening OP2 may be approximately one-third the width of the first opening OP1. For example, referring to Figures 6A to 7B, when the first opening OP1 and the second opening OP2 extend in the first horizontal direction D1, the width of the first opening OP1 in the second horizontal direction D2 may be L1 (see Figure 6A), and the width of the second opening OP2 in the second horizontal direction D2 may be L2. In other words, the width L2 of the second opening OP2 in the second horizontal direction D2 may be approximately one-third the width L1 of the first opening OP1 in the second horizontal direction D2.

[0069] Forming the second opening OP2 may include using a first insulating film IF1 on the third insulating layer IL3 as an etching mask to remove the fourth insulating layer IL4 and the third mask layer ML3, and patterning the third insulating layer IL3 and the second mask layer ML2. Afterward, the first insulating film IF1 may be removed.

[0070] A second insulating film IF2 can be conformally formed above the front surface of substrate 101. The second insulating film IF2 can be formed on the exposed side surfaces of the third insulating layer IL3 and the second masking layer ML2. The second insulating film IF2, together with the second insulating layer IL2, defines a second opening OP2. The second insulating layer IL2 can be exposed through the second opening OP2. The second insulating film IF2 may include a silicon oxide layer. The second insulating film IF2 can be formed by ALD (Alternating Deposition). After the formation of the second insulating film IF2, a second etching process can be performed. Through the second etching process, the portions of the second insulating film IF2 located on the third insulating layer IL3 and the portions of the second insulating film IF2 located on the second insulating layer IL2 can be removed.

[0071] Referring to Figures 8A and 8B, the third opening OP3 can be formed by patterning the first insulating layer IL1. The third opening OP3 can extend in a direction parallel to the second opening OP2 and the first opening OP1. That is, the third opening OP3 can extend in a horizontal direction parallel to the upper surface of the substrate 101. For example, the third opening OP3 can extend in the first horizontal direction D1, like the character line WL. As another example, the third opening OP3 can extend in the second horizontal direction D2. That is, the third opening OP3 can extend in a direction intersecting with the character line WL. In this embodiment, similar to the first opening OP1 and the second opening OP2, the third opening OP3 can be patterned in a horizontal direction different from the first horizontal direction D1 and the second horizontal direction D2 and parallel to the first opening OP1 and the second opening OP2. The target mask layer TM can be exposed through the third opening OP3.

[0072] In some embodiments, the width of the third opening OP3 may be substantially the same as the width of the second opening OP2. In some embodiments, the width of the third opening OP3 may be approximately one-third of the width of the first opening OP1. For example, when the first opening OP1, the second opening OP2, and the third opening OP3 extend in the first horizontal direction D1, the width of the third opening OP3 in the second horizontal direction D2 may be L3. In other words, the width L3 of the third opening OP3 in the second horizontal direction D2 may be substantially the same as the width L2 of the second opening OP2 in the second horizontal direction D2, and may be approximately one-third of the width L1 of the first opening OP1 in the second horizontal direction D2.

[0073] Forming the third opening OP3 may include using the second insulating film IF2 on the second insulating layer IL2 as an etching mask to remove the third insulating layer IL3 and the second mask layer ML2, and patterning the second insulating layer IL2 and the first mask layer ML1. The second insulating layer IL2 and the first mask layer ML1 may be used as etching masks to pattern the first insulating layer IL1. In some embodiments, the patterning process of the second insulating layer IL2, the first mask layer ML1, and the first insulating layer IL1 may be performed simultaneously. Alternatively, the patterning process of the second insulating layer IL2, the first mask layer ML1, and the first insulating layer IL1 may be performed sequentially. Thereafter, the second insulating layer IL2 and the first mask layer ML1 may be removed.

[0074] Referring to Figures 9A and 9B, a fourth masking layer ML4, a fifth insulating layer IL5, and a sixth insulating layer IL6 can be sequentially formed on the target masking layer TM. The fourth masking layer ML4 can cover the patterned first insulating layer IL1. The fourth masking layer ML4 can fill the third opening OP3. Although the first insulating layer IL1 and the third opening OP3 are not shown in Figure 9A because they are covered by the fourth masking layer ML4, they are represented by dashed lines in Figure 9A for ease of explanation.

[0075] The fourth masking layer ML4 may include an SOH layer. The fifth insulating layer IL5 may include a silicon nitride layer and / or a silicon oxynitride layer. The fifth masking layer ML5 may include an SOH layer. The sixth insulating layer IL6 may include a silicon nitride layer and / or a silicon oxynitride layer.

[0076] A second photoresist layer PR2 can be formed on the sixth insulating layer IL6. A second photomask can be used to pattern the second photoresist layer PR2. The patterned second photoresist layer PR2 can extend in a diagonal direction intersecting the first horizontal direction D1 and the second horizontal direction D2. As shown in FIG9A, the patterned second photoresist layer PR2 can extend in the sixth horizontal direction D6. As described with reference to FIG1A, the sixth horizontal direction D6 can be selected such that the plurality of direct contacts DC have a major axis in the third horizontal direction D3. The sixth horizontal direction D6 can be the diagonal direction shown in FIG1A, in which the plurality of direct contacts DC are separated from each other.

[0077] Referring to Figures 10A and 10B, the fourth opening OP4 can be formed by patterning the sixth insulating layer IL6 and the fifth masking layer ML5. The fourth opening OP4 can extend in a horizontal direction parallel to the upper surface of the substrate 101. For example, the fourth opening OP4 can extend in the sixth horizontal direction D6. Although the first insulating layer IL1 and the third opening OP3 are not shown because they are covered by the fifth insulating layer IL5 and the fourth masking layer ML4, for ease of explanation, the first insulating layer IL1 and the third opening OP3 are represented by dashed lines in Figure 10A.

[0078] Forming the fourth opening OP4 may include using a patterned second photoresist layer PR2 on the sixth insulating layer IL6 as an etching mask to pattern the sixth insulating layer IL6 and the fifth mask layer ML5. The remaining second photoresist layer PR2 can then be removed.

[0079] A third insulating film IF3 can be conformally formed above the front surface of substrate 101. The third insulating film IF3 can be formed on the exposed side surfaces of the sixth insulating layer IL6 and the fifth masking layer ML5. The third insulating film IF3, together with the fifth insulating layer IL5, defines a fourth opening OP4. The fifth insulating layer IL5 can be exposed through the fourth opening OP4. The third insulating film IF3 may include a silicon oxide layer. The third insulating film IF3 can be formed by ALD (Alternating Deposition). After the formation of the third insulating film IF3, a third etching process can be performed. By the third etching process, the portions of the third insulating film IF3 located on the sixth insulating layer IL6 and the portions of the third insulating film IF3 located on the fifth insulating layer IL5 can be removed.

[0080] Referring to Figures 11A and 11B, the fifth insulating layer IL5 can be patterned. Patterning the fifth insulating layer IL5 may include using the third insulating film IF3 on the fifth insulating layer IL5 as an etching mask to remove the sixth insulating layer IL6 and the fifth masking layer ML5, and then patterning the fifth insulating layer IL5. In some embodiments, the process of patterning the sixth insulating layer IL6, the fifth masking layer ML5, and the fifth insulating layer IL5 can be performed simultaneously. Alternatively, the process of patterning the sixth insulating layer IL6, the fifth masking layer ML5, and the fifth insulating layer IL5 can be performed sequentially. Although the first insulating layer IL1 and the third opening OP3 are not shown because they are covered by the fourth masking layer ML4, they are represented by dashed lines for ease of explanation.

[0081] Referring to Figures 12A and 12B, the fifth opening OP5 can be formed by patterning the fourth masking layer ML4. The fifth opening OP5 can extend in a direction parallel to the fourth opening OP4. That is, the fifth opening OP5 can extend in a horizontal direction parallel to the upper surface of the substrate 101. For example, the fifth opening OP5 can extend in a sixth horizontal direction D6. For ease of explanation, the portion of the first insulating layer IL1 that is not shown is indicated by dashed lines because it is covered by the fifth insulating layer IL5.

[0082] Forming the fifth opening OP5 may include using a fifth insulating layer IL5 on the fourth masking layer ML4 as an etching mask to remove a portion of the fourth masking layer ML4, thereby exposing the first insulating layer IL1 through the fifth opening OP5. Using the exposed first insulating layer IL1 as an etching mask, a portion of the fourth masking layer ML4 can be further removed. By further removing said portion of the fourth masking layer ML4, using the exposed first insulating layer IL1 as an etching mask, the third opening OP3 can be exposed again. By exposing the third opening OP3, the target masking layer TM can be exposed.

[0083] In some embodiments, as shown in FIG12A, the exposed target masking layer TM may have a parallelogram shape in the top view (e.g., the dashed portion between layers IL1 and IL5). This may be because the first insulating layer IL1 has been patterned on the first horizontal direction D1, and the fifth insulating layer IL5 has been patterned on the sixth horizontal direction D6, which is a diagonal direction intersecting the first horizontal direction D1.

[0084] Referring to Figures 13A and 13B, multiple direct contact holes (DCHs) can be formed by patterning the target mask layer TM. The active region ACT of substrate 101 can be exposed through the direct contact holes (DCHs). Specifically, the first impurity region SD1 of substrate 101 can be exposed through the direct contact holes (DCHs).

[0085] Patterning the target mask layer TM may include patterning the target mask layer TM exposed through the fifth opening OP5 and the third opening OP3. Specifically, patterning the target mask layer TM may include using a fifth insulating layer IL5 extending in the sixth horizontal direction D6 and a first insulating layer IL1 extending in the first horizontal direction D1 as an etching mask to pattern the target mask layer TM, for example, etching the exposed parallelogram shape of the target mask layer TM.

[0086] As shown in Figure 13A, unlike the parallelogram shape of the exposed target mask layer in Figure 12A, the etched shape of the direct contact hole DCH formed by patterning the target mask layer TM may not be a straight parallelogram, but rather a shape close to a smoothed parallelogram (e.g., with curved lines). For example, due to the etching process, the etched shape of the direct contact hole DCH may be closer to an oval shape or a twisted oval shape (e.g., a twisted oval shape with vertices shown in Figures 3A and 3B). Specifically, etching may not be performed entirely on the vertices of the parallelogram shape and the portions adjacent to them. Therefore, since these portions are not etched, a direct contact hole with a smooth parallelogram shape can be formed.

[0087] In some embodiments, the direct contact hole DCH may have a shape extending longitudinally in a third horizontal direction D3 (e.g., having a longitudinal direction). That is, the direct contact hole DCH may have a maximum width in the third horizontal direction D3. For example, the direct contact hole DCH may have an oval shape having a long axis extending in the third horizontal direction D3. For example, the direct contact hole DCH may have a shape having a long axis extending in the third horizontal direction D3 and including a first curve CL1 and a second curve CL2 recessed relative to the long axis (FIG. 3A). As another example, the direct contact hole DCH may have a shape having a long axis extending in the third horizontal direction D3 and including a first to a fourth curve CL1, CL2, CL3 and CL4 recessed relative to the long axis (FIG. 3B). That is, the direct contact hole DCH may have a shape formed by smoothing the four vertices of a parallelogram.

[0088] In some embodiments, the plurality of direct contact holes DCH may be separated from each other in the sixth horizontal direction D6.

[0089] In some embodiments, the angle at which the sixth horizontal direction D6 intersects the first horizontal direction D1 and the second horizontal direction D2 at an acute angle may be greater than the angle at which it intersects the third horizontal direction D3. In some embodiments, unlike in FIG13A, the angle at which the sixth horizontal direction D6 intersects the first horizontal direction D1 may be smaller than the angle at which it intersects the third horizontal direction D3. In some embodiments, the sixth horizontal direction D6 may be parallel to the third horizontal direction D3.

[0090] The subsequent processes for manufacturing the semiconductor device 100 will be obvious to those with ordinary knowledge of this technology, and therefore will not be described in detail here.

[0091] As shown in Figures 1A, 1B, and 5A to 13B, the semiconductor device 100 may include direct contacts DC, which can be formed by quadruple patterning and diagonal patterning to reduce misalignment between the direct contacts DC. Specifically, the plurality of direct contact holes DCH can be formed at once (e.g., simultaneously) by patterning the target mask layer TM (see Figure 13A) by quadruple patterning and diagonal patterning, thereby reducing misalignment that may occur between the plurality of direct contact holes DCH.

[0092] Figure 14 is a block diagram illustrating a system 1000 including a semiconductor device according to an embodiment.

[0093] Referring to FIG14, system 1000 may include controller 1010, input / output device 1020, memory 1030, interface 1040, and bus 1050. System 1000 may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be, for example, a portable computer, a web tablet, a mobile phone, a digital music player, or a memory card.

[0094] The controller 1010 can control the program running in the system 1000. For example, the controller 1010 may include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0095] Input / output device 1020 can be used by system 1000 to input or output data. System 1000 can use input / output device 1020 to connect to external devices (e.g., personal computers or networks) and exchange data with external devices. Input / output device 1020 may include, for example, a touch screen, a touch pad, a keyboard, or a display.

[0096] Memory 1030 may store data for operation of controller 1010, or may store data processed by controller 1010. According to an embodiment, memory 1030 may include any one of semiconductor devices 100, 100a, 100b and 200.

[0097] Interface 1040 can serve as a data transmission channel between system 1000 and external devices. Controller 1010, input / output device 1020, memory 1030 and interface 1040 can communicate with each other via bus 1050.

[0098] In summary, the various embodiments provide a semiconductor device with improved performance and reliability. Specifically, the embodiments provide a semiconductor device with direct contacts (DCs) that connect bit lines to an active region and have an elongated shape (e.g., an oval shape) extending diagonally relative to the edge of the substrate. The direct contacts are formed to overlap with a sludge region in the center of the active region (e.g., completely covering and extending beyond the sludge region), thereby increasing the contact area between the direct contacts and the sludge region. Furthermore, the direct contacts can be patterned in a single step, thereby reducing misalignment.

[0099] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, such terminology is used in a general and illustrative sense only and should be interpreted in that general and illustrative sense only, and is not intended to be limiting. In some instances, as will be apparent to those skilled in the art at the time of filing of this application, features, characteristics, and / or elements set forth in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements set forth in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

[0100] 100, 100a, 100b, 200: Semiconductor devices 101:Substrate 112: Isolation layer 113: Insulation layer 114: Polycrystalline silicon layer 122: Buffer layer 130: Lower conductive layer 132: Intermediate conductive layer 134: Upper conductive layer 136: Pattern of Insulating Top Cover 142: Inner spacer 144: Gap Fill Pattern 146: Intermediate spacer 148: External spacer 150: Contact plug 152: Metal silicide layer 154: Conductive barrier layer 156: Metal layer 210: Additional pad 1000: System 1010: Controller 1020: Input / Output Device 1030: Memory 1040: Interface 1050: Busbar ACT: Active Zone BC: Concealed Contacts BL: Bitline CL1: First curve CL2: Second curve CL3: Third Curve CL4: Fourth Curve D1: First horizontal direction D2: Second horizontal direction D3: Third horizontal direction D4: Fourth horizontal direction D5: Vertical direction D6: Sixth horizontal direction DC: Direct contact component DCH: Direct Contact Hole EX1: Area I-I', II-II', III-III': line IF1: First insulating film IF2: Second insulating film IF3: Third insulating film IL1: First insulating layer / layer IL2: Second insulating layer IL3: Third insulating layer IL4: Fourth insulating layer IL5: Fifth insulating layer / layer IL6: Sixth Insulation Layer IP: Insulation pattern L1, L2, L3: Width LP: Overlap joint pad ML1: First mask layer ML2: Second masking layer ML3: Third masking layer ML4: Fourth masking layer ML5: Fifth mask layer OP1: First opening OP2: Second opening OP3: Third opening OP4: Fourth opening OP5: Fifth opening PR1: First photoresist layer PR2: Second photoresist layer R1: Recessed space SD1: First impurity region SD2: Second impurity region SP: Spacer Structure T1: First trench TM: Target Masking Layer WL: Character Line θ1: First angle θ2: Second angle

Claims

1. A semiconductor device, comprising: A substrate having at least one active region, said at least one active region being defined by an isolation layer; At least one character line extends in a first horizontal direction inside the substrate, and the at least one character line intersects with the at least one active region; At least one bit line extends in a second horizontal direction orthogonal to the first horizontal direction, the at least one bit line being located at a vertical horizontal height higher than the at least one character line; and at least one direct contact electrically connects the at least one bit line to the at least one active area, the at least one direct contact having a maximum width in a third horizontal direction, the third horizontal direction intersecting each of the first horizontal direction and the second horizontal direction at an acute angle.

2. The semiconductor device of claim 1, wherein the at least one direct contact has an oval shape having a long axis extending in the third horizontal direction.

3. The semiconductor device of claim 1, wherein the at least one direct contact has a long axis extending in the third horizontal direction, and the shape of the at least one direct contact includes a first curve and a second curve recessed relative to the long axis.

4. The semiconductor device as claimed in claim 3, wherein the first curve and the second curve intersect at a cusp on the long axis.

5. The semiconductor device of claim 3, wherein the shape of the at least one direct contact further includes a third curve and a fourth curve recessed relative to the long axis.

6. The semiconductor device as claimed in claim 1, wherein: The third horizontal direction forms a first angle with the first horizontal direction, and the at least one active area extends in a fourth horizontal direction that intersects each of the first horizontal direction and the second horizontal direction at an acute angle, the fourth horizontal direction forming a second angle with the first horizontal direction that is greater than the first angle.

7. The semiconductor device as claimed in claim 1, wherein: The at least one active region includes a first impurity region and a plurality of second impurity regions, the plurality of second impurity regions being separated from each other by the first impurity region, and the at least one direct contact being electrically connected to the first impurity region, the first impurity region having a maximum width in the third horizontal direction.

8. The semiconductor device of claim 1, further comprising an additional pad located on the at least one active region, the additional pad being electrically connected to the at least one active region.

9. The semiconductor device of claim 1, further comprising an additional direct contact that is separated from the at least one direct contact in a diagonal direction intersecting the first horizontal direction and the second horizontal direction at an acute angle.

10. A semiconductor device, comprising: substrate; An isolation layer is located in the substrate; An active region, defined by the isolation layer, each of the active regions including a first impurity region and a plurality of second impurity regions separated from each other by the first impurity region; a character line extending in a first horizontal direction within the substrate, each of the character lines intersecting between the first impurity region and one of the plurality of second impurity regions; a bit line extending in a second horizontal direction orthogonal to the first horizontal direction, the bit line being located at a vertical horizontal height higher than the character line; and direct contacts electrically connecting the bit lines to the first impurity region, each of the direct contacts having a maximum width in a third horizontal direction intersecting each of the first and second horizontal directions at an acute angle, wherein the first impurity region has a maximum width in the third horizontal direction.

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