Non-volatile memory system, and method for grouping and storing data and error correction code data in non-volatile memory system

Abstract

Numerous embodiments of a modified packetization and error correction system for non-volatile memory cells are disclosed. In one embodiment, the system includes a memory array comprising non-volatile memory cells arranged in columns and rows, wherein the non-volatile memory cells of the memory array store a first bit of a first data packet and a second bit of a second data packet, and wherein the first packet is backed up by a first ECC block and the second packet is backed up by a second ECC block.

Description

Technical Field

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 427,406, filed November 22, 2022, entitled "Level Assignment and Error Correction for Multilevel Non-Volatile Memory Cells," and U.S. Patent Application No. 18 / 106,421, filed February 6, 2023, entitled "Grouping and Error Correction for Non-volatile Memory Cells."

[0002] Numerous embodiments of an improved hierarchical allocation and error correction system for multi-level nonvolatile memory cells are disclosed. Prior Technology

[0003] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​(hereinafter referred to as "130 Patent") discloses a discrete-gate non-volatile memory cell array, wherein the memory cells are a type of flash memory cell, and the patent is incorporated herein by reference. This memory cell 110 is shown in FIG1. ​​Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12 having a channel region 18 therebetween. A floating gate 20 is formed above and insulated from a first portion of the channel region 18 and above a portion of the source region 14 (and the floating gate 20 controls the conductivity of the first portion of the channel region 18). A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from a second portion of the channel region 18 (and controls its conductivity), and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by gate oxide. The bit line 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), thus causing electrons on the floating gate 20 to tunnel through the intermediate insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.

[0005] The memory cell 110 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 via source-side injection (SSI) with hot electrons (where the electrons are placed on the floating gate). The electron flow will move from the drain region 16 towards the source region 14. The electrons will accelerate and heat up as they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected onto the floating gate 20 via the gate oxide due to electrostatic attraction from the floating gate 20.

[0006] Memory cell 110 is read by applying a positive read voltage to drain region 16 and word line terminal 22 (thus connecting the portion of channel region 18 below the word line terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also connected, and current flows through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed with electrons), most or all of the portion of channel region below floating gate 20 is disconnected, and current does not flow through (or almost no current flows through) channel region 18, which is sensed as a programmed state or a "0" state.

[0007] Table 1 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and programming operations: Table 1: Operation of Flash Memory Cell 110 in Figure 1 WL BL SL Read 2-3V 0.6-2V 0V erase ~11-13V 0V 0V Programming 1-2V 10.5-3 A 9-10V

[0008] Other discrete-gate memory cell configurations are well known, which are other types of flash memory cells. For example, Figure 2 depicts a four-gate memory cell 210, which includes a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 above a second portion of the channel region 18 (typically coupled to a word line WL), a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference. Here, all gates except the floating gate 20 are non-floating gates, meaning that these gates are electrically connected to or can be electrically connected to a voltage source. Programming is performed by self-injection of heated electrons from the channel region 18 onto the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] Table 2 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 210 to perform read, erase, and programming operations: Table 2: Operation of Flash Memory Cell 210 in Figure 2 WL / SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V erase -0.5V / 0V 0V 0V / -8V 8-12V 0V Programming 1V 0.1-1 A 8-11V 4.5-9V 4.5-5V

[0010] Figure 3 depicts a three-gate memory cell 310, which is another type of flash memory cell. Except that memory cell 310 does not have a separate control gate, memory cell 310 is identical to memory cell 210 in Figure 2. Its erase operation (where erasure is performed via the erase gate) and read operation are similar to those in Figure 2, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and therefore, a higher voltage is applied to the source line during programming operations to compensate for the lack of a control gate bias.

[0011] Table 3 depicts the typical voltage and current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and programming operations: Table 3: Operation of Flash Memory Cell 310 in Figure 3 WL / SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V erase -0.5V / 0V 0V 11.5V 0V Programming 1V 0.2-3 A 4.5V 7-9V

[0012] Figure 4 depicts a stacked gate memory cell 410, which is another type of flash memory cell. Memory cell 410 is similar to memory cell 110 in Figure 1, except that the floating gate 20 extends over the entire channel region 18, and the control gate 22 (coupled to the word line here) extends over the floating gate 20, which is spaced apart by an insulating layer (not shown). Erasing is performed by electrons tunneling from the floating gate (FG) to the substrate via Ful-Nohan tunneling; programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16 using electrons flowing from the source region 14 toward the drain region 16; and a read operation is similar to that of memory cell 210 with a higher control gate voltage.

[0013] Table 4 depicts the typical voltage range that can be applied to the terminals of memory cell 410 and substrate 12 to perform read, erase, and programming operations: Table 4: Operation of Flash Memory Cell 410 (Figure 4) CG BL SL substrate Read 2-5V 0.6-2V 0V 0V erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V Programming 8-12V 3-5V 0V 0V

[0014] The methods and techniques described herein can be applied to other non-volatile memory technologies, such as, but not limited to, FINFET discrete gate flash or stacked gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapping in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapping in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon nanotube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electronic RAM).

[0015] Figure 5 depicts a suitable analogous multilevel cell (MLC) memory storage (e.g., where the interval between levels is 1-2 variations). And it is not as strict as digital MLC memory storage) or vector matrix multiplication neural network applications (e.g., where the interval between layers is 1-2 variability) And it is not as strict as the block diagram of the prior art memory system 500 (which is a digital MLC memory storage).

[0016] The memory system 500 includes an array 501, a column decoder 502, a high-voltage decoder 503, a row decoder 504, a bitline driver 505, an input circuit 506, an output circuit 507, control logic 508, and a bias generator 509. The memory system 500 further includes a high-voltage generation block 510, which includes a charge pump 511, a charge pump regulator 512, and a high-voltage level generator 513. The memory system 500 further includes a (programming / erasing, or weighting) algorithm controller 514, an analog circuit system 515, a control engine 516 (which may contain special functions, such as, but not limited to, arithmetic functions, activation functions, and embedded microcontroller logic), test control logic 517, and an SRAM block 518 to store intermediate data, such as data for input circuits (e.g., activation data) or output circuits (neural output data), or data to be programmed (such as data to be formed in an entire column or added to multiple columns).

[0017] Array 501 includes columns and rows of non-volatile memory cells (such as memory cells 110, 210, 310 or 410 in Figures 1 to 4, respectively).

[0018] Input circuitry 506 may include circuitry such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time-modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 506 may implement one or more of a normalization, linear, or nonlinear scaling function or arithmetic function. Input circuitry 506 may implement a temperature compensation function for the input level. Input circuitry 506 may implement an excitation function, such as a rectified linear excitation function (ReLU) or a sigmoid function. Input circuitry 506 may store digital excitation data to be used as an input signal or combined with such an input signal during programming or read-out operations. The digital excitation data may be stored in a register. Input circuitry 506 may include circuitry for driving array terminals (such as CG, WL, EG, and SL lines) and may include sample-and-hold circuitry and buffers. A DAC can be used to convert digital excitation data into an analog input voltage to be applied to the array.

[0019] Output circuit 507 may include circuitry such as ITV (intermediate-to-voltage converter), ADC (analog-to-digital converter for converting neural analog outputs to digital bits), AAC (analog-to-analog converter, such as an inter-current-to-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time-modulated pulse converter), or any other type of converter. Output circuit 507 can convert array outputs into excitation data. Output circuit 507 may implement excitation functions such as rectified linear excitation functions (ReLU) or sigmoid functions. Output circuit 507 may apply one or more of the following to the neural outputs: statistical normalization, regulation, scaling / incrementing functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shifting, logarithmic). Output circuit 507 may apply temperature compensation functions to the neural outputs or array outputs (such as bitline outputs), such as keeping the IV slope nearly constant with respect to temperature to keep the array power consumption nearly constant with respect to temperature, or improving the accuracy of the array (neural) outputs. Output circuit 507 may include a temporary register for storing output data. Output circuit 507 may include error correction logic to correct errors in the neural output. Error correction may be Hamming code, such as one that can perform single error correction and double error correction (SECDED). Errors may arise from noise, data loss, interference, etc.

[0020] Regarding digital MLC memory storage (e.g., where the hierarchical spacing is typically 12), And it can be 4 to 6 The input circuit 506 does not need to include analog circuitry, such as a D / A converter, scaling, excitation function, or arithmetic circuitry, and the output circuit 507 does not need to include analog circuitry, such as an A / D (analog-to-digital) converter, scaling, excitation function, or arithmetic circuitry. However, the output circuit 507 may require multi-level sense amplifier circuitry that translates the analog output (cell current) from the selected memory cell into digital output bits. For example, the output of a 4-level cell can be represented by 2 digital output bits, while the output of a 16-level cell can be represented by 4 digital output bits.

[0021] The algorithm controller 514 includes an ECC (Error Correction Code) engine 519, which generates ECC data, as described below.

[0022] Referring to Figure 6, in the prior art, data is typically stored in the form of characters (e.g., character 601) in analog multilevel memory cells within array 501 (where each memory cell can store two or more levels, and each level is represented using a range of analog voltages or currents), or stored as digital multilevel memory cells (where each memory cell can store two or more levels, and each level is represented using discrete levels of voltage or current). An array contains a plurality of columns and a plurality of rows. A character may, for example, include 128 bits. For a single-level cell, 128 bits require 128 cells to store information. A column may consist of multiple characters. For example, a column of 4096 cells may include 32 characters, each with 128 bits. To select a 128-bit character, a column is selected, and 128 rows are selected from the 4096 rows.

[0023] Figure 6 depicts a single example character 601, in which it comprises a specific number of non-volatile memory cells in the form of an array 501. Prior art also includes various error detection and error correction schemes that can be implemented by the ECC engine 519.

[0024] When the memory system 500 follows a NOR memory architecture, one applicable error correction scheme is a Hamming code-based error correction scheme, in which, for each bit group (e.g., word 601), a set of error correction data (e.g., ECC 602) is generated and stored along with the bit group. For example, ECC 602 can be generated by performing a Hamming function on word 601. In this way, each bit in word 601 is backed up by ECC 602. During a read operation, the memory system 500 reads word 601 and ECC 602. ECC 602 will indicate whether word 601 contains an error when read, and ECC 602 can be used to correct at most a single bit error (e.g., a "1" that is incorrectly read as "0", or a "0" that is incorrectly read as "1"). ECC 602 has limitations. Specifically, in this example, ECC 602 can only be used to correct single-bit errors. If two or more bit errors occur, ECC 602 will not be able to correct those errors.

[0025] In the case of the memory system 500 being used for neural network vector matrix multiplication, error correction can be performed on the digital output bits from the output circuit 507 (e.g., from the ADC output). In this case, multiple characters in multiple columns can be selected instead of a single character. Furthermore, in this case, multiple cells in multiple columns and single rows can be selected instead of a single cell in a single column and single row.

[0026] Refer to Table 5 for examples of single-bit errors and multi-bit errors: Table 5: Multilevel Cell Allocation Cellular current DIN0 DIN1 1 A 0 0 2 A 0 1 3 A 1 0 4 A 1 1

[0027] In the example in Table 5, each cell can store two bits of data, DIN0 and DIN1, meaning it can store data for four analog levels. A value of 00 corresponds to 1. The reading current of A, with a value of 01 corresponding to 2. The reading current of A, a value of 10 corresponds to 3. The reading current of A, and the value of 11 corresponding to 4. The reading current of A. If a cell intends to store a value of 00, but the sensed current is incorrectly detected as 2... A, not 1 A (single-level error) means the data will be interpreted as 01 instead of 00, indicating a unit cell error. In the absence of other errors, ECC 601 can be used to correct 01 to 00. However, if a cell intends to store a 00 value, but the sensed current is incorrectly detected as 4... A, not 1 A (multi-level error, e.g., >2 levels) means the data is interpreted as 11 instead of 00, containing a two-bit error. ECC 601 will not be able to correct this data.

[0028] For multi-level memory cells, an improved error correction scheme is needed that can correct errors in more than one unit cell or errors at two or more levels. Summary of the Invention

[0029] Numerous specific examples of an improved hierarchical allocation and error correction system for multi-level nonvolatile memory cells are revealed. Simple Explanation of the Diagram

[0030] Figure 1 depicts a discrete gate flash memory cell of the prior art.

[0031] Figure 2 depicts another prior art discrete gate flash memory cell.

[0032] Figure 3 depicts another prior art discrete gate flash memory cell.

[0033] Figure 4 depicts another prior art discrete gate flash memory cell.

[0034] Figure 5 depicts a memory system of the prior art.

[0035] Figure 6 depicts the data characters and related ECC data of the prior art.

[0036] Figures 7A, 7B and 7C depict the improved error correction system.

[0037] Figure 8 depicts the ECC engine used to implement the improved error correction system.

[0038] Figure 9 depicts an embodiment using the ECC engine of Figure 8. Implementation

[0039] Figures 7A, 7B, and 7C depict an improved error correction scheme for multi-level non-volatile memory cells.

[0040] In Figures 7A and 7B, the data to be stored in array 501 is divided into sub-characters, such as half-characters, rather than whole characters, and two ECC blocks are generated and stored instead of one ECC block. This embodiment depicts half-character 701, half-character 702, ECC block 703 associated with half-character 701, and ECC block 704 associated with half-character 702.

[0041] Figure 7C illustrates the cell hierarchy allocation details of the systems in Figures 7A and 7B. Here, a character comprises n cells, referred to as cells n to cell 0. As an example, a cell of an entity can store 2 bits. One bit of one half-character in cell n is backed up by ECC code in ECC block 703, and one bit of the other half-character in cell n is backed up by ECC code in ECC block 704. A cell of an entity contains one bit for half-character 701 and another bit for half-character 702. For example, cell n contains dn half-characters 701 and dn half-characters 702. If a cell intends to store a value of 00, but the sensed current is incorrectly detected as 4 µA instead of 1 µA, the data will be interpreted as 11 instead of 00, resulting in a two-bit error. ECC block 703 is used to correct errors in the first bit, while ECC block 704 is used to correct errors in the second bit. The final result is that the error value 11 will be corrected to the expected value 00. This is a substantial improvement over the previous technology.

[0042] For a two-bit cell embodiment (where a cell can store four levels), the physical cell storing ECC bits can be combined in the same way with a physical cell storing one bit for ECC block 703 and another bit for ECC block 704.

[0043] The embodiments in Figures 7A to 7C describe multi-level cells that can store two bits representing four different levels. Those skilled in the art will understand that the same principle can be applied to multi-level cells that store more than two bits using additional ECC blocks.

[0044] Alternatively, characters can be divided into two or more subcharacters, for example, four subcharacters with ECC applied to each subcharacter. The cell of an entity will contain bits of all subcharacters.

[0045] Alternatively, multiple characters can be combined into a supercharacter, which is a structure containing two or more characters with ECC implemented on each character. The cell of an entity will contain bits for two or more characters.

[0046] These concepts are illustrated in Figure 8. In Figure 8, this system stores data represented by data blocks 801. Data blocks 801 are collections of bits and can be characters, supercharacters, subcharacters, or any other group of data. Data blocks 801 are provided to ECC engine 800 (an embodiment of ECC engine 519 implementing the ECC algorithm described herein), and ECC engine 800 divides data blocks 801 into data blocks 802-n, ..., 802-1. For example, if n=2, two data blocks 802-2 and 802-1 are generated. If n=3, three data blocks 802-3, 803-3, and 803-1 are generated. If n=4, four data blocks 802-4, 803-3, 803-2, and 803-1 are generated. In one embodiment, n is also equal to the number of bits stored in each memory cell. The ECC engine 800 also generates ECC blocks 803-n, ..., 803-1, wherein each bit stored in a memory cell is backed up by one of the ECC blocks 803-n, ..., 803-1, so that the entire system of each memory cell is backed up collectively by the ECC blocks 803-n, ..., 803-1, and each ECC block in these ECC blocks backs up one bit of each memory cell.

[0047] For example, if data group 801 is a character and n=4, then four quarter-character groups (which are sub-character groups) will be generated: data group 802-4 (first quarter-character or first sub-character), 802-3 (second quarter-character or second sub-character), 802-2 (third quarter-character or third sub-character), and 802-1 (fourth quarter-character or fourth sub-character). Moreover, the memory cell stores bits from the respective data groups 802-4, 802-3, 802-2, and 802-1. The ECC engine 800 will also generate ECC blocks 803-4, 803-3, 803-2, and 803-1. Each bit stored in a memory cell is backed up by one of the ECC blocks 803-4, 803-3, 803-2, and 803-1, so that the entire memory cell is backed up collectively by the ECC blocks 803-4, 803-3, 803-2, and 803-1. Each ECC block in these ECC blocks backs up one bit of each memory cell.

[0048] Figure 9 illustrates this embodiment, wherein memory cell 901 stores bits from data packet 802-4 (symbol symbol d(802-4)), data packet 802-3 (symbol symbol d(802-3)), data packet 802-2 (symbol symbol d(802-2)), and data packet 802-1 (symbol symbol d(802-1)), backed up by ECC blocks 803-4, 803-3, 803-2, and 803-1, respectively. Based on this scheme, up to four bit errors in cell 901 (i.e., the first error, the second error, the third error, and the fourth error) can be corrected by ECC blocks 803-4, 803-3, 803-2, and 803-1.

[0049] It should be noted that, as used herein, the terms "above" and "on" inclusively include "directly on" (without intermediate materials, components, or spaces) and "indirectly on" (with intermediate materials, components, or spaces). Similarly, the term "adjacent" includes "directly adjacent" (without intermediate materials, components, or spaces) and "indirectly adjacent" (with intermediate materials, components, or spaces), "installed to" includes "directly installed to" (without intermediate materials, components, or spaces) and "indirectly installed to" (with intermediate materials, components, or spaces), and "electrically coupled" includes "directly electrically coupled to" (without intermediate materials or components electrically connecting the components together) and "indirectly electrically coupled to" (with intermediate materials or components electrically connecting the components together). For example, forming an element "above a substrate" can include forming an element directly on the substrate without any intermediate material / element, and forming an element indirectly on the substrate with one or more intermediate materials / elements.

[0050] 12: Semiconductor substrate 14: Source Region 16: Dublin Region 18: Passage Area 20: Floating gate 22: Word line terminal 24: Bitline 28: Control gate 30: Remove gate 110, 210, 310, 410: Memory cells 500: Memory System 501: Array 502: Column Decoder 503: High Voltage Decoder 504: Row decoder 505: Bit line driver 506: Input circuit 507: Output circuit 508: Control logic 509: Bias generator 510: High voltage generation block 511: Charge pump 512: Charge pump regulator 513: High voltage level generator 514: Algorithm controller 515: Analog circuitry 516: Control engine 517: Test control logic 518: SRAM block 519: ECC engine 601: Character 602: ECC 701,702: Half character 703,704: ECC block 800: ECC engine 801,802-1,802-2,802-3,802-4,802-n: Data packet <(...)>803-1,803-2,803-3,803-4,803-n: ECC block 901: Cell cell 0: Cell 0 cell 1: Cell 1 cell n-1: Cell n-1 cell n: Cell n d(802-1): Bit from data packet 802-1 d(802-2): Bit from data packet 802-2 d(802-3): Bit from data packet 802-3 d(802-4): Bit from data packet 802-4 * BL: Bit line CG: Control gate ECC: Error correction code EG: Erase gate FG: Floating gate SL: Source line *(注:原文中 、 、 、 后的内容似乎不完整,我按照已有内容进行了翻译。如果这是完整内容,请告知我,我会进一步完善翻译。)WL, SG: letter lines

Claims

1. A memory system, comprising: A memory array includes non-volatile memory cells arranged in multiple columns and rows, wherein a first non-volatile memory cell of the memory array stores a first bit and a second bit, the first bit being selected from a first data packet and the second bit being selected from a second data packet, wherein the first bit is backed up by a first ECC block and the second bit is backed up by a second ECC block, and wherein a second non-volatile memory cell of the memory array stores a portion of the first ECC block and a portion of the second ECC block.

2. As in the system of request item 1, wherein, The first data group is a first half-character, and the second data group is a second half-character, and the first half-character and the second half-character together form a character.

3. As in request item 1, where, The first data group is a first character, and the second data group is a second character, and the first character and the second character form a super character.

4. As in request item 1, where, The first ECC block can correct a first unit error in one of the non-volatile memory cells, and the second ECC block can correct a second unit error in one of the non-volatile memory cells.

5. As in request item 1, where, Each non-volatile memory cell in the memory array further stores a third bit of a third data packet backed up by a third ECC block, and a fourth bit of a fourth data packet backed up by a fourth ECC block.

6. The system as described in request item 5, wherein, The first group is a first quarter character, the second group is a second quarter character, the third group is a third quarter character, and the fourth group is a fourth quarter character, and the first quarter character, the second quarter character, the third quarter character, and the fourth quarter character form a single character.

7. As in request item 1, where, This non-volatile memory cell is a digital multilevel memory cell.

8. As in request item 1, where, This non-volatile memory cell is an analog multilevel memory cell.

9. The system as described in request item 1, wherein, This memory array is a vector-matrix multiplication array in a neural network.

10. As in request item 1 of the system, where, This non-volatile memory cell is a discrete gate flash memory cell.

11. The system as described in request item 1, wherein, The non-volatile memory cell is a stacked gate flash memory cell.

12. A method for grouping and storing data and error correction code (ECC) data in a memory system, comprising: Select a bit from a first data group; select a bit from a second data group; store the bit from the first data group in a first non-volatile memory cell in an array; store the bit from the second data group in the first non-volatile memory cell; store the ECC data of the bit from the first data group in a first ECC block in the array, wherein a portion of the first ECC block is stored in a second non-volatile memory cell; and store the ECC data of the bit from the second data group in a second ECC block in the array, wherein a portion of the second ECC block is stored in the second non-volatile memory cell.

13. As in request item 12, wherein, The first data group is a first half-character, and the second data group is a second half-character, and the first half-character and the second half-character together form a character.

14. As in request item 12, wherein, The first data group is a first character, and the second data group is a second character, and the first character and the second character form a super character.

15. As in request item 12, wherein, The first ECC block can correct a first unit error in one of the non-volatile memory cells, and the second ECC block can correct a second unit error in one of the non-volatile memory cells.

16. The method as described in request item 12, including: One bit from a third data packet is stored in the non-volatile memory cell; one bit from a fourth data packet is stored in the non-volatile memory cell; the ECC data of that bit from the third data packet is stored in a third ECC block in the array; and the ECC data of that bit from the fourth data packet is stored in a fourth ECC block in the array.

17. As in request item 16, wherein, The first data group is a first quarter character, the second data group is a second quarter character, the third data group is a third quarter character, and the fourth data group is a fourth quarter character, and the first quarter character, the second quarter character, the third quarter character, and the fourth quarter character form a single character.

18. As in request item 12, wherein, This non-volatile memory cell is a digital multilevel memory cell.

19. As in request item 12, wherein, This non-volatile memory cell is an analog multilevel memory cell.

20. As in request item 12, wherein, This array is a vector-matrix multiplication array in a neural network.

21. As in request item 12, wherein, This non-volatile memory cell is a discrete gate flash memory cell.

22. As in request item 12, wherein, The non-volatile memory cell is a stacked gate flash memory cell.

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