Image sensor with stack structure and manufacturing method thereof

Abstract

The present invention provides an image sensor comprising: a first semiconductor chip including a pixel region and a peripheral region, the pixel region including a plurality of pixels; and a second semiconductor chip coupled to a lower surface of the first semiconductor chip, the second semiconductor chip including a plurality of logic elements, the pixel region including a plurality of color filters and a fence in the pixel region, the plurality of color filters corresponding to the plurality of pixels, the fence having a grid pattern, and each of the plurality of color filters being separated from each other by the fence, the peripheral region including a shielding region and an outer shielding region, the shielding region surrounding the pixel region; and a fence insulating layer included in the outer shielding region, the fence insulating layer comprising the same material as the fence.

Description

Technical Field

[0001] [Cross-reference to related applications]

[0002] This U.S. non-provisional application claims priority to Korean Patent Application No. 10-2023-0011106, filed with the Korean Intellectual Property Office on January 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Prior Technology

[0003] Various examples and embodiments of the present invention relate to an image sensor, and more particularly to an image sensor having a stacked structure in which semiconductor wafers are coupled to each other, a system including an image sensor, a method of operating an image sensor, and / or a method of manufacturing an image sensor, etc.

[0004] Generally, an image sensor may include pixel regions and logic regions. Multiple pixels can be configured in a 2D array structure within the pixel regions, and each pixel may include a photodiode and multiple pixel transistors. Pixel transistors may include, for example, transfer transistors, reset transistors, source follower transistors, and select transistors. Logic elements for processing pixel signals from the pixel regions can be configured in the logic regions. Recently, image sensors with stacked structures have been developed. This stacked structure is formed by forming pixel regions and logic regions in separate semiconductor wafers and then stacking the two semiconductor wafers. Image sensors with stacked structures can provide high-quality and reliable image sensors by progressively increasing and / or maximizing the number of pixels in the pixel regions and improving and / or optimizing the performance of logic elements in the logic regions. Summary of the Invention

[0005] Various examples and embodiments of the present invention provide an image sensor with a stacked structure having improved blemish defects, a system including an image sensor, a method of operating an image sensor, and / or a method of manufacturing an image sensor, etc.

[0006] The objectives of the exemplary embodiments of the present invention are not limited to the foregoing objectives, and other objectives not described herein will be clearly understood by those skilled in the art from the following description.

[0007] According to at least one embodiment of the present invention, an image sensor with a stacked structure is provided. The image sensor includes: a first semiconductor wafer including a pixel region and a peripheral region, the pixel region including a plurality of pixels; and a second semiconductor wafer coupled to a lower surface of the first semiconductor wafer, the second semiconductor wafer including a plurality of logic elements, the pixel region including a plurality of color filters and a fence in the pixel region, the plurality of color filters corresponding to the plurality of pixels, the fence having a grid pattern, and each of the plurality of color filters being separated from each other by the fence, the peripheral region including a shielding region and an outer shielding region, the shielding region surrounding the pixel region; and a fence insulating layer included in the outer shielding region, the fence insulating layer comprising the same material as the fence.

[0008] According to at least one embodiment of the present invention, an image sensor with a stacked structure is provided. The image sensor includes: a first semiconductor wafer including a substrate and at least one wiring layer, the substrate including a pixel region, a peripheral region and a back insulating layer, the at least one wiring layer being located on a lower surface of the substrate, the pixel region including a plurality of pixels, and the back insulating layer being located on an upper surface of the substrate; a second semiconductor wafer coupled to the lower surface of the first semiconductor wafer, the second semiconductor wafer including a plurality of logic elements, the back insulating layer including a gate, a plurality of color filters and a TiO2 layer, the gate and the plurality of color filters being located in the pixel region, the gate including a single insulating layer having a grid pattern, and each of the plurality of color filters being separated from each other by the gate; and a gate insulating layer located on at least one via array region of an I / O pad region and a peripheral region, the gate insulating layer comprising the same material as the gate.

[0009] According to at least one embodiment of the present invention, an image sensor with a stacked structure is provided. The image sensor includes: a first semiconductor wafer including a substrate and a wiring layer, the substrate including a pixel region, a peripheral region and a back insulating layer, the wiring layer being located on a lower surface of the substrate, the pixel region including a plurality of pixels, and the back insulating layer being located on an upper surface of the substrate; and a second semiconductor wafer coupled to the lower surface of the first semiconductor wafer, the second semiconductor wafer including a plurality of logic elements, the back insulating layer including a fence in the pixel region and a plurality of color filters, the fence having a grid pattern and the plurality of color filters being separated from each other by the fence, the peripheral region including a shielding region and an outer shielding region, the shielding region surrounding the pixel region; and a fence insulating layer located in the outer shielding region, the fence insulating layer comprising the same material as the fence.

[0010] According to at least one example embodiment of the present invention, a method for manufacturing an image sensor having a stacked structure is provided. The method includes: forming a plurality of pixels in a first substrate of a first semiconductor wafer, each of the plurality of pixels including a photodiode; forming a first wiring layer on an active surface of the first substrate; forming a plurality of logic elements in a second substrate of a second semiconductor wafer; forming a second wiring layer on the active surface of the second substrate; coupling the first semiconductor wafer and the second semiconductor wafer to each other such that the first wiring layer faces the second wiring layer; thinning the first substrate, the thinning including removing a portion of a non-active surface of the first substrate; forming a back-side insulating layer on the non-active surface of the first substrate; forming a plurality of vias in at least one via array region of the first substrate; forming a plurality of color filters on the back-side insulating layer in a pixel region of the first substrate, the plurality of color filters corresponding to the plurality of pixels; forming a plurality of microlenses on the plurality of color filters; wherein forming the color filters includes: forming a fence material layer on the back-side insulating layer; forming a fence having a grid pattern in the pixel region; forming a fence insulating layer in an outer shielding region, the outer shielding region being located outside the shielding region of the first substrate; and forming a plurality of color filters inside the fence. Simple Explanation of the Diagram

[0011] The various exemplary embodiments will be more clearly understood from the following detailed description accompanying the accompanying drawings: Figure 1 is a perspective view of an image sensor with a stacked structure according to at least one example embodiment, and illustrates an exploded perspective view in which the first semiconductor wafer and the semiconductor wafer are separated from each other. Figure 2 is a plan view of the image sensor of the stacked structure of Figure 1 according to some example embodiments. Figure 3A is a cross-sectional view taken along line I-I' of Figure 2, and Figure 3B is a cross-sectional view of an image sensor according to at least one example embodiment. Figures 4A to 4C are enlarged cross-sectional views of the back insulating layer of Figure 3A according to some example embodiments. Figures 5A to 7B are plan views and corresponding cross-sections of the node separation portion of the structure of the back insulating layer of Figure 4C, which is applied according to some example embodiments. Figures 8A and 8B are cross-sectional views of an image sensor with a stacked structure according to some example embodiments and correspond to Figure 2. Figures 9A to 9G are schematic cross-sectional views illustrating a process for manufacturing the image sensor of Figure 1 with a stacked structure according to some example embodiments. Figures 10A to 10C are cross-sectional views illustrating in more detail the process of forming a fence and a fence insulating layer in relation to the color filter formed in Figure 9F, according to some exemplary embodiments. Implementation

[0012] In the following description, various exemplary embodiments are illustrated with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and redundant descriptions thereof are omitted.

[0013] Figure 1 is a perspective view of an image sensor with a stacked structure according to at least one example embodiment, and illustrates an exploded perspective view in which the first semiconductor wafer and the semiconductor wafer are separated from each other; however, the example embodiment is not limited thereto.

[0014] Referring to FIG1, an image sensor 1000 (hereinafter referred to as "image sensor") with a stacked structure according to at least one exemplary embodiment may include a first semiconductor wafer 100 and a second semiconductor wafer 200. The image sensor 1000 according to at least one exemplary embodiment may have a structure in which the first semiconductor wafer 100 is stacked on the second semiconductor wafer 200, but the exemplary embodiment is not limited thereto, and for example, the image sensor 1000 may include more than two semiconductor wafers and / or additional stacked structures, etc. The image sensor 1000 according to at least one exemplary embodiment may include, for example, a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), but is not limited thereto.

[0015] The first semiconductor chip 100 may include a pixel region PA and / or a first peripheral region PE1, but is not limited thereto. The pixel region PA is located in the central region of the first semiconductor chip 100, and the pixel region PA may include a plurality of pixels disposed in a 2D array structure. The pixel region PA may include an active pixel sensor region APS located at the center of the pixel region PA and / or an optical black pixel region OB surrounding the active pixel sensor region APS, but is not limited thereto. Pixels are also disposed in the optical black pixel region OB, but may be dummy pixels that do not perform electrical operation. In addition, the first metal layer 140 (see FIG. 3A) may be located in the upper portion of the optical black pixel region OB in order to reduce, block and / or shield light reaching the optical black pixel region OB.

[0016] The first peripheral region PE1 may include a shielding region SHA, an I / O pad region I / O PAD, and / or a chip edge region C / E, etc., but the examples are not limited thereto. The shielding region SHA may be located outside the optical black pixel region OB. The second metal layer 160 (see FIG. 3A) and / or the barrier insulating layer 125a (see FIG. 3B) may be located in at least a portion of the shielding region SHA to reduce, block, and / or shield light, etc. In addition, the first through-hole array region TVA1 and / or the second through-hole array region TVA2 may be located in a portion of the shielding region SHA. A plurality of through holes 150 (see FIG. 3A) may be configured in the first through-hole array region TVA1 and the second through-hole array region TVA2, etc., but the examples are not limited thereto.

[0017] The first perforated array region TVA1 may extend in the x-direction (e.g., a first direction relative to the surface of the image sensor 1000) as illustrated in FIG1 and be located on the bottom side in the y-direction (e.g., a second surface relative to the surface of the image sensor 1000), and the second perforated array region TVA2 may extend in the y-direction and be located on the right side in the x-direction. However, the shape and position of the first perforated array region TVA1 and the second perforated array region TVA2 are not limited to the shape and position described above. Furthermore, in the image sensor 1000 according to at least one exemplary embodiment, the number of perforated array regions is not limited to two, three, or four, etc., and the perforated array regions may be configured. In addition, according to at least one exemplary embodiment, the first perforated array region TVA1 and the second perforated array region TVA2 may be considered as regions separated from the masking region SHA.

[0018] Additionally, the plurality of vias 150 can be connected to pixels in the active pixel sensor region APS via a plurality of first lines 182 (see FIG. 3A) of the first wiring layer 180 (see FIG. 3A) of the first semiconductor wafer 100, but the example embodiment is not limited thereto. Furthermore, the plurality of vias 150 can connect the first lines 182 of the first wiring layer 180 of the first semiconductor wafer 100 to a plurality of second lines 212 (see FIG. 3A) of the second wiring layer 210 of the second semiconductor wafer 200, but the example embodiment is not limited thereto. The second lines 212 of the second wiring layer 210 of the second semiconductor wafer 200 can be connected to one or more logic elements in the logic region LA, etc. For example, the vias 150 in the first via array region TVA1 can be connected to the correlated double sampling (CDS) circuit of the logic region LA, and the vias 150 in the second via array region TVA2 can be connected to the column driver circuit of the logic region LA, but the example embodiment is not limited thereto. The detailed structure of the perforation 150 according to some exemplary embodiments will be described in more detail in the descriptions of Figures 3A and 3B.

[0019] The wafer edge region C / E may surround the shielding region SHA and occupy the outermost portion of the first semiconductor wafer 100. According to at least one exemplary embodiment, a portion of the scribe lane (S / L) may remain adjacent to the wafer edge region C / E. For illustrative purposes, in image sensors according to the related art, a metal layer is present in the wafer edge region C / E. However, in the image sensor 1000 according to at least one exemplary embodiment, a metal layer may not be present in the wafer edge region C / E, etc.

[0020] Figure 2 is a plan view of the image sensor 1000 with a stacked structure of Figure 1. Figure 3A is a cross-sectional view taken along line I-I' of Figure 2, and Figure 3B is a cross-sectional view of an image sensor according to at least one exemplary embodiment and corresponds to Figure 3A; however, the exemplary embodiments are not limited thereto. The following description will be given with reference to Figure 1, and the description already given with reference to Figure 1 will be given concisely or omitted.

[0021] Referring to Figures 2 and 3A, when the image sensor 1000 according to at least one exemplary embodiment is considered a vertical structure in the z-direction (e.g., a third direction relative to the surface of the image sensor 1000), the first substrate 101 may be positioned in the upper portion of the first semiconductor wafer 100, and the first wiring layer 180 may be positioned in the lower portion of the first semiconductor wafer 100, but is not limited thereto. The first substrate 101 may contain silicon (Si). However, the material of the first substrate 101 is not limited to Si. For example, the first substrate 101 may contain a single-element semiconductor, such as germanium (Ge), or a composite semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). A plurality of pixels may be formed in pixel regions PA, etc., of the first substrate 101. Each pixel disposed in the first substrate 101 may contain a photodiode PD and may be separated from each other by at least one deep trench isolation (DTI) 105, but is not limited thereto.

[0022] The first wiring layer 180 may be located below the first substrate 101 and includes a plurality of first lines 182 and a first interlayer insulating layer 184, but is not limited thereto. The first lines 182 in other layers (e.g., a second layer, etc.) may be connected to each other via vertical direct contacts, but is not limited thereto. Although FIG. 3A shows first lines 182 in two layers, the number of layers with first lines 182 is not limited to two. Furthermore, although it has been shown that the first lines 182 are only located in the first peripheral region PE1 in FIG. 3A, the first lines 182 may also be disposed in the pixel region PA, and / or the first lines 182 in the first peripheral region PE1 may be connected to the first lines 182 in the pixel region PA, etc. The first lines 182 in the pixel region PA may be connected to pixel transistors respectively.

[0023] The back-side insulating layer 110 may be located on the back side of the first substrate 101. The back-side insulating layer 110 may comprise at least two material layers, etc. For example, the back-side insulating layer 110 may comprise four material layers, and the uppermost layer may serve as an etch stop layer for the metal layer and / or the gate film, but is not limited thereto. Furthermore, the structure of the back-side insulating layer 110 may vary depending on the structure of the gate 120 and / or the structure of the gate insulating layer 125 on the back-side insulating layer 110, etc. The detailed structure of the back-side insulating layer 110 according to some exemplary embodiments will be described in more detail in the description of Figures 4A to 4C.

[0024] Multiple color filters 130 and / or multiple microlenses may be disposed on the back insulating layer 110 in the active pixel sensor region (APS), but the exemplary embodiment is not limited thereto. In the active pixel sensor region (APS) of FIG3A, microlenses are omitted, and only color filters 130 and fences 120 separating the color filters 130 from each other are shown; however, the exemplary embodiment is not limited thereto. The fences 120 may be connected to each other in a two-dimensional grid pattern, but are not limited thereto. The fences 120 may contain, for example, tetraethyl orthosilicate (TEOS). TEOS may be formed using a plasma process at temperatures below 400°C, but is not limited thereto. TEOS formed via the plasma process described above is called plasma-enhanced tetraethyl orthosilicate (PE-TEOS) or plasma tetraethyl orthosilicate (PTEOS).

[0025] For reference purposes, a structure and / or image sensor in which the color filter 130 and / or microlens are disposed on the opposite side of the first wiring layer 180 of the first substrate 101 in which pixels are formed is referred to as a back-side illumination (BSI) structure or a BSI image sensor. On the other hand, a structure and / or image sensor in which the color filter and / or microlens are disposed on the same side of the first wiring layer 180 of the first substrate 101, i.e., a structure and / or image sensor in which the color filter and / or microlens are disposed on the first wiring layer 180, is referred to as a front-side illumination (FSI) structure or an FSI image sensor. In the image sensor 1000 according to at least one exemplary embodiment, the first semiconductor wafer 100 may have a BSI structure, but is not limited thereto. Therefore, the image sensor 1000 according to at least one exemplary embodiment may include a BSI image sensor, etc.

[0026] Patterns and / or components may be configured on the back insulating layer 110 in the optical black pixel region OB and the first peripheral region PE1, depending on the respective region. More specifically, the first metal layer 140 may be located on the back insulating layer 110 in the optical black pixel region OB, but is not limited thereto. The first spacer 142 may be located on at least one side surface of the first metal layer 140, but is not limited thereto. According to at least one exemplary embodiment, the first spacer 142 may be omitted.

[0027] A via 150 passing through the back insulating layer 110 and the first substrate 101 may be disposed in the first via array region TVA1. The via 150 passes through the first substrate 101 of Si and may therefore correspond to, but is not limited to, through-silicon vias (TSVs). Each of the vias 150 may include an outer conductive layer 152 and a via metal layer 154, etc. The outer conductive layer 152 may include at least one metal layer. For example, the outer conductive layer 152 may include titanium (Ti) / titanium nitride (TiN) and / or tungsten (W), etc., and / or the via metal layer 154 may include aluminum (Al), etc. However, the materials of the outer conductive layer 152 and the via metal layer 154 are not limited to the materials described above.

[0028] The via 150 can be connected to the first line 182 of the first wiring layer 180 and also to the second line 212 of the second wiring layer 210 of the second semiconductor wafer 200, but the embodiments are not limited thereto. That is, the via 150 can connect the first line 182 and the second line 212 to each other, and so on.

[0029] The second metal layer 160 may be located on the back insulating layer 110 in the shielded region SHA. The second spacer 162 may be located on at least one side surface of the second metal layer 160. According to at least one exemplary embodiment, the second spacer 162 may be omitted. As described above, the first perforated array region TVA1 and the second perforated array region TVA2 may be configured in the shielded region SHA. According to at least one exemplary embodiment, the first perforated array region TVA1 and the second perforated array region TVA2 may be considered as part of the shielded region SHA. However, in the image sensor 1000 according to at least one exemplary embodiment, these regions are distinct from each other and are shown as separate regions for ease of description and clarity.

[0030] A via 150 and at least one pad 170 may be disposed in an I / O pad region I / O PAD. The via 150 in the I / O pad region I / O PAD may be the same as and / or substantially the same as the via 150 in the first via array region TVA1, but is not limited thereto. Therefore, the via 150 may be connected to a first line 182 of the first wiring layer 180 and may also be connected to a second line 212 of the second wiring layer 210 of the second semiconductor wafer 200, etc. Furthermore, in the I / O pad region I / O PAD, the via 150 may be connected to the pad 170 via an outer conductive layer 152. That is, in the I / O pad region I / O PAD, the via 150 may connect the pad 170 to the first line 182 and / or the second line 212, but is not limited thereto.

[0031] Simultaneously, according to at least one example embodiment, at least one dummy pad region may be located between the I / O pad region (I / O PAD) and the shielding region (SHA). At least one dummy pad may be located within the dummy pad region. However, the dummy pad may not be electrically operable (e.g., the dummy pad may not be operable and / or the dummy pad may not be electrically connected to a power supply and / or ground, etc.). No other components may be configured in the wafer edge region (C / E). Furthermore, although not shown, the S / L may remain adjacent to the wafer edge region (C / E).

[0032] As shown in Figure 3A, the I / O pad region (I / O PAD) and / or the wafer edge region (C / E) may be covered by the gate insulating layer 125, but the example embodiments are not limited thereto. Specifically, in the I / O pad region (I / O PAD), the gate insulating layer 125 may cover the area above the via 150, the extension of the outer conductive layer 152, and / or the exposed back insulating layer 110, etc.

[0033] In the wafer edge region C / E, the barrier insulating layer 125 may cover the back insulating layer 110. In other words, in the image sensor 1000 according to at least one example embodiment, the wafer edge region C / E does not have a separated metal layer, and therefore, the barrier insulating layer 125 may directly cover the back insulating layer 110. Furthermore, when the S / L remains adjacent to the wafer edge region C / E, the barrier insulating layer 125 may cover the back insulating layer 110 on the S / L.

[0034] The barrier insulating layer 125 may contain the same and / or substantially the same material as the barrier 120 of the active pixel sensor region (APS). For example, the barrier insulating layer 125 may contain TEOS or PTEOS, but is not limited thereto. Additionally, the barrier insulating layer 125 may have the same and / or substantially the same thickness as the barrier 120 (e.g., within + / - 10%), but is not limited thereto. For example, each of the barrier insulating layer 125 and the barrier 120 may have a thickness of approximately 3400 angstroms. However, the thickness of the barrier insulating layer 125 and the barrier 120 is not limited to the values ​​described above. According to at least one exemplary embodiment, the barrier insulating layer 125 and the barrier 120 are jointly formed by patterning the same material layer and therefore have the same thickness. The method of forming the barrier insulating layer 125 and the barrier 120 will be described in more detail below in the description of Figures 10A to 10C.

[0035] In the image sensor 1000 according to at least one example embodiment, the barrier insulating layer 125 is maintained on the back insulating layer 110 in the area outside the shielded region SHA (e.g., the area of ​​the I / O pad region I / O PAD and the wafer edge region C / E), and thus, blemish defects can be significantly improved (e.g., blemish defects can be significantly reduced). If a portion of the S / L remains adjacent to the wafer edge region C / E, the barrier insulating layer 125 can also be maintained on the back insulating layer 110 of the S / L. Generally, each of the color filters 130 on the back side of the BSI image sensor can be formed via a spin coating process, but is not limited thereto. However, during the spin coating process for the color filter 130, when there is a large and / or relatively large difference in height between the patterns on the back side of the BSI image sensor (e.g., a difference in length in the z-direction), the spin coating solution used in the spin coating process leaks and / or covers other parts of the image sensor, thereby causing blemish defects in the image captured by the image sensor 1000. However, in the image sensor 1000 according to at least one exemplary embodiment, the barrier insulating layer 125 is maintained on the outside of the shielded area SHA, and therefore, the height difference between the patterns on the back side of the image sensor 1000 can be reduced and / or minimized. Therefore, blemish defects can be significantly improved (e.g., the occurrence of blemish defects can be significantly reduced). In addition, the barrier insulating layer 125 can replace the metal layer on the outside of the shielded area SHA, and therefore, the density of the metal layer can be reduced to reduce wafer and / or wafer bending, etc.

[0036] Additionally, each of the fence 120 and the fence insulating layer 125 may include a lower conductive layer 122 (see FIG. 4A) and / or an upper insulating layer 124 (see FIG. 4A), but is not limited thereto. However, in some exemplary embodiments, the fence 120a (see FIG. 4B) and the fence insulating layer 125 may include a single insulating layer instead of a conductive layer. The structure of the back insulating layer may vary depending on whether the fence and the fence insulating layer include a lower conductive layer. This variation will be described in more detail in the descriptions of FIG. 4A to FIG. 4C.

[0037] As shown in Figure 1, the second semiconductor wafer 200 may include a logic region LA and / or a second peripheral region PE2, etc. The logic region LA is located in the central area of ​​the second semiconductor wafer 200, and multiple logic elements may be configured in the logic region LA. The logic elements may include various elements and / or components for processing pixel signals output by the pixels of the first semiconductor wafer 100. For example, the logic elements may include analog signal processing elements, analog-to-digital converters (ADCs), image signal processing elements, control elements, and the like. However, the elements included in the logic region LA are not limited to these. For example, elements (such as resistors, capacitors, etc.) for supplying power and / or grounding to pixels and / or passive elements may be configured in the logic region LA, but the exemplary embodiments are not limited to this.

[0038] The second peripheral region PE2 has a structure that surrounds the logic region LA and may be located outside the logic region LA. For example, the second peripheral region PE2 has a shape that surrounds four side surfaces of the logic region LA and is located outside the logic region LA. However, according to at least one example embodiment, the second peripheral region PE2 may be located outside only some sides (e.g., at least one side) of the logic region LA. Furthermore, although not specifically shown, one or more through-hole array regions may also be configured in the second peripheral region PE2, corresponding to the first through-hole array region TVA1 and the second through-hole array region TVA2 of the first semiconductor wafer 100, but the example embodiment is not limited thereto.

[0039] As shown in Figure 3A, when considered as a vertical structure in the z-direction, the second substrate 201 (see Figure 9B) can be positioned in the lower portion of the second semiconductor wafer 200, and the second wiring layer 210 can be positioned in the upper portion of the second semiconductor wafer 200, but the example embodiment is not limited to this. The second substrate 201 may also contain Si, etc. However, the material of the second substrate 201 is not limited to Si. One or more logic elements may be disposed in the second substrate 201, but are not limited to this.

[0040] The second wiring layer 210 may be located above the second substrate 201 and includes a plurality of second lines 212 and / or a second interlayer insulating layer 214, etc. In FIG3A, for clarity and ease of description, a single layer of second lines 212 is shown. However, the second wiring layer 210 may include a plurality of second lines 212 in multiple layers. The second lines 212 of the second wiring layer 210 may be connected to one or more logic elements in the logic region LA. In addition, the second lines 212 of the second wiring layer 210 may be connected to the first lines 182 and / or pads 170 of the first wiring layer 180 via vias 150.

[0041] As shown in Figure 1, the second semiconductor wafer 200 may be located below the first semiconductor wafer 100 and coupled to the first semiconductor wafer 100 via, for example, direct bonding, but is not limited thereto. Here, direct bonding may mean directly coupling (e.g., bonding) the insulating layers of the first semiconductor wafer 100 and the second semiconductor wafer 200 to each other. According to at least one exemplary embodiment, the first semiconductor wafer 100 and the second semiconductor wafer 200 may be coupled to each other by a release adhesive layer, etc.

[0042] In the coupling structure of the first semiconductor chip 100 and the second semiconductor chip 200, these semiconductor chips are coupled to each other such that the lower surface of the first wiring layer 180 of the first semiconductor chip 100 faces the upper surface of the second wiring layer 210 of the second semiconductor chip 200. Furthermore, vias 150 are disposed in the via array regions of the first peripheral region PE1 and the second peripheral region PE2, and the first semiconductor chip 100 and the second semiconductor chip 200 can be electrically connected to each other via the vias 150. Therefore, multiple pixel signals from the pixel region PA of the first semiconductor chip 100 can be transmitted to one or more logic elements in the logic region LA of the second semiconductor chip 200. Additionally, drive signals and power / ground signals can be transmitted from the logic elements in the logic region LA of the second semiconductor chip 200 to the pixels in the pixel region PA of the first semiconductor chip 100.

[0043] In the image sensor 1000 according to at least one example embodiment, the barrier insulating layer 125 is maintained on the back insulating layer 110 in the area outside the masked region SHA (e.g., the area of ​​the I / O pad region I / O PAD and the wafer edge region C / E), and thus, blemish defects can be significantly improved (e.g., blemish defects can be significantly reduced). Furthermore, in the image sensor 1000 according to at least one example embodiment, the metal layer outside the masked region SHA can be replaced with the barrier insulating layer 125, and thus, the density of the metal layer can be reduced to reduce wafer and / or wafer bending, etc.

[0044] Referring to Figures 2 and 3B, the image sensor 1000a according to at least one exemplary embodiment may differ from the image sensor 1000 of Figure 3A because the separation metal layer is not on the back insulating layer 110 of the shielding region SHA of the first peripheral region PE1. Specifically, the image sensor 1000a according to at least one exemplary embodiment may include a fence insulating layer 125a on the back insulating layer 110 of the shielding region SHA, but is not limited thereto. The fence insulating layer 125a may extend from the shielding region SHA to the I / O pad region I / O PAD and the wafer edge region C / E, etc. The fence insulating layer 125a in the I / O pad region I / O PAD and the wafer edge region C / E has the same structure as the fence insulating layer 125 in the image sensor 1000 of Figure 3A, but the exemplary embodiment is not limited thereto. In addition, when the dicing track (S / L) remains adjacent to the wafer edge region C / E, the fence insulating layer 125a may also extend on the back insulating layer 110 of the S / L.

[0045] In the image sensor 1000a according to at least one exemplary embodiment, the barrier insulating layer 125a is even maintained on the back insulating layer 110 of the shielded region SHA, as well as the I / O pad region I / O PAD and the wafer edge region C / E, and thus, contamination defects can be significantly improved (e.g., significantly reduced, decreased, etc.). Furthermore, in the image sensor 1000a according to at least one exemplary embodiment, the barrier insulating layer 125a can replace the second metal layer 160 of the shielded region SHA. Therefore, the density of the metal layer can be reduced to decrease wafer and / or wafer bending, etc.

[0046] Figures 4A to 4C are enlarged cross-sectional views of the back-side insulating layer 110 of Figure 3A according to some exemplary embodiments. The following description will be given with reference to Figure 3A, and the description already given with reference to Figures 1 to 3B will be given concisely or omitted.

[0047] Referring to FIG4A, in the image sensor 1000 according to at least one exemplary embodiment, the fence 120 of the active pixel sensor region APS may include a lower conductive layer 122 and / or an upper insulating layer 124, but is not limited thereto. Furthermore, similar to the fence 120, the fence insulating layer 125 of the first peripheral region PE1 may also include a lower conductive layer 122 and / or an upper insulating layer 124, etc. The lower conductive layer 122 may contain, for example, Ti / TiN, and the upper insulating layer 124 may contain, for example, TEOS and / or PTEOS. However, the materials of the lower conductive layer 122 and the upper insulating layer 124 are not limited to the materials described above. Additionally, the double-layer structure of each of the fence 120 and the fence insulating layer 125 can also be applied to the image sensor 1000a of FIG3B, but the exemplary embodiment is not limited thereto.

[0048] When each of the gate 120 and the gate insulating layer 125 includes a lower conductive layer 122, the back insulating layer 110 may include an AlO layer 112, a first HfOx layer 114, a PTEOS layer 116, and / or a second HfOx layer 118, etc., sequentially stacked on the back side of the first substrate 101, but the examples are not limited thereto. The AlO layer 112, the first HfOx layer 114, the PTEOS layer 116, and the second HfOx layer 118 may have thicknesses of, for example, 100 angstroms, 625 angstroms, 700 angstroms, and 100 angstroms, respectively. However, the thicknesses of the AlO layer 112, the first HfOx layer 114, the PTEOS layer 116, and the second HfOx layer 118 are not limited to the above values. In addition, the second HfOx layer 118 may serve as an etch stop layer for the upper metal layer and / or the upper gate film.

[0049] Referring to Figures 4B and 4C, in the image sensor 1000b according to at least one exemplary embodiment, the fence 120a of the active pixel sensor region APS may include a single insulating layer, but the exemplary embodiment is not limited thereto. That is, the fence 120a may not include a lower conductive layer. Furthermore, the image sensor 1000b according to at least one exemplary embodiment may include the fence insulating layer 125 of Figure 3A or the fence insulating layer 125a of Figure 3B in the first peripheral region PE1, but is not limited thereto. Similar to the fence 120a, the fence insulating layer 125 or the fence insulating layer 125a may include a single insulating layer, but is not limited thereto. The fence 120a and the fence insulating layer 125 or the fence insulating layer 125a may contain, for example, TEOS and / or PTEOS. However, the materials of the fence 120a and the fence insulating layer 125 or the fence insulating layer 125a are not limited to the materials described above.

[0050] When either the gate 120a or the gate insulating layer 125 comprises a single insulating layer, the back insulating layer 110a may comprise, but is not limited to, AlO layer 112, TiO2 layer 115, PTEOS layer 116a, and / or HfOx layer 118a, etc., sequentially stacked on the back side of the first substrate 101. The AlO layer 112, TiO2 layer 115, PTEOS layer 116a, and HfOx layer 118a may have thicknesses of, for example, 100 angstroms, 360 angstroms, 700 angstroms, and 100 angstroms, respectively, but the exemplary embodiments are not limited to these. However, the thicknesses of the AlO layer 112, TiO2 layer 115, PTEOS layer 116a, and HfOx layer 118a are not limited to the values ​​described above. Furthermore, the HfOx layer 118a may serve as an etch stop layer for the upper metal layer and / or the upper gate film. In addition, TiO2 layer 115 can be used as a reflective blocking layer for conductive thin films, etc.

[0051] In the image sensor 1000b according to at least one example embodiment, neither the fence 120a nor the fence insulating layer 125 or the fence insulating layer 125a contains a lower conductive layer, and the back insulating layer 110a may contain a TiO2 layer 115 instead of a first HfOx layer 114, but is not limited thereto. Furthermore, since the TiO2 layer 115 has a thickness of approximately 360 angstroms, the total thickness of the back insulating layer 110a can be reduced by approximately 265 angstroms compared to the back insulating layer 110 of FIG. 4A, but the example embodiment is not limited thereto.

[0052] Furthermore, since the back insulating layer 110a includes a conductive TiO2 layer 115, the TiO2 layer 115 can be disconnected at portions where node separation is required and / or where it is necessary. Figure 4C illustrates a structure in which the TiO2 layer 115 is disconnected at the node separation portion NDA. Because the TiO2 layer 115 is disconnected at the node separation portion NDA, a groove H can be formed in the node separation portion NDA. In other words, as shown in Figure 4C, in the node separation portion NDA in which the TiO2 layer 115 is disconnected, the PTEOS layer 116a and HfOx layer 118a in the upper region are formed to a uniform or substantially uniform thickness (e.g., + / - 10% thickness), and therefore, a groove H can be formed in the node separation portion NDA, etc. In the following, Figures 5A to 7B illustrate various node separation portions NDA in which the TiO2 layer 115 is disconnected, but the exemplary embodiments are not limited thereto.

[0053] Figures 5A to 7B are plan views and corresponding cross-sections of the node separation portion of the structure in which the back-side insulating layer 110a of Figure 4C is applied. Figures 5B, 6B, and 7B are cross-sectional views taken along lines II-II' of Figure 5A, III-III' of Figure 6A, and IV-IV' of Figure 7A, respectively, according to some example embodiments.

[0054] Figures 5A and 5B illustrate the node separation portion NDA in the I / O pad area of ​​the first peripheral region PE1, but the exemplary embodiments are not limited thereto. The node separation portion NDA may be located on both sides of the perforation 150, but is not limited thereto. In Figure 5A, the quadrilateral dashed line surrounding the perforation 150 may correspond to the node separation portion NDA.

[0055] Figures 6A and 6B illustrate the node separation portion NDA in the first perforated array region TVA1 and / or the second perforated array region TVA2 in the first peripheral region PE1, but the exemplary embodiments are not limited thereto. The node separation portion NDA may be located on both sides of the perforation 150, but is not limited thereto. In Figure 6A, the dashed lines of the grid pattern surrounding the perforation 150 may correspond to the node separation portion NDA.

[0056] Figures 7A and 7B illustrate the node separation portion NDA in the edge of the pixel region PA where the back contact BCA is located, but the exemplary embodiments are not limited thereto. The node separation portion NDA may be located on both sides of the back contact BCA, but is not limited thereto. In Figure 7A, the dashed line surrounding the back contact BCA may correspond to the node separation portion NDA.

[0057] For reference purposes, the back contact BCA may be connected to at least one DTI 105. The DTI 105 may have a structure extending through the first substrate 101 in the z-direction, but is not limited thereto. Since the DTI 105 is formed within a structure extending through the first substrate 101, crosstalk attributable to oblique incident light can be reduced, decreased, and / or avoided. The DTI 105 may include a central conductive layer and an outer insulating layer, etc. The central conductive layer may include, for example, polycrystalline silicon and / or doped polycrystalline silicon, etc. However, the material of the central conductive layer is not limited to the aforementioned materials. For example, the central conductive layer may include a metal, a metal silicate, a metal-containing conductive material, and / or the like. The outer insulating layer may surround the exterior of the central conductive layer and insulate the central conductive layer from the first substrate 101. The outer insulating layer may include, for example, oxides and / or nitrides, such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0058] The back contact BCA may be located in the edge portion of the pixel region PA, and a power supply, such as a (-) voltage (e.g., a negative voltage), may be applied to the central conductive layer of the DTI 105, but the example embodiments are not limited thereto. The (-) voltage is applied to the central conductive layer of the DTI 105 via the back contact BCA, and thus can fix holes existing on the surface of the outer insulating layer of the DTI 105, thereby improving dark current characteristics, etc.

[0059] Figures 8A and 8B are cross-sectional views of an image sensor having a stacked structure according to some exemplary embodiments and correspond to Figure 3A, but the exemplary embodiments are not limited thereto. The following description will be given with reference to Figure 1, and the descriptions given with reference to Figures 1 to 7B will be given concisely or omitted.

[0060] Referring to FIG8A, the image sensor 1000c according to at least one embodiment may differ from the image sensor 1000 or image sensor 1000a of FIG3A or FIG3B in terms of the structure of the barrier insulating layer 125b and the presence of the additional blue filter layer 130a. Specifically, in the image sensor 1000c according to at least one embodiment, the barrier insulating layer 125b may completely cover the first peripheral region PE1. That is, the barrier insulating layer 125b may cover the region above the first through-hole array region TVA1 and the second through-hole array region TVA2, as well as the masking region SHA, the I / O pad region I / O PAD, and the chip edge region C / E, but is not limited thereto. In addition, the barrier insulating layer 125b may also cover a portion of the first metal layer 140 in the optical black pixel region OB, etc. According to at least one embodiment, the barrier insulating layer 125b may not cover the first metal layer 140 in the optical black pixel region OB.

[0061] The fence 120 and fence insulating layer 125b may include a lower conductive layer 122 and an upper insulating layer 124, and the back insulating layer 110 may have the structure shown in FIG. 4A, but is not limited thereto. Therefore, in the first perforated array region TVA1 and the second perforated array region TVA2, node separation is required and / or necessary between the perforations 150. Therefore, as shown in FIG. 8A, the fence insulating layer 125b may be disconnected in the node separation portion NDA, but is not limited thereto.

[0062] Furthermore, in the image sensor 1000c according to at least one exemplary embodiment, the optical black pixel region OB and the first perforated array region TVA1 and the second perforated array region TVA2 may be covered by an additional blue filter layer 130a, but the exemplary embodiment is not limited thereto. For example, the additional blue filter layer 130a may cover the fence insulating layer 125b on the first perforated array region TVA1 and the second perforated array region TVA2 and the first metal layer 140 on the optical black pixel region OB, etc. Since the additional blue filter layer 130a is provided as described above, it is possible to block light input to the first perforated array region TVA1 and the second perforated array region TVA2 and / or further enhance the blocking of light input to the optical black pixel region OB, etc. For reference purposes, when a blue filter is formed in the active pixel sensor region APS, the additional blue filter layer 130a may be formed together, but the exemplary embodiment is not limited thereto.

[0063] Referring to FIG8B, the image sensor 1000d according to at least one exemplary embodiment may differ from the image sensor 1000c of FIG8A in terms of the structure of the fence insulating layer 125c. Specifically, in the image sensor 1000d according to at least one exemplary embodiment, the fence insulating layer 125c may completely cover the first metal layer 140 of the first peripheral region PE1 and the optical black pixel region OB, but is not limited thereto. According to at least one exemplary embodiment, the fence insulating layer 125c may not cover the first metal layer 140 in the optical black pixel region OB.

[0064] The fence 120a and fence insulating layer 125c may comprise a single insulating layer, and the back insulating layer 110a may have the structure shown in FIG. 4B, but the exemplary embodiments are not limited thereto. Therefore, in the first perforated array region TVA1 and the second perforated array region TVA2, it is necessary and / or required that the perforations 150 be separated by nodes of the back insulating layer 110a. Therefore, although not shown in FIG. 8B, the TiO2 layer 115 of the back insulating layer 110a may be disconnected in the node separation portion NDA. As described above, node separation is formed by the back insulating layer 110a, and therefore the fence insulating layer 125c may be continuously connected in the node separation portion NDA without disconnection (as shown in FIG. 8B), but is not limited thereto.

[0065] Furthermore, even in the image sensor 1000d according to at least one example embodiment, the optical black pixel region OB and the first punch array region TVA1 and the second punch array region TVA2 may be covered by an additional blue filter layer 130a, but are not limited thereto. For example, the additional blue filter layer 130a may cover the fence insulating layer 125c on the first punch array region TVA1 and the second punch array region TVA2, and the first metal layer 140 on the optical black pixel region OB, etc.

[0066] In the image sensor 1000c of FIG8A and the image sensor 1000d of FIG8B, since the barrier insulating layers 125b and 125c completely cover the first peripheral region PE1, the height difference between patterns can be reduced and / or minimized over the entire first peripheral region PE1. Therefore, the color filter 130 can be smoothly formed during the spin coating process, and blemish defects can be significantly improved (e.g., significantly reduced, decreased, etc.). For reference purposes, since the image sensor 1000c of FIG8A and the image sensor 1000d of FIG8B have a structure in which the barrier insulating layers 125b and 125c extend over the first perforated array region TVA1 and the second perforated array region TVA2, the size and / or contour of the perforation 150 can be unchanged.

[0067] Figures 9A to 9G are schematic cross-sectional views illustrating a process for manufacturing the image sensor 1000 of Figure 1 with a stacked structure according to some exemplary embodiments. The following description will be given with common reference to Figure 8A, and the descriptions already given with reference to Figures 1 to 8B will be given concisely or omitted, but the exemplary embodiments are not limited thereto. Furthermore, in Figures 9A to 9G, for clarity and ease of description, only a portion of the first perforated array region TVA1 of the first peripheral region PE1 is shown.

[0068] Referring to FIG9A, in a method for manufacturing an image sensor having a stacked structure according to at least one exemplary embodiment (hereinafter simply referred to as "method for manufacturing an image sensor"), a first semiconductor wafer 100 is fabricated. Specifically, pixels are formed in pixel regions PA of a first substrate 101 of the first semiconductor wafer 100. Each of the pixels may include a photodiode PD and a pixel transistor (not shown), but is not limited thereto. Here, the pixels may be separated from each other by a DTI 105. The DTI 105 may also be located in a first peripheral region PE1.

[0069] After a pixel is formed in the pixel region PA, a first wiring layer 180 is formed on the lower surface of the first substrate 101. Here, the lower surface of the first substrate 101 represents the active surface ACT, and the upper surface of the first substrate 101 represents the non-active surface NACT. That is, the lower surface of the first substrate 101 may correspond to the front side, and the upper surface of the first substrate 101 may correspond to the back side. The first wiring layer 180 may include a plurality of first lines 182 and / or a first interlayer insulating layer 184, etc. The first lines 182 may be connected to the pixel transistors respectively.

[0070] Next, referring to FIG. 9B, a second semiconductor wafer 200 is fabricated. Specifically, one or more logic elements (not shown) are formed in a second substrate 201 of the second semiconductor wafer 200, and a second wiring layer 210 is formed on the active surface of the second substrate 201. In FIG. 9B, the upper surface of the second substrate 201 may represent the active surface, and the lower surface of the second substrate 201 may represent the non-active surface. The second wiring layer 210 may include a plurality of second lines 212 and / or a second interlayer insulating layer 214, etc. In FIG. 9B, only one second line 212 is shown for clarity and convenience. However, in some exemplary embodiments, a plurality of second lines 212 in the multilayer may be disposed in the second interlayer insulating layer 214, and the second lines 212 may be connected to one or more logic elements, etc., of the second substrate 201.

[0071] According to some exemplary embodiments, the fabrication of the second semiconductor wafer 200 can be performed in parallel with the fabrication of the first semiconductor wafer 100, but is not limited thereto. In other words, there may be no priority order between the fabrication of the second semiconductor wafer 200 and the fabrication of the first semiconductor wafer 100. Furthermore, while the fabrication of the first semiconductor wafer 100 and the second semiconductor wafer 200 are shown in FIG. 9A and FIG. 9B as unit wafers, they can actually be performed in unit wafer form. In other words, the fabrication of the first semiconductor wafer 100 may correspond to the fabrication of a first wafer comprising multiple first semiconductor wafers 100, and the fabrication of the second semiconductor wafer 200 may correspond to the fabrication of a second wafer comprising multiple second semiconductor wafers 200, and so on.

[0072] After fabricating the first semiconductor wafer 100 and the second semiconductor wafer 200, the first semiconductor wafer 100 and the second semiconductor wafer 200 are coupled to each other by direct bonding, but are not limited thereto. For example, the first wiring layer 180 of the first semiconductor wafer 100 may be coupled to the second wiring layer 210 of the second semiconductor wafer 200. Specifically, the first interlayer insulating layer 184 of the first wiring layer 180 may be coupled to the second interlayer insulating layer 214 of the second wiring layer 210, for example, by direct bonding. Furthermore, the coupling between the first semiconductor wafer 100 and the second semiconductor wafer 200 can be performed on a unit wafer basis. In other words, a first wafer containing a plurality of first semiconductor wafers 100 may be coupled to a second wafer containing a plurality of second semiconductor wafers 200, for example, by direct bonding.

[0073] Referring to FIG9C, after the first semiconductor wafer 100 and the second semiconductor wafer 200 are coupled to each other, a portion of the back side of the first substrate 101 of the first semiconductor wafer 100 is removed to thin the first substrate 101. The removal of the back side of the first semiconductor wafer 100 can be performed, for example, by a back-polishing process, such as polishing and / or chemical mechanical polishing (CMP). As illustrated in FIG9C, the DTI 105 can be exposed by removing the back side of the first substrate 101. For example, during the back-polishing process, the DTI 105 can act as an etch stop layer.

[0074] Referring to FIG. 9D, after thinning the first substrate 101, a back-side insulating layer 110 is formed on the back side of the first substrate 101. The back-side insulating layer 110 may have the structure of FIG. 4A, but the example embodiment is not limited to this. However, a back-side insulating layer 110a with the structure of FIG. 4B, rather than the back-side insulating layer 110, may be formed. For example, when the formed fence and fence insulating layer subsequently have a double-layer structure including the lower conductive layer 122, the back-side insulating layer 110 of FIG. 4A may be formed. On the other hand, when the fence and fence insulating layer have a structure of a single insulating layer, the back-side insulating layer 110a of FIG. 4B may be formed. In the following description, for ease of description, the structure of the back-side insulating layer 110 of FIG. 4A will be described, but the example embodiment is not limited to this.

[0075] Referring to Figure 9E, at least one via 150 is subsequently formed in the first via array region TVA1. The via 150 may include an outer conductive layer 152 and a via metal layer 154, etc. The outer conductive layer 152 may include at least one metal layer. For example, the outer conductive layer 152 may include titanium (Ti) / titanium nitride (TiN) and / or tungsten (W), etc., and / or the via metal layer 154 may include aluminum (Al), etc. However, the materials of the outer conductive layer 152 and the via metal layer 154 are not limited to the aforementioned conductive materials.

[0076] As shown in FIG9E, via 150 can be connected to the first line 182 of the first wiring layer 180 and also to the second line 212 of the second wiring layer 210 of the second semiconductor wafer 200. That is, via 150 can connect the first line 182 and the second line 212 to each other. In addition, although not shown, via 150 and / or pads 170, etc., can also be formed in the I / O pad area I / O PAD. The via 150 of the I / O pad area I / O PAD can also be connected to the pad 170.

[0077] Next, referring to FIG9F, a first metal layer 140 is formed in the optical black pixel region OB. Additionally, at least one color filter 130 is formed in the active pixel sensor region APS. When the color filter 130 is formed, an additional blue filter layer 130a may be formed to cover the first perforated array region TVA1 and / or the second perforated array region TVA2, etc., of the first peripheral region PE1, but the exemplary embodiments are not limited thereto. According to at least one exemplary embodiment, the additional blue filter layer 130a may be omitted.

[0078] The color filter 130 may be configured in a 2D array structure corresponding to pixels, but is not limited thereto. In at least one exemplary embodiment, the color filter 130 may have a Bayer pattern structure including a red filter, a green filter, and a blue filter, etc. In at least one exemplary embodiment, the color filter 130 may include a yellow filter, a magenta filter, and a cyan filter, etc. In addition, the color filter 130 may additionally include a white filter.

[0079] Furthermore, before forming the color filter 130, a fence 120 and / or a fence insulating layer 125 may be formed. Therefore, an additional blue filter layer 130a may cover the fence insulating layer 125. Additionally, the fence 120 and the fence insulating layer 125 may include a lower conductive layer 122, and thus, the fence insulating layer 125 may be disconnected in the node separation portion. However, if the fence 120 and the fence insulating layer 125 only contain insulating layers, the TiO2 layer 115 of the back insulating layer 110a is disconnected in the node separation portion, but the fence insulating layer 125 may not be disconnected.

[0080] The process of forming the first metal layer 140, the fence 120, and the fence insulating layer 125 in the optical black pixel region OB will be described in more detail below in the description of Figures 10A to 10C.

[0081] Referring to Figure 9G, after forming the color filter 130 and / or an additional blue filter layer 130a, a microlens 190 is formed on the color filter 130, etc. Specifically, a lens material layer is formed on the color filter 130, and a photoresist (PR) pattern is formed on the lens material layer using a photolithography process. Subsequently, a reflow process is performed on the PR pattern to make the PR pattern hemispherical, but the example embodiment is not limited to this, and for example, the PR pattern can be formed in different shapes. Subsequently, the microlens 190 is formed by using the PR pattern as a mask to pattern the lens material layer. In addition, according to at least one example embodiment, a planarization lens layer can be formed on the color filter 130 and / or the microlens 190 can be formed on the planarization lens layer, but it is not limited to this.

[0082] Figures 10A to 10C are cross-sectional views illustrating in more detail the process of forming the fence and fence insulating layer in relation to the color filter of Figure 9F, according to some exemplary embodiments. The following description will be given with common reference to Figures 8A and 9F, and the descriptions already given with reference to Figures 1 to 9G will be given concisely or omitted, but the exemplary embodiments are not limited thereto. Furthermore, even in Figures 10A to 10C, for ease of description and clarity, only a portion of the first perforated array region TVA1 of the first peripheral region PE1 is shown, but the exemplary embodiments are not limited thereto.

[0083] Referring to FIG10A, a back-side insulating layer 110 is formed on the back side of the first substrate 101, but is not limited thereto. Furthermore, as shown in FIG9E, a perforation 150 is formed in the first perforation array region TVA1, but is not limited thereto. Subsequently, a first metal layer 140 is formed on the optical black pixel region OB. The first metal layer 140 may contain, for example, tungsten (W). However, the material of the first metal layer 140 is not limited to tungsten (W) and may be different metals and / or metal alloys. Furthermore, although not shown, a second metal layer 160 and a first metal layer 140 may be formed when a second metal layer 160 is formed in the shielding region SHA. In the following, when the second metal layer 160 is present in the shielding region SHA, the second metal layer 160 may be considered to be the same as and / or substantially the same as the first metal layer 140.

[0084] Referring to FIG10B, after the first metal layer 140 is formed on the optical black pixel region OB, a barrier insulating layer 120L is formed on the entire back side of the first substrate 101, but the example embodiment is not limited thereto. The barrier insulating layer 120L may cover the exposed area of ​​the back insulating layer 110 and / or the structures on the back insulating layer 110. For example, the barrier insulating layer 120L may cover the back insulating layer 110 in the active pixel sensor region APS and the first metal layer 140 in the optical black pixel region OB, etc. In addition, the barrier insulating layer 120L may cover the perforations 150 in the first perforated array region TVA1, etc.

[0085] Referring to Figure 10C, the barrier insulating layer 120L is subsequently patterned by a photolithography process. Therefore, the barrier 120 is formed in the active pixel sensor region APS, and the barrier insulating layer 125 is formed in the first peripheral region PE1. Here, the barrier insulating layer 120L on the first metal layer 140 in the optical black pixel region OB is removed. Furthermore, the barrier insulating layer 120L may remain on at least one side surface of the first metal layer 140 to form a first spacer 142, but the exemplary embodiments are not limited thereto. According to at least one exemplary embodiment, the first spacer 142 may not be formed, for example, the first spacer 142 may be omitted.

[0086] In the first peripheral region PE1, the fence insulating layer 125 may cover the exposed area of ​​the back insulating layer 110 and / or the structure on the back insulating layer 110. Various structures of the fence insulating layer 125 are shown in the image sensor 1000 of FIG. 3A, the image sensor 1000a of FIG. 3B, the image sensor 1000c of FIG. 8A, and the image sensor 1000d of FIG. 8B, but the exemplary embodiments are not limited thereto. After the fence 120 and the fence insulating layer 125 are formed, a color filter 130 and an additional blue filter layer 130a are formed thereon. Therefore, the structure of FIG. 9F can be formed.

[0087] While various exemplary embodiments of the concept of the present invention have been specifically illustrated and described, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0088] 100: First Semiconductor Wafer 1000, 1000a, 1000b, 1000c, 1000d: Image Sensor 101: First basement 105: Deep trench isolation 110, 110a: Backside insulation layer 112: AlO layer 114: First HfOx layer 115:TiO 2 layers 116, 116a: PTEOS layer 118: Second HfOx layer 118a:HfOx layer 120, 120a: Fence 120L, 125, 125a, 125b, 125c: Fence insulation layer 122: Lower conductive layer 124: Upper insulation layer 130: Color Filter 130a: Blue filter layer 140: First metal layer 142: First spacer 150: Perforation 152: Outer conductive layer 154: Through-hole metal layer 160: Second metal layer 162: Second spacer 170: Padding 180: First wiring layer 182: First Line 184: First interlayer insulation layer 190: Microlens 200: Second semiconductor chip 201: Second basement 210: Second wiring layer 212: Second Line 214: Second interlayer insulation layer ACT: Active Surface APS: Active Pixel Sensor Area BCA: Backside contact element C / E: Edge region of the wafer H: Groove I / O PAD: I / O pad area I-I', II-II', III-III', IV-IV': line LA: Logical Region NACT: Non-active surface NDA: Node Separation Part OB: Optical black pixel area PA: Pixel area PD: Photodiode PE1: First Surrounding Area PE2: Second Surrounding Area SHA: Covered Area TVA1: First Perforated Array Region TVA2: Second Perforated Array Region x, y, z: Direction

Claims

1. An image sensor having a stacked structure, the image sensor comprising: A first semiconductor chip includes a pixel region and a peripheral region, wherein the pixel region includes a plurality of pixels; The first semiconductor wafer includes a second semiconductor wafer coupled to the lower surface of the first semiconductor wafer, the second semiconductor wafer including a plurality of logic elements, the pixel region including a plurality of color filters and a fence, the plurality of color filters corresponding to the plurality of pixels, the fence having a grid pattern and the plurality of color filters being separated from each other by the fence, the peripheral region including a shielding region and a shielding outer region, the shielding region surrounding the pixel region, and a fence insulating layer included in the shielding outer region, the fence insulating layer comprising the same material as the fence.

2. The image sensor with a stacked structure as claimed in claim 1, wherein the first semiconductor wafer comprises: A first substrate and a first wiring layer located on the lower surface of the first substrate, wherein the plurality of pixels are contained in the pixel region of the first substrate; a back insulating layer located on the upper surface of the first substrate, wherein the fence, the color filter and the fence insulating layer are located on the back insulating layer, and the fence and the fence insulating layer have the same thickness from the upper surface of the back insulating layer.

3. The image sensor with a stacked structure as claimed in claim 2, wherein the back-side insulating layer comprises a metal layer in the shielded region or the fence insulating layer.

4. The image sensor with a stacked structure as claimed in claim 2, wherein each of the fence and the fence insulating layer comprises a lower conductive layer and an upper insulating layer; the back insulating layer comprises an AlO layer, a first HfOx layer, a tetraethyl orthosilicate (TEOS) layer and a second HfOx layer, wherein the AlO layer, the first HfOx layer, the TEOS layer and the second HfOx layer are stacked sequentially; and the second HfOx layer is a metal layer or an etch stop layer on a thin film of the fence.

5. The image sensor with a stacked structure as claimed in claim 2, wherein each of the fence and the fence insulating layer comprises a single insulating layer; and the back insulating layer comprises an AlO layer, a TiO2 layer, a tetraethyl orthosilicate (TEOS) layer and an HfOx layer, wherein the AlO layer, the TiO2 layer, the TEOS layer and the HfOx layer are stacked sequentially.

6. The image sensor with a stacked structure as claimed in claim 5, wherein the TiO2 layer is disconnected at a separation portion of the back-side insulating layer; and the AlO layer, the TEOS layer, and the HfOx layer are continuously connected in the separation portion.

7. The image sensor with a stacked structure as claimed in claim 1, wherein the peripheral region includes the shielding region, the I / O pad region, and the wafer edge region, the I / O pad region being located outside the shielding region, and the wafer edge region comprising the outermost portion of the first semiconductor wafer; at least one via array region being located in at least a portion of the shielding region; and the fence insulating layer covering the I / O pad region and the wafer edge region.

8. The image sensor with a stacked structure as described in claim 7, further comprising: A metal layer located in the shielding region outside the at least one perforated array region; And spacers, comprising the same material as the fence, the spacers being located on at least one side surface of the metal layer.

9. The image sensor with a stacked structure as claimed in claim 7, wherein the fence insulation layer is located in the shielding region outside the at least one perforated array region.

10. The image sensor with a stacked structure as claimed in claim 7, wherein the at least one perforated array region includes a plurality of perforations; the I / O pad region includes at least one pad and a plurality of perforations; and the fence insulation layer covers the area above the plurality of perforations, the area above the pad, the area between the plurality of perforations, and the area between the at least one perforated array region and the I / O pad region.

11. An image sensor having a stacked structure, the image sensor comprising: A first semiconductor wafer includes a substrate and at least one wiring layer. The substrate includes a pixel region, a peripheral region, and a back-side insulating layer. The at least one wiring layer is located on a lower surface of the substrate. The pixel region includes a plurality of pixels, and the back-side insulating layer is located on an upper surface of the substrate. A second semiconductor wafer is coupled to the lower surface of the first semiconductor wafer. The second semiconductor wafer includes a plurality of logic elements. The back-side insulating layer includes a gate, a plurality of color filters, and a TiO2 layer. The gate and the plurality of color filters are located in the pixel region. The gate includes a single insulating layer with a grid pattern, and the plurality of color filters are separated from each other by the gate. A gate insulating layer is located on an I / O pad region and at least one via array region in the peripheral region. The gate insulating layer comprises the same material as the gate.

12. The image sensor with a stacked structure as claimed in claim 11, wherein the back-side insulating layer comprises an AlO layer, the TiO2 layer, a tetraethyl orthosilicate (TEOS) layer, and an HfOx layer, and the AlO layer, the TiO2 layer, the TEOS layer, and the HfOx layer are stacked sequentially; the TiO2 layer is disconnected at node separation portions of the back-side insulating layer; and the AlO layer, the TEOS layer, and the HfOx layer are continuously connected in the node separation portions.

13. The image sensor with a stacked structure as claimed in claim 11, wherein the peripheral region includes a masking region, the I / O pad region, and a wafer edge region, the masking region surrounding the pixel region, the I / O pad region being located outside the masking region and including at least one pad and a plurality of first vias, and the wafer edge region including the outermost portion of the first semiconductor wafer; and the at least one via array region being located in at least a portion of the masking region and including a plurality of second vias.

14. An image sensor having a stacked structure, the image sensor comprising: A first semiconductor wafer includes a substrate and a wiring layer. The substrate includes a pixel region, a peripheral region, and a back-side insulating layer. The wiring layer is located on a lower surface of the substrate. The pixel region includes a plurality of pixels, and the back-side insulating layer is located on an upper surface of the substrate. The first semiconductor wafer includes a second semiconductor wafer coupled to the lower surface of the first semiconductor wafer, the second semiconductor wafer including a plurality of logic elements; the back-side insulating layer includes a fence and a plurality of color filters in the pixel region, the fence having a grid pattern and the plurality of color filters being separated from each other by the fence; the peripheral region includes a shielding region and an outer shielding region, the shielding region surrounding the pixel region; and a fence insulating layer located in the outer shielding region, the fence insulating layer comprising the same material as the fence.

15. The image sensor with a stacked structure as claimed in claim 14, wherein the back-side insulating layer comprises a metal layer in the shielded region or the fence insulating layer.

16. The image sensor with a stacked structure as claimed in claim 14, wherein the fence insulation layer in the outer masking region is located on the back insulation layer; and the fence and the fence insulation layer have the same thickness from the upper surface of the back insulation layer.

17. A method for manufacturing an image sensor having a stacked structure, the method comprising: A plurality of pixels are formed in a first substrate of a first semiconductor wafer, each of the plurality of pixels comprising a photodiode; a first wiring layer is formed on an active surface of the first substrate; a plurality of logic elements are formed in a second substrate of a second semiconductor wafer; a second wiring layer is formed on an active surface of the second substrate; the first semiconductor wafer and the second semiconductor wafer are coupled to each other such that the first wiring layer faces the second wiring layer; the first substrate is thinned, the thinning comprising removing a portion of the non-active surface of the first substrate; A back-side insulating layer is formed on the non-active surface of the first substrate; a plurality of perforations are formed in at least one perforation array region of the first substrate; a plurality of color filters are formed on the back-side insulating layer in a pixel region of the first substrate, the plurality of color filters corresponding to the plurality of pixels; and a plurality of microlenses are formed on the plurality of color filters, wherein the formation of the plurality of color filters includes: forming a fence material layer on the back-side insulating layer; forming a fence with a grid pattern in the pixel region; forming a fence insulating layer in an outer shielding region, the outer shielding region being located outside the shielding region of the first substrate; and forming the plurality of color filters inside the fence.

18. A method of manufacturing an image sensor having a stacked structure as claimed in claim 17, wherein each of the fence and the fence insulating layer comprises a lower conductive layer and an upper insulating layer; the back insulating layer comprises an AlO layer, a first HfOx layer, a tetraethyl orthosilicate (TEOS) layer and a second HfOx layer, wherein the AlO layer, the first HfOx layer, the TEOS layer and the second HfOx layer are stacked sequentially; and the second HfOx layer is an etch stop layer for forming a metal layer or the fence.

19. A method of manufacturing an image sensor having a stacked structure as claimed in claim 17, wherein each of the fence and the fence insulating layer comprises a single insulating layer; the back insulating layer comprises an AlO layer, a TiO2 layer, a tetraethyl orthosilicate (TEOS) layer, and an HfOx layer, wherein the AlO layer, the TEOS layer, and the HfOx layer are stacked sequentially; the TiO2 layer is formed to be disconnected at a node separation portion of the back insulating layer; and the AlO layer, the TEOS layer, and the HfOx layer are formed to be continuously connected in the node separation portion.

20. A method for manufacturing an image sensor having a stacked structure as described in claim 17, wherein, During the formation of the plurality of perforations: the liner and the plurality of perforations are formed in the I / O liner region of the first substrate; The fence insulation layer is formed to cover the area above the plurality of perforations, the area above the pad, the area between the plurality of perforations, and the area between the at least one perforation array area and the I / O pad area.

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