Semiconductor device including dielectric layer with uneven thickness

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded in the substrate. The dielectric layer has a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness less than the first thickness. The gate electrode is spaced from the substrate by the first portion of the dielectric layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 395,797 (i.e., priority date "December 26, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device. In particular, it relates to a semiconductor device having a dielectric layer of non-uniform thickness and a method for fabricating the same. Prior Technology

[0003] As the efficiency and miniaturization of integrated circuits (ICs) continue to improve, advancements in materials and design have resulted in successive generations of products with smaller and more complex circuits.

[0004] With the development of the semiconductor industry, the aspect ratio of trenches on a substrate is increasing, which negatively impacts the formation of gate electrodes within each trench. For example, voids may appear at the bottom of the trench, causing electronic properties to fail to meet practical requirements. Therefore, a new semiconductor device and its fabrication method are needed to improve these problems.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded in the substrate. The dielectric layer has a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a gate dielectric, a gate electrode, and a dielectric structure. The gate dielectric is embedded within the substrate. The gate electrode is spaced apart from the substrate by the gate dielectric. The dielectric structure is disposed above the gate electrode. The dielectric structure includes a stepped profile.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a trench. The method also includes forming a dielectric layer having a first thickness within the trench. The method further includes removing an upper portion of the dielectric layer, such that the upper portion of the dielectric layer has a second thickness, the second thickness being smaller than the first thickness of a lower portion of the dielectric layer. Additionally, the method includes forming a gate electrode within the trench.

[0009] The embodiments disclosed herein include a semiconductor device having a dielectric layer located within a trench defined by a substrate. The dielectric layer has a lower portion and an upper portion, the lower portion having a greater thickness and the upper portion having a smaller thickness. This structure facilitates the filling of a conductive material to form a gate electrode without creating voids within the trench. As a result, the performance of the semiconductor device is improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0012] Figure 1A is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0013] Figure 1B is a partially enlarged schematic diagram illustrating region R of a semiconductor element as shown in Figure 1A, representing some embodiments of this disclosure.

[0014] Figure 2 is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0015] Figure 3 is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0016] Figure 4 is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure.

[0017] Figure 5A is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0018] Figure 5B is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0019] Figure 5C is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0020] Figure 5D is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0021] Figure 5E is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0022] Figure 5F is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0023] Figure 5G is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments disclosed herein.

[0024] Figure 5H is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0025] Figure 5I is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0026] Figure 5J is a schematic diagram illustrating one or more stages of an exemplary method for manufacturing a semiconductor device according to some embodiments of this disclosure.

[0027] Figure 6 is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure. Implementation

[0028] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0029] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0031] Figure 1A is a cross-sectional schematic diagram illustrating a semiconductor element 100a according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 100a may include a cell region in which a memory element is formed. For example, the memory element may include a dynamic random access memory (DRAM) element, an one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. For example, a DRAM may include a transistor, a capacitor, and other components. In some embodiments, the semiconductor element 100a may include a peripheral region in which a transistor is formed.

[0032] During a read operation, a word line can be asserted to turn on the transistor. The enabled transistor allows the voltage across a capacitor to be read via a sense amplifier through the word line. During a write operation, when the word line is asserted, the data to be written can be provided on the bit line.

[0033] Semiconductor element 100a may include a substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 102 may include an elemental semiconductor, including silicon or germanium in a single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge characteristic, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe characteristic to another ratio at another location. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 102 may have a multilayer structure, or the substrate 102 may include a multilayer compound semiconductor structure.

[0034] In some embodiments, substrate 102 may include a plurality of active regions (not shown). For example, the active regions may serve as a channel for electrical connection. In some embodiments, dopants (not shown) may be incorporated into substrate 102 to form the active regions. In some embodiments, the dopants may be n-type and / or p-type. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other Group V elements, or any combination thereof. In some embodiments, the first conductivity type is p-type. In some embodiments, p-type dopants include boron (B), other Group III elements, or any combination thereof.

[0035] In some embodiments, semiconductor device 100a may include an electrically isolated region 104. In some embodiments, the electrically isolated region 104 may include a shallow trench isolation (STI). In some embodiments, a plurality of active regions may be spaced apart by the electrically isolated region 104. In some embodiments, the electrically isolated region 104 may be embedded in a substrate 102. In some embodiments, for example, the electrically isolated region 104 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0036] In some embodiments, semiconductor device 100a may include a dielectric layer 106. The dielectric layer 106 may be disposed on substrate 102. In some embodiments, the dielectric layer 106 may cover an electrically isolated region 104. In some embodiments, for example, the dielectric layer 106 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0037] In some embodiments, semiconductor element 100a may include a dielectric layer 108. The dielectric layer 108 may be disposed on dielectric layer 106. In some embodiments, for example, dielectric layer 108 may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials. In some embodiments, the dimensions (e.g., thickness) of dielectric layer 106 may differ from the dimensions of dielectric layer 108. For example, the thickness of dielectric layer 108 may be greater than the thickness of dielectric layer 106. In some embodiments, the material of dielectric layer 108 may differ from the material of dielectric layer 106. For example, dielectric layer 106 may include or be made of silicon oxide (SiO2), and dielectric layer 108 may include or be made of silicon nitride (Si3N4). In some embodiments, dielectric layer 106, dielectric layer 108, or both may be referred to as an isolation structure.

[0038] In some embodiments, substrate 102, dielectric layer 106, and / or dielectric layer 108 may define a plurality of trenches 110. Trench 110 may penetrate a portion of substrate 102. Trench 110 may penetrate dielectric layer 106. Trench 110 may penetrate dielectric layer 108. Trench 110 may be configured to accommodate a gate stack including a gate dielectric, a gate electrode, and / or other suitable elements.

[0039] In some embodiments, semiconductor element 100a may include a dielectric layer 112. In some embodiments, dielectric layer 112 may be disposed within trench 110. In some embodiments, dielectric layer 112 may be disposed on a sidewall (or side surface) of substrate 102. In some embodiments, dielectric layer 112 may be disposed on a lower surface of substrate 102. In some embodiments, dielectric layer 112 may be in contact with substrate 102. In some embodiments, dielectric layer 112 may be disposed on a sidewall (or side surface) of dielectric layer 106. In some embodiments, dielectric layer 112 may be in contact with dielectric layer 106. In some embodiments, dielectric layer 112 may be disposed on a sidewall (or side surface) of dielectric layer 108. In some embodiments, dielectric layer 112 may be in contact with dielectric layer 108.

[0040] In some embodiments, for example, dielectric layer 112 may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other high-k materials. Examples of high-k materials include a dielectric material having a dielectric constant greater than that of silicon dioxide (SiO2), or a dielectric material with a dielectric constant greater than about 3.9. In some embodiments, dielectric layer 112 may include at least one metal element, such as hafnium oxide (HfO2), silicon-doped hafnium oxide (HSO), lanthanum oxide (La2O3), aluminum lanthanum oxide (LaAlO3), zirconium silicate (ZrSiO4), aluminum oxide (Al2O3), or combinations thereof. In some embodiments, the high-k dielectric material may also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, and combinations thereof.

[0041] In some embodiments, semiconductor device 100a may include a gate electrode 114. In some embodiments, gate electrode 114 may be disposed within trench 110. Gate electrode 114 may be disposed on dielectric layer 112. Gate electrode 114 may be spaced from substrate 102 by dielectric layer 112. Gate electrode 114 may include one or more materials. For example, gate electrode 114 may include a barrier layer and a conductive layer, the conductive layer being spaced from dielectric layer 112 by barrier layer. Barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), or the like. In some exemplary embodiments, conductive layer may include tungsten (W), aluminum (Al), copper (Cu), other suitable materials, or combinations thereof. In some embodiments, gate electrode 114 may include multiple barrier layers and multiple conductive layers, the multiple conductive layers being spaced apart by multiple barrier layers. In some embodiments, gate electrode 114 may be used as a word line structure of a DRAM device. The gate electrode 114 may extend along the Y direction. In some embodiments, a portion of the dielectric layer 112 may be used as a gate dielectric 112b.

[0042] In some embodiments, semiconductor element 100a may include a dielectric structure 116. The dielectric structure 116 may be disposed on dielectric layer 108. A portion of the dielectric structure 116 may be disposed within trench 110. The dielectric structure 116 may cover gate electrode 114. In some embodiments, the dielectric structure 116 may contact the sidewalls of dielectric layer 112. In some embodiments, for example, the dielectric structure 116 may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), other suitable materials, or combinations thereof. In some embodiments, the material of the dielectric structure 116 may be different from the material of dielectric layer 112. For example, the dielectric structure 116 may include silicon nitride (Si3N4) or be made of silicon nitride (Si3N4), and the dielectric layer 112 may include silicon oxide (SiO2) or be made of silicon oxide (SiO2).

[0043] In some embodiments, semiconductor element 100a may include a bit line structure 118. The bit line structure 118 may be disposed on dielectric structure 116. The bit line structure 118 may be disposed above a word line including gate electrode 114. The bit line structure 118 may extend along the X direction. In some embodiments, the bit line structure 118 may include a multilayer structure. For example, the bit line structure 118 may include a conductive layer comprising polysilicon doped with an n-type dopant, such as arsenic (As) or phosphorus (P). The bit line structure 118 may also include titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), other suitable materials, or combinations thereof.

[0044] In some embodiments, semiconductor element 100a may include an isolation layer 120. The isolation layer 120 may be disposed on bit line structure 118. The isolation layer 120 may include silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride, flowable oxide, silicon carbide, undoped silica glass, borosilicate glass, phosphorus silica glass, borosilicate silica glass, plasma-enhanced tetraethyl orthosilicate, fluoride silicate glass, carbon-doped silicon oxide, or combinations thereof. The isolation layer 120 may serve as a hard mask configured to prevent damage to the bit line structure 118 during, for example, the formation of multiple capacitor structures.

[0045] In some embodiments, semiconductor element 100a may include a conductive contact 122. The conductive contact 122 may penetrate dielectric structure 116. The conductive contact 122 may penetrate dielectric layer 108. The conductive contact 122 may penetrate dielectric layer 106. The conductive contact 122 may be configured to electrically connect an active region (e.g., a doped region within substrate 102) and bit line structure 118. For example, the conductive contact 122 may include tungsten (W), cobalt (Co), zirconium (Zr), tantalum (Ta), titanium (Ti), aluminum (Al), ruthenium (Ru), copper (Cu), metal carbides (e.g., tantalum carbide (TaC), titanium carbide (TiC), magnesium tantalum carbide (TaMaC)), metal nitrides (e.g., titanium nitride (TiN)), transition metal aluminum nitrides, or combinations thereof.

[0046] In some embodiments, semiconductor element 100a may include a conductive contact 124. The conductive contact 124 may penetrate the isolation layer 120. The conductive contact 124 may penetrate the dielectric structure 116. The conductive contact 124 may penetrate the dielectric layer 108. The conductive contact 124 may penetrate the dielectric layer 106. The conductive contact 124 may be configured to electrically connect an active region (e.g., a doped region within substrate 102) and a capacitor structure (e.g., capacitor structure 126). For example, the conductive contact 124 may include tungsten (W), cobalt (Co), zirconium (Zr), tantalum (Ta), titanium (Ti), aluminum (Al), ruthenium (Ru), copper (Cu), metal carbides (e.g., tantalum carbide (TaC), titanium carbide (TiC), magnesium tantalum carbide (TaMaC)), metal nitrides (e.g., titanium nitride (TiN)), transition metal aluminum nitrides, or combinations thereof. It should be understood that the conductive contact 124 has a distance along the Y direction from the bit line structure 118.

[0047] In some embodiments, semiconductor element 100a may include a capacitor structure 126. The capacitor structure 126 may be disposed on isolation layer 120. The capacitor structure 126 may be disposed above bit line structure 118. The capacitor structure 126 may be electrically connected to an active region (e.g., a doped region within substrate 102) via conductive contacts 124. The capacitor structure 126 may include a capacitor electrode 126a, a capacitor dielectric 126b, and a capacitor electrode 126c.

[0048] A capacitor electrode 126a may be disposed on a conductive contact 124. The capacitor electrode 126a may be electrically connected to the conductive contact 124. The capacitor electrode 126a may serve as a lower electrode of the capacitor structure 126. In some embodiments, the capacitor electrode 126a may have multiple vertical portions connected by multiple horizontal portions to increase the capacitance of the capacitor structure 126. In some embodiments, the capacitor electrode 126a may include tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof.

[0049] The capacitor dielectric 126b can be disposed between the capacitor electrode 126a and the capacitor electrode 126c. The capacitor dielectric 126b can be conformally disposed on the capacitor electrode 126a. The capacitor dielectric 126b can include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon oxynitride (N2OSi2), or other suitable materials.

[0050] Capacitor electrode 126c may be disposed on capacitor dielectric 126b. Capacitor electrode 126c may serve as an upper electrode of capacitor structure 126. In some embodiments, capacitor electrode 126c may include tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof.

[0051] Although not shown in the figures, it should be understood that semiconductor element 100a may also include other components. For example, semiconductor element 100a may include a spacer surrounding conductive contact 122 and / or conductive contact 124. The spacer may include multiple dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high-k materials, or combinations thereof. The spacer may also include an air gap between these dielectric layers. A landing pad may cover the air gap. The landing pad may be electrically connected to capacitor structure 126. The landing pad may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof.

[0052] Please refer to Figure 1B, which is a partial enlarged view of region R of the semiconductor element shown in Figure 1A.

[0053] In some embodiments, dielectric layer 112 may include a portion 112p1 (or a lower portion) and a portion 112p2 (or an upper portion), with portion 112p2 (or the upper portion) above portion 112p1. At least a portion of portion 112p1 of dielectric layer 112 is disposed on substrate 102, and the remaining portion of portion 112p1 is disposed embedded within substrate 102. Portion 112p2 of dielectric layer 112 is disposed on substrate 102. Portions 112p1 and 112p2 may have different dimensions (e.g., thickness or length along the X direction). For example, portion 112p1 may have a thickness T1, and portion 112p2 may have a thickness T2, where thickness T2 is less than thickness T1. In some embodiments, the ratio of thickness T1 to thickness T2 may be in the range of about 0.2 to about 0.8, for example, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, or 0.8. When the ratio of thickness T1 to thickness T2 is in the range of 0.2 to 0.8, the opening defined by dielectric layer 112 can have a relatively suitable aspect ratio, which is beneficial to the formation of gate electrode 114, which will be described in detail later.

[0054] In some embodiments, portions 112p1 and 112p2 of dielectric layer 112 may define a stepped structure 112t. In some embodiments, the stepped structure 112t may be located above the gate electrode 114. The stepped structure 112t may define an opening with a different aspect ratio. In some embodiments, the stepped structure 112t may overlap along dielectric layer 108.

[0055] In some embodiments, a gate electrode 114 may be disposed on a sidewall of a portion 112p1 of the dielectric layer 112. In some embodiments, the gate electrode 114 may contact a portion 112p1 of the dielectric layer 112. In some embodiments, a surface 112s1 (or an upper surface) of a portion 112p1 of the dielectric layer 112 may be located at a bit plane, which is higher than a surface 102s1 (or an upper surface) of the substrate 102. In some embodiments, a portion 112p1 of the dielectric layer 112 may contact or overlap with a sidewall of the substrate 102 along the X direction. In some embodiments, a portion 112p1 of the dielectric layer 112 may contact or overlap with a sidewall of the dielectric layer 106 along the X direction. In some embodiments, a portion 112p1 of the dielectric layer 112 may contact or overlap with a portion of a sidewall of the dielectric layer 108 along the X direction.

[0056] Part 112p2 is connected to and located directly above part 112p1. A surface 112s2 (or an upper surface) of part 112p2 may be located at a terminating plane that is higher than surface 112s1 of dielectric layer 112. In some embodiments, surface 112s2 of dielectric layer 112 may be located at a terminating plane that is higher than surface 102s1 of substrate 102. In some embodiments, surface 112s1 may be exposed by part 112p2. In some embodiments, surface 112s2 of dielectric layer 112 may be located at a terminating plane that is substantially the same as the upper surface (not labeled) of dielectric layer 108 (or isolation structure). In some embodiments, a length of part 112p2 along the Z direction may be less than a length of part 112p1 along the Z direction. In some embodiments, part 112p2 of dielectric layer 112 may contact or overlap a portion of the sidewall of dielectric layer 108 along the X direction. In some embodiments, a portion 112p2 of the dielectric layer 112 may be spaced apart from the gate electrode 114.

[0057] In some embodiments, the dielectric structure 116 within the trench 110 may have a T-shaped profile. In some embodiments, the dielectric structure 116 may have a stepped profile corresponding to the stepped structure 112t of the dielectric layer 112. In some embodiments, the dielectric structure 116 may have a portion 116p1 and a portion 116p2, with portion 116p2 above portion 116p1. Portion 116p1 may be located above the gate electrode 114. Portion 116p2 may be located above portion 116p1. Portion 116p1 of the dielectric structure 116 may contact portion 112p1 of the dielectric layer 112. Portion 116p2 of the dielectric structure 116 may contact portion 112p2 of the dielectric layer 112. In some embodiments, portion 116p1 may overlap with the substrate 102 along the X direction. In some embodiments, portion 116p1 may overlap with the dielectric layer 106 along the X direction. In some embodiments, portion 116p1 may overlap with a portion of the dielectric layer 108 along the X direction. In some embodiments, portion 116p2 may overlap with a portion of dielectric layer 108 along the X direction. Portion 116p1 of dielectric structure 116 may have a width (or aperture) W1 along the X direction. Portion 116p2 of dielectric structure 116 may have a width (or aperture) W2 along the X direction. In some embodiments, width W2 may be greater than width W1. In some embodiments, the ratio of width W2 to width W1 may be in the range of approximately 1.1 to approximately 1.5, for example, 1.1, 1.2, 1.3, 1.4, or 1.5. In some embodiments, the ratio of the width (or aperture) defined by portion 112p2 to the width (or aperture) defined by portion 112p1 may be approximately 1.1 to approximately 1.5, for example, 1.1, 1.2, 1.3, 1.4, or 1.5, thereby facilitating the formation of material for depositing gate electrode 114.

[0058] Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor element 100b according to some embodiments of the present disclosure. Semiconductor element 100b is similar to semiconductor element 100a, with the following differences.

[0059] In some embodiments, a surface 114s1 (or upper surface) of the gate electrode 114 may be located at a plane that is substantially the same as the surface 102s1 of the substrate 102. In some embodiments, a portion 116p1 of the dielectric structure 116 may not overlap with the substrate 102 along the X direction. In some embodiments, the lower surface of the dielectric structure 116 may be located at a plane that is substantially the same as the surface 102s1 of the substrate 102.

[0060] Figure 3 is a cross-sectional schematic diagram illustrating a semiconductor element 100c according to some embodiments of the present disclosure. Semiconductor element 100c is similar to semiconductor element 100a, with the following differences.

[0061] In some embodiments, the surface 114s1 of the gate electrode 114 may be substantially aligned with or coplanar with the surface 112s1 of the dielectric layer 112. In some embodiments, the surface 102s1 of the substrate 102 may be located at a bit plane that is higher than the surface 112s1 of the dielectric layer 112. In some embodiments, a portion 112p2 of the dielectric layer 112 may overlap with the dielectric layer 106 along the X direction. In some embodiments, a portion 112p2 of the dielectric layer 112 may overlap with the substrate 102 along the X direction.

[0062] Figure 4 is a cross-sectional schematic diagram illustrating a semiconductor element 100d according to some embodiments of the present disclosure. Semiconductor element 100d is similar to semiconductor element 100a, with the following differences.

[0063] In some embodiments, the surface 112s1 of the dielectric layer 112 may be located at a plane that is substantially the same as the surface 102s1 of the substrate 102. In some embodiments, the dielectric structure 116 within the trench 110 may have a substantially uniform width (or aperture) along the X direction. In some embodiments, the dielectric structure 116 may not overlap with a portion 112p1 of the dielectric layer 112.

[0064] Figures 5A to 5J are schematic diagrams illustrating multiple stages of an exemplary method for manufacturing semiconductor devices according to some embodiments of this disclosure.

[0065] Referring to Figure 5A, a substrate 102 may be provided. An electrically isolated region 104 may be formed within the substrate 102. A dielectric layer 106 may be formed on the electrically isolated region 104. A dielectric layer 108 may be formed on the dielectric layer 106. In some embodiments, an etching process may be performed to remove a portion of the substrate 102 to form a recess, and a dielectric material may be deposited within the recess to form the electrically isolated region 104. For example, the dielectric material deposition technique may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0066] The fabrication techniques for dielectric layers 106 and 108 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0067] Referring to Figure 5B, a trench 110 can be formed. In some embodiments, an etching technique can be performed to remove a portion of the substrate 102, dielectric layer 106, and dielectric layer 108. The etching technique may include wet etching, dry etching, or other suitable techniques.

[0068] Referring to Figure 5C, a dielectric material layer 112a can be formed to cover the upper surface of the dielectric layer 108 and the side surfaces of the substrate 102, dielectric layer 106, and dielectric layer 108. A portion of the dielectric material layer 112a may be located within the trench 110. The fabrication techniques for the dielectric material layer 112a may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0069] Referring to Figure 5D, a filler material 128 may be formed within the trench 110. The filler material 128 may include a photosensitive material, such as photoresist or other suitable material. The filler material 128 may cover a portion of the dielectric material layer 112a. In some embodiments, the fabrication technique of the filler material 128 may include coating or other suitable techniques. In some embodiments, the filler material 128 may be formed over the dielectric layer 108 and fill the trench 110, and a portion of the filler material 128 may be removed by an etching technique, such that the remaining portion of the upper surface of the filler material 128 is below the upper surface of the dielectric layer 108. In some embodiments, the upper surface of the filler material 128 may be above the surface 102s1 of the substrate 102. In some embodiments, the upper surface of the filler material 128 may be above the upper surface of the dielectric layer 106.

[0070] Referring to Figure 5E, an etching technique P1 can be performed. As a result, a portion of the dielectric material layer 112a can be removed to define the dielectric layer 112. Portions 112p1 and 112p2 can be formed. A portion of the dielectric material layer 112a above the filler material 128 can be partially removed, such that portions 112p1 and 112p2 can have different thicknesses or lengths along the X direction. The etching technique P1 can include wet etching, dry etching, or other suitable techniques.

[0071] Referring to Figure 5F, filler material 128 can be removed. Dielectric layer 112 can define an opening 130. Opening 130 can have a portion 130t1 and a portion 130t2, with portion 130t2 above portion 130t1. The portion 130t2 of opening 130 has a larger aperture, defined by portion 112p2 of dielectric layer 112. The portion 130t1 of opening 130 has a smaller aperture, defined by portion 112p1 of dielectric layer 112. In some embodiments, the ratio of the aperture of portion 130t2 to portion 130t1 can be in the range of about 1.1 to about 1.5, for example, 1.1, 1.2, 1.3, 1.4, or 1.5.

[0072] Referring to Figure 5G, a conductive material 114' can be formed. At this stage, the larger aperture of the portion 130t2 of the opening 130 facilitates the filling of the conductive material 114', allowing the conductive material 114' to fill the bottom of the opening 130 with fewer or no voids. The fabrication techniques for the conductive material 114' can include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0073] Referring to Figure 5H, a portion of the conductive material 114' can be removed to create a gate electrode 114. Portions 112p1 and 112p2 of the dielectric layer 112 can be exposed via the gate electrode 114. In some embodiments, the surface 114s1 of the gate electrode 114 may be lower than the surface 102s1 of the substrate 102. In other embodiments, the surface 114s1 of the gate electrode 114 may be substantially aligned with the surface 102s1 of the substrate 102 along the X direction. In other embodiments, additional conductive material (not shown) may be formed above the gate electrode 114, and the upper surface of the additional conductive material may be substantially aligned with the surface 102s1 of the substrate 102 along the X direction. The conductive material 114' can be removed by an etching technique, such as dry etching, wet etching, or other suitable techniques.

[0074] Referring to Figure 5I, a dielectric structure 116 can be formed. The dielectric structure 116 can fill the trench 110 or the opening 130. The dielectric structure 116 can cover the dielectric layer 108. The fabrication techniques for the dielectric structure 116 can include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable processes.

[0075] Referring to Figure 5J, a bitline structure 118 can be formed over a dielectric structure 116. An isolation layer 120 can be formed over the bitline structure 118. A conductive contact 122 can be formed between the substrate 102 and the bitline structure 118. A conductive contact 124 can be formed to penetrate the dielectric structure 116 and the isolation layer 120. A capacitor structure 126, including capacitor electrodes 126a, capacitor dielectric 126b, and capacitor electrodes 126c, can be formed over the isolation layer 120 and electrically connected to the conductive contact 124. As a result, a semiconductor device (e.g., semiconductor device 100a as shown in Figure 1A) can be manufactured.

[0076] Figure 6 is a flowchart illustrating a method 200 for fabricating semiconductor elements according to some embodiments of this disclosure.

[0077] Preparation method 200 begins at step 202, in which a substrate is provided. An isolation structure is formed on the substrate. Figure 5A illustrates the stage corresponding to step 202.

[0078] Preparation method 200 continues to step 204, in which the isolation structure and a portion of the substrate are removed, thereby forming a trench. Figure 5B illustrates the stage corresponding to step 204.

[0079] Preparation method 200 continues to step 206, in which a dielectric layer is formed within the trench. Figure 5C illustrates the stage corresponding to step 206.

[0080] Preparation method 200 continues to step 208, in which a filler material is formed in the trench. Figure 5D illustrates the stage corresponding to step 208.

[0081] Preparation method 200 continues to step 210, performing an etching technique to remove an upper portion of the dielectric layer exposed by the filler material, such that the lower portion of the dielectric layer has a larger thickness, while the upper portion of the dielectric layer has a smaller thickness. Figure 5E illustrates the stage corresponding to step 210.

[0082] Preparation method 200 continues to step 212, in which the filler material is removed. An opening defined by the dielectric layer has a larger aperture at the upper part and a smaller aperture at the lower part. Figure 5F illustrates the stage corresponding to step 212.

[0083] Preparation method 200 continues to step 214, in which a conductive material is filled into the opening defined by the dielectric layer. Figure 5G illustrates the stage corresponding to step 214.

[0084] Preparation method 200 continues to step 216, in which a portion of the conductive material is removed to form a gate electrode (or a word line) within the opening defined by the dielectric layer. Figure 5H illustrates the stage corresponding to step 216.

[0085] Preparation method 200 continues to step 218, in which a dielectric structure, a bit line, and a capacitor structure are formed. As a result, a semiconductor device is fabricated. Figures 5I and 5J illustrate the stage corresponding to step 218.

[0086] Preparation method 200 is merely an example and is not intended to limit this disclosure to the content expressly described in the claims. Additional steps may be provided before, during, or after each step of preparation method 200, and some of the described steps may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 200 may include other steps not depicted in FIG. 6. In some embodiments, preparation method 200 may include one or more steps depicted in FIG. 6.

[0087] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a dielectric layer, and a gate electrode. The dielectric layer is at least partially embedded in the substrate. The dielectric layer has a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness less than the first thickness. The gate electrode is spaced apart from the substrate by the first portion of the dielectric layer.

[0088] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a gate dielectric, a gate electrode, and a dielectric structure. The gate dielectric is embedded within the substrate. The gate electrode is spaced apart from the substrate by the gate dielectric. The dielectric structure is disposed above the gate electrode. The dielectric structure includes a stepped profile.

[0089] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a trench. The method also includes forming a dielectric layer having a first thickness within the trench. The method further includes removing an upper portion of the dielectric layer, such that the upper portion of the dielectric layer has a second thickness, the second thickness being smaller than the first thickness of a lower portion of the dielectric layer. Additionally, the method includes forming a gate electrode within the trench.

[0090] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0091] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0092] 100a: Semiconductor components

[0093] 100b: Semiconductor components

[0094] 100c: Semiconductor components

[0095] 100d: Semiconductor element

[0096] 102: Base

[0097] 102s1: Surface

[0098] 104: Electrically isolated zone

[0099] 106: Dielectric layer

[0100] 108: Dielectric layer

[0101] 110: Trench

[0102] 112: Dielectric layer

[0103] 112a: Dielectric material layer

[0104] 112b: Gate dielectric

[0105] 112p1: Part

[0106] 112p2: Part

[0107] 112s1: Surface

[0108] 112s2: Surface

[0109] 112t: Stepped structure

[0110] 114: Gate electrode

[0111] 114': Conductive material

[0112] 114s1: Surface

[0113] 116: Dielectric Structure

[0114] 116p1: Part

[0115] 116p2: Part

[0116] 118: Bitline Structure

[0117] 120: Isolation layer

[0118] 122: Conductive contact

[0119] 124: Conductive Contact

[0120] 126: Capacitor Structure

[0121] 126a: Capacitor electrode

[0122] 126b: Capacitor dielectric

[0123] 126c: Capacitor electrode

[0124] 128: Filling material

[0125] 130: Opening

[0126] 130t1: Partial

[0127] 130t2: Partial

[0128] 200: Preparation method

[0129] 202: Steps

[0130] 204: Steps

[0131] 206: Steps

[0132] 208: Steps

[0133] 210: Steps

[0134] 212: Steps

[0135] 214: Steps

[0136] 216: Steps

[0137] 218: Steps

[0138] P1: Etching technology

[0139] R: Region

[0140] T1: Thickness

[0141] T2: Thickness

[0142] W1: Width

[0143] W2: Width

[0144] X: Direction

[0145] Y: direction

[0146] Z: Direction

Claims

1. A semiconductor device, comprising: One base; A dielectric layer, at least partially embedded in the substrate, wherein the dielectric layer has a first portion and a second portion, the first portion having a first thickness and the second portion having a second thickness less than the first thickness; an isolation structure disposed on the substrate, wherein the isolation structure and the substrate together define a trench to accommodate the dielectric layer; and a gate electrode spaced from the substrate by the first portion of the dielectric layer, wherein at least a portion of the first portion of the dielectric layer is disposed on the substrate, and the second portion of the dielectric layer is disposed on the substrate, the at least a portion of the first portion and the second portion of the dielectric layer contact a side surface of the isolation structure and extend along a direction substantially perpendicular to an upper surface of the substrate, wherein the isolation structure has a first dielectric layer and a second dielectric layer, the second portion of the dielectric layer is disposed on a side surface of the second dielectric layer of the isolation structure, and the first portion of the dielectric layer is disposed on a side surface of the first dielectric layer and the side surface of the second dielectric layer of the isolation structure.

2. The semiconductor device as claimed in claim 1, wherein the ratio of the second thickness to the first thickness is in the range of about 0.2 to about 0.

8.

3. The semiconductor device as claimed in claim 1, wherein an upper surface of the first portion of the dielectric layer is higher than an upper surface of the gate electrode.

4. The semiconductor device as described in claim 1 further includes: A bit line structure is disposed above the substrate, wherein the gate electrode extends along a first direction and the bit line structure extends along a second direction, which is different from the first direction.

5. A semiconductor element, comprising: One base; An isolation structure is disposed on the substrate, wherein the isolation structure and the substrate together define a trench; A gate dielectric embedded in the substrate; a dielectric layer disposed in the trench of the substrate, wherein a portion of the dielectric is embedded in the substrate, wherein the portion functions as a gate dielectric; a gate electrode spaced apart from the substrate by the gate dielectric; and a dielectric structure disposed above the gate electrode, wherein the dielectric structure includes a stepped profile, wherein the dielectric layer further comprises a first portion and a second portion, the first portion having a first thickness, the second portion having a second thickness different from the first thickness, wherein at least a portion of the first portion of the dielectric layer is disposed on the substrate, and the second portion of the dielectric layer is disposed on the substrate, and wherein the at least a portion of the first portion and the second portion of the dielectric layer contact one side surface of the isolation structure and extend along a direction substantially perpendicular to an upper surface of the substrate, wherein the dielectric structure contacts the first portion and the second portion of the dielectric layer.

6. The semiconductor element as claimed in claim 5, wherein the dielectric structure has a first width and a second width, the second width being different from the first width.

7. The semiconductor element as claimed in claim 6, wherein the dielectric structure has a T-shaped profile.

8. The semiconductor element as claimed in claim 6, wherein the ratio of the first width to the second width is in the range of about 1.1 to about 1.5.

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