Planarization method of wafer

Abstract

The embodiments disclosed herein provide a wafer planarization method, which includes the following steps: A wafer having a semiconductor structure on its front surface is provided. A protective layer is formed on the semiconductor structure. A pattern mask is formed on the back surface of the wafer, such that a first portion of the back surface is covered, and a second and third portion of the back surface is exposed, and the pattern mask has a symmetrical shape. The second and third portions are etched to form a symmetrical pattern on the back side of the wafer. A planarization process is performed to remove the protective layer located on the front surface of the wafer.

Description

Technical Field

[0001] This disclosure relates to a wafer planarization method, and more particularly to a wafer planarization method that can improve flatness. Prior Technology

[0002] The manufacturing process of semiconductor wafers involves many steps. These include forming layers (e.g., insulating and conductive layers), performing photolithography, etching the layers, and removing the layers. These steps are repeated to form various functional layers on the semiconductor wafer.

[0003] However, the incomplete planarization of each layer results in a rough surface on the semiconductor wafer during the stacking process. Furthermore, repeating the process on the incompletely planarized multilayers affects the quality of the semiconductor wafer. Summary of the Invention

[0004] The embodiments disclosed herein provide a wafer planarization method, comprising the following steps: A wafer is provided, and the front surface of the wafer has a semiconductor structure. A protective layer is formed on the semiconductor structure. A pattern mask is formed on the back surface of the wafer, such that a first portion of the back surface is covered, and a second and third portion of the back surface is exposed, wherein the pattern mask has a symmetrical shape. The second and third portions are etched to form a symmetrical pattern on the back side of the wafer. A planarization process is performed to remove the protective layer located on the front surface of the wafer, and the planarization process includes: mounting the wafer on a polishing apparatus having a polishing pad by adhering to the symmetrical pattern on the back side of the wafer, and removing the protective layer on the semiconductor structure.

[0005] In some embodiments, performing a planarization process includes the following steps: After removing the protective layer, the wafer is mounted on a polishing apparatus with a polishing pad through the surface of the adsorbed semiconductor structure. The back side of the wafer is planarized.

[0006] In some embodiments, performing a planarization process includes the following steps: pressing the wafer against the surface of a polishing pad and rotating the wafer; and providing polishing slurry on the surface of the polishing pad.

[0007] In some embodiments, the second and third portions of the wafer are etched via a wet etching process.

[0008] In some embodiments, the wet etching process includes placing a wafer including a pattern mask into an etching tank containing an etchant to remove the second and third portions through the wet etching process.

[0009] In some embodiments, the etchant is HNO3(aq), H2SO4(aq), HF(aq), or a combination thereof.

[0010] In some embodiments, the protective layer formed on the semiconductor structure is resistant to the etchant.

[0011] In some embodiments, after the planarization process, the symmetrical patterns and recesses formed on the wafer by etching will be coplanar.

[0012] In some embodiments, the pattern mask has a hollow and symmetrical pattern.

[0013] In some embodiments, the outer distance between the outer edge of the symmetrical pattern and the outer edge of the wafer may be the same or different.

[0014] In some embodiments, the second portion is the portion extending from the edge of the wafer to the outer edge of the pattern mask, while the third portion is the exposed portion near the center of the wafer.

[0015] The embodiments disclosed herein provide a wafer planarization method, comprising the following steps: A wafer is provided, and the front surface of the wafer has a semiconductor structure. An oxide layer is formed on the semiconductor structure. A pattern mask is formed on the back surface of the wafer to cover a portion of the back surface and expose an outwardly exposed portion and an inwardly exposed portion of the back surface, and the pattern mask has a symmetrical shape. The outwardly exposed portion and the inwardly exposed portion are etched to form a symmetrical pattern on the back side of the wafer. A planarization process is performed to remove the oxide layer on the front surface of the wafer and the symmetrical pattern on the back side of the wafer, and the planarization process includes the following steps: The wafer is placed in a wafer holding hole of a polishing apparatus. The wafer is clamped by a lower holder and an upper holder, wherein the lower holder includes a lower polishing pad located on the upper surface of the lower holder, and the upper holder includes an upper polishing pad located on the upper surface of the upper holder. The upper holder and the lower holder are rotated to remove the oxide layer on the front surface of the wafer and the symmetrical pattern on the back side of the wafer.

[0016] In some embodiments, the outward and inward exposed portions of the wafer are etched using a wet etching process.

[0017] In some embodiments, the wet etching process includes placing a wafer, including a patterned mask, into an etching tank containing an etchant.

[0018] In some embodiments, the etching rate of a wet etching process is controlled by adjusting the bubble position, bubble flow rate, rotational acceleration, temperature of the etching tank, acid content in the etchant, pressure of the wet etching process, or a combination thereof.

[0019] In some embodiments, the oxide layer formed on the semiconductor structure is resistant to etchants to protect the semiconductor structure and wafer from damage caused by etching.

[0020] In some embodiments, the surface of the oxide layer contacts the surface of the upper abrasive pad, and the symmetrical pattern contacts the surface of the lower abrasive pad.

[0021] In some embodiments, the surface of the oxide layer contacts the surface of the lower polishing pad, and the symmetrical pattern contacts the surface of the upper polishing pad.

[0022] In some embodiments, during the planarization process, polishing slurry is applied to the surface of the lower polishing pad and the surface of the upper polishing pad.

[0023] In some embodiments, the outer distance between the outer edge of the symmetrical pattern and the outer edge of the wafer may be the same or different. Simple Explanation of the Diagram

[0024] The following embodiments are read in conjunction with the accompanying drawings for a clear understanding of the viewpoints disclosed herein. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity in discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Figures 1 through 4B are views of a wafer planarization method in various steps according to some embodiments of the present disclosure; Figures 5 and 6 are views of a wafer planarization method according to some embodiments of the present disclosure, with respect to one of the planarization methods; Figures 7 and 8 are views of another planarization process of a wafer planarization method according to some embodiments of the present disclosure; and Figure 9 is a comparison diagram of wafer warpage without planarization and wafer warpage with planarization in some embodiments according to this disclosure. Implementation

[0025] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0026] Furthermore, for ease of description, spatially related terms such as "above," "over," "below," and "between" may be used in this disclosure to describe the relationship or function of one element or feature to another, as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used in this disclosure can be interpreted accordingly.

[0027] The terms "including," "having," and "containing" used in this disclosure are open-ended terms, meaning including but not limited to.

[0028] It should be noted that when the following figures (e.g., Figures 1 to 8) are illustrated and described as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than those in this disclosure, or some operations or steps may occur simultaneously, or some operations may be omitted, and / or some operations or steps may be repeated. Furthermore, actual operations or steps in the process stage may involve additional operations or steps performed before, during, or after wafer planarization. Therefore, this disclosure may only briefly describe a portion of these additional operations or steps. Moreover, unless otherwise stated, the same interpretations discussed for the following figures (e.g., Figures 1 to 8) can be directly applied to the other figures.

[0029] Please refer to Figure 1, which is a cross-sectional view of a wafer planarization method according to some embodiments of the present disclosure regarding the formation of a protective layer 110 over a wafer 102. A wafer (also referred to as a substrate) 102 is provided, and a semiconductor structure 104 is formed on the front surface 102F of the wafer 102. The semiconductor structure 104 refers to any structure that can be formed on the wafer 102, such as a structure after forming active and isolation regions, a structure after forming word line structures, or a structure after forming contact pads, etc. In some embodiments, the wafer 102 is, for example, a silicon wafer, a gallium nitride wafer, or a silicon carbide wafer. The protective layer 110 is then formed on the semiconductor structure 104. In some embodiments, the protective layer 110 is formed through a coating process. In some embodiments, the material of the protective layer 110 is an oxide. The protective layer 110 is configured to prevent the semiconductor structure 104 and the front surface 102F of the wafer 102 from being etched during subsequent etching processes.

[0030] Next, referring to Figures 2A to 2E, which are top views of a planarization method of wafer 102 during the formation of a pattern mask 120 on protective layer 110 according to some embodiments of the present disclosure. A pattern mask (collectively referred to as pattern mask 120), such as pattern mask 120A, pattern mask 120B, pattern mask 120C, pattern mask 120D, or pattern mask 120E, is formed on the back surface 102B of wafer 102. As shown in Figures 2A to 2E, the pattern mask 120 is a symmetrical shape, such as a circle, rectangle, star, or regular polygon.

[0031] In some embodiments, the pattern mask 120 has a hollow and symmetrical pattern. After the pattern mask 120 is formed, a first portion 122A of the back surface 102B of the wafer 102 is covered by the pattern mask 120, and a second portion 122B and a third portion 122C of the back surface 102B of the wafer 102 are exposed. Specifically, the second portion 122B of the back surface 102B of the wafer 102 refers to the portion extending from the edge of the wafer 102 to the outer edge of the pattern mask 120, while the third portion 122C of the back surface 102B of the wafer 102 refers to the exposed portion near the center CR of the wafer 102. In other words, based on the position of the pattern mask 120 on the back surface 102B of the wafer 102, the outwardly exposed portion of the pattern mask 120 is the second portion 122B, and the inwardly exposed portion is the third portion 122C.

[0032] In Figures 2A to 2E, the width between the outer edge of the first portion 122A of wafer 102 and the outer edge of the pattern mask 120 may be the same or different. In embodiments where the outer edge of the first portion 122A of wafer 102 and the outer edge of the pattern mask 120 have different widths, the first width (e.g., the first width W1 in Figure 2B) from the first outer edge OS1 of the pattern mask 120 furthest from the center CR of wafer 102 to the edge of wafer 102 closest to the first outer edge OS1 is the smallest, while the second width (e.g., the second width W2 in Figure 2B) from the second outer edge OS2 of the pattern mask 120 to the edge of wafer 102 closest to the second outer edge OS2 is the largest.

[0033] Further, as shown in Figures 2A to 2E, the width between the inner edge of the pattern mask 120 and the center CR of the wafer 102 may be the same or different. In some embodiments, when the four edges (two inner edges and two outer edges) of the pattern mask 120 are located on an imaginary line passing through the center CR of the wafer 102, the third width (e.g., the third width W3 in Figure 2B) from the first inner edge IS1 furthest from the center CR of the wafer 102 to the center CR of the wafer 102 is greater than the fourth width (e.g., the fourth width W4 in Figure 2B) from the second inner edge IS2 closest to the center CR of the wafer 102 to the center CR of the wafer 102.

[0034] Next, please refer to Figure 3, which is a schematic diagram of a planarization method for a wafer 102 according to some embodiments of the present disclosure during etching of the wafer 102 including a pattern mask 120. After forming the pattern mask 120, a photolithography process is performed on the back surface 102B of the wafer 102. Then, the wafer 102 with the pattern mask 120 is etched to form a symmetrical pattern (e.g., symmetrical pattern 130A or 130B, collectively referred to as a symmetrical pattern) on the back side of the wafer 102. Specifically, the first portion covered by the pattern mask 120 (such as the first portion 122A shown in Figures 2A to 2E) is retained without being etched, while the second and third portions exposed by the pattern mask 120 (such as the second portion 122B and the third portion 122C shown in Figures 2A to 2E) are etched. In some embodiments, the wafer 102 with the pattern mask 120 is etched by a wet etching process. In these embodiments, a wafer 102 with a patterned mask 120 is placed in an etching tank 410 containing an etchant 412. In some embodiments, the etchant 412 includes HNO3(aq), H2SO4(aq), HF(aq), or a combination thereof. In some embodiments, the etching rate of the wet etching process is controlled by adjusting etching conditions, such as bubble position, bubble flow rate, rotational acceleration, temperature of the etching tank 410, acid content, and process pressure. The patterned mask 120 is removed after the etching process. Notably, a protective layer 110 formed on the semiconductor structure 104 resists the etchant 412 to protect the semiconductor structure 104 and the wafer 102 from damage due to etching.

[0035] Please refer to Figures 4A and 4B. Figure 4A is a cross-sectional view of the etched wafer 102 based on the cross-sectional line AA' in Figure 2A, according to some embodiments of the present disclosure. Figure 4B is a cross-sectional view of the etched wafer 102 based on the cross-sectional line BB' in Figure 2A, according to the planarization method of the wafer 102 based on some embodiments of the present disclosure. After etching the back side of the wafer 102, a symmetrical pattern 130 is formed on the back side of the wafer 102. Specifically, the second portion 122B and the third portion 122C on the back surface 102B of the wafer 102 are removed to form an outer recess 140 and an inner recess 142, respectively.

[0036] Based on pattern masks (e.g., pattern masks 120A, 120B, 120C, 120D, or 120E), the outer edges of symmetrical patterns 130 may have the same or different external distances to the edge of wafer 102. For example, as shown in Figure 4A, since pattern mask 120A (as shown in Figure 2A) is circular, all external distances OD in the outer recess 140 are the same. As another example, as shown in Figure 4B, since pattern mask 120B (as shown in Figure 2B) is a regular polygon, the external distances between the outer edges of symmetrical patterns 130B and the edge of wafer 102 are different. Furthermore, the external distance OD1 between the outer edge of the symmetrical pattern 130B furthest from the center CR of wafer 102 and the edge of wafer 102 is smaller than the external distance OD2 between the outer edge of the symmetrical pattern 130B closest to the center CR of wafer 102 and the edge of wafer 102.

[0037] Similarly, the internal distances between the inner sides of the symmetrical pattern 130 and the center CR of the wafer 102 may be the same or different. For example, as shown in Figure 4A, since the pattern mask 120A (as shown in Figure 2B) is circular, the internal distance ID between the inner sides of the symmetrical pattern 130A and the center CR of the wafer 102 is the same. As another example, as shown in Figure 4B, since the pattern mask 120B (as shown in Figure 2B) is a regular polygon, the internal distances between the inner sides of the symmetrical pattern 130 and the center CR of the wafer 102 are different. Furthermore, the internal distance ID1 between the inner side of the symmetrical pattern 130 furthest from the center CR of the wafer 102 and the edge of the wafer 102 is greater than the internal distance ID2 between the inner side of the symmetrical pattern 130 closest to the center CR of the wafer 102 and the edge of the wafer 102.

[0038] Please refer to Figures 5 and 6. Figures 5 and 6 are schematic diagrams of the planarization process during a planarization method for wafer 102 according to some embodiments of this disclosure. In these steps, the protective layer 110 and the symmetrical pattern 130 are removed through the planarization process. In some embodiments, the planarization process is a single-sided planarization process or a double-sided planarization process.

[0039] In Figure 6, a planarization process (e.g., chemical mechanical planarization, CMP) is performed through a polishing apparatus 500 to remove the protective layer 110 on the wafer 102. The polishing apparatus 500 includes a support plate 502, a polishing pad 510 on the support plate 502, a wafer holder 520, a wafer chuck 522 in the wafer holder 520, a polishing slurry nozzle 530, and polishing slurry 532 in the polishing slurry nozzle 530.

[0040] Specifically, the wafer chuck 522 picks up the symmetrical pattern 130 on the back of the wafer 102 and mounts the wafer 102 onto the wafer holder 520. Next, the wafer holder 520, holding the wafer 102, rotates with downward pressure, causing the protective layer 110 to press against the surface of the polishing pad 510, and the support plate 502 also rotates. Furthermore, during the planarization process, a polishing slurry 532 containing reactive chemicals is supplied to the surface of the polishing pad 510. This causes the polishing slurry 532 to react with the surface of the protective layer 110, thereby removing the protective layer 110 from the wafer 102 through a combination of mechanical and chemical mechanisms.

[0041] Then, in Figure 6, after removing the protective layer 110, the symmetrical pattern 130 on the back side of wafer 102 is removed by a planarization process (e.g., chemical mechanical planarization). Wafer 102 is mounted on wafer datum 520 by holding the surface of the semiconductor structure 104 on wafer 102 with wafer chuck 522. Subsequently, the symmetrical pattern 130 on the back side of wafer 102 is removed by pressing down and rotating wafer 102 to bring it against the surface of polishing pad 510 with polishing slurry 532. The portion of wafer 102 that originally contained the symmetrical pattern 130 (e.g., the first portion 122A of wafer 102 in Figures 2A to 2E) is planarized, such that the outer recess 140 and the inner recess 142 (as in Figures 4A or 4B) are coplanar after polishing. In other words, after the planarization process, the back side of wafer 102 becomes flat.

[0042] Next, please refer to Figures 7 and 8. Figure 7 is a cross-sectional schematic diagram of a double-sided polishing apparatus 700 for another planarization method of wafer 102 according to some embodiments of the present disclosure, and Figure 8 is a schematic diagram based on block 705 of Figure 7 in another planarization method of wafer 102 according to some embodiments of the present disclosure. A planarization process (e.g., double-sided planarization process) is performed by the double-sided polishing apparatus 700 to remove the protective layer 110 on wafer 102 and the symmetrical pattern 130 on the back side of wafer 102.

[0043] As shown in Figure 7, the double-sided polishing apparatus 700 includes a lower fixing member 710 disposed in a wafer carrier, a lower polishing pad 712 disposed in the wafer carrier and located on the upper surface of the lower fixing member 710, an upper fixing member 720, an upper polishing pad 722 located on the lower surface of the upper fixing member 720, a plurality of wafer holders 730, a wafer holding hole 732 configured to hold the wafer 102 in the wafer holder 730, a lower driving device 744, and an upper driving device 742.

[0044] Specifically, wafer 102 is first placed in wafer holding hole 732. Next, as shown in Figure 8, lower retainer 710 and upper retainer 720 jointly clamp wafer 102. Although Figure 8 shows the surface of protective layer 110 contacting the surface of lower polishing pad 712 and symmetrical pattern 130 contacting the surface of upper polishing pad 722, this disclosure is not limited thereto. In some other embodiments, the surface of protective layer 110 contacts the surface of upper polishing pad 722, while symmetrical pattern 130 contacts the surface of lower polishing pad 712. Then, lower retainer 710 and upper retainer 720 are rotated by lower drive device 744 and upper drive device 742, respectively, thereby rotating the wafer carrier. Simultaneously, through rotation, the protective layer 110 and symmetrical pattern 130 in contact with lower polishing pad 712 and upper polishing pad 722 are polished and planarized.

[0045] Additionally, during the double-sided planarization process, polishing slurry (not shown) is added to the surfaces of the lower polishing pad 712 and the upper polishing pad 722 through polishing slurry nozzles (not shown). In some embodiments, the thickness of the protective layer 110 removed, the thickness of the symmetrical pattern 130 on the back side of the wafer 102 removed, the planarity and flatness, or a combination thereof, are controlled by adjusting the temperature of the wafer carrier, the flow rate of the polishing slurry, the formulation content of the polishing slurry, the reaction time, the process pressure, or a combination thereof.

[0046] Next, please refer to Figure 9, which is a comparison diagram of wafer warp without planarization and wafer warp with planarization in some embodiments of this disclosure. Curve 910 represents wafer warp without the planarization process provided in the embodiments of this disclosure, and curve 920 represents wafer warp of wafer 102 with the planarization process provided in the embodiments of this disclosure. As shown in Figure 9, curve 920 is significantly reduced compared to curve 910. That is, wafer warp of wafers with planarization processes (such as wafer 102 in Figures 5 and 6 or Figure 8) is significantly improved.

[0047] Therefore, the wafer planarization method disclosed in this embodiment, by forming a symmetrical pattern on the back side of the wafer, can facilitate control over the flatness and smoothness of the wafer. Furthermore, combining the formation of a symmetrical pattern with the planarization process can improve the morphology of the back side of the wafer. Similarly, this can increase the vacuum level of the wafer chuck holding the wafer, meaning that vacuum leakage can be reduced.

[0048] Although some embodiments of this disclosure have been described in considerable detail, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0049] The foregoing summary outlines the features of several embodiments in this disclosure, enabling those skilled in the art to more readily understand it. Anyone skilled in the art should understand that this disclosure can easily serve as a basis for changes or designs to other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments disclosed. Anyone skilled in the art will also understand that equivalent structures described above do not depart from the spirit and scope of this disclosure, and that modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0050] 102: Wafer / Substrate 102B: Back surface 102F: Front surface 104: Semiconductor Structure 110: Protective layer 120: Pattern Mask 120A, 120B, 120C, 120D, 120E: Pattern Mask 122A: Part One 122B: Part Two 122C: Part Three 130, 130A, 130B: Symmetrical patterns 140: Outer depression 142: Indentation 410: Etching tank 412: Etching agent 500: Polishing device 502: Support plate 510: Grinding Pad 520: Wafer Socket 522: Wafer Chuck 530: Grinding fluid nozzle 532: Grinding fluid 700: Double-sided polishing device 705: Box 710: Lower fixing component 712: Lower Grinding Pad 720: Upper fastener 722: Upper grinding pad 730: Wafer Socket 732: Wafer holding via 742: Upper drive unit 744: Lower drive unit 910, 920: Curves AA', BB': Cross-section lines CR: Center ID, ID1, ID2: Internal distance IS1: First Inner Edge IS2: Second Inner Edge OD, OD1, OD2: External distance OS1: First Outer Edge OS2: Second Outer Edge W1: First width W2: Second width W3: Third width W4: Fourth Width

[0051] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A wafer planarization method, comprising: A wafer is provided, wherein a front surface of the wafer has a semiconductor structure; A protective layer is formed on the semiconductor structure; a pattern mask is formed on a back surface of the wafer, such that a first portion of the back surface is covered and a second and a third portion of the back surface are exposed, wherein the pattern mask has a symmetrical shape; the second and third portions are etched to form a symmetrical pattern on a back side of the wafer. And perform a planarization process to remove the protective layer located on the front surface of the wafer, wherein the planarization process includes: mounting the wafer on a polishing apparatus having a polishing pad by adhering to the symmetrical pattern on the back side of the wafer. And remove the protective layer on the semiconductor structure.

2. The method as described in claim 1, wherein performing the planarization process includes: After removing the protective layer, the wafer is mounted on the polishing apparatus with the polishing pad through the surface that holds the semiconductor structure. And to planarize the back side of the wafer.

3. The method as described in claim 2, wherein performing the planarization process includes: Press the wafer down to bring it against the surface of the polishing pad and rotate the wafer; And an abrasive fluid is provided on the surface of the abrasive pad.

4. The method as described in claim 1, wherein the etching of the second portion and the third portion of the wafer is performed through a wet etching process.

5. The method as described in claim 4, wherein the wet etching process includes: The wafer, including the pattern mask, is placed in an etching tank containing an etchant to remove the second and third portions through the wet etching process.

6. The method as described in claim 5, wherein the etchant is HNO3(aq), H2SO4(aq), HF(aq), or a combination thereof.

7. The method as described in claim 5, wherein the protective layer formed on the semiconductor structure is resistant to the etchant.

8. The method as described in claim 7, wherein after the planarization process, the symmetrical pattern and recessed portion formed by etching on the wafer will be coplanar.

9. The method as described in claim 1, wherein the pattern mask has a hollow and symmetrical pattern.

10. The method as described in claim 1, wherein an external distance between the outer edge of the symmetrical pattern and the outer edge of the wafer is the same or different.

11. The method as described in claim 1, wherein the second portion is the portion extending from the edge of the wafer to the outer edge of the pattern mask, and the third portion is the exposed portion near the center of the wafer.

12. A method for planarizing a wafer, comprising: A wafer is provided, wherein a front surface of the wafer has a semiconductor structure; An oxide layer is formed on the semiconductor structure; A pattern mask is formed on a back surface of the wafer to cover a portion of the back surface and expose an outwardly exposed portion and an inwardly exposed portion of the back surface, wherein the pattern mask has a symmetrical shape; the outwardly exposed portion and the inwardly exposed portion are etched to form a symmetrical pattern on a back side of the wafer. And perform a planarization process to remove the oxide layer on the front surface of the wafer and the symmetrical pattern on the back surface of the wafer, wherein the planarization process includes: placing the wafer in a wafer holding hole of a polishing apparatus; The wafer is held by a lower fixing member and an upper fixing member, wherein the lower fixing member includes a lower polishing pad located on the upper surface of the lower fixing member, and the upper fixing member includes an upper polishing pad located on the upper surface of the upper fixing member; and the upper fixing member and the lower fixing member are rotated to remove the oxide layer on the front surface of the wafer and the symmetrical pattern on the back surface of the wafer.

13. The method as described in claim 12, wherein etching the outward exposed portion and the inward exposed portion of the wafer is performed through a wet etching process.

14. The method as described in claim 13, wherein the wet etching process includes: The wafer, including the pattern mask, is placed into an etching tank containing an etchant.

15. The method as described in claim 14, wherein the etching rate of the wet etching process is controlled by adjusting the bubble position, bubble flow rate, rotational acceleration, temperature of the etching tank, acid content in the etchant, pressure of the wet etching process, or a combination thereof.

16. The method of claim 14, wherein the oxide layer formed on the semiconductor structure is resistant to the etchant to protect the semiconductor structure and the wafer from damage due to etching.

17. The method as described in claim 12, wherein the surface of the oxide layer contacts the surface of the upper abrasive pad, and the symmetrical pattern contacts the surface of the lower abrasive pad.

18. The method as described in claim 12, wherein the surface of the oxide layer contacts the surface of the lower polishing pad, and the symmetrical pattern contacts the surface of the upper polishing pad.

19. The method as described in claim 12, wherein during the planarization process, an abrasive slurry is applied to the surface of the lower abrasive pad and the surface of the upper abrasive pad.

20. The method as described in claim 12, wherein an external distance between the outer edge of the symmetrical pattern and the outer edge of the wafer is the same or different.

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