Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a substrate and a capacitor. The capacitor is located on the substrate. The capacitor includes a first electrode, a second electrode, a first dielectric layer, and a second dielectric layer. The first electrode is located on the substrate. The first electrode has a first surface and a second surface opposite to each other. The second electrode is located on the first electrode. The first dielectric layer is located between the first surface and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode, and between the second surface and the second electrode.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure including a capacitor and a method for manufacturing the same. Prior Technology

[0002] In semiconductor structures that include capacitors (such as dynamic random access memory (DRAM) structures), bending or collapse of the capacitors will reduce the reliability of the semiconductor structure. Therefore, improving the reliability of semiconductor structures is a continuous goal. Summary of the Invention

[0003] This invention provides a semiconductor structure and its manufacturing method, which can improve the reliability of the semiconductor structure.

[0004] This invention proposes a semiconductor structure including a substrate and a capacitor. The capacitor is located on the substrate. The capacitor includes a first electrode, a second electrode, a first dielectric layer, and a second dielectric layer. The first electrode is located on the substrate. The first electrode has a first surface and a second surface opposite to each other. The second electrode is located on the first electrode. The first dielectric layer is located between the first surface and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode, and between the second surface and the second electrode.

[0005] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a capacitor on the substrate. The capacitor includes a first electrode, a second electrode, a first dielectric layer, and a second dielectric layer. The first electrode is located on the substrate. The first electrode has a first surface and a second surface opposite to each other. The second electrode is located on the first electrode. The first dielectric layer is located between the first surface and the second electrode. The second dielectric layer is located between the first dielectric layer and the second electrode, and between the second surface and the second electrode.

[0006] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, a first dielectric layer is located between the first surface of the first electrode and the second electrode, and a second dielectric layer is located between the first dielectric layer and the second electrode, and between the second surface of the first electrode and the second electrode. That is, a first dielectric layer and a second dielectric layer are provided on the first surface of the first electrode. This prevents the capacitor from bending or collapsing, thereby improving the structural strength of the capacitor and the reliability of the semiconductor structure. Furthermore, the first dielectric layer can balance the thickness of the capacitor dielectric layer (including the first dielectric layer and the second dielectric layer) located on the first surface (e.g., the inner surface) and the second surface (e.g., the outer surface) of the first electrode. Additionally, the first dielectric layer can enhance the stepped coverage capability of the capacitor dielectric layer (including the first dielectric layer and the second dielectric layer) located on the first surface (e.g., the inner surface) of the first electrode.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0008] Figures 1A to 1G are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Figure 2 is a top view of the capacitor in Figure 1G. Implementation

[0009] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. Additionally, the features in the top view are not drawn to the same scale as those in the sectional view. In fact, for clarity of explanation, the dimensions of various features can be arbitrarily increased or decreased.

[0010] Figures 1A to 1G are cross-sectional views illustrating the manufacturing process of a semiconductor structure according to some embodiments of the present invention. Figure 2 is a top view of the capacitor in Figure 1G. Furthermore, in Figure 2, a portion of some components in Figure 1G is omitted to clearly illustrate the arrangement of the components in Figure 2.

[0011] Referring to Figure 1A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, although not shown in the figure, depending on the type of semiconductor structure, corresponding components may be present on and / or within the substrate 100. For example, the substrate 100 may have necessary components (not shown), such as isolation structures, doped regions, and / or buried word lines, and may have necessary components (not shown), such as dielectric layers and / or interconnect structures (e.g., bit lines and contact windows), which are omitted here.

[0012] Next, a stacked structure SS1 can be formed on the substrate 100. The stacked structure SS1 may include a dielectric layer 102, a support layer 104, a dielectric layer 106, and a support layer 108. The dielectric layer 102 is located on the substrate 100. In some embodiments, the material of the dielectric layer 102 is, for example, an oxide (e.g., silicon oxide). The support layer 104 is located on the dielectric layer 102. In some embodiments, the material of the support layer 104 is, for example, a nitride (e.g., silicon nitride). The dielectric layer 106 is located on the support layer 104. In some embodiments, the material of the dielectric layer 106 is, for example, an oxide (e.g., silicon oxide). The support layer 108 is located on the dielectric layer 106. In some embodiments, the material of the support layer 108 is, for example, a nitride (e.g., silicon nitride). In some embodiments, the stacked structure SS1 may further include a termination layer 110. The termination layer 110 is located between the dielectric layer 102 and the substrate 100. In some embodiments, the material of the termination layer 110 is, for example, a nitride (e.g., silicon nitride).

[0013] Referring to Figure 1B, an opening OP1 can be formed in the stacked structure SS1. The opening OP1 can penetrate the support layer 108, dielectric layer 106, support layer 104, dielectric layer 102, and termination layer 110. In some embodiments, the stacked structure SS1 can be patterned to form the opening OP1. The patterning process may include lithography and etching processes.

[0014] Referring to Figure 1C, an electrode material layer 112 can be conformally formed on the stacked structure SS1 and the opening OP1. In some embodiments, the material of the electrode material layer 112 is, for example, titanium nitride. In some embodiments, the electrode material layer 112 is formed by, for example, chemical vapor deposition.

[0015] Referring to Figure 1D, a dielectric material layer 114 can be conformally formed on the electrode material layer 112. In some embodiments, the material of the dielectric material layer 114 is, for example, a high dielectric constant material. In some embodiments, the material of the dielectric material layer 114 is, for example, hafnium oxide (HfO), zirconium oxide (ZrO), or niobium oxide (NbO). In some embodiments, the dielectric material layer 114 is formed by, for example, atomic layer deposition.

[0016] Referring to Figure 1E, the dielectric material layer 114 and the electrode material layer 112 can be patterned to form the dielectric layer 114a and the electrode 112a. In some embodiments, a patterned mask layer (e.g., a patterned photoresist layer and / or a patterned hard mask layer) (not shown) can be used as a mask to perform an etching process (e.g., a dry etching process) on the dielectric material layer 114 and the electrode material layer 112 to form the dielectric layer 114a and the electrode 112a, and expose a portion of the support layer 108.

[0017] Furthermore, a portion of the support layer 108 can be removed, exposing a portion of the dielectric layer 106. In some embodiments, the method for removing the portion of the support layer 108 is, for example, dry etching. Next, the dielectric layer 106 can be removed, exposing the support layer 104. In some embodiments, the method for removing the dielectric layer 106 is, for example, wet etching. Next, a portion of the support layer 104 can be removed, exposing a portion of the dielectric layer 102. In some embodiments, the method for removing the portion of the support layer 104 is, for example, dry etching. Then, the dielectric layer 102 can be removed. In some embodiments, the method for removing the dielectric layer 102 is, for example, wet etching.

[0018] Referring to Figure 1F, after removing dielectric layer 102, dielectric layer 116 can be conformally formed on electrode 112a, dielectric layer 114a, support layer 104, support layer 108, and termination layer 110. In some embodiments, the material of dielectric layer 116 is, for example, a high dielectric constant material. In some embodiments, the material of dielectric layer 116 is, for example, hafnium oxide, zirconium oxide, niobium oxide, or a zirconium oxide / aluminum oxide / zirconium oxide (ZAZ) composite material. In some embodiments, the method for forming dielectric layer 116 is, for example, atomic layer deposition or chemical vapor deposition.

[0019] Referring to Figure 1G, an electrode layer 118 can be conformally formed on the dielectric layer 116. In some embodiments, the material of the electrode layer 118 is, for example, titanium nitride. In some embodiments, the electrode layer 118 is formed by, for example, chemical vapor deposition.

[0020] Next, an electrode layer 120 can be formed on the electrode layer 118. Herein, an electrode 122 can be formed. In this embodiment, the electrode 122 may include both the electrode layer 118 and the electrode layer 120, but the invention is not limited thereto. The electrode layer 120 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the electrode layer 120 is, for example, doped silicon germanium (SiGe), tungsten, or a combination thereof. In some embodiments, the method for forming the electrode layer 120 is, for example, chemical vapor deposition.

[0021] Using the above method, a capacitor 124 can be formed on the substrate 100. Hereinafter, the semiconductor structure 10 of the above embodiment will be described with reference to FIG1G and FIG2. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0022] Referring to Figures 1G and 2, the semiconductor structure 10 includes a substrate 100 and a capacitor 124. In some embodiments, the semiconductor structure 10 may be a memory structure, such as a dynamic random access memory (DRAM) structure. In some embodiments, the capacitor 124 may be used as a capacitor in a DRAM.

[0023] Capacitor 124 is located on substrate 100. Capacitor 124 includes electrode 112a, electrode 122, dielectric layer 114a, and dielectric layer 116. Electrode 112a is located on substrate 100. In some embodiments, electrode 112a can be used as the lower electrode of capacitor 124. Electrode 112a has surfaces S1 and S2 opposite to each other. In some embodiments, the cross-sectional shape of electrode 112a may include a U-shape. When the cross-sectional shape of electrode 112a includes a U-shape, surface S1 may be the inner surface of electrode 112a, and surface S2 may be the outer surface of electrode 112a.

[0024] Electrode 122 is located on electrode 112a. In some embodiments, electrode 122 can be used as the upper electrode of capacitor 124. Electrode 122 can be a single-layer structure or a multi-layer structure. In this embodiment, electrode 122 is an example of a multi-layer structure and includes electrode layer 118 and electrode layer 120, but the present invention is not limited thereto. Electrode layer 118 is located on electrode 112a. Electrode layer 120 is located on electrode layer 118.

[0025] A dielectric layer 114a is located between surface S1 and electrode 122. The dielectric layer 114a prevents capacitor 124 from bending or collapsing, thereby improving the structural strength of capacitor 124 and the reliability of semiconductor structure 10. In some embodiments, the dielectric layer 114a may directly contact surface S1. The top view shape of the dielectric layer 114a may be annular and may surround electrode layer 120. In some embodiments, the dielectric layer 114a and electrode 112a may not contain the same metal element. In some embodiments, the material of dielectric layer 114a is, for example, a high dielectric constant material, thereby increasing the capacitance of capacitor 124. In some embodiments, the material of dielectric layer 114a is, for example, hafnium oxide, zirconium oxide, or niobium oxide. In some embodiments, the material of dielectric layer 114a is, for example, a material with a dielectric constant greater than 20, such as hafnium oxide, zirconium oxide, niobium oxide, lanthanum oxide, or tantalum oxide. In some embodiments, the material of dielectric layer 114a is, for example, a material with a bandgap greater than 8 electron volts, such as aluminum oxide.

[0026] A dielectric layer 116 is located between dielectric layer 114a and electrode 122, and between surface S2 and electrode 122. In some embodiments, dielectric layer 114a may not be located between surface S2 and dielectric layer 116. In some embodiments, dielectric layer 116 may directly contact surface S2. In some embodiments, the material of dielectric layer 114a may be different from the material of dielectric layer 116. In other embodiments, the material of dielectric layer 114a may be the same as the material of dielectric layer 116. In some embodiments, the material of dielectric layer 116 is, for example, a high dielectric constant material, thereby increasing the capacitance of capacitor 124. In some embodiments, the material of dielectric layer 116 is, for example, hafnium oxide, zirconium oxide, niobium oxide, or a zirconium oxide / aluminum oxide / zirconium oxide (ZAZ) composite material. In some embodiments, the material of dielectric layer 116 is, for example, a material with a dielectric constant greater than 20, such as hafnium oxide, zirconium oxide, niobium oxide, lanthanum oxide, or tantalum oxide. In some embodiments, the material of dielectric layer 116 is, for example, a material with a bandgap greater than 8 electron volts, such as aluminum oxide.

[0027] In some embodiments, the thickness T1 of the dielectric layer 116 on surface S1 (e.g., the inner surface) may be less than the thickness T2 of the dielectric layer 116 on surface S2 (e.g., the outer surface). The thickness of the dielectric layer 114a on surface S1 (e.g., the inner surface) is less than the thickness T2 of the dielectric layer 116 on surface S2 (e.g., the outer surface). Therefore, the thicknesses of the capacitor dielectric layers (including dielectric layers 114a and 116) on surfaces S1 (e.g., the inner surface) and S2 (e.g., the outer surface) can be balanced by the dielectric layer 114a.

[0028] The semiconductor structure 10 may further include a support layer 104 and a support layer 108. The support layer 104 is located on the surface S2 of the electrode 112a. The support layer 104 can directly contact the electrode 112a. The support layer 108 is located on the surface S2 of the electrode 112a. The support layer 108 can directly contact the electrode 112a. The support layer 104 may be located between the support layer 108 and the substrate 100. A dielectric layer 116 may be located on the support layers 104 and 108. The semiconductor structure 10 may further include a termination layer 110. The termination layer 110 may be located between the support layer 104 and the substrate 100. The dielectric layer 116 may be located on the termination layer 110.

[0029] Furthermore, the details of each component in the semiconductor structure 10 (such as materials, arrangement methods, and formation methods) have been described in detail in the above embodiments and will not be described again here.

[0030] Based on the above embodiments, in the semiconductor structure 10 and its manufacturing method, the dielectric layer 114a is located between the surface S1 of the electrode 112a and the electrode 122, and the dielectric layer 116 is located between the dielectric layer 114a and the electrode 122, and between the surface S2 of the electrode 112a and the electrode 122. That is, the dielectric layer 114a and the dielectric layer 116 are provided on the surface S1 of the electrode 112a. This prevents the capacitor 124 from bending or collapsing, thereby improving the structural strength of the capacitor 124 and the reliability of the semiconductor structure 10. In addition, the dielectric layer 114a can balance the thickness of the capacitor dielectric layer (including the dielectric layer 114a and the dielectric layer 116) located on the surface S1 (e.g., the inner surface) of the electrode 112a and the surface S2 (e.g., the outer surface) of the electrode 112a. In addition, dielectric layer 114a can enhance the step coverage capability of the capacitor dielectric layer (including dielectric layer 114a and dielectric layer 116) located on the surface S1 (e.g., inner surface) of electrode 112a.

[0031] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0032] 10: Semiconductor Structure 100: Base 102, 106, 114a, 116: Dielectric layers 104, 108: Support layer 110: Termination Layer 112: Electrode material layer 112a, 122: Electrodes 114: Dielectric material layer 118, 120: Electrode layers 124: Capacitor OP1: Opening S1, S2: Surface SS1: Stacked structure T1, T2: Thickness

Claims

1. A semiconductor structure, comprising: Base; And a capacitor, located on the substrate, and comprising: a first electrode, located on the substrate and having a first surface and a second surface opposite to each other; a second electrode, located on the first electrode; a first dielectric layer, located between the first surface and the second electrode; and a second dielectric layer, located between the first dielectric layer and the second electrode and between the second surface and the second electrode, and located on the opposite side of the first electrode, wherein the thickness of the second dielectric layer on the first surface is less than the thickness of the second dielectric layer on the second surface, and the thickness of the first dielectric layer on the first surface is less than the thickness of the second dielectric layer on the second surface.

2. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer is not located between the second surface and the second dielectric layer.

3. The semiconductor structure as claimed in claim 1, wherein the cross-sectional shape of the first electrode includes a U-shape.

4. The semiconductor structure as claimed in claim 1, wherein the first dielectric layer and the first electrode do not contain the same metal element.

5. The semiconductor structure as claimed in claim 1, wherein the material of the first dielectric layer comprises a high dielectric constant material.

6. The semiconductor structure as claimed in claim 1, wherein the material of the first dielectric layer includes hafnium oxide, zirconium oxide, niobium oxide, lanthanum oxide, or tantalum oxide.

7. The semiconductor structure of claim 1, wherein the material of the first dielectric layer comprises a material with a dielectric constant greater than 20.

8. The semiconductor structure as described in claim 1, further comprising: A first support layer is located on the second surface of the first electrode; and a second support layer, located on the second surface of the first electrode, wherein the first support layer is located between the second support layer and the substrate, and the second dielectric layer is located on the first support layer and the second support layer.

9. A method for manufacturing a semiconductor structure, comprising: Provide a base; and forming a capacitor on the substrate, wherein the capacitor includes: a first electrode located on the substrate and having a first surface and a second surface opposite to each other; a second electrode located on the first electrode; a first dielectric layer located between the first surface and the second electrode; and a second dielectric layer located between the first dielectric layer and the second electrode and between the second surface and the second electrode, and located on the opposite side of the first electrode, wherein the thickness of the second dielectric layer on the first surface is less than the thickness of the second dielectric layer on the second surface, and the thickness of the first dielectric layer on the first surface is less than the thickness of the second dielectric layer on the second surface.

10. A method for manufacturing a semiconductor structure as claimed in claim 9, wherein the method for forming the first electrode and the first dielectric layer comprises: A stacked structure is formed on the substrate; An opening is formed in the stacked structure; An electrode material layer is formed conformally with the opening on the stacked structure; A dielectric material layer is conformally formed on the electrode material layer; and a patterning process is performed on the dielectric material layer and the electrode material layer to form the first dielectric layer and the first electrode.

11. A method for manufacturing a semiconductor structure as claimed in claim 10, wherein the method for forming the dielectric material layer includes atomic layer deposition.

12. A method for manufacturing a semiconductor structure as claimed in claim 10, wherein the stacked structure comprises: A third dielectric layer is located on the substrate; A first support layer is located on the third dielectric layer; The fourth dielectric layer is located on the first support layer; And a second support layer, located on the fourth dielectric layer.

13. The method for manufacturing a semiconductor structure as described in claim 12, further comprising: Remove a portion of the second support layer, thereby exposing a portion of the fourth dielectric layer; Remove the fourth dielectric layer to expose the first support layer; Remove a portion of the first support layer, thereby exposing a portion of the third dielectric layer; And remove the third dielectric layer.

14. A method for manufacturing a semiconductor structure as claimed in claim 13, wherein the method for forming the second dielectric layer comprises: After the third dielectric layer is removed, the second dielectric layer is conformally formed on the first electrode, the first dielectric layer, the first support layer, and the second support layer.

15. A method for manufacturing a semiconductor structure as claimed in claim 9, wherein the method for forming the second dielectric layer includes atomic layer deposition or chemical vapor deposition.

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