Electronic package and fabricating method thereof

Abstract

An electronic package has a circuit structure formed around a mounting area defined by a circuit board, so that a groove is formed in the mounting area, and an electronic component is mounted in the groove. By embedding the electronic component in the groove, the thickness of the electronic package can be significantly reduced to meet the requirements of thinning.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging process, and more particularly to an electronic package that meets the requirements for thinning and its manufacturing method. Prior Technology

[0002] With the evolution of semiconductor packaging technology, semiconductor devices have developed different packaging types. In order to improve electrical functions and save packaging space, the industry has developed stacked multiple packaging structures to form a package on package (POP) packaging type, so as to present the heterogeneous integration characteristics of system-on-package (SiP). Therefore, system integration is achieved through stacking design, which is beneficial for various thin and small electronic products.

[0003] Figure 1 is a cross-sectional schematic diagram of a conventional semiconductor package 1. As shown in Figure 1, the semiconductor package 1 includes a semiconductor wafer 10, a first packaging substrate 11, a second packaging substrate 12, a plurality of solder pillars 17, and a packaging colloid 15.

[0004] Specifically, the first packaging substrate 11 has a core layer 110 and a plurality of circuit layers 111, and the second packaging substrate 12 has a core layer 120 and a plurality of circuit layers 121, so that the semiconductor wafer 10 is disposed on the first packaging substrate 11 by a plurality of conductive bumps 101 in a flip-chip manner, and an undercoat 16 is formed between the semiconductor wafer 10 and the first packaging substrate 11 to cover the conductive bumps 101, and the second packaging substrate 12 is provided with a packaging module 1a by a plurality of solder balls 19.

[0005] Furthermore, the solder pillars 17 are used to stack and electrically connect the circuit layer 111 of the first packaging substrate 11 and the circuit layer 121 of the second packaging substrate 12. The encapsulant 15 covers the solder pillars 17 and the semiconductor wafer 10.

[0006] However, in conventional semiconductor packages 1, both the first packaging substrate 11 and the second packaging substrate 12 have core layers 110 and 120, and the semiconductor wafer 10 is disposed on the first packaging substrate 11, resulting in a significant increase in the thickness H of the semiconductor package 1, making it impossible to meet the requirement of thinning. In addition, the encapsulant 15 needs to cover the entire surface area of ​​the upper side of the first packaging substrate 11 to cover the solder pillars 17 and the semiconductor wafer 10, making it impossible to reduce the amount of encapsulant 15 used, and thus making it difficult to reduce manufacturing costs.

[0007] Therefore, how to overcome the various problems of the aforementioned conventional technologies has become an urgent issue that needs to be addressed. Summary of the Invention

[0008] In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a circuit board having a first side and a second side opposite to each other, wherein the first side of the circuit board defines a mounting area; a circuit structure formed on the periphery of the mounting area and electrically connected to the circuit board, wherein the circuit structure forms a groove in the mounting area of ​​the circuit board and exposes a portion of the circuit board; a first electronic component disposed on the circuit board in the groove and electrically connected to the circuit board; and a second electronic component disposed on the first electronic component and electrically connected to the circuit structure.

[0009] The present invention also provides a method for manufacturing an electronic package, comprising: providing a circuit board body, wherein the circuit board body has a first side and a second side opposite to each other, and the first side of the circuit board body defines a mounting area; forming a circuit structure around the mounting area to electrically connect the circuit board body, and forming a groove in the mounting area of ​​the circuit board body with the circuit structure forming a recess and exposing a portion of the circuit board body; mounting a first electronic component on the circuit board body in the groove to electrically connect the circuit board body; and mounting a second electronic component on the first electronic component and electrically connecting the second electronic component and the circuit structure.

[0010] In the aforementioned electronic package and its manufacturing method, the first electronic component is electrically connected to the circuit board via flip-chip bonding, and the second electronic component is electrically connected to the circuit structure via wire bonding.

[0011] In the aforementioned electronic package and its manufacturing method, the circuit board has an external circuit layer on the first side, and a portion of the external circuit layer on the first side is exposed outside the placement area. The manufacturing method of the electronic package further includes forming insulating layers on the first side and the second side of the placement area of ​​the circuit board before placing the first electronic component, thereby exposing a portion of the external circuit layer. This results in the electronic package including insulating layers formed on the first side and the second side of the placement area of ​​the circuit board, respectively, and an exposed portion of the external circuit layer.

[0012] In the aforementioned electronic packaging components and manufacturing methods, the circuit board system is a core-layer type circuit board body, which includes a core layer and augmentation structures formed on opposite surfaces of the core layer. An external circuit layer is formed on the augmentation structures on opposite surfaces of the core layer, and the circuit board body contacts and is electrically connected to the circuit structure on the external circuit layer on the first side.

[0013] In the aforementioned electronic packaging components and manufacturing methods, the circuit board system is a coreless circuit board body, which includes stacked die-placement structures and at least one add-on structure. The die-placement structure forms an external circuit layer on the first side of the circuit board body, which is embedded in the die-placement structure and flush with and exposed on the surface of the first side of the circuit board body.

[0014] As can be seen from the above, the electronic package and its manufacturing method of the present invention mainly utilize the design of the groove to place the electronic component in the groove formed by the circuit board and the circuit structure, thereby significantly reducing the thickness of the electronic package. Therefore, compared with the stacked packaging of the prior art, the electronic package of the present invention can meet the requirements of thinning.

[0015] Furthermore, the electronic component is only disposed in the groove, without forming an encapsulation layer to cover the electronic component. Therefore, compared with the stacked packaging of the prior art, the electronic package of the present invention can avoid the accumulation of heat energy, and the groove can more effectively dissipate the heat energy generated by the package. Simple Explanation of the Diagram

[0016] Figure 1 is a cross-sectional schematic diagram of a conventional semiconductor package.

[0017] Figures 2A to 2G are cross-sectional schematic diagrams of the manufacturing method of the first embodiment of the electronic package of the present invention.

[0018] Figures 3A to 3H are cross-sectional schematic diagrams of the manufacturing method of the second embodiment of the electronic package of the present invention. Implementation

[0019] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0020] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are only for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0021] Figures 2A to 2G are cross-sectional schematic diagrams illustrating the manufacturing method of the first embodiment of the electronic package 2 of the present invention. In this embodiment, the circuit board body 20' of the electronic package 2 has a core layer.

[0022] As shown in Figure 2A, a core layer 20 is provided, which has a first circuit layer 21 and a complex conductive structure 22.

[0023] In this embodiment, the core layer 20 has a first surface 20a and a second surface 20b. For example, the core layer 20 is a copper-coated laminate (CCL), which includes a body 200, and a first metal layer 201, resembling a copper foil, is formed on the two opposing surfaces 200a and 200b of the body 200. Specifically, the material forming the body 200 is a substrate containing glass fiber and organic resin, such as BT (Bismaleimide Triazine), FR4, or FR5, and there are no particular limitations.

[0024] In one embodiment, a plurality of vias 220 penetrating the first metal layer 201 and the body 200 are formed by mechanical, laser, etching, or other suitable means. A plurality of conductive structures 22 are formed in the plurality of vias 220 using processes such as plating through holes (PTH) and patterning processes (e.g., inner layer development etching stripping lines (DES)). A second metal layer 202 is then formed on the plurality of conductive structures 22 and the first metal layer 201, thereby forming the first circuit layer 21. Furthermore, the material of the second metal layer 202 is, for example, copper.

[0025] As shown in Figure 2B, a first dielectric layer 230 is formed on the first surface 20a and the second surface 20b of the core layer 20.

[0026] In this embodiment, the material forming the first dielectric layer 230 is such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials. For example, the first dielectric layer 230 is made of ABF, with a coefficient of thermal expansion (CTE) of 13 to 17 ppm / ℃.

[0027] Next, the plurality of first blind holes 230a are formed by mechanical, laser, etching or other suitable means.

[0028] As shown in Figure 2C, a build-up process is performed on the first dielectric layer 230 to form a build-up structure 23, thereby forming a circuit board body 20' with corresponding first side 20'a and second side 20'b.

[0029] In this embodiment, the added layer structure 23 may adopt the redistribution layer (RDL) specification, and the added layer structure 23 includes the first dielectric layer 230 having a plurality of first blind vias 230a, a plurality of first conductive pillars 231 formed in the plurality of first blind vias 230a, and a second circuit layer (outer circuit layer 232) formed on the plurality of first conductive pillars 231 and the first dielectric layer 230.

[0030] Furthermore, a mounting area A is defined on the first side 20'a of the circuit board 20' for connecting external components, such as the first electronic component 80 described later. Therefore, a first insulating layer 24 is formed on the first dielectric layer 230 and the external circuit layer 232 in the mounting area A (as shown in FIG2C), and a portion of the external circuit layer 232 in the mounting area A is exposed to the first insulating layer 24. In one embodiment, the material forming the first insulating layer 24 is an epoxy resin such as green paint, and the first insulating layer 24 forms a plurality of openings 240 after exposure and development.

[0031] As shown in Figure 2D, a second dielectric layer 250 and a third metal layer 251 are sequentially formed on the first side 20'a of the circuit board 20', and the second dielectric layer 250 covers the outer circuit layer 232 and the first insulating layer 24.

[0032] In this embodiment, the material forming the second dielectric layer 250 is a dielectric material such as ABF, PBO, PI, PP, or others. For example, the second dielectric layer 250 is PP with a CTE of 10 ppm / ℃. Furthermore, the material of the third metal layer 251 is such as copper.

[0033] As shown in Figures 2E and 2F, a circuit structure 25 is formed around the setting area A on the first side 20'a of the circuit board 20'.

[0034] In this embodiment, the circuit structure 25 adopts the RDL specification, and the circuit structure 25 includes the second dielectric layer 250, a plurality of second conductive pillars 252, and a third circuit layer 25a. Specifically, the third metal layer 251 can be patterned, and a plurality of second blind vias 252a penetrating the second dielectric layer 250 and the third metal layer 251 can be formed by mechanical, laser, etching, or other suitable methods. The plurality of second conductive pillars 252 are formed in the plurality of second blind vias 252a using electroplating and patterning processes. A fourth metal layer 253 is then formed on the plurality of second conductive pillars 252 and the third metal layer 251, so that the third metal layer 251 and the fourth metal layer 253 form the third circuit layer 25a. Furthermore, the material of the fourth metal layer 253 is, for example, copper.

[0035] In one embodiment, the first conductive post 231 and the outer circuit layer 232 of the added layer structure 23 are electrically connected to the second conductive post 252 and the third circuit layer 25a of the circuit structure 25.

[0036] As shown in Figure 2F, a second insulating layer 26 is formed on the second side 20'b of the circuit board 20' and the circuit structure 25, exposing a portion of the external circuit layer 232 and the third circuit layer 25a. Then, a portion of the second dielectric layer 250 on the first side 20'a of the circuit board 20' located in the setting area A is removed, so that a groove S is formed in the setting area A, and the groove S does not extend into the circuit board 20', thereby forming the packaging substrate 2a.

[0037] In this embodiment, a portion of the second dielectric layer 250 in the setting area A can be removed by means such as plasma etching to form the groove S and expose the first insulating layer 24 and a portion of the external circuit layer 232.

[0038] In one embodiment, the second insulating layer 26 is formed on the periphery of the setting area A, and the material forming the second insulating layer 26 is an epoxy resin such as green paint.

[0039] As shown in Figure 2G, a first electronic component 80 is disposed on the outer circuit layer 232 of the circuit board body 20' in the groove S via a second conductive bump 83, for example, by flip-chip bonding, to electrically connect the circuit board body 20'. A second electronic component 81 is disposed in the groove S and disposed on the first electronic component 80 via a bonding member 82. The second electronic component 81 is electrically connected to the third circuit layer 25a of the circuit structure 25 by wire bonding from the plurality of electrode pads 810 on the working surface 81a of the second electronic component 81, to form an electronic package 2. A plurality of first conductive bumps 27 are formed on the outer circuit layer 232 on the second side 20'b of the circuit board body 20' for the electronic package 2 to be disposed on a circuit board 9. The first electronic component 80 is electrically connected to the outer circuit layer 232 of the circuit board body 20' through a plurality of openings 240 of the first insulating layer 24, such as solder balls.

[0040] Furthermore, the electronic component 80 is an active component, a passive component, or a combination of both, wherein the active component is, for example, a semiconductor chip or a memory chip, and the passive component is, for example, a resistor, a capacitor, or an inductor.

[0041] In one embodiment, the bonding member 82 is a base adhesive formed on the non-functional surface 81b of the second electronic component 81, thereby being disposed on the first electronic component 80 through the bonding member 82. Furthermore, the first conductive bump 27 and the second conductive bump 83 are, for example, solder balls.

[0042] In one embodiment, the circuit board 9 may be a printed circuit board (PCB).

[0043] Figures 3A to 3H are cross-sectional schematic diagrams illustrating the manufacturing method of the electronic package 3 according to a second embodiment of the present invention. In this embodiment, the circuit board body 30 of the electronic package 3 is a coreless type.

[0044] As shown in Figure 3A, a carrier 7 is provided, and a layered crystal structure 31 is symmetrically formed on opposite sides of the carrier 7.

[0045] In this embodiment, the carrier 7 is a temporary carrier plate, which can be a plate with metal layers on opposite sides, such as a copper foil substrate, which includes a plate body 70, a metal layer 72 formed on the surface of the plate body 70, and a seed layer 71 formed on the metal layer 72.

[0046] Furthermore, the die-placement structure 31 can adopt the redistribution layer (RDL) specification and be formed by a patterned process. The die-placement structure 31 includes a first dielectric layer 310 having a plurality of first blind vias 310a, a plurality of first conductive pillars 311 formed in the plurality of first blind vias 310a, a first circuit layer 312 formed on the plurality of first conductive pillars 311 and the first dielectric layer 310, and an external circuit layer 313 embedded in the first dielectric layer 310, flush with and exposed on the surface of the first dielectric layer 310.

[0047] In one embodiment, the material forming the first dielectric layer 310 is such as Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP), or other dielectric materials. For example, the first dielectric layer 310 is made of ABF, with a coefficient of thermal expansion (CTE) of 13 to 17 ppm / ℃.

[0048] As shown in Figure 3B, a build-up process is performed on the die-placement structure 31 to form at least one build-up structure 32. In this embodiment, a two-layer build-up structure 32 is formed.

[0049] In this embodiment, the dual-layer structure 32 adopts the RDL specification, and each dual-layer structure 32 includes a second dielectric layer 320 having a plurality of second blind vias 320a, a plurality of second conductive pillars 321 formed in the plurality of second blind vias 320a, and a second circuit layer 322 formed on the plurality of second conductive pillars 321 and the second dielectric layer 320. The dual-layer structure 32 is formed by a patterning process and is electrically connected to each other.

[0050] In one embodiment, the crystal structure 31 is electrically connected to at least one of the two added-layer structures 32.

[0051] In one embodiment, the material forming the second dielectric layer 320 is a dielectric material such as ABF, poly(p-diazole)benzene (PBO), PI, PP, or others. For example, the second dielectric layer 320 is made of ABF with a CTE of 13 to 17 ppm / °C.

[0052] As shown in Figure 3C, the board 70 and its metal layer 72 and seed layer 71 are removed to form two circuit boards 30 with corresponding first sides 30a and second sides 30b. The circuit boards 30 include stacked die-placement structures 31 and at least one add-on structure 32. The die-placement structure 31 forms an external circuit layer 313 on the first side 30a of the circuit board 30. The external circuit layer 313 is embedded in the die-placement structure 31, flush with it, and exposed on the surface of the first side 30a of the circuit board 30.

[0053] As shown in Figure 3D, a first insulating layer 33 is formed on the first side 30a of the circuit board 30.

[0054] In this embodiment, a setting area A' is defined on the first side 30a of the circuit board 30, and the first insulating layer 33 is formed only in the setting area A' (as shown in FIG. 3D), and the outer circuit layer 313 of the circuit board 30 is exposed to the first insulating layer 33. In one embodiment, the material forming the first insulating layer 33 is an epoxy resin such as green paint, and the first insulating layer 33 forms a plurality of openings 330 after exposure and development.

[0055] As shown in Figure 3E, a third dielectric layer 340 and a first metal layer 341 are sequentially formed on the first side 30a of the circuit board body 30, and the third dielectric layer 340 covers the first insulating layer 33 in the setting area A'.

[0056] In this embodiment, the material forming the third dielectric layer 340 is a dielectric material such as ABF, PBO, PI, PP, or others. For example, the third dielectric layer 340 is PP with a CTE of 10 ppm / ℃. Furthermore, the material of the first metal layer 341 is such as copper.

[0057] As shown in Figure 3F, a circuit structure 34 is formed around the setting area A' on the first side 30a of the circuit board 30.

[0058] In this embodiment, the circuit structure 34 adopts the RDL specification and includes a third dielectric layer 340, a plurality of third conductive pillars 342, and a third circuit layer 34a. A plurality of third blind vias 340a are formed through the third dielectric layer 340 and the first metal layer 341 by mechanical, laser, etching, or other suitable methods. The plurality of third conductive pillars 342 are formed in the plurality of third blind vias 340a using electroplating and patterning processes. A second metal layer 343 is then formed on the plurality of third conductive pillars 342 and the first metal layer 341, so that the first metal layer 341 and the second metal layer 343 form the third circuit layer 34a. Furthermore, the material of the second metal layer 343 is, for example, copper.

[0059] In one embodiment, the circuit structure 34 is electrically connected to the crystal structure 31.

[0060] As shown in Figure 3G, a second insulating layer 35 is formed on the second side 30b of the circuit board 30 and the circuit structure 34. Then, a portion of the third dielectric layer 340 located on the first side 30a of the circuit board 30 and in the setting area A' is removed, so that a groove S' is formed in the setting area A', and the groove S' does not extend into the circuit board 20', so as to form the packaging substrate 3a.

[0061] In this embodiment, a portion of the third dielectric layer 340 in the setting area A' is removed by means such as plasma etching to form the groove S', and the first insulating layer 33 and a portion of the first circuit layer 312 are exposed.

[0062] In one embodiment, the second insulating layer 35 is formed on the periphery of the setting area A' on the first side 30a of the circuit board body 30, and the material forming the second insulating layer 35 is an epoxy resin such as green paint.

[0063] As shown in Figure 3H, a first electronic component 80 is disposed on the outer circuit layer 313 of the circuit board 30 in the groove S' by means of second conductive bumps 83, for example, by flip-chip method, to electrically connect the circuit board 30. A second electronic component 81 is disposed in the groove S' and disposed on the first electronic component 80 by means of a bonding member 82. The second electronic component 81 is electrically connected to the third circuit layer 25a of the circuit structure 25 by wire bonding from the plurality of electrode pads 810 on the working surface 81a of the second electronic component 81 to form an electronic package 3. A plurality of first conductive bumps 36 are formed on the second circuit layer 322 on the second side 30b of the circuit board 30 for the electronic package 3 to be disposed on a circuit board 9. The first electronic component 80 is electrically connected to the outer circuit layer 313 of the circuit board 20' by means of solder balls through a plurality of openings 330 of the first insulating layer 33.

[0064] Furthermore, the electronic component 80 is an active component, a passive component, or a combination of both, wherein the active component is, for example, a semiconductor chip or a memory chip, and the passive component is, for example, a resistor, a capacitor, or an inductor.

[0065] In one embodiment, the bonding member 82 is a base adhesive formed on the non-functional surface 81b of the second electronic component 81, thereby being disposed on the first electronic component 80 through the bonding member 82. Furthermore, the first conductive bump 36 and the second conductive bump 83 are, for example, solder balls.

[0066] In one embodiment, the circuit board 9 may be a printed circuit board (PCB).

[0067] As described above, the manufacturing method of the present invention mainly utilizes the design of the grooves S and S' formed by the circuit board bodies 20' and 30 and the circuit structures 25 and 34 to place multiple electronic components in the grooves S and S', thereby significantly reducing the thickness H1 and H2 of the electronic package 2 and 3. Therefore, compared with the conventional package on package (PoP) technology, the electronic package 2 and 3 of this embodiment can meet the requirements of thinning.

[0068] Furthermore, by forming the grooves S and S', the diameter of the second conductive bump 83 used to connect the first electronic component 80 and the packaging substrate 2a and 3a can be ignored, thereby further reducing the thickness H1 and H2 of the electronic package 2 and 3.

[0069] Furthermore, the multiple electronic components (such as the first electronic component 80 and the second electronic component 81) are only disposed in the grooves S and S', without forming an encapsulation layer to cover the first electronic component 80 and the second electronic component 81. Therefore, compared with the stacked packaging of the prior art, the electronic package 2 and 3 of this embodiment can avoid the accumulation of heat energy, and the grooves S and S' can more effectively dissipate the heat energy generated by the first electronic component 80 and the second electronic component 81.

[0070] On the other hand, the thickness H2 of the coreless electronic package 3 is smaller than the thickness H1 of the core-based electronic package 2.

[0071] The present invention also provides an electronic package 2,3, which includes a circuit board body 20', 30, a circuit structure 25, 34, a first electronic component 80 and a second electronic component 81.

[0072] The circuit board bodies 20' and 30 have opposing first sides 20'a and 30a and second sides 20'b and 30b, and the first sides 20'a and 30a of the circuit board bodies 20' and 30 define a setting area A and A'.

[0073] The circuit structures 25 and 34 are formed on the periphery of the setting areas A and A' and are electrically connected to the circuit boards 20' and 30, so that the setting areas A and A' of the circuit boards 20' and 30 form a groove S and S', and a portion of the circuit boards 20' and 30 is exposed.

[0074] The first electronic component 80 is disposed on the circuit board 20', 30 in the groove S, S' and is electrically connected to the circuit board 20', 30 by flip-chip bonding; the second electronic component 81 is disposed on the first electronic component 80 and is electrically connected to the circuit structure 25, 34 by wire bonding.

[0075] In one embodiment, the circuit board 20', 30 has external circuit layers 232, 313 on the first side 20'a, 30a, and the portion of the external circuit layers 232, 313 on the first side 20'a, 30a is exposed in the placement area A, A'. The electronic package 2, 3 further includes first insulating layers 24, 33 formed on the first side 20'a, 30a and the second side 20'b, 30b of the placement area A, A' of the circuit board 20', 30, respectively, with the exposed portion of the external circuit layers 232, 313. Furthermore, a second insulating layer 26, 35 is also formed on the outer surface of the circuit structure 25, 34 with the exposed portion of the third circuit layers 25a, 34a.

[0076] In one embodiment, the circuit board 20' is a core layer type circuit board, which includes a core layer 20 and uplift structures 23 formed on two surfaces 200a and 200b of the core layer 20, wherein an outer circuit layer 232 is formed on the uplift structures 23 on the opposite surfaces 200a and 200b of the core layer 20, and the circuit board 20' contacts and is electrically connected to the circuit structure 25 on the outer circuit layer 232 on the first side 20'a.

[0077] In one embodiment, the circuit board 30 is a coreless circuit board, which includes stacked die-placement structures 31 and at least one add-in structure 32. The die-placement structure 31 forms an external circuit layer 313 on the first side 30a of the circuit board 30, which is embedded in the die-placement structure 31 and flush with and exposed on the surface of the first side 30a of the circuit board 30.

[0078] In summary, the electronic package and its manufacturing method of the present invention utilize the design of the groove to place the package in the packaging substrate, thereby significantly reducing the thickness of the electronic package. Therefore, compared with the stacked packaging of the prior art, the electronic package of the present invention can meet the requirements of thinning.

[0079] Furthermore, by forming this groove, the diameter of the conductive bumps used to connect the package and the packaging substrate can be ignored, thereby further reducing the thickness of the electronic package. Also, since the package is only disposed in the groove of the packaging substrate without forming a packaging layer to cover it, compared to conventional stacked packaging, the electronic package of the present invention can avoid heat accumulation, and the groove can more effectively dissipate the heat generated by the package.

[0080] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0081] 1: Semiconductor package 1a: Packaging module 10: Semiconductor wafers 101: Conductive bump 11: First packaging substrate 110, 120: Core Layer 111, 121: Line layer 12: Second packaging substrate 15: Encapsulating colloid 16: Base rubber 17: Solder pillar 19: Solder ball 2, 3: Electronic packages 2a, 3a: Packaging substrate 20: Core Layer 20', 30: Circuit board body 20a: First surface 20b: Second surface 20'a, 30a: First side 20'b, 30b: Second side 200:Ontology 200a, 200b: Surface 201, 341: First metal layer 202, 343: Second metal layer 21, 312: First line layer 22: Conductive structure 220: Through hole 23, 32: Add-on structure 31: Crystal structure 230, 310: First dielectric layer 230a, 310a: First blind hole 231, 311: First conductive pillar 232, 313: External Line Layer 322: Second Line Layer 24, 33: First insulating layer 240, 330: Opening 25, 34: Line Structure 25a, 34a: Third line layer 250, 320: Second dielectric layer 251: Third metal layer 252, 321: Second conductive pillar 252a, 320a: Second blind hole 253: Fourth metal layer 26, 35: Second insulating layer 27, 36: First conductive bumps 340: Third dielectric layer 340a: Third blind hole 342: Third conductive post 7: Bearing components 70:Plate body 71: Seed layer 72: Metal layer 80: First electronic component 81: Second electronic component 81a: Surface of Action 81b: Non-acting surface 810: Electrode pad 82: Connecting parts 83: Second conductive bump 9: Circuit board A, A': Set the region H, H1, H2: Thickness S, S': Groove

Claims

1. An electronic package, comprising: The circuit board has a first side and a second side facing each other, and the first side of the circuit board defines a mounting area; a circuit structure is formed on the periphery of the mounting area and includes a second dielectric layer, a plurality of second conductive pillars and a third circuit layer, and is electrically connected to the circuit board; the circuit structure forms a groove in the circuit board and the mounting area, such that a portion of the circuit board is exposed outside the groove, and the groove does not extend into the circuit board; a first electronic component is disposed on the circuit board in the groove and is electrically connected to the circuit board; and a second electronic component is disposed in the groove and on the first electronic component, and the second electronic component is electrically connected to the circuit structure.

2. The electronic package as described in claim 1, wherein, The first electronic component is electrically connected to the circuit board via flip-chip bonding, and the second electronic component is electrically connected to the circuit structure via wire bonding.

3. The electronic package as described in claim 1, wherein, The circuit board has an external circuit layer on the first side, and a portion of the external circuit layer on the first side is exposed outside the mounting area. The electronic package further includes insulating layers formed on the first side and the second side of the mounting area of ​​the circuit board, respectively, to expose the portion of the external circuit layer.

4. The electronic package as described in claim 1, wherein, The circuit board system is a core-layer type circuit board body, which includes a core layer and two additional layers formed on opposite surfaces of the core layer. An external circuit layer is formed on the additional layers on opposite surfaces of the core layer, and the circuit board body contacts and is electrically connected to the circuit structure on the external circuit layer on the first side.

5. The electronic package as described in claim 1, wherein, The circuit board system is a coreless circuit board body, which includes stacked die-placement structures and at least one add-in structure. The die-placement structure forms an external circuit layer on the first side of the circuit board body, which is embedded in the die-placement structure and flush with and exposed on the surface of the first side of the circuit board body.

6. A method for manufacturing an electronic package, comprising: A circuit board is provided, wherein the circuit board system has a first side and a second side opposite to each other, and the first side of the circuit board defines a mounting area; a circuit structure is formed around the mounting area, the circuit structure including a second dielectric layer, a plurality of second conductive pillars and a third circuit layer, for electrically connecting the circuit board, and the circuit structure forms a groove in the mounting area of ​​the circuit board, such that a portion of the circuit board is exposed outside the groove, and the groove does not extend into the circuit board; a first electronic component is disposed on the circuit board in the groove for electrically connecting the circuit board; and a second electronic component is disposed in the groove and on the first electronic component, and electrically connected to the circuit structure.

7. The method for manufacturing an electronic package as described in claim 6, wherein, The first electronic component is electrically connected to the circuit board via flip-chip bonding, and the second electronic component is electrically connected to the circuit structure via wire bonding.

8. The method for manufacturing an electronic package as described in claim 6, wherein, The circuit board has an external circuit layer on the first side, and a portion of the external circuit layer on the first side is exposed outside the placement area. The manufacturing method of the electronic package further includes forming an insulating layer on the first side and the second side of the placement area of ​​the circuit board before placing the first electronic component, thereby exposing the portion of the external circuit layer.

9. The method for manufacturing an electronic package as described in claim 6, wherein, The circuit board system is a core-layer type circuit board body, which includes a core layer and two additional layers formed on opposite surfaces of the core layer. An external circuit layer is formed on the additional layers on opposite surfaces of the core layer, and the circuit board body contacts and is electrically connected to the circuit structure on the external circuit layer on the first side.

10. A method for manufacturing an electronic package as described in claim 6, wherein, The circuit board system is a coreless circuit board body, which includes stacked die-placement structures and at least one add-in structure. The die-placement structure forms an external circuit layer on the first side of the circuit board body, which is embedded in the die-placement structure and flush with and exposed on the surface of the first side of the circuit board body.

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