Memory cell, integrated circuit, and forming method of gain-cell random access memory

Abstract

A memory cell includes: a write transistor on a substrate and including a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor on a substrate and including a second gate terminal coupled to the storage node; and a capacitor spaced apart from the first read transistor and the write transistor and further spaced apart from the substrate by means of the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node and the memory cell has a first area and the capacitor has a second area, the ratio of the second area to the first area being equal to or less than 0.8.

Description

Technical Field

[0001] The embodiments of the present invention relate to a memory and a method for forming the same, and more specifically to a gain unit random access memory unit and a method for forming the same. Prior Technology

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. With the development of ICs, various memory storage methods have been developed to meet diverse needs. One advancement in memory storage development is random access memory (RAM). RAM is a form of memory that can be read or written in any order. Summary of the Invention

[0003] According to some embodiments, a memory cell includes a write transistor, a first read transistor, and a capacitor. The write transistor is on a substrate and includes a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node. The first read transistor is on the substrate and includes a second gate terminal coupled to the storage node. The capacitor is spaced apart from the first read transistor and the write transistor, and further spaced apart from the substrate by the first read transistor and the write transistor. The capacitor is coupled to the storage node. The memory cell has a first area, and the capacitor has a second area. The ratio of the second area to the first area is equal to or less than 0.8.

[0004] According to some embodiments, an integrated circuit includes a plurality of memory cells, write bit lines, and write word lines. Each memory cell has a first region comprising a plurality of columns and a plurality of rows. Each of the plurality of memory cells includes a write transistor, a first read transistor, and a capacitor. The write transistor includes a first gate terminal, a first source / drain region, and a second source / drain region electrically coupled to a storage node. The first read transistor includes a second gate terminal, a third source / drain region, and a fourth source / drain region electrically coupled to the storage node. The capacitor is electrically coupled to the storage node and has a second area, wherein the ratio of the second area to the first area in the first region is equal to or less than 0.8. The write bit lines are electrically coupled to the first source / drain region of each of the plurality of memory cells in the first row of the plurality of rows, and the write word lines are electrically coupled to the first gate terminal of each of the plurality of memory cells in the first column of the plurality of columns.

[0005] According to some embodiments, a method for forming a gain unit random access memory cell includes: forming an isolation region in a substrate; forming a write transistor, a first read transistor, and a second read transistor on the substrate, wherein the write transistor is spaced apart from the first read transistor and the second read transistor by means of the isolation region; forming a first conductor layer on the substrate, the first conductor layer including write bit lines, read bit lines, and a plurality of interconnect conductors, wherein the write bit lines are coupled to a first source / drain region of the write transistor and the read bit lines are coupled to a first source / drain region of the second read transistor. The first read transistor has a source / drain region; a second conductor layer is formed above the first conductor layer, the second conductor layer including a storage node, wherein the storage node is coupled to a second source / drain region of the write transistor and a gate terminal of the first read transistor; and a capacitor is formed above the second conductor layer, the capacitor having a lower electrode coupled to the storage node, a high-dielectric-constant dielectric material overlying the lower electrode, and an upper electrode overlying the high-dielectric-constant dielectric material; and thermal annealing is performed after forming the capacitor, the thermal annealing causing the material of the high-dielectric-constant dielectric material to transform into a highly symmetrical crystalline phase. Simple Explanation of the Diagram

[0006] The best understanding of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1A-1E show circuit diagrams of various embodiments of a gain cell random access memory (GCRAM) cell with capacitors coupled to the storage node. Figures 2A-2B show top and three-dimensional views of some embodiments of a GCRAM cell with capacitors coupled to the storage node and two parallel read transistors. Figures 3A-3B show top and three-dimensional views of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two serially connected read transistors. Figures 4A-4E show cross-sectional views of various embodiments of the capacitors in the GCRAM cell. Figures 5A-5C show three-dimensional views of some embodiments of the crystalline phase of a high dielectric constant dielectric material coupled to a capacitor within a GCRAM cell. Figures 6A-6B show graphs of some embodiments comparing the voltage measured in a GCRAM cell using a capacitor at the storage node with the voltage measured in a GCRAM cell without a capacitor at the storage node. Figure 7 shows a circuit diagram of some embodiments of a GCRAM array that includes multiple columns and rows of GCRAM cells. Figure 8 shows timing diagrams of read and write operations performed by some embodiments of the circuit shown in Figure 1C. Figures 9-15 show a series of three-dimensional views of some embodiments of a method for forming a GCRAM cell with a capacitor coupled to a storage node. Figure 16 shows flowcharts of some embodiments of a method for forming a GCRAM cell with a capacitor coupled to a storage node. Implementation

[0007] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0009] The gain-cell random-access memory (GCRAM) cell includes a write transistor and a read transistor. A first source / drain region of the write transistor is coupled to the write bit line, and the gate of the write transistor is coupled to the write word line. A second source / drain region of the write transistor is coupled to the gate of the read transistor, forming a storage node. Data values ​​are represented by charges at the storage node, which are stored through capacitance at the storage node. Furthermore, the capacitance at the storage node is defined by the capacitance formed by the gate dielectric layer of the read transistor. During operation, data is written to the GCRAM cell by enabling the write transistor, which forms a conductive path between the write bit line and the storage node and stores charge at the storage node. The amount of charge is based on the voltage of the write bit line and the capacitance at the storage node.

[0010] Because GCRAM cells can use only two transistors, they offer a smaller footprint (i.e., the space occupied by the memory cell on the substrate) than other types of memory. This smaller footprint allows GCRAM cells to form smaller and / or denser memory arrays than other types of memory. For example, a two- or three-transistor GCRAM array can be half the size and / or up to twice the density compared to a six-transistor static RAM (SRAM) array. Therefore, GCRAM arrays are suitable for a wide range of digital applications, including embedded memory, artificial intelligence applications, machine learning applications, level 2 cache, level 3 cache, etc.

[0011] While GCRAM cells offer many advantages, even the simplest GCRAM cell has several drawbacks. Due to the low capacitance at the storage node, GCRAM cells have lower charge retention than other memory cells. Furthermore, read and write transistors exhibit leakage currents (e.g., subthreshold leakage from the write transistor and gate leakage from either transistor), which can discharge or introduce unwanted charge at the storage node. The relatively small charge retained at the storage node, coupled with leakage currents, results in the lower charge retention capacity of GCRAM cells compared to other types of memory. One solution is to introduce one or more refresh circuits to maintain the charge of the GCRAM cells in the array. However, using refresh circuits increases the space on the substrate dedicated to the GCRAM array and increases the power required to maintain the array, leading to a loss of power efficiency. Therefore, a GCRAM cell with enhanced retention time is needed without sacrificing the relatively small footprint of the GCRAM cell.

[0012] This disclosure provides a GCRAM cell having a capacitor with read transistors and write transistors vertically stacked. For example, the capacitors may be overlaid on the read and write transistors in the back-end-of-line (BEOL) of the integrated circuit (IC), while the read and write transistors may be in the front-end-of-line (FEOL) of the IC.

[0013] The capacitor is coupled in parallel to the capacitance formed by the gate dielectric of the read transistor to the storage node. This increases the capacitance at the storage node, thereby increasing the charge on the storage node during writing. Since leakage current takes longer to deplete the charge on the storage node, this increase results in a longer retention time. Furthermore, because the voltage at the storage node is proportional to the charge, the gate voltage of the read transistor remains at the write value for a longer period. In some embodiments, the improved retention capability is more than 100 times longer than the retention time of a GCRAM cell without a capacitor. Additionally, because the lateral area is smaller than that of a GCRAM cell without a capacitor, the capacitor does not increase the occupied area of ​​the GCRAM cell.

[0014] Figures 1A-1E show circuit diagrams of various embodiments of a GCRAM cell with capacitors coupled to the storage node. Figures 1A and 1C correspond to embodiments with two transistors, while Figures 1B and 1D correspond to embodiments with three transistors.

[0015] As shown in circuit diagram 100a of Figure 1A, write transistor 102 and first read transistor 104a are coupled together at storage node 106. Write transistor 102 includes a first source / drain region 108, a first gate terminal 110, and a second source / drain region 112. As used herein, one or more source / drain regions may refer individually or collectively to a source region or a drain region, depending on the context. First source / drain region 108 is coupled to write bit line 114. First gate terminal 110 is coupled to write word line 116. Second source / drain region 112 is coupled to storage node 106. First read transistor 104a includes a third source / drain region 118, a second gate terminal 120, and a fourth source / drain region 122. In some embodiments, third source / drain region 118 is coupled to read word line 124. In a further embodiment, the fourth source / drain region 122 is coupled to the read bit line 126. The second gate terminal 120 is coupled to the storage node 106.

[0016] Capacitor 128 is coupled to storage node 106 and ground wire 130. In some embodiments, capacitor 128 is a three-dimensional BEOL capacitor. In other embodiments, capacitor 128 is a two-dimensional BEOL capacitor comprising a high-dielectric-constant dielectric with a highly symmetrical crystalline phase. In yet another embodiment, capacitor 128 is a three-dimensional BEOL capacitor comprising a high-dielectric-constant dielectric with a highly symmetrical crystalline phase. Capacitor 128 has a first capacitance. First read transistor 104a has a gate dielectric layer with a second capacitance 129. For clarity, the second capacitance 129 is shown separately from the first read transistor 104a; the second capacitance 129 is not a separate capacitor but is measured on the gate dielectric layer of the first read transistor 104a. The first capacitance is more than twice that of the second capacitance 129, and capacitor 128 is electrically coupled in parallel with the second capacitance 129. Therefore, the introduction of capacitor 128 increases the capacitance at storage node 106 by at least three times. The increased capacitance at storage node 106 results in an increase in the charge stored at storage node 106 during write operations. This increased stored charge causes the leakage current of the write transistor 102 and the first read transistor 104a to require a longer time to reduce the stored charge. Therefore, data retention increases.

[0017] GCRAM cells can store either "1" bits or "0" bits. A "1" bit is stored during a write operation, where write bit line 114 is at a voltage higher than the threshold voltage of the first read transistor 104a (e.g., Vdd). A "0" bit is stored during a write operation, where write bit line 114 is at a voltage lower than the threshold voltage of the first read transistor 104a (e.g., 0 volts). During a write operation, write transistor 102 is enabled, and charge flows between write bit line 114 and storage node 106, causing storage node 106 to maintain the voltage introduced by write bit line 114. After the write operation, write transistor 102 is deactivated, thereby isolating write bit line 114 from storage node 106. Charge remains at storage node 106, causing storage node 106 to maintain the voltage introduced by write bit line 114. During a read operation, the read bit line 126 is pre-charged by applying a voltage (e.g., Vdd) for a certain time interval, and then the voltage of the read word line 124 is set to 0 to read the stored bit. Then, after the read time interval, the obtained signal is read by reading the voltage of the read bit line 126. If the voltage measured at the read bit line 126 is equal to or approximately equal to the applied voltage, the voltage at the storage node is not higher than the threshold voltage, and the stored voltage is determined to be a "0" bit. If the voltage measured at the read bit line 126 is at or approximately zero volts, the voltage at the storage node is higher than the threshold voltage, and the stored voltage is determined to be a "1" bit.

[0018] The voltage at storage node 106 is based on the voltage provided by write bit line 114 during a write operation. The voltage at storage node 106 is maintained by the presence of charge held at storage node 106 and is proportional to the charge held at storage node 106. Therefore, when leakage currents (e.g., gate leakage, subthreshold leakage, junction leakage, etc.) from write transistor 102 and first read transistor 104a change the charge held at storage node 106, the voltage is also affected.

[0019] When the voltage at storage node 106 is at or near the threshold voltage of the first read transistor, noise in the IC housing the GCRAM cell can make the read operation unpredictable. That is, if leakage current causes the retention voltage to approach the threshold voltage, the determination of the stored signal will be dominated by noise. The time required for leakage current to introduce or remove enough charge to bring the voltage at storage node 106 to the threshold voltage is called the retention time of the GCRAM cell. The increased capacitance and charge at storage node 106 due to the introduction of capacitor 128 results in a longer retention time. This can further reduce the occupied area of ​​the GCRAM array by reducing the number of update circuits used to maintain the charge of the storage nodes. The reduction in update circuitry can further reduce power consumption.

[0020] As shown in circuit diagram 100b of Figure 1B, in some embodiments, a second read transistor 104b is coupled to a first read transistor 104a. The second read transistor 104b has a fifth source / drain region 132 coupled to a fourth source / drain region 122, a third gate terminal 134 coupled to a read word line 124, and a sixth source / drain region 136 coupled to a read bit line 126. A third source / drain region 118 is coupled to a reset line 138, which is grounded during read operations.

[0021] During a read operation, a GCRAM cell is selected from the GCRAM array to read by applying a voltage (e.g., Vdd) to read bit line 126 and a high voltage to read word line 124. The high voltage is because it exceeds the threshold voltage of the second read transistor 104b. The voltage on read bit line 126 is then measured. If the voltage measured at read bit line 126 is equal to or approximately equal to the applied voltage, the voltage at the storage node is not higher than the threshold voltage, and the storage voltage is determined to be a "0" bit. If the voltage measured at read bit line 126 is at or approximately zero volts, the voltage at the storage node is higher than the threshold voltage, and the storage voltage is determined to be a "1" bit.

[0022] As shown in circuit diagrams 100c and 100d of Figures 1C and 1D, in some embodiments, the circuits shown in Figures 1A and 1B have an N-type write transistor 102. The write transistor 102 and the first read transistor 104a are or include P-type or N-type transistors. In some embodiments, the write transistor 102 and the first read transistor 104a are the same transistor type (e.g., both are N-type transistors). In other embodiments, as shown in Figures 1A and 1B, the write transistor 102 and the first read transistor 104a are different transistor types (e.g., the write transistor 102 is a P-type transistor and the first read transistor 104a is an N-type transistor).

[0023] As shown in circuit diagram 100e of Figure 1E, in some embodiments, the GCRAM cell may include a plurality of transistors connected in parallel between read bit line 126 and read word line 124, the plurality of transistors including a first read transistor 104a and a parallel transistor 140. The second gate terminal 120 of the first read transistor 104a and the fourth gate terminal 142 of the parallel transistor 140 are coupled in parallel to the storage node 106. The parallel transistor 140 has a seventh source / drain region 144, which is coupled in parallel to the fourth source / drain region 122 of the first read transistor 104a to the read bit line 126. The first read transistor 104a and the parallel transistor 140 share a third source / drain region 118.

[0024] Figures 2A-2B show a top view 200a and a three-dimensional view 200b of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two parallel read transistors. The GCRAM cell shown in Figures 2A-2B is one embodiment of the circuit shown in Figure 1E. Figures 2A and 2B are described simultaneously.

[0025] The second gate terminal 120 of the first read transistor 104a and the fourth gate terminal 142 of the parallel transistor 140 are coupled to the storage node 106 through multiple contacts 206 (as shown in FIG. 2A) and a first via layer 208 (see FIG. 2B). The seventh source / drain region 144 of the parallel transistor 140 is coupled in parallel to the fourth source / drain region 122 of the first read transistor 104a to the read bit line 126. The first read transistor 104a and the parallel transistor 140 share a third source / drain region 118.

[0026] The plurality of contacts 206 further extend to the first gate terminal 110 and the first, second, third, and fourth source / drain regions (108, 112, 118, 122). The plurality of contacts 206 extend to a first conductor layer, which includes a write bit line 114, a read bit line 126, and an interconnect 207. The read bit line 126 and the write bit line 114 extend in a first direction 228. A first via layer 208 extends between the first conductor layer and a second conductor layer including the storage node 106. In some embodiments, the write word line 116 and / or the read word line 124 are on the second conductor layer. The write word line 116 and the read word line 124 extend in a second direction 230 perpendicular to the first direction 228.

[0027] A capacitor 128 (as shown in FIG. 2A) is overlaid on a storage node 106 on a third direction 232 and coupled to the storage node 106 through a second via layer 210. The capacitor 128 is further overlaid on a write transistor 102, a first read transistor 104a, and a parallel transistor 140. In some embodiments, a third conductor layer 212 extends between the capacitor 128 and the storage node 106. The third conductor layer 212 serves as a platform for a third via layer 214 extending between the third conductor layer 212 and the capacitor 128. The capacitor 128 is further coupled to a ground conductor 130 through a fourth via layer 216.

[0028] In some embodiments, capacitor 128 includes a lower electrode 218, a high-dielectric-constant dielectric 220, and an upper electrode 222. In alternative embodiments, the high-dielectric-constant dielectric 220 is replaced with a dielectric that does not have a high dielectric constant. The lower electrode 218 and the upper electrode 222 comprise conductive materials such as aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), platinum (Pt), tungsten (W), nickel (Ni), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaxNy), iridium oxide (IrO2), negatively doped polycrystalline silicon, positively doped polycrystalline silicon, or the like. High dielectric constant dielectrics include one or more metal oxides (e.g., hafnium oxide (HfxOy, HfO2), hafnium silicon oxide (HfxSiyOz), hafnium aluminum oxide (HfxAlyOz), hafnium gadolinium oxide (HfxGdyOz), hafnium zirconium oxide (HfxZryOz), hafnium lanthanum oxide (HfxLayOz), hafnium strontium oxide (HfxSryOz), hafnium yttrium oxide (HfxYyOz), titanium strontium oxide (STO, SrTiO3), zirconium oxide (ZrO2), titanium oxide (TiO2), barium titanate (BaTiO3), etc.), metal nitrides (e.g., hafnium oxynitride (HfON), zirconium oxynitride (ZrON)) or similar.

[0029] In some embodiments, the high-dielectric-constant dielectric has a highly symmetrical crystalline phase, such as a cubic, tetragonal, or hexagonal phase. High-dielectric-constant dielectric materials with highly symmetrical crystalline phases have a larger dielectric constant than those without highly symmetrical crystalline phases. The dielectric constant of a high-dielectric-constant dielectric depends on the materials constituting the high-dielectric-constant dielectric and the symmetry of the crystalline phases of those materials. In some embodiments, the high-dielectric-constant dielectric 220 has a dielectric constant greater than 35. A dielectric constant greater than 35 results in capacitor 128 having a capacitance more than twice that at the gate dielectric layers of the first read transistor 104a and the parallel transistor 140, without increasing the capacitor area by more than 60% to 80% of the GCRAM cell area. In some embodiments, if the dielectric constant is less than 35, capacitor 128 will have a lower capacitance, thereby reducing the charge held at the storage node and the resulting GCRAM cell retention time. When using a three-dimensional capacitor configuration (see Figures 4B-4E), the capacitance can be further increased.

[0030] In some embodiments, the write transistor 102, the first read transistor 104a, and the parallel transistor 140 are FEOL devices embedded in the substrate 224. The write transistor 102 and the first read transistor 104a are further separated by an isolation region 226. In some embodiments, the FEOL device is or includes one or more planar FETs, finned FETs, gate-all-around (GAA) devices, etc. In some embodiments, when viewed from top to bottom, the first read transistor 104a, the write transistor 102, and the second read transistor 104b together span a first area, and wherein, when viewed from top to bottom, the capacitor 128 spans a second area, the second area being between 60% and 80% of the first area.

[0031] Figures 3A-3B show a top view (300a) and a three-dimensional view (300b) of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two series-connected read transistors. The GCRAM cell shown in Figures 3A-3B is one embodiment of the circuit shown in Figure 1B. Figures 3A and 3B are described simultaneously. For clarity, write word line 116 and read word line 124 are not shown in Figures 3A and 3B.

[0032] In some embodiments, the first read transistor 104a and the second read transistor 104b are coupled in series. In a further embodiment, the fourth source / drain region 122 of the first read transistor 104a and the fifth source / drain region 132 of the second read transistor 104b overlap each other to form a common source / drain region 302. The common source / drain region 302 extends from the channel of the first read transistor 104a to the channel of the second read transistor 104b. The storage node 106 is coupled to the second source / drain region 112 of the write transistor 102 and the second gate terminal 120 of the first read transistor 104a, but not to the third gate terminal 134 of the second read transistor 104b. The third gate terminal 134 of the second read transistor 104b is instead coupled to the read word line 124.

[0033] In some embodiments, a first read transistor 104a, a write transistor 102, and a second read transistor 104b are located within a first GCRAM cell region 304, the first GCRAM cell region 304 having a first area measured parallel to the upper surface of the substrate 224. A capacitor 128 has a second area measured parallel to the upper surface of the substrate 224. The second area is between 60% and 80% of the first area. In some embodiments, the first GCRAM cell region 304 has an outer boundary in a second direction 230 between the outermost outer wall of the first write transistor 102 and the outermost outer wall of the first read transistor 104a, and is confined in a first direction between the outer edge of the first source / drain region 108 and the outer edge of the third source / drain region 118.

[0034] The area of ​​capacitor 128 is smaller than the area of ​​the first GCRAM cell region 304, resulting in remaining area at the level of capacitor 128 that can be used to route vias (e.g., the first via 306) between capacitor 128 and other capacitors in the GCRAM cell array. The availability of space around capacitor 128 and above the first GCRAM cell region 304 for routing the first via 306 increases implementation flexibility while reducing the footprint in embodiments using wiring between capacitors. The first via 306 is flush with capacitor 128 and extends between the third conductor layer 212 and the fourth conductor layer 308, which is flush with the ground conductor 130.

[0035] Figures 4A-4E show cross-sectional views (400a, 400b, 400c, 400d, 400e) of various embodiments of the capacitor in the GCRAM cell.

[0036] As shown in Figure 4A, in some embodiments, capacitor 128 has a planar layout. The lower electrode 218 has a first thickness t1 between about 0.1 nm and 30 nm, between about 1 nm and 20 nm, or other similar ranges. The high-dielectric-constant dielectric 220 has a second thickness t2 between about 1 nm and 10 nm, between about 2 nm and 8 nm, or other similar ranges. The upper electrode 222 has a third thickness t3 between about 0.1 nm and 30 nm, between about 1 nm and 20 nm, or other similar ranges. Capacitor 128 and other components of the GCRAM cell on the substrate (see, for example, 224 in Figure 2B) are surrounded by an interlayer dielectric 406. For clarity, the interlayer dielectric 406 is not shown in the previous figures.

[0037] As shown in Figure 4B, in some embodiments, capacitor 128 has a three-dimensional layout with a protrusion 404 extending from the base 402 of the upper electrode 222. The addition of the protrusion 404 increases the surface area of ​​the electrodes in capacitor 128, thereby increasing capacitance. In some embodiments, the high-dielectric-constant dielectric 220 does not have a highly symmetrical crystalline phase because the three-dimensional layout increases the capacitance of capacitor 128 to more than twice the capacitance of the first readout transistor (see 104a in Figure 1A) and the parallel transistor (see 140 in Figure 2A, if present).

[0038] As shown in FIG4C, in some embodiments, capacitor 128 has a cylindrical three-dimensional layout, wherein lower electrode 218 surrounds cylindrical protrusion 408 from upper electrode 222. As shown in FIG4D, in some embodiments, capacitor 128 has a multi-finned three-dimensional layout, wherein lower electrode 218 includes a plurality of fins 410 surrounded by upper electrode 222. As shown in FIG4E, in some embodiments, capacitor 128 has a multi-finged three-dimensional layout, wherein lower electrode 218 surrounds dielectric structure 412 including a plurality of protrusions 414, and upper electrode 222 also surrounds the plurality of protrusions 414.

[0039] Figures 5A-5C show three-dimensional views (500a, 500b, 500c) of some embodiments of the crystalline phase of a high dielectric constant within a capacitor coupled to a GCRAM cell. In some embodiments, the highly symmetrical crystalline phase includes one of a cubic, tetragonal, or hexagonal phase.

[0040] As shown in the three-dimensional view 500a of Figure 5A, in some embodiments, the high dielectric constant dielectric (see, for example, 220 in Figure 2B or Figure 3B) has a cubic phase. In the cubic phase, the first lattice constant a1, the second lattice constant a2, and the third lattice constant a3 have equal lengths. The lattice constants (a1, a2, a3) represent the length of the unit cell along different repeating axes. In the cubic phase, the first lattice angle α, the second lattice angle β, and the third lattice angle γ are equal to 90 degrees. The lattice angles (α, β, γ) represent the angles between the unit cell and the lattice constants.

[0041] As shown in the three-dimensional view 500b of Figure 5B, in some embodiments, the high dielectric constant dielectric (see, for example, 220 in Figure 2B or Figure 3B) has a tetragonal phase. In the tetragonal phase, the first lattice constant a1 and the second lattice constant a2 have equal lengths, and the third lattice constant a3 has a different length than the first lattice constant a1 and the second lattice constant a2. Furthermore, the first lattice angle α, the second lattice angle β, and the third lattice angle γ of the unit cell of the tetragonal phase are all equal to 90 degrees.

[0042] As shown in the three-dimensional view 500c of Figure 5C, in some embodiments, the high dielectric constant dielectric (see, for example, 220 in Figure 2B or Figure 3B) has a hexagonal phase. In the hexagonal phase, the first lattice constant a1, the second lattice constant a2, and the third lattice constant a3 have the same length, and the fourth lattice constant c has a different length than the first lattice constant a1. Furthermore, the first lattice angle α, the second lattice angle β, and the third lattice angle γ of the hexagonal phase unit cell are equal to 120 degrees, while the fourth lattice angle γ is equal to 90 degrees.

[0043] Figures 6A-6B show graphs 600a, 600b of some embodiments comparing the voltage measured in a GCRAM cell using a capacitor at the storage node with the voltage measured in a GCRAM cell without a capacitor at the storage node.

[0044] As shown in graph 600a of Figure 6A, in the embodiment where a capacitor (see 128 in Figure 1A) is present at the storage node (see 106 in Figure 1A), for the first time period 603, the first voltage 602 measured at the storage node when a "1" bit is written to the GCRAM cell is higher than the second voltage 604 measured at the storage node when a "0" bit is written to the GCRAM cell. Furthermore, in the embodiment where no capacitor (see 128 in Figure 1A) is present at the storage node (see 106 in Figure 1A), for the second time period 607, the third voltage 606 measured at the storage node when a "1" bit is written to the GCRAM cell is higher than the fourth voltage 608 measured at the storage node when a "0" bit is written to the GCRAM cell. That is, after the second time period 607, in the embodiment without a capacitor, the voltage measured at the storage node (see 106 in Figure 1A) no longer indicates the initial stored value. The first time period 603 is greater than the second time period 607. In some embodiments, where the first capacitance of the capacitor (see 128 in Figure 1A) is more than twice the second capacitance measured at the gate dielectric layer of the first readout transistor, the first time period 603 is more than 100 times the second time period 607.

[0045] As shown in graph 600b of Figure 6B, in an embodiment where there is a capacitor (see 128 in Figure 1B) at the storage node (see 106 in Figure 1B) and the second read transistor (see 104b in Figure 1B), the first difference 610 between the voltage measurements performed at the read bit line when a "1" bit is stored and when a "0" bit is stored is a first value 614 after the first time period 615. When a "1" bit is stored at the storage node and is not updated, the voltage measurement difference 610 is discovered by measuring the voltage of the read bit line (see 126 in Figure 1B) at multiple time intervals. Then, the voltage at the read bit line (see 126 in Figure 1B) when a "0" bit is stored at the storage node is measured at multiple time intervals. The difference 610 of the voltage measurements shown in graph 600b is obtained by subtracting the obtained "0" bit voltage measurement value from the "1" bit voltage measurement.

[0046] In embodiments where no capacitor is present at the storage node (see 106 in FIG. 1A) (see 128 in FIG. 1A), the second difference 612 of the voltage measurement performed at the read bit line when storing a "1" bit and when storing a "0" bit is at a second value 616 after a first time period 615. In both embodiments, the voltage difference between the "1" bit reading and the "0" bit reading decays over time. However, in embodiments where a capacitor (see 128 in FIG. 1A) is coupled to the storage node (see 106 in FIG. 1A), the initial voltage difference between the two measurements is greater than the voltage difference measured in the embodiment without a capacitor (see 128 in FIG. 1A). Furthermore, in embodiments where a capacitor (see 128 in FIG. 1A) is coupled to the storage node (see 106 in FIG. 1A), the voltage difference between two measurements at subsequent measurement intervals is also greater than the voltage difference measured in the embodiment without a capacitor (see 128 in FIG. 1A). The voltage measurement difference 610 of the embodiment with a capacitor (see 128 in FIG. 1A) decays at a slower rate than the voltage measurement difference 612 of the embodiment without a capacitor (see 128 in FIG. 1A).

[0047] Figure 7 shows a circuit diagram 700 of some embodiments of a GCRAM array including multiple columns and rows of GCRAM cells.

[0048] The GCRAM array includes multiple columns (704a, 704b, 704c) and rows (706a, 706b) containing multiple GCRAM cells (702a-702f). GCRAM cells in the first row 706a (e.g., first GCRAM cell 702a, second GCRAM cell 702b, and third GCRAM cell 702c) are coupled to a first write bit line 114a and a first read bit line 126a. GCRAM cells in the second row 706b (e.g., fourth GCRAM cell 702d, fifth GCRAM cell 702e, and sixth GCRAM cell 702f) are coupled to a second write bit line 114b and a second read bit line 126b. GCRAM cells in the first column 704a (e.g., first GCRAM cell 702a and fourth GCRAM cell 702d) are coupled to a first write word line 116a and a first read word line 124a. The GCRAM cells in the second column 704b (e.g., the second GCRAM cell 702b and the fifth GCRAM cell 702e) are coupled to the second write word line 116b and the second read word line 124b. The GCRAM cells in the third column 704c (e.g., the third GCRAM cell 702c and the sixth GCRAM cell 702f) are coupled to the third write word line 116c and the third read word line 124c.

[0049] The first GCRAM cell 702a is shown coupled to the first write bit line 114a, the first write word line 116a, the first read bit line 126a, and the first read word line 124a. The second GCRAM cell 702b and the third GCRAM cell 702c are located in the first row 706a of the plurality of rows, along with the first GCRAM cell 702a. The second GCRAM cell 702b and the third GCRAM cell 702c are coupled to the first write bit line 114a and the first read bit line 126a, but the second GCRAM cell 702b is coupled to the second write word line 116b and the second read word line 124b, while the third GCRAM cell 702c is coupled to the third write word line 116c and the third read word line 124c. The first GCRAM cell 702a and the fourth GCRAM cell 702d are located in the first column 704a of the plurality of rows. The first GCRAM cell 702a and the fourth GCRAM cell 702d are coupled to the first write word line 116a and the first read word line 124a, but the fourth GCRAM cell 702d is coupled to the second write word line 116b and the first read word line 124a.

[0050] Figure 8 shows a timing diagram 800 of read and write operations performed by some embodiments of the circuit shown in Figure 1C.

[0051] Timing diagram 800 illustrates the signals provided to the GCRAM cell during operation. When a "1" bit is written, the write bit line (see 114 in Figure 1B) is driven to a high voltage (e.g., Vdd) during write operation 802, as shown by write bit line signal 114sa. When a "0" bit is written, the write bit line (see 114 in Figure 1B) is driven to a low voltage (e.g., 0 volts) during write operation 802, as shown by second write bit line signal 114sb. In some embodiments where the write transistor (see 102 in Figure 1B) is a p-type transistor, the write word line (see 116 in Figure 1B) is driven to a low voltage (e.g., -Vdd) below the threshold voltage of the write transistor (see 102 in Figure 1B), as shown by write word line signal 116s, coupling the write bit line (see 114 in Figure 1B) to the storage node (see 106 in Figure 1B) for a period of time 802g. Then the write character line signal returns to its original voltage (e.g., 0 volts) after 116 seconds until another write operation is required.

[0052] Prior to read operation 804, the read bit line (see 126 in Figure 1B) is driven to a high voltage (e.g., Vdd), as shown in the pre-charge phase 806 of read bit line signal 126s. Read operation 804 begins for a duration T0 during which the read word line (see 124 in Figure 1B) is driven to a high voltage (e.g., Vdd), as shown in read word line signal 124s. The read word line signal 124s, rising above the threshold voltage of the second read transistor (see 104b in Figure 1B), couples the read bit line signal 126s to the fourth source / drain region 122 of the first read transistor (see 104a in Figure 1B). Subsequently, if a "1" bit is stored at the storage node (see 106 in FIG. 1B), the read bit line signal 126s is driven to a low voltage (e.g., 0 volts) during period 808 due to coupling to the reset line (see 138 in FIG. 1B), which remains at 0 volts during read operation 804. If a "0" bit is stored at the storage node (see 106 in FIG. 1B), the read bit line signal 126s will remain at a high voltage (e.g., Vdd) during period 808 because the first read transistor will not be activated and the reset line (see 138 in FIG. 1B) will not be coupled to the read bit line (see 126 in FIG. 1B). After returning the read bit line signal 126s to a high voltage (e.g., Vdd) in another precharge phase, the read operation can be repeated in time periods T1 and T2.

[0053] Figures 9-15 illustrate a series of three-dimensional views (900-1500) of some embodiments of a method for forming a GCRAM cell with capacitors coupled to a storage node. While Figures 9-15 are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted, in whole or in part.

[0054] As shown in the three-dimensional view 900 of Figure 9, an isolation region 226 is formed within a substrate 224. In some embodiments, the isolation region 226 is a shallow trench isolation region, a deep trench isolation region, or other types of isolation region. In some embodiments, the substrate 224 is or includes silicon, sapphire, the like, or any combination thereof. In some embodiments, the isolation region 226 is or includes an insulating material, such as silicon oxide (SiO2), silicon nitride (Si3N4), or the like. The isolation region 226 is formed by etching openings in the substrate and then filling the openings with an insulating material.

[0055] As shown in the three-dimensional view 1000 of Figure 10, a write transistor 102, a first read transistor 104a, and a parallel transistor 140 are formed on a substrate 224. The transistors (e.g., write transistor 102, first read transistor 104a, and parallel transistor 140) are formed by forming gate dielectric layers and gate terminals (e.g., first gate terminal 110, second gate terminal 120, and fourth gate terminal 142) stacked over channel regions in the substrate 224. The gate dielectric layer and gate terminals are formed by depositing a conformal gate dielectric layer and a conformal gate material (e.g., polysilicon) layer on the substrate 224. The conformal gate dielectric layer and conformal gate material layer are then patterned to form the gate dielectric layer and gate terminals. After forming the gate dielectric layer and gate terminals, dopants are implanted into the substrate 224 to form source / drain regions (e.g., first, second, third, fourth, and seventh source / drain regions (e.g., 108, 112, 118, 122, 144)). In some embodiments, an additional gate replacement step is performed to form gate terminals comprising a conductive metal or metal nitride, such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), or the like. In some embodiments, the first gate terminal 110, the second gate terminal 120, and the fourth gate terminal 142 extend over the isolation region 226.

[0056] As shown in the three-dimensional view 1100 of Figure 11, the plurality of contacts 206 and the first conductive layer are formed above the substrate 224. In some embodiments, the first conductive layer includes read bit lines 126, write bit lines 114, and interconnects 207. In some embodiments, the plurality of contacts 206 and / or the first conductive layer includes a conductive material, such as aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), platinum (Pt), tungsten (W), nickel (Ni), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), negatively doped polycrystalline silicon, positively doped polycrystalline silicon, or the like. In some embodiments, the plurality of contacts 206 and the first conductive layer are formed using a dual damascene process, one or more single damascene processes, etc.

[0057] As shown in the three-dimensional view 1200 of Figure 12, a first via layer 208 and a second conductive layer are formed above the substrate 224. The second conductive layer includes a storage node 106. In some embodiments, the second conductive layer further includes a read word line 124 and a write word line 116. In some embodiments, the first via layer 208 and the second conductive layer are made of or include the same material as the plurality of contacts 206 and / or the first conductive layer. In some embodiments, the first via layer 208 and the second conductive layer are formed using a dual damascene process, one or more single damascene processes, etc.

[0058] As shown in the three-dimensional view 1300 of Figure 13, a second via layer 210 and a third conductive layer 212 are formed above the substrate 224. The second via layer 210 couples the storage node to the third conductive layer 212. In some embodiments, the second via layer 210 and the third conductive layer 212 are made of or contain the same material as the plurality of contacts 206 and / or the first conductive layer. In some embodiments, the second via layer 210 and the third conductive layer 212 are formed using a dual damascene process, one or more single damascene processes, etc.

[0059] As shown in the three-dimensional view 1400 of Figure 14, a third via layer 214 and a capacitor 128 are formed above a third conductive layer 212. The third via layer 214 couples the lower electrode 218 of the capacitor 128 to the third conductive layer 212. In some embodiments, the third via layer 214 is or comprises the same material as the plurality of contacts 206 and / or the first conductive layer. In some embodiments, the third via layer 214 and the capacitor 128 are formed using one or more damascene processes, one or more deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.), followed by a patterning process or the like.

[0060] In other words, capacitor 128 can be formed by multiple deposition processes to create a conformal lower electrode layer, a conformal high-dielectric-constant dielectric layer, and a conformal upper electrode layer. The conformal lower electrode layer, conformal high-dielectric-constant dielectric layer, and conformal upper electrode layer are then patterned to form capacitor 128. In other embodiments, such as those shown in Figures 4A-4E, additional dry etching, wet etching, and deposition steps can be used to form a 3D capacitor on the third via layer 214.

[0061] In some embodiments, the high-dielectric-constant dielectric 220 comprises an amorphous structure when initially deposited. Thermal annealing transforms the amorphous structure into a crystalline high-dielectric-constant dielectric 220. In a further embodiment, a conformal top electrode layer is formed prior to thermal annealing to form a highly symmetrical crystalline phase with a dielectric constant greater than 35. During thermal annealing, the top electrode 222 introduces additional stress into the high-dielectric-constant dielectric 220. This additional stress causes the material of the high-dielectric-constant dielectric 220 to transform into a highly symmetrical crystalline phase, such as a cubic, tetragonal, or hexagonal phase.

[0062] As shown in the three-dimensional view 1500 of Figure 15, a fourth via layer 216 and a grounding conductor 130 are formed above the capacitor 128. The fourth via layer 216 couples the grounding conductor 130 to the upper electrode 222 of the capacitor 128. In some embodiments, the fourth via layer 216 and the grounding conductor 130 are made of or comprise the same material as the plurality of contacts 206 and / or the first conductor layer. In some embodiments, the first via layer 208 and the second conductor layer are formed using a dual damascene process, one or more single damascene processes, etc.

[0063] Figure 16 illustrates a flowchart of some embodiments of a method 1600 for forming a GCRAM cell with capacitors coupled to a storage node. While this and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the shown order or actions. Therefore, in some embodiments, the actions may be performed in a different order than shown and / or simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0064] At block 1602, an isolation zone is formed in the base. See, for example, Figure 9.

[0065] At block 1604, a write transistor, a first read transistor, and a second read transistor are formed on the substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by an isolation region. See, for example, Figure 10.

[0066] At block 1606, a first conductor layer is formed on the substrate. The first conductor layer includes write bit lines, read bit lines, and multiple interconnect conductors, wherein the write bit lines are coupled to the source / drain regions of the write transistor and the read bit lines are coupled to the source / drain regions of the second read transistor. See, for example, Figure 11.

[0067] At block 1608, a second conductor layer is formed above the first conductor layer. The second conductor layer includes a storage node, which is coupled to the second source / drain region of the write transistor and the gate terminal of the first read transistor. See, for example, Figure 12.

[0068] At block 1610, a capacitor is formed above the second conductor layer, the capacitor having a lower electrode coupled to the storage node and an upper electrode coupled to the ground wire. See, for example, Figure 14.

[0069] At block 1612, thermal annealing is performed, which causes the high dielectric constant material to transform into a highly symmetrical crystalline phase. See, for example, Figure 14.

[0070] This disclosure describes an integrated capacitor structure coupled to the storage nodes of a GCRAM device. The capacitor structure provides ultra-high dielectric properties through a highly symmetrical crystalline phase, a maximized region overlaid on the transistor structure in the GCRAM, and a minimum region contained within the GCRAM cell boundaries. This provides improved GCRAM retention time and power, and performance-per-unit-area (PPA). Furthermore, the GCRAM device features strategically designed metal layer wiring to improve spacing. To achieve this, read word line metals, write bit line metals, and read word line metals may be located in the first two wiring layers above the transistor device (e.g., read bit lines and write bit lines in the first wiring layer, and read word lines and write word lines in the second wiring layer). Each of these read word line metals, write bit line metals, and read word line metals may be a global line connection coupled to multiple GCRAM cells. To achieve a sufficient thermal budget for crystallization, lower metal locations (e.g., the third or fourth conductor layer) are used for ultra-high dielectric constant capacitors, such as metal-insulator-metal (MIM) capacitors (see Figure 4A). The capacitor structure is strategically positioned at lower metal locations (e.g., at the third or fourth conductor layer) to increase the thermal budget available for forming high dielectric constant dielectrics.

[0071] Some embodiments relate to a memory cell comprising: a write transistor on a substrate and including a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor on a substrate and including a second gate terminal coupled to the storage node; and a capacitor spaced apart from and further separated from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node, wherein the memory cell has a first area and the capacitor has a second area, wherein the ratio of the second area to the first area is equal to or less than 0.8. In some embodiments, the capacitor comprises a high dielectric constant dielectric material having a dielectric constant greater than 35. In some embodiments, the memory cell further comprises a second read transistor on a substrate, wherein, when viewed from above, the first read transistor, the write transistor, and the second read transistor together span a first region, and wherein, when viewed from above, the capacitor spans a second region, the second region being between 60% and 80% of the first region. In some embodiments, when viewed from top to bottom, the first area is defined by the span of a memory cell region including the first read transistor, the write transistor, and the second read transistor, wherein when viewed from top to bottom, the second area is defined by the span of the capacitor, and wherein the second area is between 60% and 80% of the first area. In some embodiments, the second read transistor has a third gate terminal extending in a first direction and parallel to a second gate terminal of the first read transistor, and wherein the second and third gate terminals are connected to a storage node. In some embodiments, the capacitor includes an upper electrode, a lower electrode, and a high-dielectric-constant dielectric having a symmetrical crystalline phase. In some embodiments, the symmetrical crystalline phase is a cubic, tetragonal, or hexagonal phase. In some embodiments, the capacitor includes an upper electrode, a lower electrode, and an insulator between the upper and lower electrodes, and wherein the capacitor is a three-dimensional capacitor, wherein the insulator extends along the respective sidewalls of the lower and upper electrodes. In some embodiments, the first read transistor further includes a gate dielectric layer having a first capacitance, wherein the capacitor has a second capacitance more than twice the first capacitance. In some embodiments, the memory cell further includes conductive lines above the write transistor and the first read transistor, wherein the conductive lines have an L-shaped top geometry and form a storage node.

[0072] Other embodiments relate to an integrated circuit comprising: a plurality of memory cells in a first region having a plurality of columns and a plurality of rows, each of the plurality of memory cells comprising: a write transistor including a first gate terminal, a first source / drain region and a second source / drain region electrically coupled to a storage node; a first read transistor including a second gate terminal, a third source / drain region and a fourth source / drain region electrically coupled to a storage node; and a capacitor electrically coupled to a storage node, wherein the capacitor has a second area and wherein the ratio of the second area in the first region to the first area is equal to or less than 0.8; a write bit line electrically coupled to the first source / drain region of each of the plurality of memory cells in a first row of the plurality of rows; and a write word line electrically coupled to the first gate terminal of each of the plurality of memory cells in a first column of the plurality of columns. In some embodiments, the integrated circuit further includes: a read bit line electrically coupled to a fourth source / drain region of each of the plurality of memory cells in a first row of the plurality of rows; and a read word line electrically coupled to a third source / drain region of each of the plurality of memory cells in a first column of the plurality of columns. In some embodiments, each of the plurality of memory cells has a second read transistor including a third gate terminal, a fifth source / drain region electrically coupled to the third source / drain region, and a sixth source / drain region, and wherein the integrated circuit further includes: a read bit line electrically coupled to a sixth source / drain region for each of the plurality of memory cells in the first row of the plurality of rows. In some embodiments, the first read transistor is an N-type transistor, and wherein the write transistor is a P-type transistor. In some embodiments, the plurality of memory cells are on a semiconductor substrate and include a first memory cell, wherein a write transistor and a first read transistor of the first memory cell are embedded on top of the semiconductor substrate, and wherein a capacitor of the first memory cell is overlaid on and spaced apart from the write transistor and the first read transistor of the first memory cell. In some embodiments, the plurality of memory cells include a first memory cell, and the capacitor of the first memory cell includes a high dielectric constant dielectric material with a dielectric constant greater than 35. In some embodiments, the plurality of memory cells include a first memory cell with only three transistors.

[0073] Other embodiments relate to a method of forming a gain unit random access memory (GCRAM) cell, comprising: forming an isolation region in a substrate; forming a write transistor, a first read transistor, and a second read transistor on the substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by the isolation region; forming a first conductor layer on the substrate, the first conductor layer including write bit lines, read bit lines, and a plurality of interconnect conductors, wherein the write bit lines are coupled to a first source / drain region of the write transistor, and the read bit lines are coupled to a first source / drain region of the second read transistor; forming a second conductor layer on the first conductor layer, the second conductor layer including a storage node, wherein the storage node is coupled to a second source / drain region of the write transistor and a gate terminal of the first read transistor; forming a capacitor on the second conductor layer, the capacitor having a lower electrode coupled to the storage node, a high dielectric constant overlying the lower electrode, and an upper electrode overlying the high dielectric constant; and performing thermal annealing after forming the capacitor, the thermal annealing causing the material of the high dielectric constant to transform into a highly symmetrical crystalline phase. In some embodiments, the first and second read transistors are formed as a common source / drain region in the substrate. In some embodiments, the storage node is further formed as a gate terminal coupled to the second read transistor. In some embodiments, the method of forming a GCRAM cell further includes forming a third conductor layer on top of a second conductor layer prior to forming a capacitor, wherein the third conductor layer contacts a first via extending between the third conductor layer and the storage node, and wherein the capacitor is formed to contact a second via extending between the third conductor layer and the lower electrode of the capacitor.

[0074] It should be understood that, throughout this document and the claims, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements in a diagram or series of diagrams. In themselves, these terms do not imply any temporal order or structural proximity of these elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, "first dielectric layer" as described in conjunction with the first figure may not necessarily correspond to "first dielectric layer" as described in conjunction with another figure, and may not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0075] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0076] 100a, 100b, 100c, 100d, 100e, 700: Circuit Diagram 102: Writing to a transistor 104a: First readout transistor 104b: Second readout transistor 106: Storage Node 108: First source / drain region 110: First gate terminal 112: Second source / drain region 114: Write bit line 114a: First write bit line 114b: Second write bit line 114sa: Write bit line signal 114sb: Second write bit line signal 116: Write character line 116a: First write character line 116b: Second write character line 116c: Third write character line 116s: Write character line signal 118: Third source / drain region 120: Second gate terminal 122: Fourth source / drain region 124: Read character lines 124a: First read character line 124b: Second read character line 124c: Third read character line 124s: Read character line signal 126: Read bit lines 126a: First read bit line 126b: Second read bit line 126s: Read bit line signal 128: Capacitor 129: Second capacitor 130: Grounding wire 132: Fifth Source / Drain Region 134: Third gate terminal 136: Sixth Source / Drain Region 138: Reset Line 140: Parallel Transistor 142: Fourth gate terminal 144: Seventh Source / Drain Region 200a, 300a: Top view 200b, 300b, 500a, 500b, 500c, 900, 1000, 1100, 1200, 1300, 1400, 1500: 3D View 206: Contact element 207: Internal Connection 208: First Through-hole Layer 210: Second through-hole level 212: Third Conductor Layer 214: Third Through-hole Layer 216: The Fourth Through-hole Layer 218: Lower electrode 220: High dielectric constant dielectric material 222: Upper electrode 224: Base 226: Quarantine Zone 228: First Direction 230: Second Direction 232: Third-party 302: Shared source / drain region 304: First GCRAM cell region 306: First through hole 308: Fourth Conductor Layer 400a, 400b, 400c, 400d, 400e: Sectional Views 402: Base 404, 414: Protrusions 406: Interlayer Dielectric 408: Cylindrical protrusion 410: Fin 412: Dielectric Structure 600a, 600b: Curve graph 602: First voltage 603, 615: First time period 604: Second voltage 606: Third voltage 607: Second Time Period 608: Fourth Voltage 610: Difference / First Difference 612: Difference / Second Difference 614: First value 616: Second value 702a: First GCRAM Unit 702b: Second GCRAM Unit 702c: Third GCRAM unit 702d: Fourth GCRAM unit 702e: Fifth GCRAM Unit 702f: Sixth GCRAM unit 704a: Column / First Column 704b: Column / Second Column 704c: Column / Third Column 706a: line / first line 706b: line / second line 800: Timing Diagram 802: Write operation 804: Read operation 806: Pre-charging phase 808: During the period 1600: Method 1602, 1604, 1606, 1608, 1610, 1612: Square C: Fourth lattice constant T0, T1, T2: Time period a1: First lattice constant a2: Second lattice constant a3: Third lattice constant t1: First thickness t2: Second thickness t3: Third thickness α: First lattice angle β: Second lattice angle γ: Third lattice angle ϴ: Fourth lattice angle

Claims

1. A memory unit, comprising: A written transistor is constructed on a substrate and includes a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node. A first read transistor is on the substrate and includes a second gate terminal coupled to the storage node and a gate dielectric layer having a first capacitance. And a capacitor, spaced apart from the first read transistor and the write transistor, and further spaced apart from the substrate by means of the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node, wherein the capacitor comprises a high dielectric constant dielectric material having a dielectric constant greater than 35, and the capacitor has a second capacitance more than twice that of the first capacitance.

2. The memory cell of claim 1, wherein the memory cell has a first area and the capacitor has a second area, wherein the ratio of the second area to the first area is equal to or less than 0.

8.

3. The memory cell as claimed in claim 1, wherein the capacitor comprises an upper electrode, a lower electrode, and the high dielectric constant dielectric having a symmetrical crystalline phase.

4. The memory cell of claim 1, wherein the capacitor includes an upper electrode, a lower electrode and an insulator between the upper electrode and the lower electrode, and wherein the capacitor is a three-dimensional capacitor, wherein the insulator extends along the respective sidewalls of the lower electrode and the upper electrode.

5. The memory cell of claim 2 further includes a second read transistor on the substrate, wherein, when viewed from top to bottom, the first area is defined by the span of the memory cell region including the first read transistor, the write transistor and the second read transistor, the second area is defined by the span of the capacitor, and the second area is between 60% and 80% of the first area.

6. The memory unit as described in claim 1 further includes: Conductive lines are placed above the write transistor and the first read transistor, wherein the conductive lines have an L-shaped top geometry and form the storage node.

7. An integrated circuit, comprising: A first region comprising multiple memory cells, having multiple columns and multiple rows, each of the multiple memory cells comprising: a write transistor including a first gate terminal, a first source / drain region, and a second source / drain region electrically coupled to a storage node; a first read transistor including a second gate terminal, a third source / drain region, and a fourth source / drain region electrically coupled to the storage node, and a gate dielectric layer having a first capacitance; and a capacitor electrically coupled to the storage node, wherein the capacitor comprises a high dielectric constant dielectric material having a dielectric constant greater than 35, and the capacitor having a second capacitance more than twice that of the first capacitance; a write bit line electrically coupled to the first source / drain region of each of the multiple memory cells in the first row of the multiple rows; and a write word line electrically coupled to the first gate terminal of each of the multiple memory cells in the first column of the multiple columns.

8. The integrated circuit as claimed in claim 7, further comprising: Read bit lines electrically coupled to the fourth source / drain region of each of the plurality of memory cells in the first row of the plurality of rows; And read character lines, electrically coupled to the third source / drain region of each of the plurality of memory cells in the first column of the plurality of columns.

9. The integrated circuit as claimed in claim 7, wherein each of the plurality of memory cells includes a second read transistor, the second read transistor including a third gate terminal, a fifth source / drain region electrically coupled to the third source / drain region, and a sixth source / drain region, wherein the integrated circuit further includes: Read bit lines electrically coupled to the sixth source / drain region of each of the plurality of memory cells in the first row of the plurality of rows.

10. A method for forming a gain unit random access memory unit, comprising: An isolation zone is formed in the substrate; A write transistor, a first read transistor, and a second read transistor are formed on the substrate, wherein the write transistor is spaced apart from the first read transistor and the second read transistor by means of the isolation region, and the first read transistor includes a gate dielectric layer with a first capacitor; a first conductor layer is formed on the substrate, the first conductor layer including write bit lines, read bit lines, and a plurality of interconnect conductors, wherein the write bit lines are coupled to a first source / drain region of the write transistor and the read bit lines are coupled to a first source / drain region of the second read transistor; a second conductor layer is formed on the first conductor layer, the second conductor layer including a storage node, wherein the storage node is coupled to a second source / drain region of the write transistor and a gate terminal of the first read transistor; And a capacitor is formed on the second conductor layer, the capacitor having a lower electrode coupled to the storage node, a high dielectric constant dielectric material covering the lower electrode, and an upper electrode on the high dielectric constant dielectric material; After the capacitor is formed, thermal annealing is performed, which causes the material of the high dielectric constant to transform into a highly symmetrical crystalline phase, wherein the dielectric constant of the high dielectric constant of the capacitor is greater than 35, and the capacitor has a second capacitance that is more than twice the first capacitance.

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