Method of manufacturing semiconductor structure

Abstract

Some embodiments disclosed herein provide a method for manufacturing a semiconductor structure comprising the following steps: A substrate is provided, wherein an active device layer is provided on the substrate. A stacked film layer is formed on the active device layer. A photoresist plateau layer is formed on the stacked film layer. A barrier layer is conformally deposited on the photoresist plateau layer. A photoresist layer is formed on the barrier layer, wherein the top surface of the photoresist layer is higher than the topmost surface of the barrier layer. The photoresist layer is etched until a plurality of exposed top surfaces of the barrier layer are exposed to form a plurality of first openings, wherein via patterns correspond to regions of the first openings. Based on the first openings, the barrier layer, the photoresist plateau layer, and the stacked film layer are etched until a plurality of top surfaces of the active device layer are exposed to form a plurality of second openings.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a semiconductor structure. More specifically, this disclosure relates to a method for manufacturing a semiconductor structure using a photoresist plateau layer and a photoresist layer located on the photoresist plateau layer. Prior Technology

[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. Furthermore, DRAM performance is improved by reducing the pitch between semiconductor structures. However, the shrinking size of semiconductor structures, in addition to increasing the difficulty of manufacturing processes, also makes the components within the semiconductor structure more prone to leakage due to close spacing.

[0003] Therefore, reducing leakage current to improve the process yield of semiconductor structures has become an important issue in semiconductor manufacturing. Summary of the Invention

[0004] Some embodiments disclosed herein provide a method for manufacturing a semiconductor structure including the following steps: A substrate and an active device layer located on the substrate are provided. A stacked film layer is formed on the active device layer. A barrier layer is conformally formed on a photoresist plateau layer. The barrier layer is conformally formed on the photoresist plateau layer. The photoresist plateau layer is etched until a plurality of top surfaces of the barrier layer are exposed to form a plurality of first openings. Based on the first openings, the barrier layer, the photoresist plateau layer, and the stacked film layer are etched until a plurality of top surfaces of the active device layer are exposed to form a plurality of second openings.

[0005] In some embodiments, forming the first opening includes the following steps: A photomask layer including a via pattern is formed on a photoresist layer using a lithography process, wherein the photomask layer exposes a plurality of exposed top surfaces of the photoresist layer. The photoresist layer is etched at the locations of the exposed top surfaces until the top surface of the barrier layer is exposed. The photomask layer is then removed.

[0006] In some embodiments, the through-hole pattern corresponds to the area of ​​the first opening.

[0007] In some embodiments, the through-hole pattern is defined by boundary rules.

[0008] In some embodiments, in a top view, the boundary rule is defined as the shortest distance from the edge of the first opening to the nearest edge of the photoresist platform layer being between 0.1 micrometers and 5 micrometers.

[0009] In some embodiments, after etching the blocking layer, the photoresist platform layer, and the stacked film layer to form the second opening, the second opening is filled with a conductive material to form a plurality of interconnect structures in the stacked film layer.

[0010] In some embodiments, the photoresist platform layer is a KrF photoresist platform layer.

[0011] In some embodiments, the photoresist layer is an ArF photoresist layer.

[0012] In some embodiments, since the etch selectivity of the photoresist layer is greater than that of the barrier layer, the first opening is etched until the top surface of the barrier layer is exposed.

[0013] In some embodiments, since the etch selectivity of the barrier layer is greater than that of the photoresist platform layer, and the etch selectivity of the photoresist platform layer is greater than that of the stacked film layers, a second opening is formed after etching through the barrier layer.

[0014] Some embodiments disclosed herein provide a method for manufacturing a semiconductor structure comprising the following steps: A substrate is provided, wherein an active device layer is provided on the substrate. A stacked film layer is formed on the active device layer. A photoresist plateau layer is formed on the stacked film layer based on a via pattern. A barrier layer is conformally deposited on the photoresist plateau layer. A photoresist layer is formed on the barrier layer, wherein the top surface of the photoresist layer is higher than the topmost surface of the barrier layer. Based on the via pattern, the photoresist layer is etched until a plurality of exposed top surfaces of the barrier layer are exposed to form a plurality of first openings, wherein the via pattern corresponds to regions of the first openings. Based on the first openings, the barrier layer, the photoresist plateau layer, and the stacked film layer are etched until a plurality of top surfaces of the active device layer are exposed to form a plurality of second openings.

[0015] In some embodiments, in a top view, the shortest distance from the edge of the first opening to the nearest edge of the photoresist platform layer is between 0.1 micrometers and 5 micrometers.

[0016] In some embodiments, the through-hole pattern includes a single through-hole pattern, a multiple through-hole pattern, or a combination thereof.

[0017] In some embodiments, the thickness of the photoresist platform layer is 100 nanometers to 200 nanometers.

[0018] In some embodiments, the second thickness measured from the top surface of the photoresist layer on the stacked film layer to the top surface of the barrier layer is greater than the first thickness measured from the top surface of the photoresist layer to the top surface of the barrier layer located on the photoresist platform layer.

[0019] In some embodiments, after etching the photoresist layer to form a first opening, the photoresist layer is used as a negative photoresist layer when etching the blocking layer, the photoresist platform layer, and the stacked film layer to form a second opening.

[0020] In some embodiments, the first etch selectivity of the photoresist layer is greater than the second etch selectivity of the barrier layer.

[0021] In some embodiments, the second etch selectivity of the blocking layer is greater than the third etch selectivity of the photoresist platform layer, and the third etch selectivity of the photoresist platform layer is greater than the fourth etch selectivity of the stacked film layer.

[0022] In some embodiments, the method further includes the following steps: filling the second opening with conductive material; planarizing excess conductive material outside the second opening to form a conductive layer, wherein after planarizing the excess conductive material outside the second opening, the top surface of the conductive layer is coplanar with the top surfaces of the stacked film layers.

[0023] In some embodiments, the bottom surface of the conductive layer is in contact with the top surface of the active device layer. Simple Explanation of the Diagram

[0024] The following embodiments are read in conjunction with the accompanying drawings for a clear understanding of the viewpoints disclosed herein. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity in discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Figure 1 is a top view of a method for manufacturing a photoresist platform layer for forming a semiconductor structure according to some embodiments of the present disclosure; Figures 2 and 3 are cross-sectional views of a method for manufacturing a semiconductor structure based on the AA' section line of Figure 1 according to some embodiments of this disclosure, during the formation of a photoresist plateau layer; Figures 4 through 6 are cross-sectional views based on section line AA' of Figure 1, illustrating a method for manufacturing a semiconductor structure with a plurality of first openings according to some embodiments of this disclosure; and Figures 7 and 8 are cross-sectional views of a method for manufacturing a semiconductor structure based on the AA' section line of Figure 1 when forming a plurality of interconnect structures, according to some embodiments of the present disclosure. Implementation

[0025] Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0026] Furthermore, for ease of description, spatially related terms such as "above," "over," "below," and "between" may be used in this disclosure to describe the relationship or function of one element or feature to another, as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatially related terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used in this disclosure can be interpreted accordingly.

[0027] The terms "including," "having," and "containing" used in this disclosure are open-ended terms, meaning including but not limited to.

[0028] As the critical dimension (CD) of semiconductor structures becomes smaller, the vias formed in semiconductor structures through lithography also become smaller. However, the thickness of the photoresist layer no longer meets the CD resolution of the vias and cannot provide sufficient etch resistance for via formation. Therefore, the embodiments disclosed herein provide a method for fabricating semiconductor structures using a photoresist plateau layer and a photoresist layer located on the photoresist plateau layer.

[0029] It should be noted that when the following figures (e.g., Figures 1 to 8) are illustrated and described as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than those in this disclosure, or some operations or steps may occur simultaneously, or some operations may be omitted, and / or some operations or steps may be repeated. Furthermore, actual operations or steps in the process stage may be performed before, during, or after the formation of the semiconductor structure (e.g., semiconductor structure 100 in Figure 8) to form the semiconductor structure 100. Therefore, this disclosure may only briefly describe a portion of these additional operations or steps. Moreover, unless otherwise stated, the same interpretations discussed for the following figures (e.g., Figures 1 to 8) can be directly applied to the other figures.

[0030] Please refer to Figures 1 through 3. Figure 1 is a top view of a method for manufacturing a photoresist platform layer for forming a semiconductor structure according to some embodiments of the present disclosure, and Figures 2 and 3 are cross-sectional views of a method for manufacturing a semiconductor structure based on the AA' section line of Figure 1 according to some embodiments of the present disclosure during the formation of the photoresist platform layer.

[0031] As shown in Figure 2, a substrate 102 is provided, and an active device layer 110 disposed on the substrate 102 is provided. In some embodiments, the substrate 102 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 102 may include elemental semiconductors, such as germanium. In some embodiments, the substrate 102 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. In some embodiments, the substrate 102 may include compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. Furthermore, in some embodiments, the substrate 102 may selectively have a semiconductor-on-insulator (SOI) structure. Additionally, the active device layer 110 includes gate structures, bit line structures, contact plugs, and other active elements.

[0032] Next, a stacked film layer 120 is formed on the active device layer 110. Furthermore, to improve the resolution of the via pattern on the subsequently formed photoresist layer 150, a photoresist plateau layer 130 (as shown in Figure 3) is formed on the stacked film layer 120. Specifically, as shown in Figure 2, a photoresist layer 130P is formed on the stacked film layer 120. Then, based on the via pattern and boundary rules, a mask layer 132 is formed on the photoresist layer 130P to expose a plurality of top surfaces of the photoresist layer 130P. The via pattern and boundary rules will be described in detail later. Subsequently, as shown in Figure 3, a photolithography process is performed on the exposed top surfaces, and a plurality of portions of the photoresist layer 130P (e.g., Figure 2) are removed to form the photoresist plateau layer 130 on the stacked film layer 120. In some embodiments, the photoresist plateau layer 130 is a KrF photoresist layer. In some embodiments, the thickness of the photoresist platform layer 130 is between 100 nanometers (nm) and 200 nm. Additionally, the via pattern is designed based on the requirements of the interconnect structure, wherein the interconnect structure is configured to electrically connect the active device layer 110 to the upper conductive component. Furthermore, since the upper conductive component requires multiple subsequent operations to obtain, and the focus of this disclosed embodiment is not on the upper conductive component, it is not shown in the figures. Moreover, the thickness of the photoresist platform layer 130 may be related to the size of each opening (e.g., the first opening OP1 in Figure 6 and the second opening OP2 in Figure 7, also referred to as vias).

[0033] Considering the general operation of designing openings (first opening OP1 in Figure 6 and second opening OP2 in Figure 7) in semiconductor structures (e.g., semiconductor structure 100 in Figure 8), openings arranged adjacent to each other cannot usually be accurately predicted. Therefore, a photoresist platform layer 130 is formed on the stacked film layer 120 based on the via pattern. As shown in the top view of Figure 1, in some embodiments, depending on the via pattern, the shortest distance from the edge of each opening (shown by dashed lines) of the via pattern to the edge of the photoresist platform layer 130 is between 0.1 micrometers (µm) and 5 µm. In this document, the shortest distance from the edge of each opening of the via pattern to the edge of the photoresist platform layer 130 is referred to as the boundary rule. As shown in Figure 1, via patterns include single via patterns, multiple via patterns, or combinations thereof. Furthermore, the number of different via patterns can vary.

[0034] Furthermore, according to the exemplary embodiments disclosed herein, the first via pattern HP1 is a single via pattern. The first boundary distance D1 refers to the shortest distance in the Y direction from the edge of the first via pattern HP1 to the nearest edge of the photoresist platform layer 130, and the first boundary distance D1 is between 0.1 μm and 5 μm. The second boundary distance D2 refers to the shortest distance in the X direction from the other edge of the first via pattern HP1 to the other nearest edge of the photoresist platform layer 130, and the second boundary distance D2 is between 0.1 μm and 5 μm. Additionally, in some embodiments, the shape of the photoresist platform layer 130 can be various shapes, such as a rectangle or a shape along the edge of the via pattern (e.g., the first via pattern HP1), as long as the relative positional relationship between the via pattern (e.g., the first via pattern HP1) and the photoresist platform layer 130 conforms to the boundary rules.

[0035] According to an exemplary embodiment of this disclosure, the second via pattern HP2 is a multi-via pattern. In Figure 1, the second via pattern HP2 includes three openings, but the second via pattern HP2 can be of any number and is not intended to limit this disclosure. The third boundary distance D3 refers to the shortest distance in the Y direction from the edge of the second via pattern HP2 (e.g., the edge of the opening closest to the edge of the photoresist platform layer 130) to the nearest edge of the photoresist platform layer 130, and the third boundary distance D3 is between 0.1 μm and 5 μm. The fourth boundary distance D4 refers to the shortest distance in the X direction from another edge of the second via pattern HP2 to another nearest edge of the photoresist platform layer 130, and the fourth boundary distance D4 is between 0.1 μm and 5 μm. In some embodiments, the shape of the photoresist platform layer 130 can be various shapes, such as a rectangle or a shape along the edge of the via pattern (e.g., the second via pattern HP2), as long as the relative positional relationship between the via pattern (e.g., the second via pattern HP2) and the photoresist platform layer 130 conforms to the boundary rules.

[0036] According to an exemplary embodiment of this disclosure, the third via pattern HP3 is a multi-via pattern. Furthermore, the third via pattern HP3 is a high-density via pattern, meaning the openings in the third via pattern HP3 are relatively close to each other. In Figure 1, the third via pattern HP3 includes five openings, but the third via pattern HP3 can be any number and is not intended to limit this disclosure. The fifth boundary distance D5 refers to the shortest distance in the Y direction from the edge of the third via pattern HP3 to the nearest edge of the photoresist platform layer 130, and the fifth boundary distance D5 is between 0.1 μm and 5 μm. The sixth boundary distance D6 refers to the shortest distance in the X direction from another edge of the third via pattern HP3 (e.g., the edge of the third via pattern HP3 closest to another edge of the photoresist platform layer 130), and the sixth boundary distance D6 is between 0.1 μm and 5 μm. In some embodiments, as long as the relative positional relationship between the via pattern (e.g., the third via pattern HP3) and the photoresist platform layer 130 conforms to the boundary rules, the shape of the photoresist platform layer 130 can be various shapes, such as a rectangle or a shape along the edge of the via pattern (e.g., the third via pattern HP3).

[0037] According to an exemplary embodiment of this disclosure, the fourth via pattern HP4 is a multi-via pattern. In this exemplary embodiment, the fourth via pattern HP4 may include an upper pattern, an intermediate pattern adjacent to the upper pattern, and a lower pattern adjacent to the intermediate pattern. That is, the upper pattern is a single via pattern containing one opening, and the intermediate and lower patterns are both multi-via patterns containing three openings. However, the number of fourth via patterns HP4 can be any and is not intended to limit this disclosure. Furthermore, the boundary distance of the upper pattern conforms to boundary rules, and the boundary distances of the intermediate and lower patterns also conform to boundary rules. In an exemplary embodiment of the lower pattern, the seventh boundary distance D7 refers to the shortest distance in the Y direction from the edge of the lower pattern to the nearest edge of the photoresist platform layer 130, and the seventh boundary distance D7 is between 0.1 μm and 5 μm. In an exemplary embodiment of the lower pattern, the eighth boundary distance D8 refers to the distance from the edge of the fourth via pattern HP4 (e.g., the edge of the opening of the lower pattern closest to the edge of the photoresist platform layer 130) to the nearest edge of the photoresist platform layer 130, and the eighth boundary distance D8 is between 0.1 μm and 5 μm. The shape of the photoresist platform layer 130 can be various, such as a rectangle along the edge of the via pattern (e.g., the fourth via pattern HP4), as long as the relative positional relationship between the via pattern (e.g., the fourth via pattern HP4) and the photoresist platform layer 130 conforms to the boundary rules. Furthermore, since the configuration of the shape of the photoresist platform layer 130 and the number of openings between the upper, middle, and lower patterns is irregular, the spacing between the openings in the upper, middle, and lower patterns is also irregular. In the X direction, the spacing between the openings in the lower pattern is a first spacing S1, while the spacing between the openings in the middle pattern is a second spacing S2. In this exemplary embodiment, since the number of lower and middle patterns is the same and the size of the lower pattern is larger than the size of the middle pattern, the first spacing S1 is larger than the second spacing S2. The interval between the openings of the lower pattern and the middle pattern is the third interval S3. The first interval S1, the second interval S2 and the third interval S3 all conform to the boundary rules, thus ensuring that the opening of the fourth via pattern HP4 is completely located inside the boundary of the photoresist platform layer 130.

[0038] Furthermore, the maximum outer diameter of each opening in different via patterns can be different. In the exemplary embodiment of Figure 1, each opening of the third via pattern HP3 is significantly smaller than each opening of the second via pattern HP2. Additionally, the maximum outer diameter of each opening ranges from 30 nanometers (nm) to 150 nm. The maximum outer diameter of each opening will be described in detail later.

[0039] Further, please refer to Figures 4 through 6. Figures 4 through 6 are cross-sectional views based on section line AA' of Figure 1, illustrating a method for fabricating a semiconductor structure with a plurality of first openings according to some embodiments of this disclosure. As shown in Figure 4, a barrier layer 140 is conformally deposited on the top surface of the photoresist platform layer 130 and on the top surface of the stacked film layer 120 not covered by the photoresist platform layer 130. The barrier layer 140 is deposited using an atomic layer deposition (ALD) process. In some embodiments, the material of the barrier layer 140 includes oxides and SiN.

[0040] Next, a photoresist layer 150 is formed on the barrier layer 140. Furthermore, the top surface of the photoresist layer 150 is higher than the top surface of the barrier layer 140. In some embodiments, the photoresist layer 150 is an ArF photoresist layer. In some embodiments, the photoresist layer 150 is formed by a spin coating process.

[0041] As shown in Figure 5, a photomask layer 160 comprising a plurality of openings 162 based on via patterns (e.g., shown in Figure 1) is formed over a photoresist layer 150 via a photolithography process. In other words, the openings 162 in the photomask layer 160 correspond to a first via pattern HP1, a second via pattern HP2, a third via pattern HP3, and a fourth via pattern HP4 (e.g., shown in Figure 1). In some embodiments, the openings 162 of the first via pattern HP1 (e.g., shown in Figure 1) have a first maximum outer diameter OD1 (e.g., shown in Figure 8), and each opening 162 of the second via pattern HP2 (e.g., shown in Figure 1) has a first maximum outer diameter OD1 (e.g., shown in Figure 8). Each opening 162 of the fourth via pattern HP4 (e.g., shown in Figure 1) has a third maximum outer diameter OD3 (e.g., shown in Figure 8). In some embodiments, the first maximum outer diameter OD1 is equal to or different from the second maximum outer diameter OD2, the third maximum outer diameter OD3, and the fourth maximum outer diameter OD4. In some embodiments, the second maximum outer diameter OD2 is equal to or different from the third maximum outer diameter OD3 and the fourth maximum outer diameter OD4. In some embodiments, the third maximum outer diameter OD3 is equal to or different from the fourth maximum outer diameter OD4. In other words, the first maximum outer diameter OD1, the second maximum outer diameter OD2, the third maximum outer diameter OD3, and the fourth maximum outer diameter OD4 may be the same as or different from each other.

[0042] Subsequently, as shown in Figure 6, the photoresist layer 150 is etched at the locations of a plurality of openings 162 (as shown in Figure 5) in the photoresist layer 150 until a plurality of top surfaces of the barrier layer 140 are exposed. Then, after etching, the photomask layer 160 (as shown in Figure 5) is removed. In some embodiments, the photoresist layer 150 is etched using a dry etching process. Furthermore, since the first etch selectivity of the photoresist layer 150 is greater than the second etch selectivity of the barrier layer 140, the photoresist layer 150 is etched until a plurality of top surfaces of the barrier layer 140 are exposed to form the first openings OP1. In other words, due to the etch selectivity ratio between the photoresist layer 150 and the barrier layer 140, the etching process stops at the top surface of the barrier layer 140 and does not continue etching downwards. As described above regarding boundary rules, each first opening OP1 conforms to the boundary rules after etching the photoresist layer 150. That is, the distance from the edge of each first opening OP1 based on the first via pattern HP1 (as shown in Figure 1) to the edge of the photoresist platform layer 130 is the second boundary distance D2, the distance from the edge of each first opening OP1 based on the second via pattern HP2 (as shown in Figure 1) to the edge of the photoresist platform layer 130 is the fourth boundary distance D4, the distance from the edge of each first opening OP1 based on the third via pattern HP3 (as shown in Figure 1) to the edge of the photoresist platform layer 130 is the sixth boundary distance D6, and the distance from the edge of each first opening OP1 based on the fourth via pattern HP4 (as shown in Figure 1) to the edge of the photoresist platform layer 130 is the eighth boundary distance D8.

[0043] It is worth mentioning that in the embodiment where the photoresist layer 150 is formed via a spin coating process, the photoresist layer 150 above the photoresist platform layer 130 can be uniform and thin. Furthermore, the second thickness T2 measured from the top surface of the photoresist layer 150 on the stacked film layer 120 to the top surface of the barrier layer 140 is greater than the first thickness T1 measured from the top surface of the photoresist layer 150 to the top surface of the barrier layer 140 on the photoresist platform layer 130. In this way, on the one hand, since the first thickness T1 of the photoresist layer 150 is thinner (e.g., thinner than the second thickness T2 of the photoresist layer 150), the top surface of the photoresist layer 150 corresponds to a high resolution corresponding to the exposure opening 162 during the lithography process. On the other hand, since the second thickness T2 of the photoresist layer 150 is thicker (for example, thicker than the first thickness T1 of the photoresist layer 150), the photoresist layer 150 disposed above the stacked film layer 120 rather than above the photoresist platform layer 130 can resist the etching process and not be etched.

[0044] Please refer to Figures 7 and 8. Figures 7 and 8 are cross-sectional views of a method for manufacturing a semiconductor structure based on the AA' section line of Figure 1 when forming a plurality of interconnect structures according to some embodiments of this disclosure. As shown in Figure 7, a plurality of second openings OP2 are formed by etching a barrier layer 140, a photoresist plateau layer 130, and a stacked film layer 120 based on a plurality of first openings OP1 (as shown in Figure 6) until a plurality of top surfaces of the active device layer 110 are exposed. Specifically, after forming the first openings OP1 (as shown in Figure 6) in the photoresist layer 150, a photolithography process (e.g., including exposure and development) is performed. Subsequently, after etching, the barrier layer 140, the photoresist plateau layer 130, and the stacked film layer 120 covered by the remaining photoresist layer 150 are retained without being etched. In some embodiments, the second openings OP2 are formed by a dry etching process. In addition, the second etch selectivity of the blocking layer 140 is greater than the third etch selectivity of the photoresist platform layer 130, and the third etch selectivity of the photoresist platform layer 130 is greater than the etch selectivity of the stacked film layer 120.

[0045] Subsequently, as shown in Figure 8, the remaining photoresist layer 150, the remaining barrier layer 140, and the remaining photoresist platform layer 130 (as shown in Figure 7) are removed by a stripping process. In some embodiments, the stripping process is performed using diluted HF (dHF) or HNO3. Then, conductive material is filled into each second opening OP2 (as shown in Figure 7) to form a plurality of interconnect structures 170 and to form a semiconductor structure 100. Specifically, each second opening OP2 (as shown in Figure 7) is completely filled with conductive material. Next, excess conductive material outside each second opening OP2 (as shown in Figure 7) is planarized to form a conductive layer 170, also referred to as an interconnect structure 170. Furthermore, after planarizing the excess conductive material outside each second opening OP2 (as shown in Figure 7), the top surface of the conductive layer 170 is coplanar with the top surface of the stacked film layer 120. The bottom surface of the conductive layer 170 contacts each top surface of the active device layer 110. In some embodiments, the conductive material includes Cu, W, and other suitable conductive materials. In some embodiments, the maximum outer diameter of the conductive layer is 30 nm to 150 nm. As mentioned above, in the exemplary embodiment of Figure 8, the first maximum outer diameter OD1 of the conductive layer 170 based on the first via pattern HP1 (as shown in Figure 1) is 30 nm to 150 nm, the second maximum outer diameter OD2 of the conductive layer 170 based on the second via pattern HP2 (as shown in Figure 1) is 30 nm to 150 nm, the third maximum outer diameter OD3 of the conductive layer 170 based on the third via pattern HP3 (as shown in Figure 1) is 30 nm to 150 nm, and the fourth maximum outer diameter OD4 of the conductive layer 170 based on the fourth via pattern HP4 (as shown in Figure 1) is 30 nm to 150 nm. By setting up a photoresist layer 150, a barrier layer 140 and a photoresist platform layer 130, the combined height of the photoresist layer 150, the barrier layer 140 and the photoresist platform layer 130 provides sufficient etching height for the second opening OP2.

[0046] In summary, this disclosed embodiment provides a method for fabricating a semiconductor structure using a photoresist plateau layer on a stacked film layer, a barrier layer on the photoresist plateau layer, and a photoresist layer on the barrier layer. By setting the photoresist plateau layer and adjusting the thickness of the photoresist layer, the photoresist layer above the photoresist plateau layer becomes thinner, thereby improving the CD resolution of each first aperture. Furthermore, the photoresist layer located above the stacked film layer (not the photoresist layer not above the photoresist plateau layer) is thicker, thereby improving the etch resistance of the photoresist layer at areas where apertures are not formed. Moreover, the combined height of the photoresist layer, barrier layer, and photoresist plateau layer provides sufficient etching height for the second aperture, thus improving the CD resolution of each second aperture and the yield of the outline of each second aperture. In addition, the semiconductor structure fabrication method provided by this disclosed embodiment can expand the process window between different via patterns.

[0047] Although some embodiments of this disclosure have been described in considerable detail, other embodiments are also possible. Therefore, the spirit and scope of the claims should not be limited to the embodiments described herein.

[0048] The foregoing summary outlines the features of several embodiments in this disclosure, enabling those skilled in the art to more readily understand it. Anyone skilled in the art should understand that this disclosure can easily serve as a basis for changes or designs to other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments disclosed. Anyone skilled in the art will also understand that equivalent structures described above do not depart from the spirit and scope of this disclosure, and that modifications, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

[0049] 100: Semiconductor Structure 102:Substrate 110: Active Device Layer 120: Stacked film layers 130: Photoresist plateau layer 130P, 150: Photoresist layer 132: Masking layer 140: Barrier Layer 160: Photomask layer 162: Opening 170: Interconnect structure / conductive layer AA': Section line D1: Distance to the first boundary D2: Second boundary distance D3: Distance to the third boundary D4: Distance to the fourth boundary D5: Distance to the fifth boundary D6: Distance to the sixth boundary D7: Seventh boundary distance D8: Distance to the eighth boundary HP1: First through-hole pattern HP2: Second through-hole pattern HP3: Third through-hole pattern HP4: Fourth through-hole pattern OD1: First maximum outer diameter OD2: Second largest outer diameter OD3: Third largest outer diameter OD4: Fourth largest outer diameter OP1: First opening OP2: Second opening S1: First Interval S2: Second Interval S3: Third Interval T1: First thickness T2: Second thickness X, Y: Direction

[0050] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for manufacturing a semiconductor structure, comprising: A substrate and an active device layer located on the substrate are provided; A stacked film layer is formed on the active device layer; A photoresist plateau layer is formed on the stacked film layer; a barrier layer is conformally formed on the photoresist plateau layer; a photoresist layer is formed on the barrier layer, wherein the top surface of the photoresist layer is higher than the top surface of the barrier layer; a photomask layer including a via pattern is formed on the photoresist layer through a photolithography process, wherein the photomask layer exposes a plurality of exposed top surfaces of the photoresist layer; the photoresist layer is etched at the locations of the exposed top surfaces of the photoresist layer until the plurality of top surfaces of the barrier layer are exposed to form a plurality of first openings; the photomask layer is removed; and based on the first openings, the barrier layer, the photoresist plateau layer, and the stacked film layer are etched until the plurality of top surfaces of the active device layer are exposed to form a plurality of second openings.

2. The method as described in claim 1, wherein the through-hole pattern corresponds to the region of the first openings.

3. The method as described in claim 2, wherein the via pattern is defined by a boundary rule.

4. The method as described in claim 3, wherein, in a top view, the boundary rule is defined as the shortest distance from one edge of each of the first openings to the nearest edge of the photoresist platform layer being between 0.1 micrometers and 5 micrometers.

5. The method as described in claim 1, wherein after etching the barrier layer, the photoresist platform layer and the stacked film layer to form the second openings, conductive material is filled into the second openings to form a plurality of interconnect structures in the stacked film layer.

6. The method as described in claim 1, wherein the photoresist plateau layer is a KrF photoresist plateau layer.

7. The method as described in claim 1, wherein the photoresist layer is an ArF photoresist layer.

8. The method as described in claim 1, wherein the first openings are etched until the top surfaces of the barrier layer are exposed because the etch selectivity of the photoresist layer is greater than that of the barrier layer.

9. The method as described in claim 8, wherein the second openings are formed after etching through the barrier layer because the etch selectivity of the barrier layer is greater than that of the photoresist platform layer, and the etch selectivity of the photoresist platform layer is greater than that of the stacked film layers.

10. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate has an active device layer; A stacked film layer is formed on the active device layer; Based on a via pattern, a photoresist plateau layer is formed on the stacked film layers; a barrier layer is conformally deposited on the photoresist plateau layer; a photoresist layer is formed on the barrier layer, wherein the top surface of the photoresist layer is higher than the top surface of the barrier layer; based on the via pattern, the photoresist layer is etched until a plurality of exposed top surfaces of the barrier layer are exposed to form a plurality of first openings, wherein the via pattern corresponds to the regions of the first openings; and based on the first openings, the barrier layer, the photoresist plateau layer, and the stacked film layers are etched until a plurality of top surfaces of the active device layer are exposed to form a plurality of second openings.

11. The method as described in claim 10, wherein, in a top view, the shortest distance from the edge of each of the first openings to the nearest edge of the photoresist platform layer is between 0.1 micrometers and 5 micrometers.

12. The method as described in claim 10, wherein the through-hole pattern includes a single through-hole pattern, a multiple through-hole pattern, or a combination thereof.

13. The method as described in claim 10, wherein the thickness of the photoresist platform layer is 100 nanometers to 200 nanometers.

14. The method of claim 10, wherein a second thickness measured from a top surface of the photoresist layer on the stacked film layer to a top surface of the barrier layer is greater than a first thickness measured from the top surface of the photoresist layer to the top surface of the barrier layer located on the photoresist platform layer.

15. The method as claimed in claim 10, wherein after etching the photoresist layer to form the first openings, the photoresist layer is used as a negative photoresist layer when etching the barrier layer, the photoresist platform layer and the stacked film layer to form the second openings.

16. The method as described in claim 10, wherein a first etch selectivity of the photoresist layer is greater than a second etch selectivity of the barrier layer.

17. The method as described in claim 16, wherein the second etch selectivity of the blocking layer is greater than a third etch selectivity of the photoresist platform layer, and the third etch selectivity of the photoresist platform layer is greater than a fourth etch selectivity of the stacked film layers.

18. The method as described in claim 10, further comprising: A conductive material is filled into each of the second openings; And planarize the excess conductive material located outside each of the second openings to form a conductive layer, wherein after planarizing the excess conductive material located outside each of the second openings, a top surface of the conductive layer is coplanar with a top surface of the stacked film layer.

19. The method as described in claim 18, wherein the bottom surface of the conductive layer is in contact with each of the top surfaces of the active device layer.

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