Double-sided fan-out packaging method and packaging structure

Abstract

This invention discloses a double-sided fan-out packaging method and structure, comprising the following steps: first, preparing a carrier sheet with symmetrically arranged peelable structures on both sides; then, completing multi-layer RDL wiring in stages; then, double-sided wafer mounting; double-sided molding; separating the carrier sheet; and finally, separating into packaged wafers. This invention employs a packaging technology that processes both sides simultaneously, creating a symmetrical structure on both sides. This can offset phenomena such as bending and dimensional instability caused by performance differences between multiple layers of polymer materials and metal materials. The fan-out packaging technology using a pre-rewiring layer can solve the problem of high-precision fan-out packaging for high-density wiring. Furthermore, the symmetrical double-sided structure effectively offsets warpage caused by multi-layer wiring. Therefore, the double-sided pre-rewiring layer fan-out structure is more conducive to meeting the high-density, high-integration packaging requirements for wiring layers exceeding four, improving processing efficiency, doubling the output of packaged wafers, and effectively reducing packaging costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a double-sided fan-out packaging method and packaging structure. Prior Technology

[0002] Fan-out packaging, based on the fabrication order between the die and the redistribution layer (RDL), can be divided into three main forms: top-facing die-first packaging, bottom-facing die-first packaging, and bottom-facing redistribution layer-first packaging.

[0003] Redundancy layer pre-packaging offers several advantages: Firstly, the multi-layer RDL (Redirect Diffraction Layer) is fabricated directly on the carrier wafer, unlike the other two fan-out packaging methods which fabricate it on the plastic reconfiguration wafer. This facilitates the fabrication of ultra-fine, multi-layer, high-density RDL wiring, thereby increasing the number of input / output (IO) leads and improving product performance. Secondly, tested, high-quality wafers are directly bonded to the pre-fabricated under-bump-metal (UBM) on the redundancy layer using a face-down flip-chip bonding method. This reduces wafer displacement caused by mold flow impact during wafer-level plastic packaging and subsequent photolithography alignment difficulties, while also improving packaging yield and avoiding wafer yield losses due to the RDL wiring process. Summary of the Invention

[0004] To address the technical problems existing in the prior art, the present invention aims to provide a double-sided fan-out packaging method and packaging structure.

[0005] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: In a first aspect, the present invention discloses a double-sided fan-out packaging method, comprising the following steps: fabricating a carrier sheet, wherein a peelable structure is symmetrically arranged on both sides of the carrier sheet; a first insulating layer with openings is arranged on both sides of the peelable structure away from the carrier sheet; a first metal layer is first formed and then a second metal layer is formed at the openings; multilayer RDL wiring is arranged on the side of the second metal layer away from the carrier sheet; a chip is mounted on the side of the multilayer RDL wiring away from the carrier sheet; the chip is encapsulated to cover the chip on both sides of the carrier sheet; and the carrier sheet is disassembled to obtain the packaged chip.

[0006] In one embodiment of the present invention, the chip includes metal bumps, wherein the chip mounting step includes: attaching the chip to the UBM of the carrier sheet by flip-chip technology, and soldering the metal bumps to the UBM by reflow soldering.

[0007] In one embodiment of the present invention, the wafer fabrication steps include: for an integrated circuit (IC) wafer, using bump fabrication technology, forming copper-tin bumps on the interconnects, and then thinning and dicing to form a wafer.

[0008] In one embodiment of the present invention, the peelable structure includes a separable copper foil and an intermediate layer, or a release film and an intermediate layer, wherein a first insulating layer with openings is provided on both sides of the peelable structure away from the carrier sheet, including: obtaining the first insulating layer with openings by adhering an insulating film or applying insulating adhesive to both sides of the peelable structure away from the carrier sheet.

[0009] Secondly, the present invention also discloses a double-sided fan-out packaging structure, which is prepared by a double-sided fan-out packaging method as described in the first aspect. The packaging structure includes: a first insulating layer, wherein an opening is provided on the first insulating layer, and a first metal layer is formed first and then a second metal layer is formed at the opening; an RDL wiring layer is disposed on the first insulating layer; a second insulating layer is disposed on the RDL wiring layer; a UBM is disposed at the opening position of the second insulating layer; a wafer, which is attached to the UBM by flip-chip technology, and the metal bumps on the wafer are soldered to the UBM; and a molding compound layer for covering the wafer.

[0010] Thirdly, the present invention also discloses another double-sided fan-out packaging method, comprising: fabricating a carrier sheet, wherein peelable structures are symmetrically arranged on both sides of the carrier sheet; forming adhesive layers on both sides of the peelable structures away from the carrier sheet; bonding pre-fabricated RDL lines to the peelable structures and part of the adhesive layers, and then interconnecting the bottom-layer plated connectors and RDLs by drilling, electroless plating or physical vapor deposition to complete multi-layer RDL wiring; forming UBMs on the multi-layer RDL wiring, and applying solder to the formed UBMs to form solder joints; attaching a chip to the solder joints; encapsulating the chip to cover both sides of the carrier sheet; and disassembling the carrier sheet to obtain the packaged chip.

[0011] In one embodiment of the present invention, the chip mounting step includes: attaching the chip to the solder joints using flip-chip technology, and soldering the metal bumps on the chip to the UBM using reflow soldering.

[0012] In one embodiment of the present invention, for an IC wafer, NiAu is first deposited in the interconnect area, and then thinned and diced to form a wafer.

[0013] In one embodiment of the present invention, after the carrier sheet is split, NiAu plating is performed on the exposed UBM.

[0014] Fourthly, the present invention also discloses a double-sided fan-out packaging structure, which is prepared by a double-sided fan-out packaging method as described in the third aspect. The packaging structure includes: a wafer, wherein the wafer is made by plating NiAu in the IC wafer interconnection port area and then thinning and dicing; a molding layer for covering the wafer; an adhesive layer; and multilayer RDL wiring, wherein the exposed UBM is treated with NiAu plating.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0016] 1) This invention discloses a double-sided fan-out packaging method, which adopts packaging technology that processes both sides simultaneously, so that the front and back sides form a symmetrical structure. This can offset the bending and dimensional instability caused by the performance differences between multiple polymer materials and metal materials, improve processing efficiency, double the output of packaged chips, and effectively reduce packaging costs. The redistribution layer packaging fan-out technology can solve the problem of high-density wiring precision fan-out packaging. In addition, the double-sided structure can effectively offset the warping caused by multiple wiring layers. Therefore, the double-sided redistribution layer fan-out structure is more conducive to meeting the packaging requirements of high density and high integration with more than 4 wiring layers.

[0017] 2) This invention discloses a double-sided fan-out packaging method, which can first electroplate Sn and then Cu in the early stage of board-level RDL forming, or use tin plating and copper paste to fill the opening of the insulating layer, which can avoid the warping problem after board disassembly, reduce process risk and improve production efficiency.

[0018] 3) This invention discloses a double-sided fan-out packaging method. Compared with the traditional FC bump chip processing, the method uses NiAu plating on the IC wafer connection port, which can reduce the cost of forming a bump on a traditional IC wafer, while meeting the requirements of good soldering performance. At the same time, in the RDL forming section, RDL lines can be stamped on copper foil, and then the pre-made RDL lines are bonded to the carrier sheet. Then, the interconnection between the bottom plated connection port (e.g., the bottom pad) and the RDL is achieved by drilling, plating or PVD, which reduces the cost of RDL forming and insulating adhesive forming and shortens the process processing time. Simple Explanation of the Diagram

[0019] Figure 1 is a structural schematic diagram of step one of Embodiment 1 of the present invention; Figure 2 is a structural schematic diagram of step two in Embodiment 1 of the present invention; Figure 3 is a structural schematic diagram of step three in Embodiment 1 of the present invention; Figure 4 is a structural schematic diagram of step four in Embodiment 1 of the present invention; Figure 5 is a structural schematic diagram of step five in Embodiment 1 of the present invention; Figure 6 is a structural schematic diagram of step six in Embodiment 1 of the present invention; Figure 7 is a structural schematic diagram of step seven in Embodiment 1 of the present invention; Figure 8 is a structural schematic diagram of step seven in Embodiment 1 of the present invention; Figure 9 is a structural schematic diagram of step eight in Embodiment 1 of the present invention; Figure 10 is a structural schematic diagram of step ten in Embodiment 1 of the present invention; Figure 11 is a structural schematic diagram of step two in Embodiment 2 of the present invention; Figure 12 is a structural schematic diagram of step three in Embodiment 2 of the present invention; Figure 13 is a structural schematic diagram of step three in Embodiment 2 of the present invention; Figure 14 is a schematic diagram of the structure of the prefabricated RDL circuit in Embodiment 2 of the present invention; Figure 15 is a schematic diagram of the multilayer RDL wiring structure in Embodiment 2 of the present invention; Figure 16 is a structural schematic diagram of step four in Embodiment 2 of the present invention; Figure 17 is a structural schematic diagram of step five in Embodiment 2 of the present invention; Figure 18 is a structural schematic diagram of step five in Embodiment 2 of the present invention; Figure 19 is a structural schematic diagram of step six in Embodiment 2 of the present invention; Figure 20 is a structural schematic diagram of step eight in Embodiment 2 of the present invention. Implementation

[0020] To enable the Examiner Committee to understand the technical features, content, advantages, and effects of this invention, the invention is hereby described in detail with reference to the accompanying drawings and attachments, and in the form of embodiments. The drawings used are for illustrative purposes only and to assist in the description, and may not represent the actual proportions and precise configurations after the implementation of this invention. Therefore, the proportions and configurations of the attached drawings should not be used to interpret or limit the scope of this invention in actual implementation.

[0021] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0023] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0024] Example 1

[0025] As shown in Figure 1-10, a double-sided fan-out packaging method is provided, including the following steps: Step 1: As shown in Figure 1, a special carrier sheet 101 is made. The carrier sheet 101 has a peelable structure 1010 symmetrically arranged on both sides. The peelable structure includes a separable copper foil and an intermediate layer, or a release film and an intermediate layer. The intermediate layer can be one or more of silicon, silicon dioxide, various types of glass, metal, and organic materials, with strong heat resistance and not easily deformed.

[0026] Step 2: As shown in Figure 2, apply insulating film or insulating adhesive to both sides to obtain the first insulating layer 102. The thickness of the first insulating layer 102 is 10-20μm. The first insulating layer 102 can be made of a photolithographic material and the pattern can be formed by exposure and development, or it can be made of a non-photolithographic material and the pattern can be formed by laser drilling.

[0027] Step 3: As shown in Figure 3, when the peelable structure includes a separable copper foil and an intermediate layer, the separable copper foil serves as the conductive layer. Using electroplating technology, a first metal layer (e.g., a tin layer, i.e., a Sn layer) is first formed at the openings (formed by exposure development or laser drilling) of the first insulating layer 102, followed by a second metal layer (e.g., a copper layer, i.e., a Cu layer). The formation methods include, but are not limited to, electroplating and filling with metal paste. The thickness of the first metal layer is 10 μm, and the thickness of the second metal layer is 5 μm. It should be noted that the materials of the first and second metal layers can be the same or different; this invention does not impose specific limitations on this.

[0028] Step 4: As shown in Figure 4, the first RDL circuit layer is fabricated using rewiring technology to form RDL wiring layer 103. Specifically, a conductive layer is first deposited, which can be formed by chemical copper plating or physical sputtering. The conductive layer material can be Cu or Ti / Cu. Then, a photoresist film layer is formed, and finally, the RDL pattern is formed by electroplating and etching of the conductive layer.

[0029] It is understandable that by repeating steps three and four, a single-layer RDL routing layer can be repeatedly formed on the carrier sheet, and the final RDL routing layer includes multiple layers of RDL routing.

[0030] Step 5: As shown in Figure 5, the second insulating layer 104 is formed. The material of the second insulating layer 104 can be photolithographic, and the pattern can be formed by exposure and development, or a non-photolithographic film can be used, and the pattern can be formed by laser drilling. The thickness of the second insulating layer 104 depends on the thickness of the first RDL layer and needs to extend about 10μm-20μm beyond the metal surface.

[0031] Step Six: As shown in Figure 6, the UBM metal layer is fabricated using double-sided redistribution technology. Specifically, the UBM metal layer can be formed by chemical copper plating or physical sputtering, and the material of the UBM metal layer is Cu or Ti / Cu; then a photoresist film layer is formed, and finally the UBM105 pattern is formed by electroplating and conductive layer etching.

[0032] Step 7: As shown in Figure 7-8, for the IC wafer, using bumping technology, copper-tin bumps (CuSn bumps) are formed on the connection ports. Then, thinning and dicing are performed to form wafer 106 (i.e., a single wafer). The connection port can be a metal pad, which can be understood as a connection port on the wafer. It should be noted that the pad is a metal area connected to the wafer; it is the input / output interface of the wafer, connecting the internal circuitry and external circuitry. The single, good wafer 106 with metal bumps is attached to the front-side UBM105 using flip-chip technology. Reflow soldering is then used to solder the metal bumps on wafer 106 to the front-side wiring of the UBM105. The same process is used to solder the metal bumps on the back-side wafer 106 to the back-side wiring of the UBM105.

[0033] Step 8: As shown in Figure 9, a molding layer 107 is formed using board-level molding technology to encapsulate the mounted chip 106.

[0034] Step 9: Perform the board separation process, separate the carrier sheet 101, and remove the copper foil layer of the carrier board remaining at the bottom of the insulating layer and wiring layer on both sides by rapid etching; or separate the board by mechanical force, using external force to separate the release film from the insulating layer and wiring layer on both sides.

[0035] Step 10: As shown in Figure 10, the entire board of products is cut into packaged chips, which are then tested, packaged, and shipped.

[0036] A double-sided fan-out package structure includes: a first insulating layer 102, on which openings are formed by exposure development or laser drilling, and a first metal layer and a second metal layer are formed at the openings; an RDL wiring layer 103, disposed on the second metal layer and the first insulating layer 102; a second insulating layer 104, disposed on the RDL wiring layer 103; a UBM 105, disposed at the opening position of the second insulating layer 104; and a chip 106, which has CuSn bumps on its connectors. The chip 106 is attached to the UBM 105 on the front side using flip-chip technology, and the metal bumps on the chip 106 are soldered to the UBM 105 by reflow soldering, wherein the UBM is disposed on a carrier substrate.

[0037] The molding layer 107 is used to cover the wafer 106.

[0038] Example 2

[0039] As shown in Figures 1 and 11-20, a double-sided fan-out packaging method is provided, including the following steps: Step 1: As shown in Figure 1, a special carrier sheet 101 is made. The carrier sheet 101 has a peelable structure symmetrically arranged on both sides. The peelable structure includes a separable copper foil and an intermediate layer, or a release film and an intermediate layer. The intermediate layer can be one or more of silicon, silicon dioxide, various types of glass, metal, and organic materials. It has strong temperature resistance and is not easy to deform.

[0040] Step 2: As shown in Figure 11, an adhesive layer 108 is formed on the carrier sheet 101. The adhesive layer 108 can be made of an adhesive insulating adhesive.

[0041] Step 3: As shown in Figures 12-15, the prefabricated RDL lines 109 are bonded to the carrier sheet 101 using adhesive. Then, the copper foil on the carrier sheet 101 and the RDL lines 109 are interconnected through drilling, electroless plating, or PVD. Repeat the above steps to complete the multi-layer RDL wiring, thus forming the surface UBM110 pattern. Different prefabricated lines (e.g., Figures 14 and 15) formed according to product requirements can be created through printing, 3D printing, or stamping.

[0042] Step 4: As shown in Figure 16, apply solder to the shaped UBM (e.g., copper pads or aluminum pads) to form solder joints 111.

[0043] Step 5: As shown in Figures 17-18, the IC wafer is first plated with NiAu in the connector area, and then thinned and diced to form chip 112. The single good chip 112 is then attached to the solder joint 111 on the front side using flip-chip technology. Reflow soldering is then used to solder the metal bumps on the chip 112 to the UBM110 of the wiring on the front side. The same process is used to solder the metal bumps on the chip 112 on the back side to the UBM110 of the wiring on the back side.

[0044] Step Six: As shown in Figure 19, a molding layer 107 is formed using board-level molding technology to encapsulate the mounted chip 112. Molding can be performed on both sides one by one, or both sides can be molded simultaneously through mold design and technology development, thereby eliminating the warping problem after molding on only one side.

[0045] Step 7: Perform the board separation process, separate the carrier sheet 101, and remove the insulating film on both sides and the copper foil layer of the peelable structure remaining at the bottom of the wiring layer using a rapid etching method; or separate the board by mechanical force, using external force to separate the release film from the insulating film and wiring layer on both sides; then perform NiAu plating treatment (or tin printing) on ​​the exposed UBM113 to prevent Cu oxidation.

[0046] Step 8: As shown in Figure 20, the entire board of products is cut into packaged chips, which are then tested, packaged, and shipped.

[0047] The present invention also provides a double-sided fan-out package structure, comprising: a wafer 112, which is formed by plating NiAu in the IC wafer interconnection area and then thinning and dicing; a molding compound 107 for covering the wafer 112; an adhesive layer 108; and pre-fabricated RDL lines 109.

[0048] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0049] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any modifications or equivalent substitutions made to the present invention without departing from the spirit and scope thereof should be covered within the protection scope of the patent application of the present invention.

[0050] 101: Carrier plate 1010: Peelable structure 102: First insulating layer 103: RDL routing layer 103 104: Second insulating layer 105: UBM 106: Chip 107: Molding layer 108: Adhesive layer 109: RDL Line 110:UBM 111: Solder joint 112: Chip 113:UBM

Claims

1. A double-sided fan-out packaging method, characterized in that it includes: A carrier substrate is fabricated, with symmetrically arranged peelable structures on both sides. These peelable structures are formed by stacking a release film or separable copper foil with an intermediate layer. A first insulating layer with openings is formed on both sides of the peelable structure away from the carrier substrate. Adjacent first and second metal layers are sequentially formed at the openings by electroplating and / or filling with metal paste. The first metal layer includes a tin layer, and the second metal layer includes a copper layer. Multilayer RDL wiring is formed on the side of the second metal layer away from the carrier substrate. A wafer, including metal bumps, is mounted on the side of the multilayer RDL wiring away from the carrier substrate. The wafer is encapsulated using board-level molding technology, covering both sides of the carrier substrate. The carrier substrate is then split into two parts, and residual separable copper foil or release film is removed by rapid etching or mechanical peeling to obtain two independent packaged wafers. The wafer mounting step includes: Using flip-chip technology, the chip is attached to the UBM of the carrier chip. The metal bumps are soldered to the UBM by reflow soldering. The chip fabrication steps include: For the IC wafer, using bump manufacturing technology, copper-tin bumps are formed on the interconnects, and then the wafer is thinned and diced to form the chip.

2. The double-sided fan-out packaging method as described in claim 1, wherein, The first insulating layer with openings is provided on both sides of the peelable structure away from the carrier sheet, including: obtaining the first insulating layer with openings by adhering an insulating film or applying insulating adhesive to both sides of the peelable structure away from the carrier sheet.

3. A double-sided fan-out package structure, characterized in that it is prepared using the double-sided fan-out package method as described in claim 1 or 2, the method comprising: A carrier substrate is fabricated, with symmetrically arranged peelable structures on both sides. These peelable structures are formed by stacking a release film or separable copper foil with an intermediate layer. A first insulating layer with openings is formed on both sides of the peelable structure away from the carrier substrate. Adjacent first and second metal layers are sequentially formed at the openings by electroplating and / or filling with metal paste. The first metal layer includes a tin layer, and the second metal layer includes a copper layer. Multilayer RDL wiring is formed on the side of the second metal layer away from the carrier substrate. A wafer, including metal bumps, is mounted on the side of the multilayer RDL wiring away from the carrier substrate. The wafer is encapsulated using board-level molding technology, covering both sides of the carrier substrate. The carrier substrate is then split into two parts, and residual separable copper foil or release film is removed by rapid etching or mechanical peeling to obtain two independent packaged wafers. The wafer mounting step includes: The chip is mounted onto the UBM (Underlying Machine Bump) of the carrier wafer using flip-chip technology. Reflow soldering is then used to solder the metal bumps to the UBM. The chip fabrication steps include: For the IC wafer, using bump manufacturing technology, copper-tin bumps are formed on the interconnects, followed by thinning and dicing to form the chip. The package structure includes: a first insulating layer with openings, where a first metal layer is formed first, followed by a second metal layer; an RDL (Radio Deposit Layer) wiring layer disposed on the first insulating layer; a second insulating layer disposed on the RDL wiring layer; a UBM located at the openings in the second insulating layer; a chip mounted onto the UBM using flip-chip technology, with the metal bumps on the chip soldered to the UBM; and a molding compound layer covering the chip.

4. A double-sided fan-out packaging method, characterized in that it includes: A carrier sheet is fabricated, with symmetrically arranged peelable structures on both sides. These peelable structures are formed by stacking a release film or separable copper foil with an intermediate layer. An adhesive layer is formed on both sides of the peelable structure away from the carrier sheet. This adhesive layer is an adhesive insulating layer. Pre-fabricated RDL lines are bonded to the peelable structure and a portion of the adhesive layer. Interconnection between the plated bottom layer and the RDL is achieved through drilling, electroless plating, or physical vapor deposition, completing the multi-layer RDL wiring. Different pre-fabricated RDL lines used in fabricating the multi-layer RDL wiring are formed by printing, 3D printing, or stamping. UBMs are formed on the multi-layer RDL wiring, and solder is applied to the formed UBMs to form solder joints. A chip is attached to the solder joints. The chip is then encapsulated using board-level molding compounding technology, covering both sides of the carrier sheet. The carrier sheet is split into two parts, and the residual separable copper foil or release film is removed by rapid etching or mechanical peeling to obtain two independent packaged wafers. The wafer mounting step includes: attaching the wafer to the solder joint using flip chip technology, and soldering the metal bumps on the wafer to the UBM by reflow soldering. The wafer fabrication step includes: for the IC wafer, first plating NiAu in the connection port area, and then thinning and dicing to form the wafer.

5. The double-sided fan-out packaging method as described in claim 4, wherein, It also includes: after separating the carrier sheet, performing NiAu plating on the exposed UBM.

6. A double-sided fan-out package structure, characterized in that it is prepared using the double-sided fan-out package method as described in claim 4 or 5, the method comprising: A carrier sheet is fabricated, with symmetrically arranged peelable structures on both sides. These peelable structures are formed by stacking a release film or separable copper foil with an intermediate layer. An adhesive layer is formed on both sides of the peelable structure away from the carrier sheet. This adhesive layer is an adhesive insulating layer. Pre-fabricated RDL lines are bonded to the peelable structure and a portion of the adhesive layer. Interconnection between the plated bottom layer and the RDL is achieved through drilling, electroless plating, or physical vapor deposition, completing the multi-layer RDL wiring. Different pre-fabricated RDL lines used in fabricating the multi-layer RDL wiring are formed by printing, 3D printing, or stamping. UBMs are formed on the multi-layer RDL wiring, and solder is applied to the formed UBMs to form solder joints. A chip is attached to the solder joints. The chip is then encapsulated using board-level molding compounding technology, covering both sides of the carrier sheet. The carrier sheet is split into two parts, and the residual separable copper foil or release film is removed by rapid etching or mechanical peeling to obtain two independent packaged wafers. The wafer mounting step includes: attaching the wafer to the solder joint using flip-chip technology, and then soldering the metal bumps on the wafer to the UBM using reflow soldering. The wafer fabrication step includes: for the IC wafer, first plating NiAu in the connection port area, and then thinning and dicing to form the wafer. The package structure includes: a wafer, wherein the wafer is made by plating NiAu in the connection port area of ​​the IC wafer, and then thinning and dicing; a molding layer for covering the wafer; an adhesive layer, wherein the adhesive layer is formed on both sides away from the carrier sheet; and multilayer RDL wiring, with the exposed UBM areas treated with NiAu plating.

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