Testing method and test system

Abstract

A detection method and a detection system. The detection method is used to scan a three-dimensional memory chip. The three-dimensional memory chip includes multiple memory chips stacked on top of each other. The detection method includes: dividing each memory chip into multiple memory blocks; performing detection in each memory block to detect the total number of failed first signal lines from multiple first signal lines extending along a first direction in each memory block, and detecting the total number of failed memory cells in each memory block; determining a failure bit number threshold based on the total number of failed first signal lines, comparing the total number of failed memory cells with the failure bit number threshold, and determining whether to set a marker for the number of first signal lines.

Description

Technical Field

[0001] This invention relates to a method and system, and more particularly to a detection method and detection system. Prior Technology

[0002] In three-dimensional memory chips, as packaging and stacking become increasingly complex, a large number of additional, failed memory cells are often created. However, this influx of failed memory cells complicates the analysis of the causes of failure. Summary of the Invention

[0003] This invention provides a detection method and system that can efficiently identify stacking defects in three-dimensional memory chips.

[0004] The detection method of the present invention is used to scan a three-dimensional memory chip. The three-dimensional memory chip includes multiple memory chips stacked on top of each other. The detection method includes: dividing each memory chip into multiple memory blocks; performing detection in each memory block to detect the total number of failed first signal lines from multiple first signal lines extending along a first direction in each memory block, and detecting the total number of failed memory cells in each memory block; determining a failure bit number threshold based on the total number of failed first signal lines, comparing the total number of failed memory cells with the failure bit number threshold, and determining whether to set a marker for the number of first signal lines.

[0005] The detection system of the present invention includes a three-dimensional memory chip and a testing apparatus. The three-dimensional memory chip includes multiple layers of stacked memory chips. The testing apparatus is coupled to the three-dimensional memory chip and performs the following: dividing each memory chip into multiple memory blocks; performing detection in each memory block to detect the total number of failed first signal lines from multiple first signal lines extending along a first direction in each memory block, and detecting the total number of failed memory cells in each memory block; determining a failure bit number threshold based on the total number of failed first signal lines, comparing the total number of failed memory cells with the failure bit number threshold, and determining whether to set a marker for the number of first signal lines.

[0006] Based on the above, the detection method and detection system of the present invention can determine the distribution pattern of failed memory cells in memory chips, thereby simplifying the complex representation of failed memory cells. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of a memory chip according to Embodiment 1 of the present invention. Figure 2 is a flowchart of a detection method according to the present invention. Figure 3 is a flowchart of a detection method according to the present invention. Figure 4 is a flowchart of a detection method according to the present invention. Figure 5 is a flowchart of a detection method according to the present invention. Figure 6 is a flowchart of a detection method according to the present invention. Figure 7 is a flowchart of a detection method according to the present invention. Figure 8A is a block diagram of the detection system of Embodiment 1 of the present invention. Figure 8B is a schematic diagram of a detection system according to another embodiment of the present invention. Implementation

[0008] Figure 1 is a schematic diagram of a memory chip 1 according to an embodiment of the present invention. The memory chip 1 is divided into multiple memory blocks. Figure 1 illustrates various distribution patterns of failed memory cells in the memory chip 1. To facilitate analysis and summarization of failure causes, the failed memory cells shown in Figure 1 will be divided into three categories, thereby summarizing and simplifying the number of failed memory cells that appear in large quantities in the three-dimensional chip through the simplified distribution patterns of the three categories of failed memory cells (or failed bits).

[0009] In detail, although not explicitly shown, memory chip 1 includes multiple memory libraries, each of which is further divided into multiple memory blocks. However, to facilitate the illustration of the distribution of failed memory cells in each memory block, only the memory blocks in memory chip 1 are shown in Figure 1, and the labels for memory libraries are omitted.

[0010] In memory chip 1, each dot represents a failed memory cell. On memory block A11 of memory chip 1, multiple failed memory cells are arranged and connected to the same word line extending along the X-axis; therefore, this word line can be identified as the failed word line FWL. In some cases, this distribution pattern of failed memory cells may be caused by defects on the word line. Instead of recording the location of each failed memory cell, the distribution of failed memory cells in memory block A11 can be represented by recording the failed word line FWL to represent all failed memory cells in memory block A11.

[0011] Furthermore, in memory block A12 of memory chip 1, there are multiple failed memory cells arranged and connected to the same bit line extending along the Y-axis. Therefore, this bit line can be identified as the failed bit line FBL. Similar to the description of the failed bit line in the previous paragraph, given the distribution of failed memory cells in memory block A12, it can also be changed to record the failed bit line FBL to represent all the failed memory cells in memory block A12.

[0012] Finally, memory block A13 in the memory chip contains multiple independent failed memory cells FBC1~FBC3. Unlike the arrangement of failed memory cells in memory blocks A11 and A12, these independent failed memory cells are arranged on different word lines and different bit lines, and the occurrence of each failed memory cell is like an independent event. Given this arrangement of failed memory cells, it is necessary to record the addresses of all failed memory cells.

[0013] Therefore, based on the above, the distribution patterns of failed memory cells can be classified into three types: arranged along character lines, arranged along bit lines, and independently distributed. Depending on their respective distribution patterns, they can be represented by corresponding failed character lines, failed bit lines, or independently distributed failed memory cells.

[0014] Figure 2 is a flowchart of a detection method according to the present invention. The detection method in Figure 2 can be applied to detect faulty memory cells in a memory chip, and the faulty memory cells in the memory chip are represented in a manner related to that described in Figure 1. Generally speaking, the detection method in Figure 2 can be used to detect whether faulty memory cells in a memory block are concentrated on a few specific first-order lines.

[0015] In detail, the detection method in Figure 2 includes steps S21 to S26. In step S21, the memory chip is first divided into multiple memory blocks. Specifically, each memory chip contains multiple memory libraries, and each memory library contains memory blocks of the same size and number, so that the failed memory cells in each memory block can be analyzed in subsequent steps.

[0016] In step S22, the selected memory blocks are detected to determine the total number of failed first signal lines from a plurality of first signal lines extending along a first direction, the total number of failed second signal lines from a plurality of second signal lines extending along a second direction, and the total number of failed memory cells in each memory block. In short, this step detects the total number of failed memory cells, the total number of failed first signal lines, and the total number of failed second signal lines.

[0017] Generally, each memory block has multiple first signal lines extending along a first direction, and multiple second signal lines extending along a second direction different from the first direction. A memory cell can be located at the intersection of each first and second signal line. For example, the first signal line can be a word line, used to control the on / off state of each corresponding memory cell. The second signal line can be a bit line, used for data transmission with each corresponding memory cell.

[0018] In step S23, the threshold for the number of failed bits can be determined based on the total number of failed first signal lines. Furthermore, in step S24, the total number of failed memory cells can be compared with the threshold for the number of failed bits to determine whether the target memory block belongs to the distribution pattern of the first type of failed memory cells.

[0019] In detail, steps S23 and S24 are used to determine whether failed memory cells in the target memory block are concentrated on a portion of the first signal lines, that is, the concentration trend of failed memory cells in the memory block. To determine this, the corresponding failure bit number threshold can first be determined based on the total number of failed first signal lines. In some embodiments, when the total number of failed first signal lines is less than or equal to the signal line threshold, the failure bit number threshold can be set to a first number, and when the total number of failed first signal lines is greater than the signal line threshold, the failure bit number threshold can be set to a second number greater than the first number. For example, when the total number of failed first signal lines is less than or equal to the threshold of one signal line, the failure bit number threshold can be set to a first number of four. And when the total number of failed first signal lines is greater than one, the failure bit number threshold can be set to a second number of eight. In this way, the threshold for the number of failed bits can be adjusted according to the total number of failed first signal lines, thus appropriately determining whether the failed memory cells in the target memory block are concentrated on a few specific failed first signal lines.

[0020] In some embodiments, depending on the possible different sizes of memory blocks, the signal line thresholds in the above steps may be multiple thresholds to determine which interval the total number of failed first signal lines falls within, and a corresponding threshold for the number of failed bits can be set according to each interval.

[0021] Following step S24, if the total number of failed memory cells is greater than or equal to the threshold for the number of failed bits, then proceed to step S25. If the total number of failed memory cells is less than the threshold for the number of failed bits, then proceed to step S26.

[0022] In step S25, the total number of failed first signal lines can be determined as the number of marked first signal lines, and the number of partial second signal lines caused by the failed memory cells marked as first failed signal lines can be set as the assumed number of marked second signal lines. Specifically, since the comparison results in step S24 have determined that the failed memory cells in the target memory block are concentrated on a few specific failed first signal lines, the total number of failed first signal lines can be used to represent the failed memory cells in the target memory block. On the other hand, since the failed memory cells in the target memory block have a distribution pattern concentrated on specific first signal lines, statistics can be performed on the failed memory cells distributed on these marked first failed signal lines to count the number of partial second signal lines distributed among the failed memory cells marked as first failed signal lines, and this partial number of second signal lines can be set as the assumed number of marked second signal lines to facilitate subsequent judgment.

[0023] If the comparison result in step S24 is negative, or if step S25 ends, the process will proceed to step S26. In step S26, the location of the target memory block will be changed to detect and determine the next target memory block.

[0024] Overall, steps S22 to S26 can be regarded as a step S10, which detects memory blocks in the memory chip one by one, and determines whether the failed memory cells in each memory chip are concentrated on a few specific first signal lines, thereby setting the total number of failed first signal lines and the number of assumed marked second signal lines.

[0025] Figure 3 is a flowchart of a detection method according to the present invention. The detection method in Figure 3 can be applied to detect faulty memory cells in a memory chip, and the faulty memory cells in the memory chip are represented in a manner related to that described in Figure 1. In this embodiment, the detection method in Figure 3 can be performed, for example, following the detection method in Figure 2. Specifically, after determining the number of marker first signal lines for each memory block in the detection method of Figure 2, that is, whether the concentration trend of faulty memory cells is arranged along the direction of the first signal lines, it can be further detected and determined whether the faulty memory cells are independently distributed in the memory block.

[0026] The detection method in Figure 3 includes steps S31 to S33. In step S31, it is first determined whether the total number of first failed signal lines in the target memory block is equal to the total number of second failed signal lines. By determining whether the total number of first failed signal lines and the total number of second failed signal lines are equal, it can be determined whether the failed memory cells have a tendency to be arranged along the first signal line or the second signal line. Since the independent distribution of failed memory cells presents a random distribution, when it is determined that the total number of first failed signal lines and the total number of second failed signal lines are equal, it can be determined that the failed memory cells in the target memory block are independently distributed. Therefore, in step S31, when it is determined that the total number of first failed signal lines and the total number of second failed signal lines are equal, the process proceeds to step S32 to set the corresponding parameters. If not, the process proceeds to step S33.

[0027] In step S32, in response to determining that the memory cells in the target memory block are independently distributed, the total number of first failure signal lines can be set as the number of independently failed memory cells.

[0028] Furthermore, if the comparison result in step S31 is negative, or if step S32 is completed, step S33 will be entered to change the location of the target memory block and detect and judge the next target memory block.

[0029] In this embodiment, the condition for whether the failed memory cells are independently distributed is whether the total number of failed first signal lines is equal to the total number of failed second signal lines. However, in other embodiments, the condition for whether the failed memory cells are independently distributed may also be that the difference between the total number of failed first signal lines and the total number of failed second signal lines is within a preset range. Alternatively, the total number of failed second signal lines may also be used as the number of independently distributed failed memory cells.

[0030] Overall, steps S31 to S33 can be regarded as a step S11, which involves detecting memory blocks in the memory chip one by one and determining whether the failed memory cells in each memory chip are independently distributed, thereby setting the number of independently failed memory cells.

[0031] Figure 4 is a flowchart of a detection method according to the present invention. The detection method in Figure 4 can be applied to detect faulty memory cells in a memory chip, and the faulty memory cells in the memory chip are represented in a manner related to that described in Figure 1. In this embodiment, the detection method in Figure 4 can be executed, for example, following the detection methods in Figures 2 and 3. Specifically, after executing the detection methods in Figures 2 and 3, it can be determined whether the faulty memory cells in each memory block are concentrated along a few specific first signal lines or are independently distributed. Furthermore, after executing the detection methods in Figures 2 and 3, the faulty memory cells in the target memory block can be set to be distributed along a few specific second signal lines.

[0032] The detection method in Figure 4 includes step S41. In step S41, the total number of failed second signal lines is subtracted from the assumed number of labeled second signal lines and the number of independent failed memory cells to obtain the number of labeled second signal lines. Specifically, after executing the detection methods in Figures 2 and 3, two distribution patterns of failed memory cells in the target memory block have been analyzed. Therefore, in step S41, the third distribution pattern can be directly determined based on the previous analysis results.

[0033] Specifically, the total number of failed second signal lines can be subtracted from the number of assumed marked second signal lines and the number of independently failed memory cells. When failed memory cells in a target memory block are determined to be distributed along certain first signal lines, assumed marked second signal lines can be set to store the number of failed second signal lines caused by those memory cells. Therefore, by subtracting the number of assumed marked second signal lines and the number of independently failed memory cells from the total number of failed second signal lines, the number of failed second signal lines detected caused by memory cells of the first two distribution types (i.e., distributed along the first signal lines and independently distributed) can be excluded, thus obtaining the number of failed second signal lines caused by failed memory cells distributed along certain second signal lines (i.e., the number of marked second signal lines).

[0034] Overall, step S41 can be regarded as step S12, which is executed after steps S10 and S11. After judging the first two distribution patterns of the failed memory cells in the target memory block, it judges whether the failed memory cells are distributed along a few specific second signal lines based on the previous judgment results, and calculates the number of marked second signal lines.

[0035] Figure 5 is a flowchart of the detection method according to Embodiment 1 of the present invention. The detection method shown in Figure 5 can be continued from the detection methods in Figures 2 to 4, and can be used to determine whether the target memory block is invalid or defective.

[0036] The detection method in Figure 5 includes steps S51 to S54. In step S51, it is determined whether the number of marked second signal lines in the target memory block exceeds the failure threshold of the first block. Specifically, the determination of the number of marked second signal lines follows the determination of the number of marked first signal lines and the number of independent signal lines. When the failed memory cells are not simply distributed along a few specific first signal lines or exhibit a sporadic independent distribution pattern, the remaining failed memory cells will be classified as failures of the second signal lines. Therefore, the number of marked second signal lines may include not only the distribution pattern of failed memory cells along the second signal lines, but also more complex distribution patterns of failed memory cells that cannot be summarized by the three distributions in Figure 1. Therefore, when it is determined that the number of marked second signal lines is too large, that is, greater than the failure threshold of the first block, the process proceeds to step S52.

[0037] In step S52, it is determined whether the total number of failed first signal lines minus the number of independently failed memory cells in the target memory block is greater than the failure threshold of the second block. Specifically, the number of independently failed memory cells is subtracted from the total number of failed first signal lines, corresponding to the failed memory cells detected in the initial detection phase. If the result after subtraction is greater than the failure threshold of the second block, it means that the judgment results of steps S51 and S52 are both yes, and the process proceeds to step S53.

[0038] In step S53, in response to the first block failure threshold and the second block failure threshold both being reached, the target memory block can be set as a failed memory block.

[0039] After step S53 is completed, or if the result of either step S51 or S52 is negative, step S54 will be entered to replace the target memory block and determine whether the next target memory block is invalid, until all target memory blocks have been determined.

[0040] Overall, steps S51 to S54 can be regarded as step S13, which is executed after steps S10 to S12. Based on the distribution pattern of the failed memory cells determined in steps S10 to S12, it is determined whether to set the target memory block as a failed memory block.

[0041] Figure 6 is a flowchart of the detection method according to Embodiment 1 of the present invention. The detection method shown in Figure 6 can be continued from the detection methods in Figures 2 to 5, and can be used to determine whether each memory bank is a failed memory bank or a defective memory bank.

[0042] In step S61, it can be determined whether the number of failed memory blocks in the target memory bank is greater than the memory bank failure threshold. If the determination result in step S61 is yes, then step S62 is performed, and the target memory bank is set as a failed memory bank or a defective memory bank based on the number of failed memory blocks.

[0043] For example, the memory bank failure threshold could be five. When the number of failed memory blocks in the target memory bank is determined to be greater than or equal to the five-fold failure threshold, the target memory bank can be classified as a failed memory bank. Conversely, when the number of failed memory blocks in the target memory bank is determined to be less than the five-fold failure threshold, the target memory bank can be classified as a slightly defective memory bank.

[0044] Finally, after step S62 is completed, or if the judgment result of step S61 is negative, step S63 will be entered to change the target memory bank to judge the next memory bank, until all memory banks have been judged.

[0045] Overall, steps S61 to S63 can be regarded as step S14, which is executed after steps S10 to S13, and is used to set the target memory bank as defective or invalid.

[0046] Figure 7 is a flowchart of the detection method according to Embodiment 1 of the present invention. The detection method shown in Figure 7 can be continued from the detection methods in Figures 2 to 6 to determine whether the three-dimensional memory chip has defects in the stacking structure.

[0047] The detection method in Figure 7 includes steps S71-S72. In step S71, all failed memory libraries in the three-dimensional memory chip are analyzed to determine whether they overlap vertically, and the overlapping positions are marked accordingly. Specifically, after identifying failed memory libraries for each layer of the memory chip, the positions of the memory libraries are analyzed to determine whether they overlap vertically. When overlapping failed memory libraries are identified in the three-dimensional memory chip, the overlapping positions are marked, and the number of overlapping failed memory libraries at the marked positions is determined.

[0048] In step S72, based on the number of marked locations and the number of failed memory libraries corresponding to each marked location, it can be determined whether the 3D memory chip has defects in its stacking structure. Specifically, the number of failed memory libraries occurring at the same marked location is first counted to determine the exact number of failed memory libraries at that location. Based on the number of failed memory libraries at that marked location, it can be determined whether the 3D memory chip has defects. In some embodiments, the number of failed memory libraries at the marked location can be compared with multiple chip failure thresholds to determine which range the 3D memory chip falls into, and thereby determine the defect level of the 3D memory chip.

[0049] For example, in a three-dimensional memory chip with four stacked layers, if the number of failed memory cells at the marked location reaches three or more, it means that the stacking structure has caused three of the four memory layers to fail or be damaged. Therefore, the three-dimensional memory chip can be judged as having a more serious defect. Conversely, if the number of failed memory cells at the marked location is less than three, although the stacking structure has a defect, it is less severe. Therefore, the three-dimensional memory chip can be judged as having a less severe defect.

[0050] To give another example, for a four-layer three-dimensional memory chip, if it is determined that two of the layers have eight interconnected failed memory banks in the same location, the three-dimensional memory chip can be judged as having a more serious defect. Conversely, if only one layer of the three-dimensional memory chip has eight interconnected failed memory banks, the three-dimensional memory chip can be judged as having a less serious defect.

[0051] Overall, steps S71 to S73 can be regarded as step S15, which is executed after steps S10 to S14, to determine whether the three-dimensional memory chip has defects and the degree of defects.

[0052] Figure 8A is a block diagram of the detection system 8a according to Embodiment 1 of the present invention. The detection system 8a includes a three-dimensional memory chip 80 and a testing device 81. The three-dimensional memory chip 80 includes multiple layers of memory chips stacked on top of each other. The testing device 81 is coupled to the three-dimensional memory chip 80 and can be used to perform the detection methods described in Figures 2 to 7 above to determine whether there are defects in the three-dimensional memory chip 80 caused by stacking.

[0053] In some embodiments, the testing device 81 may be, for example, a notebook computer or related testing equipment. The testing device 81 may include a central processing unit and memory for performing tests on the three-dimensional memory chip 80.

[0054] Figure 8B is a schematic diagram of a detection system 8b according to another embodiment of the present invention. The detection system 8b also includes a three-dimensional memory chip 80 and a built-in self-test (BIST) circuit 82 disposed within the three-dimensional memory chip 80. Specifically, the three-dimensional memory chip 80 includes multiple stacked memory chips, interconnected and transmitting signals through vias or interconnection structures. Each memory chip contains an array of memory cells. Below the stacked memory chips, a logic chip is disposed, coupled to the memory chips. The logic chip has logic circuits that can access the data stored in the memory chips and perform corresponding operations. The built-in self-test circuit 82 is disposed on the logic chip and connected to the memory chips through metal traces and vias. The built-in self-test circuit 82 can access the memory chips and perform the detection methods described in Figures 2-7 above to determine whether the three-dimensional memory chip 80 has defects caused by stacking.

[0055] In some embodiments, although not explicitly illustrated, the test apparatus 81 may also be composed of multiple BIST circuits. Specifically, the multiple BIST circuits of the test apparatus 81 may be respectively disposed in the memory chip. Each BIST circuit can test the memory chip of that layer and determine the result including the number of first marker signal lines, the number of second marker signal lines, the number of independent failed memory cells, the number of failed memory blocks, and / or the number of failed memory libraries of that layer. Furthermore, each BIST circuit can share the result with the BIST circuits of other layers, thereby determining whether there are defects in the stacked structure in the three-dimensional memory chip. For the above-described operation of each BIST circuit testing and determining the result including the number of first marker signal lines, the number of second marker signal lines, the number of independent failed memory cells, the number of failed memory blocks, and / or the number of failed memory libraries of that layer, please refer to the relevant paragraphs above, which will not be repeated here.

[0056] In summary, the detection method and system of the present invention can determine the distribution pattern of failed memory cells in a memory chip, thereby simplifying the complex representation of failed memory cells. Based on this, the correlation between failed memory libraries of different memory chips can be determined, and thus, whether there are defects in the three-dimensional memory chip caused by stacking can be identified.

[0057] 1: Memory chip 8a, 8b: Detection system 80: Three-dimensional memory chip 81: Testing equipment 82: Built-in self-test circuit A11~A13: Blocks FBL, FWL: Line FBC1~FBC3: Memory cells S10~S14, S21~S26, S31~S33, S41, S51~S54, S61~S63, S71~S72: Steps

Claims

1. A detection method for scanning a three-dimensional memory chip, the three-dimensional memory chip comprising a plurality of memory chips stacked on top of each other, the detection method comprising: Each memory chip is divided into multiple memory blocks; The detection process involves performing a test on each memory block to detect a total number of failed first signal lines from a plurality of first signal lines extending along a first direction in each memory block, and to detect a total number of failed memory cells in each memory block. A failure bit count threshold is adjusted based on the total number of failed first signal lines, and the total number of failed memory cells is compared with the failure bit count threshold. Based on this comparison, it is determined whether to set a number of marked first signal lines. The plurality of marked first signal lines corresponding to the number of marked first signal lines are used to indicate that the multiple failed memory cells in each memory block are concentrated on these marked first signal lines. When the total number of failed first signal lines is less than or equal to a signal line threshold, the failure bit count threshold is set to a first count. When the total number of failed first signal lines is greater than the signal line threshold, the failure bit count threshold is set to a second count greater than the first count.

2. The detection method as described in claim 1, wherein when the total number of failed memory cells is greater than or equal to the number of failed bits threshold, the total number of failed first signal lines is determined as the number of marked first signal lines.

3. The detection method as described in claim 1, comprising: The total number of failed second signal lines is detected from a plurality of second signal lines extending along a second direction in each memory block, wherein the first direction is different from the second direction.

4. The detection method as described in claim 3, comprising: In response to the setting of the number of the first signal lines of the marker, a portion of the number of the second signal lines generated by the number of the first signal lines of the marker is determined, and the portion of the number of the second signal lines is set as an assumed number of the second signal lines of the marker.

5. The detection method as described in claim 4, comprising: Subtract the assumed number of marked second signal lines from the total number of failed second signal lines to obtain a number of marked second signal lines.

6. The detection method as described in claim 5, further comprising, before calculating the number of the second signal lines of the marker: The determination of whether to set an independent failure memory cell number is made by comparing the total number of first failure signal lines with the total number of second failure signal lines.

7. The detection method as described in claim 6, wherein when the total number of first failure signal lines is equal to the total number of second failure signal lines, the total number of first failure signal lines is set as the number of independent failure memory cells.

8. The detection method as described in claim 7 further includes subtracting the assumed number of marked second signal lines and the number of independently failed memory cells from the total number of failed second signal lines to obtain the number of marked second signal lines.

9. The detection method as described in claim 1 further includes: When the total number of failed first signal lines minus the number of independently failed memory cells in each memory block is greater than or equal to a first block failure threshold, and when the number of marked second signal lines in the same memory block is greater than or equal to a second block failure threshold, the corresponding memory block is set as a failed memory block.

10. The detection method as described in claim 9, wherein each memory chip is further divided into multiple memory libraries, each memory library including the memory blocks, and the detection method further includes: Based on the number of invalid blocks in each memory bank that are set as invalid memory blocks, determine whether to set each memory bank as an invalid memory bank.

11. The detection method as described in claim 10, further comprising: Based on the failed memory libraries in the three-dimensional memory chip, select the failed memory libraries that overlap with each other in a vertical position; And based on the number of failed memory libraries that overlap in that vertical position, it is determined whether the three-dimensional memory chip has a stacking structure defect.

12. A detection system, comprising: A three-dimensional memory chip, comprising multiple layers of stacked memory chips; And a testing apparatus, coupled to the three-dimensional memory chip, for performing the following: dividing each memory chip into multiple memory blocks; performing detection in each memory block to detect a total number of failed first signal lines from multiple first signal lines extending along a first direction in each memory block, and detecting a total number of failed memory cells in each memory block; adjusting a failure bit count threshold based on the total number of failed first signal lines, comparing the total number of failed memory cells with the failure bit count threshold, and determining whether to set a number of marked first signal lines, wherein the multiple marked first signal lines corresponding to the number of marked first signal lines are used to indicate that the multiple failed memory cells in each memory block are concentrated on the marked first signal lines. When the total number of failed first signal lines is less than or equal to a signal line threshold, the threshold for the number of failed bits is set to a first number; and when the total number of failed first signal lines is greater than the signal line threshold, the threshold for the number of failed bits is set to a second number greater than the first number.

13. The testing system as claimed in claim 12, wherein the testing system is an external testing device and / or a built-in self-test (BIST) circuit built into a logic chip in the three-dimensional memory chip.

14. The detection system as claimed in claim 12, wherein the testing system includes a plurality of built-in self-test (BIST) circuits disposed in the multilayer memory chips, each of the BIST circuits being used to determine the number of the first signal lines of the marker in the corresponding memory chip.

15. The detection system of claim 13, wherein one of the built-in self-test circuits is configured to share the corresponding number of the first signal lines of the marker with at least one of the other built-in self-test circuits.

16. The detection system as claimed in claim 14, wherein each of the built-in self-test circuits is further configured to: set the corresponding memory block as a failed memory block when the total number of failed first signal lines minus the number of independently failed memory cells in each memory block is greater than or equal to a first block failure threshold, and when the number of marked second signal lines in the same memory block is greater than or equal to a second block failure threshold.

17. The detection system as claimed in claim 16, wherein each memory chip is further divided into multiple memory libraries, each memory library including memory blocks, and each built-in self-test circuit is further configured to: determine whether to set each memory library as a failed memory library based on the number of failed blocks in each memory library that are set as the failed memory blocks.

18. The detection system of claim 17, wherein the testing apparatus is further configured to: select, based on the failed memory libraries in the three-dimensional memory chip, those failed memory libraries that overlap each other in a vertical position; and determine, based on the number of the failed memory libraries that overlap each other in the vertical position, whether the three-dimensional memory chip has a stacking structure defect.

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