Packaging substrate and manufacturing method of the same

Abstract

This embodiment relates to a packaging substrate and a method for manufacturing the same. The packaging substrate according to this embodiment may include: a glass substrate including a first surface and a second surface facing each other; and an upper layer stacked above the first surface or a lower layer stacked below the second surface, the packaging substrate having an edge region. The edge region includes: an edge of the glass substrate; and a region of the glass substrate that protrudes further than the upper or lower layer. The method for manufacturing the packaging substrate includes: preparing a glass substrate including a first surface and a second surface facing each other, and forming an upper layer above the first surface; removing a portion of the upper layer along a cutting line designated as a predetermined cutting position to form a removal line; forming a filament on the glass substrate along the removal line; and cutting the glass substrate using the filament. Accordingly, defects occurring on the surface and cross-section of the substrate can be easily detected.

Description

Technical Field

[0001] This embodiment relates to a semiconductor packaging substrate and a method for manufacturing the semiconductor packaging substrate, and also relates to the technology of packaging substrates including glass substrates and the method for manufacturing them. Prior Technology

[0002] In the manufacturing of electronic components, the process of implementing circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling wafers into a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies in the semiconductor industry, which enable the rapid development of electronic products, are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms, including linewidths of sub-micrometer nanometers, tens of millions of cells, high-speed operation, and massive heat dissipation. However, it lacks a robust, relatively perfect packaging technology as a foundation. Therefore, compared to the performance of the semiconductor technology itself, the electrical performance of the semiconductor is determined by packaging technology and its electrical connections.

[0004] While ceramics or resins are currently being used as packaging substrates, research is underway on the application of silicon or glass as high-end packaging substrates. In particular, packaging substrates with cavity structures have been developed by using glass substrates.

[0005] On the other hand, the re-distribution layer (RDL) in the packaging process is a general term for the technology of using wafer-level packaging (WLP) to change the position of pre-formed electrical terminals (e.g., aluminum pads) to arbitrary locations. This RDL is used as a method to eliminate design limitations existing in the semiconductor manufacturing process through packaging, that is, it is being applied to the stacking of semiconductor chips.

[0006] As relevant prior art, there are US Patent Publication No. 2022 / 0336481A1 and Korean Patent Publication No. 10-2020-0133340, etc. Summary of the Invention

[0007] [The problem the invention aims to solve] [ ]

[0008] The purpose of this embodiment is to provide a packaging substrate and a method thereof that can easily detect defects that may occur on the glass substrate in the glass substrate and the packaging substrate on which multiple components are mounted.

[0009] Furthermore, the purpose of this embodiment is to provide a packaging substrate and its manufacturing method that can simultaneously detect defects appearing on the surface and cross-section of a glass substrate.

[0010] In addition, the purpose of this embodiment is to reduce the time and cost of inspecting and testing the quality of glass substrates.

[0011] [Methods used to solve problems] [ ]

[0012] To achieve the above objectives, a packaging substrate according to one embodiment may include: a glass substrate including a first surface and a second surface facing each other; and an upper layer or a lower layer, the upper layer being stacked above the first surface and the lower layer being stacked below the second surface, the glass substrate potentially having an edge region. The edge region may include: an edge of the glass substrate; and a region in the glass substrate that protrudes further than the upper layer or the lower layer.

[0013] The upper layer may include a first insulating layer stacked on top of the first surface.

[0014] The edge of the first insulating layer can be configured such that it extends from the edge of the glass substrate toward the inside, and the edge region can include the edge of the glass substrate and the edge of the first insulating layer.

[0015] Additionally, the lower layer may include a second insulating layer stacked below the second surface, and the edge of the second insulating layer may be configured such that it extends from the edge of the glass substrate toward the inside. The edge region may include the edge of the glass substrate and the edge of the second insulating layer.

[0016] The width from the edge of the first insulating layer to the edge of the glass substrate can be from 5 μm to 200 μm.

[0017] The width from the edge of the second insulating layer to the edge of the glass substrate can be from 5 μm to 200 μm.

[0018] According to one embodiment, the edge region may be curved.

[0019] The corners of the glass substrate in the edge region may be curved.

[0020] According to other embodiments, the edge region may be processed into a chamfer.

[0021] The corners of the glass substrate in the edge region can be chamfered.

[0022] The upper layer or the lower layer may each have a tapered shape that gradually thins towards the edge region.

[0023] The upper layer or the lower layer may have a tapered shape that gradually thins towards the cut surface of the glass substrate.

[0024] Semiconductor components can be mounted on the upper part of the upper layer.

[0025] To achieve the above objectives, a method for manufacturing a packaging substrate according to one embodiment can manufacture the packaging substrate by including the following steps: preparing a glass substrate comprising a first surface and a second surface facing each other, and forming an upper layer above the first surface; removing a portion of the upper layer along a cutting line designated as a predetermined cutting position to form a removal line; forming a filamentation process along the removal line on the glass substrate; and cutting the glass substrate using the filament.

[0026] According to one embodiment of the method for manufacturing a packaging substrate, before the filamentation process step, the method may further include: a step of forming a lower layer below the second surface; and a step of removing a portion of the lower layer along the cutting line to form a removal line.

[0027] The width of the removal line can be 5 μm or more. Furthermore, the width of the removal line can be 200 μm or less.

[0028] The upper layer and / or the lower layer may have a tapered shape that gradually thins towards the cut surface of the glass substrate.

[0029] The step of cutting the glass substrate may be to separate the glass substrate into two or more parts by applying tensile stress or rotational force to the filament, so as to form a cut surface on the glass substrate.

[0030] According to one embodiment of the method for manufacturing a packaging substrate, after the step of cutting the glass substrate, a step of grinding the cut surface of the cut glass substrate may be included.

[0031] The edge region of the glass substrate includes: the edge of the glass substrate; and a region in the glass substrate that protrudes further than the upper layer or the lower layer.

[0032] The method for manufacturing a packaging substrate according to one embodiment may further include a step of detecting defects selected from any one of the cut surfaces of the glass substrate, removal lines of the upper layer, removal lines of the lower layer, and combinations thereof.

[0033] [Invention Effects] [ ]

[0034] According to this embodiment, defects that may occur on the packaging substrate and / or glass substrate can be easily detected. Furthermore, according to this embodiment, defects occurring on both the surface and cross-section of the glass substrate can be detected simultaneously. Additionally, according to this embodiment, breakage, cracks, and other defects that may occur on the glass substrate can be detected effectively and at low cost. Simple Explanation of the Diagram

[0035] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of the packaging substrate according to this embodiment. Figure 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment. Parts (a) and (b) of Figure 3 are conceptual diagrams illustrating a portion of the packaging substrate according to this embodiment using cross-section. Figure 4, in parts (a) to (e), are flowcharts illustrating the process of generating the distribution layer during the manufacturing of the packaging substrate according to this embodiment, using cross-sections. Figure 5, in parts (a) to (e), are flowcharts illustrating the process of generating the upper layer during the manufacturing of the packaging substrate according to this embodiment, using cross-sections. Figure 6, from (a) to (c), are cross-sectional views illustrating the packaging substrate according to this embodiment. Figure 7 is a top view of the packaging substrate according to this embodiment, where Gr represents a glass crack and Gh represents glass chipping. Parts (a) to (c) of Figure 8 are flowcharts illustrating the manufacturing process of a packaging substrate according to one embodiment using cross-sections. Part (a) is laser ablation, part (b) is laser filamentation, and part (c) is separation. Parts (a) to (c) of Figure 9 are flowcharts illustrating the manufacturing process of a packaging substrate according to another embodiment using cross-sections, where (a) is laser ablation, (b) is laser filamentation, and (c) is separation. Figure 10 (a) and (b) are photographs of the manufacturing process of the packaging substrate according to this embodiment. The left side of (a) is a sectional view and the right side is a top view. Figure 11 is a photograph of a cross-section of the polished glass substrate according to this embodiment. The solid line represents the cutting line (CL), and the dashed line represents the edge of the polished glass. Parts (a) and (b) of Figure 12 are respectively a view from above of the state of the glass substrate according to another embodiment (a) and a photograph (b) of a portion thereof. Implementation

[0036] Hereinafter, several embodiments will be described in detail with reference to the accompanying drawings to enable those skilled in the art to easily implement these embodiments. However, these embodiments can be implemented in many different ways and are not limited to the embodiments described in this specification. Throughout this specification, the same reference numerals are used to refer to the same or similar components.

[0037] Throughout this specification, the term "combination of..." used in the Markush form description refers to a mixture or combination of one or more elements selected from the group of elements described in the Markush form, thereby implying that the present invention includes one or more elements selected from the group of said elements.

[0038] Throughout this specification, unless otherwise specified, terms such as "first," "second," or "A," "B," etc., are used to distinguish them from each other. Furthermore, unless explicitly stated otherwise in the text, singular designations should be understood to include plural designations.

[0039] In this specification, “~” can refer to a compound that includes a compound equivalent to “~” or a derivative of “~”.

[0040] In this specification, "B is located on A" means that B is located on A in direct contact with A or in the presence of other layers in between, and should not be interpreted as B being located on the surface of A in contact with A.

[0041] In this specification, "A connected to B" means that A and B are directly connected or connected through other constituent elements between A and B, unless otherwise stated, the interpretation is not limited to a direct connection between A and B.

[0042] Unless otherwise specified, the use of the singular in this specification is to be interpreted as including the meaning of singular or plural as the context suggests.

[0043] In the process of developing semiconductor devices that can achieve high performance with greater integration and thinner thickness, the inventors realized that in addition to the components themselves, the packaging is an important factor in improving performance. They conducted research on this and confirmed that, unlike existing interposers and organic substrates, which use two or more layers of substrate as packaging substrates on the motherboard, using a single-layer glass substrate and a cavity structure can help to make the packaging substrate thinner and improve the electrical characteristics of the semiconductor device.

[0044] On the other hand, during the manufacturing process, glass substrates may suffer damage such as cracks or chipping due to internal stress and / or external impacts. Inspecting this damage requires costly cross-sectional analysis. For example, detecting cracks or damage may require examining all cut surfaces of the glass substrate using a microscope, which can be time-consuming and expensive. In this case, it was confirmed that substrate inspection can be easily performed by making the glass substrate protrude from the upper or lower layers towards the cut surfaces. In other words, it was confirmed that surface and cross-sectional defects of the glass substrate can be quickly detected by exposing a portion of the substrate without the use of instruments such as microscopes, thus completing the present invention.

[0045] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of the packaging substrate according to this embodiment. Figure 2 is a conceptual diagram illustrating the structure of the packaging substrate according to another embodiment using cross-section. Parts (a) and (b) of Figure 3 are conceptual diagrams illustrating a portion of the packaging substrate according to this embodiment using cross-section.

[0046] To achieve the aforementioned objective, the semiconductor device 100 according to this embodiment includes: a semiconductor element section 30, including one or more semiconductor elements (a first semiconductor element 32, a second semiconductor element 34, and a third semiconductor element 36); a packaging substrate 20 electrically connected to the semiconductor elements; and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to the semiconductor elements 32, 34, and 36 and connects the semiconductor elements to the external electrical signals.

[0047] According to one embodiment, the packaging substrate 20 includes: a substrate layer 22; an upper layer 26 located on a surface of the substrate layer 22; and a cavity portion 28, wherein a cavity element 40 may be located in the cavity portion 28.

[0048] The semiconductor element section 30 refers to an element mounted on a semiconductor device and attached to the packaging substrate 20 via connecting electrodes or the like. Specifically, the semiconductor element section 30 can be, for example, computing elements such as CPUs and GPUs (first semiconductor element 32, second semiconductor element 34), memory elements such as memory chips (third semiconductor element 36), etc. However, any semiconductor element mounted on a semiconductor device can be used without restriction.

[0049] The motherboard 10 can be a motherboard for printed circuit boards, printed wiring boards, etc.

[0050] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the substrate layer.

[0051] The substrate layer 22 may include: a glass substrate 21, including a first region 221 and a second region 222, the first region 221 having a first thickness 211, and the second region 222 being adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness 211; a plurality of core vias 23 penetrating the glass substrate 21 in the thickness direction; and a distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23, and electrically connecting a first surface 213 of the glass substrate 21 and a second surface 214 facing the first surface 213 through the core vias 23. That is, the substrate layer 22 includes the glass substrate 21, the core vias 23, the cavity portion 28, or all of these, wherein the glass substrate 21 includes a first surface 213 and a second surface 214 facing each other.

[0052] The second region 222 of the substrate layer 22 can serve as a cavity structure.

[0053] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, the two surfaces being generally parallel to each other, so that the glass substrate 21 as a whole has a predetermined thickness.

[0054] The internal space 281 is formed by the thickness difference between the first region 221 and the second region 222, and serves to accommodate part or all of the cavity element 40.

[0055] The glass substrate 21 may include through holes 23 penetrating the first surface 213 and the second surface 214. The through holes 23 may be formed entirely in the first region 221 and the first and second regions 222, and may be formed with the desired spacing and pattern.

[0056] As packaging substrates for semiconductor devices, existing technologies have employed stacked silicon substrates and organic substrates. In the case of silicon substrates, due to the characteristics of semiconductors, parasitic elements may arise when used in high-speed circuits, resulting in relatively large power losses. Furthermore, organic substrates require large areas to form more complex patterns, which is not in line with the trend towards manufacturing ultra-miniaturized electronic devices. To form complex patterns within a predetermined size, pattern refinement is practically necessary, but the properties of materials such as polymers used in organic substrates limit the potential for pattern refinement.

[0057] In this embodiment, as a method to solve these problems, the glass substrate 21 is used as a support for the substrate layer 22. In addition, by applying through-holes 23 formed through the glass substrate 21 together with the glass substrate 21, a packaging substrate 20 with characteristics such as shorter current flow length, smaller size, faster response, and less loss is provided.

[0058] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, such as a borosilicate glass substrate or an alkali-free glass substrate, but the present invention is not limited thereto.

[0059] The through-hole 23 extends through the glass substrate 21. The through-hole 23 can be formed by removing a predetermined area of ​​the glass substrate 21, specifically by etching the plate-shaped glass using physical and / or chemical methods.

[0060] Specifically, during the formation of the through hole 23, defects (flaws) can be formed on the surface of the glass substrate by means of laser or other methods, followed by chemical etching, laser etching, etc., but the present invention is not limited thereto.

[0061] Based on the unit area (1cm × 1cm) of the glass substrate 21, 100 to 3,000 through holes 23, 100 to 2,500 through holes 23, or 225 to 1,024 through holes 23 can be provided. When the spacing conditions are met, it is more conducive to the formation of conductive layers, etc., and the performance of the encapsulation substrate can be improved.

[0062] The distribution layer 24 includes a distribution pattern 241 serving as a conductive layer and an insulating layer 223. The distribution pattern 241 electrically connects the first surface 213 and the second surface 214 of the glass substrate 21 through through-holes, and the insulating layer 223 surrounds the distribution pattern 241. A conductive layer is formed inside the substrate layer 22 through the through-holes 23, thereby serving as an electrical path across the glass substrate 21. This allows for the connection of the upper and lower parts of the glass substrate 21 over a relatively short distance, resulting in faster electrical signal transmission and lower loss characteristics. For example, the conductive layer can be a copper plating layer, but the invention is not limited to this.

[0063] The shape of the cavity 28 can be circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and its shape is not limited.

[0064] The cavity element 40 can be cylindrical, rectangular hexahedral, or polygonal in shape.

[0065] The cavity portion 28 may include: a cavity distribution pattern as a conductive layer for electrically connecting the cavity element 40 and the distribution layer 24; and an insulating layer surrounding the cavity distribution pattern.

[0066] On the other hand, according to another embodiment, the cavity portion can be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion 28 can be formed according to the same process as the forming process of the through hole 23, and the area and shape penetrating the glass substrate 21 can be different from the area and shape of the through hole 23.

[0067] In this embodiment, the insulating layer can be formed after the cavity elements 40 are arranged in the cavity. That is, the insulating layer can also be formed in the cavity 28 through the process of forming the insulating layer 223 described above.

[0068] The distribution pattern 241 can be formed into a pattern that can be electrically connected to the cavity element 40.

[0069] The cavity element 40 may include active devices such as transistors or power transmission elements such as multilayer ceramic capacitors (MLCCs), i.e., passive elements.

[0070] When a component such as a transistor that converts the electrical signal between the motherboard and the semiconductor element section into an appropriate level is applied as the cavity element 40, and the configuration is such that the transistor is applied in the path of the package substrate 20, a semiconductor device 100 with more efficiency and faster speed can be provided.

[0071] Furthermore, power transmission elements, such as multilayer ceramic capacitors (MLCCs), play a crucial role in the performance of semiconductor devices. Typically, more than 200 passive power transmission elements are used in semiconductor devices, and their performance during power transmission is also affected by the characteristics of the conductive layer surrounding the element. In one embodiment, non-circular vias can be used where a low-resistance conductive layer is required, such as in the power transmission elements described above, instead of using circular vias.

[0072] On the other hand, passive components such as capacitors can be individually inserted into and applied to the cavity element 40. Electrodes of a group of multiple passive components can also be exposed in a form embedded between the insulating layers (cavity element insulating layers) and then inserted into the cavity element. In the latter case, the operability of the packaging substrate manufacturing is made smoother, and it is more conducive to reliably positioning the insulating layer in the space between complex components.

[0073] The glass substrate 21 serves as an intermediary, connecting the semiconductor element section 30 to the motherboard 10 at its upper and lower parts, respectively. The through-hole 23 serves as a channel for transmitting these electrical signals, thus enabling smooth signal transmission. To distinguish it from the through-hole in the second region 222 described below, the through-hole disposed in the first region 221 is referred to as the first region through-hole 231.

[0074] The upper layer 26 is located on the first surface 213.

[0075] The upper layer 26 includes an upper partition layer 25 and an upper connection layer 27. The upper connection layer 27 is located on the upper partition layer 25. The uppermost surface of the upper layer 26 can be protected by a cover layer 60. An opening is formed in the cover layer 60 that can directly contact the connection electrode of the semiconductor element part 30.

[0076] The upper distribution layer 25 includes: an upper insulating layer 253 located on the first surface 213; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion thereof electrically connected to the distribution layer 24, the upper distribution pattern 251 being embedded in the upper insulating layer 253. The upper distribution layers 25, arranged vertically to each other, can be connected to each other through blind vias 252.

[0077] The upper insulating layer 253 can be used in any semiconductor element or packaging substrate as an insulating layer, such as epoxy resin containing fillers, but is not limited thereto.

[0078] The insulating layer can be formed by forming a coating and curing the coating, or by laminating an insulating film in an uncured or semi-cured state onto the substrate layer 22 and then curing it. In this case, if a depressurized lamination method is used, the insulator can be embedded into the space inside the through-hole 23, thereby enabling efficient processing.

[0079] According to one embodiment, even when multiple insulating layers are stacked and applied, it may be difficult to distinguish between the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Furthermore, insulating layer 223 and upper insulating layer 253 may use the same insulating material, in which case the boundary may be indistinguishable. Alternatively, according to another embodiment, by setting different pressures and temperatures for curing the multilayer insulating layers, the boundaries of the insulating layers can also be generated.

[0080] The upper distribution pattern 251 refers to a conductive layer located within the upper insulating layer 253 in a predetermined shape, for example, it can be formed by a build-up layer method. Specifically, an insulating layer is formed, and after removing unwanted portions of the insulating layer, a conductive layer is formed by copper plating or the like. After selectively removing unwanted portions of the conductive layer, an insulating layer is re-formed on the conductive layer, and after removing unwanted portions again, a conductive layer is formed by gold plating. By repeating this process, the upper distribution pattern 251 of the conductive layer formed in the vertical or horizontal direction can be formed in the desired pattern.

[0081] The upper distribution pattern 251 is located between the substrate layer 22 and the semiconductor element portion 30. Therefore, in order to smoothly transmit electrical signals with the semiconductor element portion 30 and to fully accommodate the desired complex pattern, at least a portion of the upper distribution pattern 251 includes a fine pattern. Here, a fine pattern refers to a width and spacing of less than 4μm, less than 3.5μm, less than 3μm, less than 2.5μm, or 1μm to 2.3μm (hereinafter, the description of fine patterns is the same).

[0082] The upper connection layer 27 includes: an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and located on the upper insulating layer 253; and an upper connection electrode 271, which electrically connects the semiconductor element portion 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or it may be embedded with at least a portion exposed on the upper insulating layer. For example, when the upper connection pattern 272 is located on one surface of the upper insulating layer 253, the upper insulating layer 253 may be formed by means of gold plating or the like; when a portion of the upper connection pattern 272 is exposed on the upper insulating layer 253 while being embedded in the upper insulating layer 253, a portion of the insulating layer or conductive layer may be removed by surface grinding, surface etching, or the like after forming a copper plating layer.

[0083] Similar to the upper partitioning pattern 251 described above, at least a portion of the upper connection pattern 272 may include fine patterns. Thus, the upper connection pattern 272, including fine patterns, allows for the electrical connection of a greater number of components even in a narrow area, thereby enabling smoother electrical signal connections between components or with external components, and ultimately achieving more integrated packaging.

[0084] The upper connecting electrode 271 can be directly connected to the semiconductor element section 30 via terminals or the like, or it can be connected via a component connecting section 51 such as a solder ball.

[0085] The cavity portion 28 includes a cavity distribution layer 282 and an internal space 281. The cavity distribution layer 282 is located above and / or below the second region 222 and is electrically connected to the distribution layer 241. The cavity element 40 is located in the internal space 281. The cavity distribution layer 282 can be formed through the second region through-hole 232.

[0086] Specifically, compared to the first region 221, the glass substrate 21 of the second region 222 is thinner, and the cavity element 40 can be located in the internal space 281 formed by the thickness difference between the two. In addition, the through-hole 23 and the distribution layer 24 formed in the glass substrate 21 serve as electrical connection structures to connect the cavity element 40 to external elements.

[0087] In addition, as described above, a cavity portion 28 can be formed that penetrates the first region 221 instead of the second region 222, that is, penetrates the first surface 213 and the second surface 214 of the glass substrate 1, and the cavity element 40 can be arranged in the cavity portion 28.

[0088] The packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the distribution pattern 241 located on at least a portion of the second surface 214 of the substrate layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52, such as solder balls. Furthermore, the distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown) located below the substrate layer 22. The component connection portion 51 and the board connection portion 52 are collectively referred to as the connection portion 50.

[0089] According to one example, in addition to the glass substrate 21, other additional substrates may not be applied to the packaging substrate 20 located between the semiconductor element section 30 and the motherboard 10.

[0090] Conventionally, an interposer and an organic substrate are laminated together and applied between the component and the motherboard. This multi-level approach is understood to be used for at least two reasons: one is the scale problem of directly bonding the fine pattern of the component to the motherboard; the other is the potential for wiring damage due to differences in thermal expansion coefficients during bonding or the operation of the semiconductor device. In this implementation, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor component is used, and fine patterns of minute scale are formed on the first surface and upper layer of the glass substrate to a degree sufficient for component mounting to address these problems.

[0091] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0092] Parts (a) to (e) of Figure 4 and parts (a) to (e) of Figure 5 are flowcharts illustrating the manufacturing process of the packaging substrate according to this embodiment using cross-sections.

[0093] First, as shown in part (a) of Figure 4, a glass substrate 21a having a flat first surface and a flat second surface is prepared. To form a through-hole, a defect (flaw) 21b is formed on the glass surface at a predetermined location. The glass substrate can be a substrate suitable for electronic devices, such as an alkali-free glass substrate, but is not limited to this. Products manufactured by companies such as Corning Incorporated, Schott AG, and AGC can be used as commercial products. The formation of the defect (flaw) can be achieved using methods such as mechanical etching or laser irradiation.

[0094] As shown in part (b) of Figure 4, an etching step is performed on the glass substrate 21a with defects 21b to form through-holes 23 through a physical or chemical etching process. During the etching process, through-holes are formed at the defective portion of the glass substrate 21a, and the surface of the glass substrate 21a can also be etched. To prevent this etching of the glass surface, a mask or the like can be used. However, considering the inconvenience of removing the mask after application, the defective glass substrate itself can be etched. In this case, the thickness of the glass substrate with through-holes may be somewhat less than the thickness of the original glass substrate.

[0095] Following this, as shown in portions (c) and (d) of FIG4, a conductive layer 21d is formed on the glass substrate 21a, thereby enabling the substrate layer manufacturing step. The conductive layer can be a representative metal layer containing copper, but is not limited thereto.

[0096] The surface properties of glass (including the surface of the glass substrate and the surface of the vias) differ from those of copper, resulting in poor adhesion. In this implementation example, both dry and wet methods can be used to improve the adhesion between the glass surface and the metal.

[0097] The dry method is a sputtering method, which involves sputtering metal onto the glass surface and the inner diameter of the via to form a seed layer 21c. During the formation of the seed layer 21c, different types of metals such as titanium, chromium, and nickel can be sputtered together with copper. In this case, the glass-metal adhesion can be improved through the anchoring effect of the interaction between the glass surface morphology and the metal particles.

[0098] The wet method is a primer treatment method that uses compounds with functional groups such as amines for pretreatment to form the primer layer 21c. Depending on the desired level of adhesion, a silane coupling agent is used for pretreatment, followed by primer treatment using compounds or particles with amine functional groups. As described above, the support substrate of the implemented example needs to have high performance sufficient to form fine patterns, and this high performance should be maintained after primer treatment. Accordingly, when such a primer contains nanoparticles, nanoparticles with an average diameter of 150 nm or less are preferably used; for example, particles with amine groups are preferred. As an example, the primer layer can be formed using adhesion enhancers such as the CZ series manufactured by MEC Corporation.

[0099] For the seed layer / base coating 21c, the conductive layer can selectively form a metal layer to be in a state where the conductive layer is removed or not removed and therefore not required to form. Furthermore, for the seed layer / base coating 21c, after selectively activating or deactivating the portions where a conductive layer needs to be formed (or not) during gold plating, subsequent processes can be performed. For example, the activation or deactivation process can employ light irradiation of a predetermined wavelength, chemical treatment, etc. The metal layer can be formed using methods such as copper plating used in the manufacture of semiconductor devices, but is not limited to these methods.

[0100] As shown in part (e) of Figure 4, the portion of the distribution layer can be removed if it is not needed. After a portion of the seed layer is removed or deactivated, gold plating is performed, thereby forming a conductive layer with a pre-defined pattern, and thus forming an etched layer 21e of the distribution layer.

[0101] Figure 5 illustrates the manufacturing steps for forming an insulating layer and an upper parting pattern according to one embodiment.

[0102] As shown in part (a) of Figure 5, the via can be formed through an insulating layer forming step, in which the insulating layer fills the hollow space after the distribution layer, which serves as the conductive layer, is formed. In this case, a suitable insulating layer can be a thin-film insulating layer, for example, a method using depressurized lamination of a thin-film insulating layer. If depressurized lamination is performed in this way, the insulating layer is fully embedded in the hollow space inside the via, thereby forming an insulating layer without gaps.

[0103] The manufacturing steps of the upper layer are described in parts (b) to (e) of Figure 5.

[0104] The upper layer manufacturing step involves forming an upper partitioning layer, including an upper insulating layer and an upper partitioning pattern, on a substrate layer. The upper insulating layer can be formed by coating a resin composition for forming insulating layer 23a or by laminating an insulating film; laminating an insulating film is preferred for simplicity. The insulating film can be laminated and cured; if a depressurized lamination method is used, the insulating resin can also fully penetrate the layers without conductive layers inside the through-holes. The upper insulating layer is also in direct contact with the glass substrate in at least a portion, thus requiring a layer with sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have an adhesion test value of 4B or higher according to ASTM D3359.

[0105] The upper parting pattern is formed by repeatedly forming the insulating layer 23a and the conductive layer 23c according to the pre-set pattern, followed by etching the unwanted parts to form the etch layer 23d. In the case of conductive layers formed adjacent to each other with an insulating layer in between, they can be formed by performing a gold plating process after forming blind vias 23b in the insulating layer. The blind vias 23b can be formed by dry etching methods such as laser etching and plasma etching, or by wet etching methods using a mask layer and an etching solution.

[0106] Afterwards, although not shown, the connecting layer and the covering layer can be formed.

[0107] The upper connection pattern and upper connection electrode can also be formed through a process similar to that of forming the upper partial layer. Specifically, the upper connection pattern and upper connection electrode can be formed by etching an insulating layer on the insulating layer 23e, then re-forming a conductive layer on it, and finally forming an etched layer of conductive layer. However, etching may not be used; instead, a method of selectively forming only conductive layers may be employed. The cover layer can be formed with openings (not shown) at positions corresponding to the upper connection electrodes to expose them, and can be directly connected to component connection portions or component terminals.

[0108] If the upper layer is formed, the lower connecting layer and the capping layer are formed, and the process for forming the lower layer can be performed. The lower sublayer and / or the lower connecting layer can be formed in a manner similar to the upper connecting layer and capping layer forming steps described above, and the capping layer (not shown) can be selectively formed.

[0109] According to this embodiment, one or more semiconductor elements can be mounted on the packaging substrate 20. During the manufacturing process of the packaging substrate, multiple packaging substrates can be manufactured simultaneously on a large-area substrate, and the packaging substrate 20 can be cut into predetermined units, i.e., cut into units that are individual packaging substrates. For example, during the manufacturing process of the packaging substrate, a strip substrate with multiple individual products arranged across dummy areas, a quad substrate with dummy areas disposed between multiple strip substrates, and a panel substrate with dummy areas disposed between multiple quad substrates can be fabricated using a glass substrate as the substrate. The glass substrate (substrate or substrate layer) can have a pattern of a predetermined size during or after the upper and / or lower layer configuration, and can be cut while individual semiconductor wafers or wafer units are already mounted, or cut in a state where individual semiconductor wafers or wafer units can be mounted. The substrate cutting, separation, and partitioning processes described above can be referred to as dicing or singulation. Hereinafter, depending on the context, "packaging substrate" may refer to either a pre-monolithized packaging substrate on which individual packaging substrates are disposed, or a substrate in a state of being monolithized into a single product.

[0110] In this specification, cutting or dicing can refer to dividing a packaging substrate, which includes a glass substrate as a substrate layer, into multiple units. Furthermore, a substrate using a glass substrate as a substrate layer can be referred to in various ways as a substrate, glass substrate, packaging substrate, etc.

[0111] Figure 6, from (a) to (c), are cross-sectional views illustrating the packaging substrate according to this embodiment.

[0112] Referring to Figures 1 to 5, through-holes 23 and cavities 28 can be formed in the glass substrate 21. A distribution layer 24 and a cover layer 60, etc., can be formed in the upper layer. The lower layer can also have a multilayer structure including an insulating layer and a metal distribution pattern. In the following figures, for ease of explanation, the glass substrate 21 and the encapsulation substrate 20 including the upper layer 70 formed on the first surface 213 of the glass substrate 21 and the lower layer 80 formed on the second surface 214 will be briefly described, and detailed descriptions of other configurations will be omitted.

[0113] Referring to FIG6, the upper layer 70 is disposed on the first surface 213 of the glass substrate 21. Optionally, the lower layer 80 may be disposed on the second surface 214 of the glass substrate 21.

[0114] The upper layer 70 may include an upper partitioning layer 71 and a first cover layer 72. The upper partitioning layer 71 has a multilayer stacked structure including an upper metal pattern (upper partitioning pattern) and an upper insulating layer. The first cover layer 72 is formed on the upper partitioning layer 71 and protects the substrate. The specific configuration of the upper partitioning pattern and the upper insulating layer in the upper partitioning layer 71 is omitted in the figure.

[0115] The lower layer 80 may also include a lower partition layer 81 and a second cover layer 82. The lower partition layer 81 has a multilayer structure including a lower metal pattern (lower partition pattern) and a lower insulating layer. The second cover layer 82 is formed on top of the lower partition layer 81 and ultimately planarizes the substrate and protects the substrate. The configuration of the lower partition pattern and the lower insulating layer in the lower partition layer 81 is omitted in the figure.

[0116] The first cover layer 72 and / or the second cover layer 82 can be implemented with solder resist to protect the surface circuitry from the influence of the external environment. Alternatively, according to an embodiment, the first cover layer 72 and / or the second cover layer 82 can be implemented as a polyimide film as a heat-resistant insulating film with high thermal stability and high mechanical strength.

[0117] Through-holes, cavities, and metal pattern layers are formed on the glass substrate 21, and the packaging substrate can be cut into specific units when or before mounting semiconductor elements (not shown) on the upper layer 70.

[0118] The packaging substrate can be cut along the dicing line. The dicing line is configured in a pre-defined position and is the location where the cutting is to be performed.

[0119] In this embodiment, a portion of the upper layer 70 and / or a portion of the lower layer 80 corresponding to the cutting line may not be provided with a metal pattern layer. That is, the portion of the upper layer 70 and / or the portion of the lower layer 80 that is to be cut and removed may only be provided with an insulating layer or a protective layer.

[0120] Typically, the cut packaging substrate 20 has a cross-section as shown in part (a) of FIG6. That is, the cut surface and the first surface or the cut surface and the second surface of the packaging substrate 20 have a generally angular shape, and the corners have a relatively sharp shape.

[0121] In the structure shown in part (a) of FIG6, cracks and damage originating from the edges or cut surfaces of the glass substrate 21 are likely to occur. Therefore, according to an embodiment of the present invention, an encapsulation substrate as shown in part (b) or part (c) of FIG6 is proposed.

[0122] According to this embodiment, as shown in part (b) of FIG6, the cut surface of the glass substrate 21 can be more convex than the upper layer 70 and / or the lower layer 80. That is, the glass substrate 21 can have an edge that is more convex than the upper layer 70 and / or the lower layer 80, i.e., it can have an edge region 213a. The first and / or second surfaces of the glass substrate 21 can be exposed to the outside by removing the upper layer 70 and / or the lower layer 80 from the edge region of the first surface and / or the edge region of the second surface adjacent to the cut surface of the glass substrate 21.

[0123] According to this embodiment, as shown in part (b) of FIG6, the cut surface of the glass substrate 21 may have a shape that is more convex than the upper partial layer 71 and / or the lower partial layer 81. That is, the glass substrate 21 may have an edge that is more convex than the upper partial layer 71 and / or the lower partial layer 81, i.e., an edge region 213a. The edge regions of the first surface and / or the edge regions of the second surface adjacent to the cut surface of the glass substrate 21 can be exposed to the outside by removing the upper partial layer 71 and / or the lower partial layer 81. The upper partial layer 71 and / or the lower partial layer 81 may be disposed on the upper layer 70 and the lower layer 80 in the form of two or more layers, three or more layers, four or more layers, or five or more layers, respectively. In addition, layers of 10 or less, 8 or less, or 6 or less may be disposed.

[0124] According to this embodiment, the upper layer 70 may further include an insulating layer such as a first cover layer 72 stacked on the first surface, and the edge of the insulating layer is disposed from the edge of the glass substrate 21 toward the inward side, and the edge region 213a may include the region from the edge of the glass substrate 21 to the edge of the insulating layer.

[0125] Additionally, the lower layer 80 may also include an insulating layer such as a second cover layer 82 stacked on the second surface, and the edge of the insulating layer is disposed from the edge of the glass substrate 21 toward the inward side, and the edge region 213a may include the region from the edge of the glass substrate 21 to the edge of the insulating layer.

[0126] The cutting process can be the process of cutting the panel substrate into a quadrilateral substrate.

[0127] The cutting process can be the process of cutting a quadrilateral substrate into a strip-shaped substrate.

[0128] The cutting process can be the process of cutting a strip substrate into individual packaging substrates.

[0129] These are collectively referred to as the process of cutting into unit cells.

[0130] In the dicing process of the packaging substrate 20, i.e., the process of dicing into unit units, the upper layer 70 or the lower layer 80 can be removed. Through this process, after the dicing process, the side surface of the glass substrate 21 can protrude more in the dicing direction compared to the layers stacked on the upper or lower part. The removal method can be laser irradiation, etc., but is not limited to this.

[0131] As the width of the edge region 213a exposed after removing the upper layer 70 or the lower layer 80, a portion of the upper or lower layer can be removed, such that the width from the edge of the insulating layer to the edge of the glass substrate 21 is, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more. Alternatively, a portion of the upper or lower layer can be removed, such that the width of the edge region 213a is less than 200 μm, less than 150 μm, less than 100 μm, or less than 80 μm. That is, the width of the removed portion (removal line) can be more than twice or more than 2.2 times the width described above. Furthermore, the width of the removed portion (removal line) can be less than four times or less than three times the width described above.

[0132] As shown in part (b) of Figure 6, the glass substrate 21 protrudes in the direction of the cut surface, so that the thickness of the cross section of the encapsulation substrate 20 can be reduced in the direction of the upper layer 70 or the lower layer 80 toward the glass substrate 21, thereby giving it an overall flat "U" shape with a tapered shape facing each other.

[0133] As shown in part (c) of Figure 6, the corner portion of the edge region 213a of the protruding glass substrate 21 can be chamfered into a round shape. That is, the edge region 213a disposed at the corner (edge) of the glass substrate 21 can be a curved surface.

[0134] Alternatively, according to one example, the edge region 213a disposed at the corner of the glass substrate 21 can be chamfered.

[0135] According to one example, the upper layer 70 or the lower layer 80 can also be removed or ground in a conical shape that gradually thins towards the cross-section.

[0136] As shown in Figure 6, when the upper layer is removed in the edge region 213a of the glass substrate 21, the glass substrate 21 exposes an amount corresponding to the amount of the upper layer that has been removed.

[0137] The width from the edge of the insulating layer to the edge of the glass substrate 21 can be, for example, 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more. Furthermore, the width of the edge region 213a can be less than 200 μm, less than 150 μm, less than 100 μm, or less than 80 μm.

[0138] Figure 7 is a top view of the packaging substrate according to this embodiment.

[0139] As shown in Figure 7, when the packaged substrate 20, cut into units, is viewed from above, a first cover layer 72 is formed on a first surface of the glass substrate 21, and an upper layer including the first cover layer 72 is removed in the edge region 213a. When the glass substrate 21 has a quadrilateral shape, the upper layer can be removed along the four sides of the glass substrate 21. In other words, the edge of the first cover layer 72 is disposed from the edge of the glass substrate 21 toward the inward side, that is, the edge of the first cover layer 72 is disposed closer to the inward side than the edge of the glass substrate 21, and the edge region 213a can refer to the region from the edge of the glass substrate 21 to the edge of the first cover layer 72.

[0140] According to one example, glass cracks or fragments can be easily observed in the edge region 213a of the exposed glass substrate 21.

[0141] As mentioned above, when a glass substrate is used as the base material structure for a packaging substrate, there is a high probability that the substrate may crack or develop fissures due to internal stress and external impact during the manufacturing process. In order to detect these defects, it is necessary to analyze all cross-sections of the cut packaging substrate. To perform cross-sectional analysis, it is necessary to inspect the cut surfaces of the packaging substrate using microscopes or the like, but this is time-consuming and costly.

[0142] According to this embodiment, as shown in FIG7, defects such as cracks or breaks can be quickly and accurately detected by inspecting only the exposed area 213a of the glass substrate 21. In other words, by inspecting the edge area 213a of the glass substrate 21 where the upper or lower layer has been removed, as well as defects in the cut surface of the glass substrate, surface and cross-sectional inspections of the glass substrate can be performed simultaneously without the need for expensive equipment.

[0143] Figure 8, in sections (a) to (c), is a flowchart illustrating the manufacturing process of the packaging substrate according to this embodiment using cross-section.

[0144] According to the embodiment of FIG8, the upper layer 70 is formed on the first surface of the glass substrate 21, and a semiconductor element (not shown) can be stacked on the upper layer 70.

[0145] First, as shown in part (a) of Figure 8, a laser can be used to remove a specified width of the upper layer 70 along the cutting line, thereby forming a removal line (laser ablation).

[0146] A green laser or a UV laser can be used to remove the upper layer 70 that is stacked along a cutting line such as a cutting street, specifically to remove an insulating layer such as ABF.

[0147] At this time, the width of the removed upper layer 70, i.e., the width of the removal line, can be approximately 10 μm to 600 μm. The width can be 10 μm or more, 14 μm or more, 20 μm or more, 30 μm or more, 40 μm or more, 50 μm or more, 60 μm or more, or 70 μm or more. The width can be less than 600 μm, less than 550 μm, less than 500 μm, less than 450 μm, less than 400 μm, less than 380 μm, less than 360 μm, less than 340 μm, less than 320 μm, less than 300 μm, less than 280 μm, less than 260 μm, less than 240 μm, less than 220 μm, less than 200 μm, or less than 180 μm. The width of the removed upper layer 70 can be set to approximately twice or more the width of the desired protruding edge region of the glass substrate 21.

[0148] On the other hand, as shown in the figure, when the upper layer 70 is removed by laser, no defects are actually formed in the glass substrate 21.

[0149] Then, as shown in part (b) of FIG8, a filamentation process can be performed to form a filament along the dicing line on the glass substrate 21 where the upper layer has been removed (laser filamentation).

[0150] The method of cutting a substrate using a laser beam such as an infrared laser (IR laser) involves focusing an ultrashort laser beam inside a glass substrate 21 and irradiating the laser beam along a desired cutting path, thereby causing internal filamentation and forming a cutting groove of a predetermined depth inside the glass substrate 21. By forming filaments, defects can be formed inside the glass substrate 21 along the cutting surface.

[0151] When an ultrashort laser beam passes through the glass substrate 21, a portion of it is absorbed, transferring energy to the constituent molecules. Due to the high energy density of the ultrashort laser pulse, the absorbed energy density is also high, resulting in the instantaneous formation of plasma within the glass substrate 21. When continuous pulses enter, this plasma also affects the optical properties of subsequent pulses. The plasma thus generated disappears after a predetermined lifetime, transforming into a structure different from the surrounding material. However, depending on the cutting and processing conditions, a narrow and long blank space is formed along the thickness direction in the area irradiated by the ultrashort laser beam; this is called a "filamentation."

[0152] Unlike gaps or cracks caused by thermal expansion, the pulse width of a laser filament is shorter than the reaction time of a molecular bond structure. Therefore, it does not affect the surrounding molecules with heat or vibrational energy, but rather forms a thin slit instantaneously due to the energy being concentrated on the irradiated part of the ultra-short wave laser beam.

[0153] As shown in part (c) of Figure 8, if a light filament is formed, it can be used to cut the glass substrate 21, that is, the glass substrate 21 can be separated into units.

[0154] As shown in the figure, in order to cut the glass substrate 21, tensile stress or rotational force (rotational torque) can be applied to the optical filament, thereby separating the glass substrate 21 into two or more units.

[0155] According to another embodiment, a laser or a dicing saw can also be used to separate the glass substrate 21.

[0156] As described above, when the glass substrate 21 is separated into defined units, as shown in part (c) of FIG8, the insulating layer of the upper layer 70 has a tapered shape that gradually thins along the direction of the cut surface of the glass substrate 21, and the glass substrate 21 has a shape in which the upper layer 70 is exposed and protrudes in the direction of the cut surface.

[0157] According to this embodiment, when the upper layer 70 is removed using a green laser, the laser scanning speed irradiating the upper layer 70 can be from 20 mm / s to 40 mm / s. The laser scanning speed irradiated to form a filament can be from 50 mm / s to 150 mm / s or from 80 mm / s to 120 mm / s.

[0158] Figure 9, in sections (a) to (c), is a flowchart illustrating the manufacturing process of a packaging substrate according to another embodiment using cross-section.

[0159] As shown in part (a) of FIG9, an upper layer 70 is formed on the first surface of the glass substrate 21, and a lower layer 80 is formed on the second surface. That is, in the glass substrate 21 of FIG8, the upper layer 70 is formed only on the first surface of the first and second surfaces, so only the upper layer 70 is removed. However, in the case of FIG9, a lower layer 80 including an insulating layer is also formed on the second surface of the glass substrate 21, so the insulating layer on both surfaces can be removed.

[0160] The width of the upper layer 70 to be removed and the width of the lower layer 80 can have the same range. Specifically, the width of the lower layer 80 to be removed, based on the width from the edge of the insulating layer to the edge of the glass substrate in the unit glass substrate, can be 5 μm or more, 7 μm or more, 10 μm or more, or 15 μm or more. Furthermore, the width can be 200 μm or less, 150 μm or less, 100 μm or less, or 80 μm or less.

[0161] The widths of the upper layer 70 and the lower layer 80 to be removed can vary depending on the design of the semiconductor components or motherboard being mounted. The removal width of the lower layer 80 can be greater than that of the upper layer 70; specifically, the difference between the removal widths of the upper layer 80 and the lower layer 70 can be greater than 1 μm, 3 μm, 5 μm, or 10 μm. The difference can be less than 20 μm.

[0162] The irradiation intensity of the laser used to remove the insulating layer is no greater than the irradiation intensity used to form the filament, so that no damage or defects are formed on the glass substrate 21 even if the laser is used on both sides.

[0163] The insulating layer can be removed by simultaneously or sequentially irradiating the two surfaces on which the upper layer 70 and the lower layer 80 are formed. On the other hand, the laser used to remove the upper layer 70 and the lower layer 80 can act on both surfaces, but as shown in part (b) of FIG9, the laser used to generate the filament can be irradiated on only one of the first and second surfaces (on a single side).

[0164] As shown in part (c) of Figure 9, the separation of the glass substrate 21 after the filamentation process can be based on tension or rotational torque caused by external force.

[0165] Figure 10, in parts (a) and (b), are photographs of the manufacturing process of the packaging substrate according to this embodiment.

[0166] As shown in part (a) of Figure 8 or part (a) of Figure 9, part (a) of Figure 10 is also a photograph of a sectional view and a top view of the glass substrate 21 (the glass substrate before it was separated into units) with the upper layer 70 removed. In other words, it is an enlarged photograph of the dashed rectangular area that is part of the substrate in part (a) of Figure 9.

[0167] As shown in the sectional view of part (a) of Figure 10, the upper layer 70 is removed by a specified width w. In the top view, it can be confirmed that the glass substrate 21 is exposed by an amount corresponding to the width w that was removed. Furthermore, as can be observed in the sectional view, no defects are formed in the glass substrate 21 even after the upper layer 70 is removed. In addition, the removed upper layer 70 may have a tapered shape that gradually thins towards the cutting surface to be cut.

[0168] Part (b) of Figure 10 is a photograph showing the cut edge of the glass substrate 21 after it has been cut into units according to parts (a) of Figure 8 and (a) of Figure 9. The glass substrate 21 is separated in a generally straight line, and on both surfaces of the glass substrate, the upper layer 70 and the lower layer 80 are respectively arranged at a predetermined distance from the edge of the glass substrate inward.

[0169] As shown in the figure, filaments are formed in the glass substrate 21 along predetermined cutting lines and can be separated based on them. This separation can reduce the possibility of defects occurring or inherent in the glass, and even if defects do occur, they can be identified by a quick and relatively simple method, thereby further improving the efficiency of semiconductor packaging substrate manufacturing processes that include unitized processes of glass substrates.

[0170] On the other hand, according to one embodiment, the edge regions disposed at the corners of the glass substrate 21 can be processed into curved surfaces. That is, the edge regions of the glass substrate 21 can be ground. In other words, the corners (edges) of the glass substrate 21 can be smoothed from a sharp state after cutting (see the example photograph in Figure 11).

[0171] Figure 11 is a photograph of a cross-section of the polished glass substrate according to this embodiment.

[0172] As shown in the figure, the cut surface of the glass substrate 21 protruding from the upper or lower layer (denoted as "CL" in Figure 11) can be polished to appear circular when viewed in cross-section by grinding. The edge of the glass substrate removed by the grinding process can be about 10 μm or more, 20 μm or more, 30 μm or more, or 50 μm or more, and can be about 100 μm or less.

[0173] By grinding, the corners of the cut surface can be formed into a curved shape as shown in Figure 11, or, according to other embodiments, can be transformed into a C-shaped (curved shape) or R-shaped (round shape) chamfer.

[0174] When viewed from the side (or cross-section), the side of the package substrate 20 with a cut surface, corresponding to its thickness, can be ground. For example, the shape of the ground side can be such that the corner where the side of the package substrate 20 intersects with the top surface is chamfered (Flat Edge), or the side connecting the top surface and the bottom surface is ground into a round shape, such that the central part of the side protrudes (Pencil Edge), etc.

[0175] The side surface (edge) of the packaging substrate 20 can be in the shape of a straight line or a broken piece of glass immediately after the cut surface is formed, and can be manufactured into a shape with a specified radius of curvature by grinding. In this case, the radius of curvature is called the side radius of curvature.

[0176] The side curvature radius of the packaging substrate 20 can be 0.05 mm or more, 0.1 mm or more, 0.15 mm or more, or 0.2 mm or more. The side curvature radius can be less than 2.0 mm, less than 1.8 mm, less than 1.6 mm, less than 1.2 mm, less than 1 mm, less than 0.8 mm, or less than 0.6 mm. In this case, workability can be improved by minimizing the occurrence of breakage of the packaging substrate or glass substrate during manufacturing and transportation.

[0177] For example, when grinding, by setting the blade's design angle to 90˚±1˚ and the cutting amount to 0.08mm to 0.14mm, a packaging substrate with an edge curvature radius of 0.241mm can be manufactured.

[0178] Additionally, by way of example, when grinding is performed, a packaging substrate with an edge curvature radius of 0.522 mm can be manufactured by setting the blade design angle to 120˚±1˚ and the cutting amount to 0.05 mm to 0.12 mm.

[0179] Figure 12, in parts (a) and (b), respectively shows the state of the glass substrate according to another embodiment as viewed from above and a photograph of a portion thereof. In the glass substrate, not only can its cross-section be made circular, but the portions corresponding to the corners of the quadrilaterals when viewed from above can also be made circular. Figure 12, in part (a), shows the state of the unit glass substrate as viewed from above; the corners of the first surface 213 and the second surface 214 can also be rounded as shown in the figure.

[0180] When viewed from above, the square packaging substrate has four corners, each of which is rounded to have a predetermined curvature, thereby eliminating angular portions. This radius of curvature is called the substrate radius of curvature. The substrate radius of curvature can be 0.5 mm or more, 1 mm or more, 1.2 mm or more, or 1.5 mm or more. Alternatively, the substrate radius of curvature can be less than 8 mm, 7 mm or less, 6 mm or less, or 5 mm or less. In this case, the occurrence of corner breakage, etc., can be minimized, while ensuring the stable availability of areas in the upper and / or lower layers for configuring conductive layers.

[0181] On the other hand, according to this embodiment, the vertices of the quadrilateral glass substrate 21 can also be curved by grinding. If the vertex portion is ground, the risk of damage or breakage can be reduced when moving the glass substrate 21 or transporting it via a tray or the like. By setting the curvature of the ground vertex portion of the glass substrate 21 to a diameter with the smallest deviation from a predetermined target value, an appropriate value can be derived.

[0182] Unprocessed glass substrates after cutting exhibit uneven right-angle deviations on their cut surfaces, and the cut edges may also show serrations, thus posing an additional risk of damage such as breakage or fragmentation. Grinding glass substrates to achieve curved edges or chamfered cut surfaces can significantly reduce this risk of additional damage. Furthermore, when moving glass substrates or encapsulation substrates or transporting them on pallets for additional processes, external impacts can be appropriately dispersed, and defects caused by cracks or fragmentation can be minimized.

[0183] According to another embodiment, grinding can be applied not only to the protruding glass substrate 21, but also to the upper or lower layer.

[0184] The packaging substrate and its manufacturing method according to the embodiments described above can effectively detect defects that may occur in the packaging substrate including the glass structure, and can effectively protect the glass substrate from external impacts.

[0185] The present invention has been described above with reference to the embodiments illustrated in the accompanying drawings. However, these are merely examples, and those skilled in the art will understand that various modifications and equivalent embodiments can be derived from them. In other words, the scope of the present invention is not limited to the described embodiments, but rather includes various modifications or variations made by those skilled in the art using the basic concepts of the embodiments defined in the appended claims. Therefore, the true scope of protection of the present invention should be determined by the technical ideas in the appended claims.

[0186] 10: Motherboard 100: Semiconductor devices 20: Packaging substrate 21, 21a: Glass substrate 21b: Defect 21c: Seed layer / base layer 21d: Conductive layer 21e: Etched layer 211: First thickness 212: Second thickness 213: First Page 213a: Edge region 214: Second page 213a: Edge region 22: Substrate layer 221: Area 1 222: Second Zone 223: Insulation layer 23: Through hole 23a: Insulation layer 23b: Conductive layer 23c: Conductive layer 23d: Etched layer 23e: Insulation layer 231: Through-hole in the first region 232: Second region through hole 24: Allocation Layer 241: Pattern Allocation 26, 70: Upper layer 25, 71: Upper part of the layer 251: Upper part pattern 252: Blind Hole 253: Upper insulation layer 27: Upper connection layer 271: Electrode connected above 272: The pattern above is connected. 28: Cavity 281: Interior Space 282: Cavity Distribution Layer 30: Semiconductor Components Division 32: First semiconductor element 34: Second semiconductor element 36: Third semiconductor element 40: Cavity element 60: Covering layer 72: First Covering Layer 80: Lower layer 81: Lower part of the layer 82: Second Covering Layer CL: Cutting line Gr: Glass crack Gh: Glass shards w: width

Claims

1. A method for manufacturing a packaging substrate, comprising: The steps include preparing a glass substrate comprising a first surface and a second surface facing each other, and forming an upper layer over the first surface, wherein the glass substrate has an edge region; and ablating a portion of the upper layer with a first laser along a cutting line designated as a predetermined cutting position to form a removal line, wherein the removal line exposes the glass substrate, wherein the first laser is a green laser or an ultraviolet laser. Following the step of forming the removal line, a filamentation process is performed whereby a second laser is used to form a filament on the exposed glass substrate along the removal line, wherein the irradiation intensity of the first laser is not greater than the irradiation intensity used to form the filament, and wherein the second laser is an infrared laser; a step of cutting the glass substrate using the filament; and a step of detecting defects selected from the edge region of the glass substrate, the cut surface of the glass substrate, the removal line of the upper layer, and any one of the groups consisting of these combinations.

2. A method for manufacturing a packaging substrate as claimed in claim 1, wherein the method further comprises, prior to the filamentation process step: The step of forming a lower layer below the second surface; And the step of removing a portion of the lower layer along the cutting line to form the removal line.

3. A method for manufacturing a packaging substrate as claimed in claim 1 or 2, wherein the width of the removal line is 5 μm or more.

4. A method for manufacturing a packaging substrate as claimed in claim 1 or 2, wherein the upper layer or the lower layer has a tapered shape that thins toward the cut surface of the glass substrate.

5. A method for manufacturing a packaging substrate as claimed in claim 1, wherein the step of cutting the glass substrate is a step of separating the glass substrate into two or more parts by applying tensile stress or rotational force to the filament to form a cut surface on the glass substrate.

6. A method for manufacturing a packaging substrate as claimed in claim 1, wherein after the step of cutting the glass substrate, the method further comprises: The step of grinding the cut surface of the glass substrate being cut.

7. A method for manufacturing a package substrate as claimed in claim 1 or 2, wherein the edge region includes: The edge of the glass substrate; And the region of the glass substrate that protrudes further than the upper layer or the lower layer.

8. A packaging substrate manufactured by the method for manufacturing a packaging substrate as described in claim 1, comprising: A glass substrate, comprising a first surface and a second surface facing each other; The glass substrate includes an upper layer or a lower layer, wherein the upper layer is stacked above the first surface and the lower layer is stacked below the second surface. The edge region includes the edge of the glass substrate and a region of the glass substrate that protrudes further than the upper layer or the lower layer.

9. The packaging substrate of claim 8, wherein the upper layer includes a first insulating layer stacked over the first surface, the edge of the first insulating layer being disposed inside the edge of the glass substrate, the edge region including the edge of the glass substrate and the edge of the first insulating layer.

10. The packaging substrate of claim 9, wherein the lower layer includes a second insulating layer stacked below the second surface, the edge of the second insulating layer being disposed inside the edge of the glass substrate, the edge region including the edge of the glass substrate and the edge of the second insulating layer.

11. The packaging substrate as claimed in claim 10, wherein the width from the edge of the first insulating layer to the edge of the glass substrate, the width from the edge of the second insulating layer to the edge of the glass substrate, or both, are each independently formed to be from 5 μm to 200 μm.

12. The packaging substrate as claimed in claim 8, wherein the corners of the glass substrate are curved in the edge region.

13. The packaging substrate as claimed in claim 8, wherein the corners of the glass substrate are chamfered in the edge region.

14. The packaging substrate as claimed in claim 8, wherein the upper layer or the lower layer each has a tapered shape that thins toward the edge region.

15. The packaging substrate as claimed in claim 8, wherein semiconductor elements are mounted on the upper portion of the upper layer.

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