Pulse width modulation signal generation method and circuit

Abstract

A pulse width modulation (PWM) signal generation method involves a controller converting a duty cycle into a preset value and a delay value. A counter counts the count and inputs the count value into a comparator. The comparator outputs a first digital signal at a first level to a lookup table. When the count value reaches the preset value, the comparator outputs a first digital signal at a second level to the lookup table. When the lookup table determines that the first digital signal has changed from the first level to the second level, it converts the first digital signal into two second digital signals based on the delay value. A delay number is calculated based on the delay value, and a double data rate register is output to generate a third digital signal that is not delayed or is delayed by half a clock cycle compared to the first digital signal based on the two second digital signals. An output delay circuit delays the third digital signal by a preset time based on the delay number to generate and output a PWM signal with the duty cycle.

Description

Technical Field

[0001] This invention relates to a method for generating digital signals, and more particularly to a method for generating pulse width modulation signals. Prior Technology

[0002] Referring to Figure 1, a basic method for generating a pulse width modulation (PWM) signal is as follows: a comparator (not shown) compares a target value with the level of a carrier wave S generated by a counter (not shown). When the level of the carrier wave S is less than the target value, the comparator sets the output digital signal D to a high level until the level of the carrier wave S reaches (equals) the target value. Then, the comparator sets the digital signal D to a low level, thereby generating a PWM signal with a target duty cycle.

[0003] As shown in Figure 2, comparing the right and left images, it can be seen that when the PWM signal frequency is 200kHz, if more duty states are to be generated within one cycle (5μs) of the PWM signal (compare the right and left images in Figure 2) to improve the resolution of the PWM signal, the frequency of the clock signal generating the carrier S needs to be increased. For example, if the clock signal is 200MHz, the carrier S can generate 1000 level changes within one cycle (5μs) of the PWM signal, allowing the PWM signal's duty cycle to generate 1000 states, which is approximately 9.96 bits of resolution. Therefore, when the PWM signal's duty cycle needs to generate 13000 states, i.e., have 13.66 bits of resolution, the clock signal frequency needs to be as high as 2.6GHz, i.e., 5μs / (1 / 2.6G) = 13000. Summary of the Invention

[0004] Therefore, the object of the present invention is to provide a pulse width modulation signal generation method and circuit that can generate a high-resolution pulse width modulation signal without increasing the frequency of the pulse signal.

[0005] Therefore, the pulse width modulation signal generation method of the present invention includes: a controller determining a working cycle based on a clock signal, converting the working cycle into a preset value and a delay value, and inputting the preset value into a comparator and the delay value into a lookup table; the controller controlling a counter to count according to the clock signal and inputting a count value into the comparator; the controller controlling the comparator to output a first digital signal at a first level to the lookup table, until the comparator determines that the count value has reached the preset value, the comparator outputs the first digital signal at a second level to the lookup table; the controller instructing the lookup table to determine that the first digital signal changes from the first level to the second level. At that time, based on the delay value, a trigger delay data is obtained by looking up the table. The first digital signal is converted into two second digital signals and output to an output double data rate register. At the same time, a delay number is calculated based on the delay value and output to an output delay circuit. The controller causes the output double data rate register to generate and output a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double data rate compared to the first digital signal and is not delayed or is delayed by half a clock cycle of the clock signal. The controller causes the output delay circuit to delay the third digital signal by a preset time based on the delay number to generate and output a pulse width modulation signal with the working cycle.

[0006] Furthermore, a pulse width modulation signal generation circuit for implementing the above method according to the present invention includes a controller, a counter electrically connected to the controller, a comparator electrically connected to the controller and the counter, a lookup table electrically connected to the controller and the comparator, an output double data rate register electrically connected to the controller and the lookup table, and an output delay circuit electrically connected to the controller, the lookup table, and the output double data rate register. The controller determines a working cycle based on a clock signal, converts the working cycle into a preset value and a delay value, inputs the preset value to the comparator, and inputs the delay value to the lookup table. The counter, controlled by the controller, counts according to the clock signal and inputs a count value to the comparator. The comparator, controlled by the controller, outputs a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the preset value. When the value is set, the comparator outputs the first digital signal at the second level to the lookup table; the lookup table, controlled by the controller, determines when the first digital signal changes from the first level to the second level, and according to the delay value, obtains a trigger delay data from the lookup table, converts the first digital signal into two second digital signals and outputs them to the output double data rate register, and simultaneously calculates a delay number according to the delay value and outputs it to the output delay circuit; the output double data rate register, controlled by the controller, generates and outputs a third digital signal to the output delay circuit according to the two second digital signals, the third digital signal having double data rate compared to the first digital signal and not delayed or delayed by half a clock cycle of the clock signal; the output delay circuit, controlled by the controller, delays the third digital signal by a preset time according to the delay number to generate and output a pulse width modulation signal with the working cycle.

[0007] In some embodiments of the present invention, the controller controls the counter to count up or down the clock cycle of the clock signal according to the clock signal, and the counter also inputs a directional value representing the counting direction to the comparator to notify the comparator that the counter is currently counting up or down; when the controller controls the counter to count up, the preset value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1); when the controller controls the counter to count down, the preset value is (M+1) clock cycles and the delay value is (1-N) clock cycles.

[0008] In some embodiments of the present invention, when the counter counts up, the first level is a high level, the second level is a low level, and the two second digital signals cause the trailing edge of the third digital signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle of the clock signal; when the counter counts down, the first level is a low level, the second level is a high level, and the two second digital signals cause the leading edge of the third digital signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle of the clock signal.

[0009] In some embodiments of the present invention, the output delay circuit includes a plurality of series-connected delay elements and a multiplexer electrically connected to the output terminals of the delay elements. The multiplexer causes the third digital signal to pass through the delay elements in an equal number of delays before outputting the pulse width modulation signal, wherein each delay element can delay by 78 picoseconds.

[0010] The advantages of this invention are as follows: when the pulse signal is 200MHz and the pulse width modulation signal is 200KHz, by using the lookup table, the output double data rate register, and the output delay circuit, without increasing the frequency of the pulse signal, when the output delay circuit has 32 delay elements, the resolution of the generated pulse width modulation signal can be increased by 5 bits from the original 9.96 bits to a resolution of 14.96 bits, meeting the requirements for high resolution, and capable of making a small pulse width modulation of 78ps. Simple Explanation of the Diagram

[0011] Other features and effects of the present invention will be clearly shown in the embodiments with reference to the drawings, wherein: Figure 1 is a schematic diagram of the basic method for generating pulse width modulation signals; Figure 2 is a schematic diagram illustrating the method of improving the resolution of pulse width modulation signals; Figure 3 illustrates the main flowchart steps of an embodiment of the pulse width modulation signal generation method of the present invention. Figure 4 is a circuit block diagram of an embodiment of the pulse width modulation signal generation circuit of the present invention; Figure 5 is a detailed circuit block diagram of the output delay circuit in this embodiment; Figure 6 illustrates the process of generating a pulse width modulation signal with a duty cycle of 480.625 clock cycles based on the carrier number in this embodiment; Figure 7 illustrates that the output double data rate register of this embodiment generates a digital signal with double data rate and trailing edge delay of half a clock cycle based on the two input digital signals; 8 illustrates the output double data rate of this embodiment The register generates a digital signal with double data rate without delay at the trailing edge based on the input two digital signals; 9 illustrates the process of generating a pulse-wave width modulated signal with a working period of 480.625 clock cycles based on the case of the number of carrier downs in this embodiment; 10 illustrates the output double data rate of this embodiment The register generates a digital signal with double data rate with no leading edge delay based on the input two digital signals; 11 illustrates the output double data rate of this embodiment The register generates a digital signal with double data rate and a leading edge delay of half a clock cycle based on the input two digital signals; 12 illustrates the process of generating a pulse-width-width modulated signal with a working period of 499.9 clock cycles based on the case of the number of carriers up and the number of carriers down in this embodiment. Implementation

[0012] Before the invention is described in detail, it should be noted that in the following explanatory content, similar components are represented by the same number.

[0013] 3 is a flow step of one embodiment of a pulse-wave width-modulated signal generation method of the invention, and it is implemented by a pulse-wave width-modulated signal (hereinafter referred to as PWM) generating circuit of the invention shown in FIG. As shown in FIG. The controller 1 provides a simultaneous pulse signal CLK to the counter 2, the table looker 4, the ODDR register 5 and the output delay circuit 6 to drive its operation, and the above components may be, but are not limited to, using the built-in IP (Silicon Intelligence) of the Kintex-7 FPGA (Field Programmable Gate Array) published by Xilinx.

[0014] In this embodiment, the clock signal CLK is based on a frequency of 200MHz, meaning one clock cycle is 5ns (nanoseconds). As shown in Figure 5, the output delay circuit 6 essentially consists of a plurality of series-connected delay elements (tap) 61 and a multiplexer 62 electrically connected to the output terminals of these delay elements 61. Controlled by the multiplexer 62, the signal can be input from the first delay element 61, pass through a preset number of delay elements 61, and then be output by the multiplexer 62, thus achieving the purpose of delaying the signal for a certain period. In this embodiment, there are, for example, but not limited to, 31 delay elements 61, and each delay element 61 can delay for, for example, but not limited to, 78 picoseconds (ps). Therefore, the output delay circuit 6 is equivalent to providing 5-bit resolution.

[0015] This embodiment uses a PWM signal with a frequency of 200kHz as an example for explanation. Therefore, as shown in step S1 of Figure 3, when a PWM signal is to be generated, the controller 1 in this embodiment first determines a duty cycle of the PWM signal to be generated based on the clock signal CLK, for example, the clock cycle of the clock signal CLK is 480.625, that is, a duty cycle of 480.625 x 5ns (nanoseconds) is generated within one cycle (5μs) of the PWM signal, and the duty cycle is converted into a preset value and a delay value. For example, when the counter 2 is set to count from 0, the integer part (480) of 480.625 is used as the preset value, and the decimal part (0.625) of 480.625 is used as the delay value. The preset value (480) is input to the comparator 3, and the delay value (0.625) is input to the lookup table 4.

[0016] Next, as shown in step S2 of Figure 3, the controller 1 controls the counter 2 to count up according to the clock signal CLK and inputs the count value generated by the count into the comparator 3. Specifically, the counter 2 counts according to the clock signal CLK to generate a continuously counting (sawtooth wave) carrier signal f1 as shown in Figure 6, and outputs the carrier signal f1 and a direction value dir representing the counting direction to the comparator 3. The count value is the current level of the carrier signal f1. The direction value dir is 0 to represent counting up and 1 to represent counting down, but it is not limited to this.

[0017] Then, as shown in step S3 of Figure 3, the controller 1 controls the comparator 3 to output a first digital signal D11 located at a first level (e.g., high level) to the lookup table 4 according to the direction value dir (e.g., 0), as shown in Figure 6, and compares whether the count value (level) of the carrier signal f1 reaches (equal to or greater than) the preset value. If so, as shown in Figure 6, the comparator 3 causes the first digital signal D11 to change from the first level (high level) to the second level (low level) and outputs the first digital signal D11 to the lookup table 4.

[0018] Next, in step S4 of Figure 3, the controller 1 instructs the lookup table 4 to determine when the first digital signal D11 changes from the first level to the second level. Based on the delay value (0.625), a trigger delay data is obtained by looking up the table. Based on the trigger delay data, the first digital signal D11 is converted into two second digital signals D21 and D22, and the two second digital signals D21 and D22 are output to the output double data rate register 5. At the same time, the lookup table 4 also calculates a delay number TN based on the delay value and outputs the delay number TN to the output delay circuit 6.

[0019] Specifically, the lookup table 4 performs the following process: when the first digital signal D11 transitions from a high level to a low level (i.e., the counter 2 is counting up), and the lookup table 4 determines that the delay value (0.625) is greater than or equal to 0.5, then the first data in the trigger delay data is set to 1 and the second data to 0; conversely, if the lookup table 4 determines that the delay value is less than 0.5, then the first data in the trigger delay data is set to 0 and the second data to 0. Therefore, in this embodiment, the first data in the trigger delay data is 1 and the second data is 0. Next, the lookup table 4 converts the first digital signal D11 into a second digital signal D21 based on the first data (1) in the trigger delay data, as shown in Figure 7. The first data (1) causes the trailing edge of the second digital signal D21 to be delayed by one clock cycle compared to the first digital signal D11, while the second data (0) causes the trailing edge of the second digital signal D22 to remain the same as the first digital signal D11 without delay. Thus, it can be seen that when the counter 2 counts, the trigger delay data is used to determine whether the trailing edges of the second digital signals D21 and D22 should be delayed by one clock cycle compared to the first digital signal D11.

[0020] Specifically, the lookup table 4 determines the delay value based on the delay value. If the delay value is greater than or equal to 0.5, it calculates the delay number TN based on the value obtained by subtracting 0.5 from the delay value. The delay number TN refers to the number of delay elements 61 connected in series in the output delay circuit 6. Therefore, in this embodiment, the lookup table 4 calculates the delay number TN based on 0.125 (0.625-0.5). Thus, one clock cycle (1 / 200MHz) is 5 nanoseconds (ns), 0.125 clock cycles is 0.625 nanoseconds (ns), or 625 picoseconds (ps). Since one delay element is 78 picoseconds, 625 picoseconds is equivalent to using 8 (625 / 78) delay elements 21. Therefore, the delay number TN is 8. Furthermore, as shown in Figure 4, the lookup table 4 also transmits a trigger signal TD to notify the output delay circuit 6 to load the delay number TN.

[0021] Next, step S5 of Figure 3 is performed. The controller 1 instructs the output double data rate register 5 to generate and output a third digital signal D31 to the output delay circuit 6 based on the two input second digital signals D21 and D22. As shown in Figure 7, the third digital signal D31 has double the data rate compared to the first digital signal D11 and its trailing edge is delayed by half a clock cycle. This is because the trailing edge of the second digital signal D21 is at a high level (1) while the trailing edge of the second digital signal D22 is at a low level (0), which causes the trailing edge of the third digital signal D31 to be delayed by half a clock cycle compared to the first digital signal D11. Conversely, in another case, as shown in Figure 8, if the trailing edges of the two second digital signals D21 and D22 are both low (0), the trailing edge of the generated third digital signal D31' will be the same as that of the first digital signal D11 without delay.

[0022] Next, as shown in step S6 of Figure 3, the controller 1 instructs the multiplexer 62 of the output delay circuit 6 to delay the input third digital signal D31 by a preset time (i.e., 8 x 78 = 624 picoseconds, close to the above-mentioned 625 picoseconds) through eight series-connected delay elements 61 according to the delay number (8) before outputting to generate a PWM signal D41 with a working period of 480.625 clock cycles, as shown in Figure 6.

[0023] Furthermore, when generating a PWM signal with a working cycle of 480.625 clock cycles, but the controller 1 sets the counter 2 to start counting down from the maximum value (e.g., 500), since time cannot be reversed, in the above step S1, (480+1) will be used as the preset value and (1-0.625) will be used as the delay value. That is, 480.625 clock cycles are obtained by subtracting (delay) 0.375 clock cycles from the 481st clock cycle. Therefore, the preset value (481) is input to the comparator 3 and the delay value (0.375) is input to the lookup table 4.

[0024] Therefore, in step S2, the counter 2 starts counting from the maximum value (e.g., 500) and generates and outputs the carrier signal f2 and the direction value (1) representing the counting direction, as shown in FIG9, to the comparator 3. Then, in step S3, the comparator 3 outputs a first digital signal D12 located at a first level (e.g., low level) to the lookup table 4 according to the direction value (1), as shown in FIG9, and compares whether the count value (level) of the carrier signal f2 reaches the preset value (481). If so, as shown in FIG9, the comparator 3 changes the first digital signal D12 from the first level (low level) to the second level (high level) and outputs the first digital signal D12 to the lookup table 4.

[0025] Next, in step S4 of Figure 4, the controller 1 instructs the lookup table 4 to determine when the first digital signal D12 changes from the first level to the second level. Based on the delay value (0.375), a trigger delay data is obtained by looking up the table. That is, the lookup table 4 determines that the delay value (0.375) is less than 0.5, and thus sets the first data and the second data of the generated trigger delay data to 1. As shown in Figure 10, the lookup table 4 adjusts the first... A digital signal D12 is converted into two second digital signals D23 and D24 and output to the output double data rate register 5. The first data (1) ensures that the leading edge of the second digital signal D23 is not delayed compared to the first digital signal D12 and remains the same as the first digital signal D12. Similarly, the second data (1) also ensures that the leading edge of the second digital signal D24 is not delayed and remains the same as the first digital signal D12. Conversely, as shown in Figure 11, if the delay value is greater than 0.5, the first data in the trigger delay data will be 0 and the second data will be 1, causing the leading edge of the second digital signal D23 to be delayed by one clock cycle compared to the first digital signal D12, but the leading edge of the second digital signal D24 remains undelayed and remains the same as the first digital signal D12. Therefore, when counter 2 counts down, the trigger delay data is used to determine whether the leading edge of the second digital signal D23 and D24 should be delayed by one clock cycle compared to the first digital signal D12.

[0026] At the same time, the lookup table 4 also calculates a delay number based on the delay value (0.375) and outputs the delay number to the output delay circuit 6. In this example, the delay number is 24, which is 1875 picoseconds (0.375 clock cycles) / 78 picoseconds.

[0027] Then, in step S5 of Figure 3, the controller 1 instructs the output double data rate register 5 to generate and output a third digital signal D32 to the output delay circuit 6 based on the two input second digital signals D23 and D24. As shown in Figure 10, the third digital signal D32 has double the data rate compared to the first digital signal D12 and its leading edge is not delayed. This is because the leading edges of the two second digital signals D23 and D24 are both at a high level (1), which makes the leading edge of the third digital signal D32 not delayed compared to the first digital signal D12. Conversely, as shown in Figure 11, if the leading edge of the second digital signal D23 is at a low level (0) and the leading edge of the second digital signal D24 is at a high level (1), the leading edge of the generated third digital signal D32' will be delayed by half a clock cycle compared to the first digital signal D12.

[0028] Next, in step S6 of Figure 4, the controller 1 instructs the multiplexer 62 of the output delay circuit 6 to delay the input third digital signal D32 by a preset time (i.e., 78 x 24 = 1872 picoseconds, close to the above-mentioned 1875 picoseconds) through 24 series-connected delay elements 61 according to the delay number (24) to generate and output a PWM signal D42 with the working cycle (480.625 clock cycles), as shown in Figure 9.

[0029] Furthermore, as shown in Figure 12, when the working period of the PWM signal to be generated is an extreme value, such as 499.9 clock cycles, and the carrier wave generated by the up and down count of the counter 2, i.e., the triangular wave f3 shown in the figure, is used to generate the PWM signal, the controller 1 sets the preset value to 499 and the delay value to 0.9 for the up count of the counter 2. Thus, as shown in Figure 12, after the comparator 3 outputs a first digital signal D13 with a working period of 499 clock cycles, the first digital signal D13 is delayed by half a clock cycle (0.5) through the lookup table 4 and the output double data rate register 5 to generate and output a third digital signal D33 to the output delay circuit 6. The output delay circuit 6 then outputs a PWM signal D43 with a working period of 499.9 clock cycles after a delay of about 0.4 clock cycles, based on the delay number calculated by the lookup table 4 based on the delay value (0.9) - 0.5 (0.4).

[0030] When counter 2 counts down, controller 1 sets the preset value to (499+1) and the delay value to (1-0.9). Thus, as shown in Figure 12, comparator 3 initially outputs a first digital signal D14 with a working cycle of 500 clock cycles. Then, the first digital signal D14 is not delayed by lookup table 4 and output double data rate register 5 (because the delay value (0.1) is less than 0.5) and generates and outputs a third digital signal D34 to output delay circuit 6. Then, output delay circuit 6 delays the third digital signal D34 by 0.1 clock cycles according to the delay number calculated by lookup table 4 based on the delay value (0.1) to generate and output a PWM signal D44 with 499.9 working cycles.

[0031] It is worth mentioning that although this embodiment takes the frequency of the clock signal CLK as 1000 times that of the PWM signal as an example, it is not limited to this. For example, the frequency of the clock signal CLK can be approximately 64 times or more of the frequency of the PWM signal and is applicable to this embodiment.

[0032] In summary, the above embodiments, through the lookup table 4, the output double data rate register 5, and the output delay circuit 6, can increase the resolution of the generated PWM signal's duty cycle from the original 9.96 bits to 14.96 bits without increasing the frequency of the clock signal. When the output delay circuit 6 has 31 delay elements, it can provide more than 13,000 duty cycle states, meeting the high-resolution requirements, and can perform a tiny pulse width modulation of 78 ps, thus effectively achieving the efficacy and purpose of the present invention.

[0033] However, the above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the scope of the patent application and the contents of the patent specification shall still fall within the scope of the patent of the present invention.

[0034] 1: Controller 2: Counter 3: Comparator 4: Lookup Table (LUT) 5: Output Double Data Rate Register (ODDR) 6: Output Delay Circuit (ODELAY) 61: Delay element 62: Multiplexer S1~S6: Steps CLK: Clock signal f1, f2: Carrier signals dir: direction value D11, D12, D13, D14: First digital signal D21, D22, D23, D24: Second digital signal D31, D31', D32, D32', D33, D34: Third digital signal TN: Delay Count TD: Trigger signal D41, D42, D43, D44: PWM signals

Claims

1. A method for generating a pulse width modulation signal, comprising: A controller determines a duty cycle based on a clock signal, converts the duty cycle into a preset value and a delay value, inputs the preset value into a comparator, and inputs the delay value into a lookup table. The controller controls a counter to count based on the clock signal and inputs a count value into the comparator. The controller controls the comparator to output a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the preset value. Then, the comparator outputs the first digital signal at a second level to the lookup table. The controller instructs the lookup table to determine when the first digital signal changes from the first level to the second level. Based on a trigger delay data obtained from the lookup table using the delay value, the controller converts the first digital signal into two second digital signals and outputs them to an output double data rate register. Simultaneously, it calculates a delay value based on the delay value and outputs it to an output delay circuit. The controller causes the output double data rate register to generate and output a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double the data rate compared to the first digital signal and is not delayed or is delayed by half a clock cycle of the clock signal. The controller also causes the output delay circuit to delay the third digital signal by a preset time based on the delay value to generate and output a pulse width modulation signal with the duty cycle.

2. The pulse width modulation signal generation method as described in claim 1, wherein, The controller controls the counter to count up or down the clock signal for the clock cycles. The counter also inputs a directional value representing the counting direction to the comparator to notify the comparator whether the counter is currently counting up or down. When the controller controls the counter to count up, the preset value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1). When the controller controls the counter to count down, the preset value is (M+1) clock cycles and the delay value is (1-N) clock cycles.

3. The pulse width modulation signal generation method as described in claim 2, wherein, When the counter counts up, the first level is high and the second level is low, and the two second-digit signals cause the trailing edge of the third-digit signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle. When the counter counts down, the first level is low and the second level is high, and the two second-digit signals cause the leading edge of the third-digit signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle.

4. A method for generating a pulse width modulation signal as described in any one of claims 1 to 3, wherein, The output delay circuit includes a plurality of series-connected delay elements and a multiplexer electrically connected to the output terminals of the delay elements. The multiplexer causes the third digital signal to pass through the delay elements in an equal number of delays before outputting the pulse width modulation signal, wherein each delay element can delay by 78 picoseconds.

5. A pulse width modulation signal generation circuit, comprising: One controller; A counter electrically connected to the controller; a comparator electrically connected to the controller and the counter; a lookup table electrically connected to the controller and the comparator; an output double data rate register electrically connected to the controller and the lookup table; and an output delay circuit electrically connected to the controller, the lookup table, and the output double data rate register; wherein the controller determines a duty cycle based on a clock signal, converts the duty cycle into a preset value and a delay value, and inputs the preset value into the comparator and the delay value into the lookup table; the counter, controlled by the controller, counts according to the clock signal and inputs a count value into the comparator; the comparator, controlled by the controller, outputs a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the preset value, at which point the comparator outputs the first digital signal at a second level to the lookup table; The lookup table device, controlled by the controller, determines when the first digital signal changes from the first level to the second level. Based on the delay value, it looks up a trigger delay data in the table, converts the first digital signal into two second digital signals, and outputs them to the output double data rate register. Simultaneously, it calculates a delay number based on the delay value and outputs it to the output delay circuit. The output double data rate register, controlled by the controller, generates and outputs a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double the data rate compared to the first digital signal and is either not delayed or delayed by half a clock cycle. The output delay circuit, controlled by the controller, delays the third digital signal by a preset time based on the delay number to generate and output a pulse width modulation signal with the working cycle.

6. The pulse width modulation signal generation circuit as described in claim 5, wherein, The controller controls the counter to count up or down the clock signal for the clock cycles. The counter also inputs a directional value representing the counting direction to the comparator to notify the comparator whether the counter is currently counting up or down. When the controller controls the counter to count up, the preset value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1). When the controller controls the counter to count down, the preset value is (M+1) clock cycles and the delay value is (1-N) clock cycles.

7. The pulse width modulation signal generation circuit as described in claim 6, wherein, When the counter counts up, the first level is high and the second level is low, and the two second-digit signals cause the trailing edge of the third-digit signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle. When the counter counts down, the first level is low and the second level is high, and the two second-digit signals cause the leading edge of the third-digit signal generated by the output double data rate register to be either not delayed or delayed by half a clock cycle.

8. The pulse width modulation signal generating circuit as described in any one of claims 5 to 7, wherein, The output delay circuit includes a plurality of series-connected delay elements and a multiplexer electrically connected to the output terminals of the delay elements. The multiplexer causes the third digital signal to pass through the delay elements in an equal number of delays before outputting the pulse width modulation signal, wherein each delay element can delay by 78 picoseconds.

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