Integrated circuit device and method of forming the same

Abstract

Some embodiments relate to an integrated circuit (IC) device whose substrate includes a P-well region and a dielectric structure. The dielectric structure is located at the surface of the substrate, extends downward into the substrate, and is located at the lateral perimeter of the P-well region. The IC device also includes a dielectric layer located above the P-well region and extending laterally above the dielectric structure. The IC device also includes an N+ gate structure located above the dielectric layer and including at least one P+ region located above the P-well region on the substrate and the dielectric structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit device and a method for forming the same. Prior Technology

[0002] Ultra-low power complementary metal-oxide-semiconductor (CMOS) reference voltage circuits are becoming increasingly important in the implementation of various types of integrated circuit (IC) devices, including, but not limited to, display drivers, digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). A corresponding focus is on providing highly accurate reference voltages across a range of process technologies in a cost-effective manner. Summary of the Invention

[0003] One embodiment of this disclosure provides an integrated circuit device. The integrated circuit device includes a substrate and a dielectric structure. The substrate includes a P-well region, and the dielectric structure is located on the surface of the substrate, extending downward into the substrate, and at the lateral perimeter of the P-well region. The integrated circuit device also includes a dielectric layer located above the P-well region and laterally extending above the dielectric structure. The integrated circuit device further includes an N+ gate structure located above the dielectric layer and including at least one P+ region, which is located above the P-well region of the substrate and the dielectric structure.

[0004] Another aspect of this disclosure provides an integrated circuit device. The integrated circuit device includes a reference voltage circuit. The reference voltage circuit includes a flip-gate element (FGD) and a normal gate element (NGD). The flip-gate element includes a first P-well region located in a substrate, a first N+ source-drain region and a second N+ source-drain region located in the first P-well region, and a P+ gate structure. The P+ gate structure is located above the first P-well region and, in a plan view of the integrated circuit device, between the first N+ source-drain region and the second N+ source-drain region. The P+ gate structure includes a first N+ region aligned side-by-side with the first N+ source-drain region in a plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in a plan view. The normal gate element includes a second P-well region located in a substrate, a third N+ source-drain region and a fourth N+ source-drain region located in the second P-well region, and an N+ gate structure. The N+ gate structure is located above the second P-well region and, in the plan view, lies between the third and fourth N+ source-drain regions. The N+ gate structure includes at least one P+ region extending between the third and fourth N+ source-drain regions in the plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

[0005] Another aspect of this disclosure provides a method for forming an integrated circuit device. The method includes providing a substrate including a P-well region. The method further includes forming a trench on the upper surface of the P-well region. The method further includes forming a dielectric structure in the trench. The method further includes forming a dielectric layer over the P-well region and the dielectric structure. The method further includes forming an N+ gate structure over the dielectric layer. The method further includes forming at least one P+ region in the N+ gate structure, the at least one P+ region being located over the P-well region and the dielectric structure. Simple Explanation of the Diagram

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various components may be arbitrarily increased or decreased. Figure 1 shows a schematic diagram of some embodiments of a CMOS-only reference voltage circuit according to the present disclosure. Figure 2 shows a cross-sectional view of some embodiments of a shallow trench isolation (STI) structure with a "recessed" feature according to this disclosure, as shown in a normal gate element (NGD) of a CMOS reference voltage circuit, which may adversely affect the accuracy of the CMOS reference voltage circuit. Figure 3 shows the current-voltage (IV) curves of NGD under different bias voltages according to the present disclosure, which can exhibit the "hump" effect caused by the dip feature, which adversely affects the accuracy of the CMOS reference voltage. Figures 4A and 4B show the layout and cross-sectional view of an NGD including a gate inversion doped region according to the present disclosure, respectively. Figure 5 illustrates an exemplary current flow in an NGD affected by a gate inversion doped region according to the present disclosure. Figure 6 shows an IV curve illustrating exemplary gamma values, which can be used to quantify the effect of the hump effect of NGD on the critical voltage. Figure 7 shows the IV curves and related gamma values ​​of NGD with and without gate inversion doped regions according to this disclosure. Figure 8 shows an exemplary temperature coefficient comparison with reference voltage performance for NGD with and without gate inversion doped regions according to this disclosure. Figures 9A to 9F show cross-sectional views of several embodiments of NGD and corresponding FGD with gate inversion doped regions implemented according to this disclosure at various manufacturing stages. Figure 9G shows a different cross-sectional view of FGD of Figure 9F according to the present disclosure. Figure 9H shows a plan view of FGD 104 in relation to Figure 9G according to the present disclosure. Figure 10 illustrates a method for forming some embodiments of NGD including the gate inversion doped regions of Figures 9A to 9F according to the present disclosure. Implementation

[0007] This disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, the following description of forming a first component on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0009] Figure 1 illustrates schematic diagrams of some embodiments of a CMOS-only reference voltage circuit 100 according to this disclosure. As shown, the reference voltage circuit 100 may include a normal gate transistor device (NGD) 102 and a flipped gate transistor device (FGD) 104, their gate terminals connected together and connected to the drain terminal of the FGD 104. Furthermore, a first current source I1 may be present between a first voltage terminal (e.g., drain voltage VDD) and the drain terminal of the FGD 104. A second current source I2 may connect the source terminal of the NGD 102 to a second voltage terminal (e.g., ground reference or source voltage VSS). Embodiments of current sources I1 and I2 may include one or more transistors and / or other components, but these sources are not discussed in more detail herein. In some embodiments, a plurality of (e.g., N 1) FGD 104s may be coupled together in parallel, and a plurality of (e.g., N 2) NGD 102s may be coupled together in parallel, wherein the parallel elements may be coupled together at one or more of their gate, source and drain terminals.

[0010] In some embodiments, NGD 102 may be a standard or "regular" nMOS transistor device, which may include a p-doped (P+) substrate, an n-doped (N+) drain region and an N+ source region in the substrate, and an N+ polysilicon gate structure located above the substrate. Therefore, in the regular gate device NGD 102, the doping (e.g., implantation or diffusion) of the gate structure (N+) is opposite to the doping of the substrate (P+). FGD 104 may be an nMOS transistor device, which also includes a P+ substrate and an N+ drain region and an N+ source region in the substrate. However, FGD 104 also includes a "flipped" gate structure, which may include a P+ polysilicon gate having one or more inverted doped (N+) regions (e.g., at the lateral edges of the gate structure). Therefore, as used herein, the substrate and gate structure of FGD 104 have the same or similar doping (P+), and are therefore "flipped" compared to NGD 102. Moreover, as used in this paper, the source / drain region can refer to the source or drain individually or collectively, depending on the context.

[0011] In some embodiments, the reference voltage circuit 100 may utilize the difference in polysilicon work function between one or more NGD 102 and FGD 104 to establish a reference voltage Vref. Furthermore, in some embodiments, the reference voltage Vref may be determined by the current density I1 / N1 of one or more FGD 104 and the current density I2 / N2 of one or more NGD 102. Additionally, since the NGD 102 and FGD 104 operate within the subthreshold range of the reference voltage circuit 100, the subthreshold current ratio and associated standard deviation of the NGD 102 and FGD 104 may affect the accuracy of the reference voltage Vref. In some embodiments, the reference voltage Vref generated by the reference voltage circuit 100 may be specified as follows:

[0012]

[0013] Vt,FGD is the critical voltage of FGD 104, Vt,NGD is the critical voltage of NGD 102, n is the ideality factor (e.g., the quality factor or emission coefficient of the Shockley ideal diode equation), and VT is the thermal voltage (e.g., also from the Shockley ideal diode equation).

[0014] When operating NGD 102 and FGD 104 in the subcritical region, a phenomenon known as the "corner effect" can affect the performance (e.g., accuracy, precision, and / or thermal stability) of the reference voltage circuit 100. Generally, the corner effect is an enhancement of leakage current at the edge of the active region isolated by a shallow trench isolation (STI) structure in a CMOS transistor. In some cases, the corner effect may be affected by the presence of a "divot" feature typically associated with STI structures.

[0015] Figure 2 shows a cross-sectional view of some embodiments of a dielectric (STI) structure 204 having such a recessed feature 210 according to the present disclosure, as shown in NGD 102, which may adversely affect the performance of the reference voltage circuit 100. As shown in Figure 2, the dielectric structure 204 may be formed laterally toward a P-well region 206 of a substrate, on which a gate structure 202 and a dielectric layer (e.g., a gate oxide structure) 208 may be formed. In 90-nanometer (nm) technology and other low-cost processes, it may be difficult to control the presence, shape, size, and / or depth of the recessed feature 210. As a result, due to the greater control exerted by the gate structure 202 in the vicinity of the recessed feature 210, changes in the shape of the recessed feature 210 may cause a corresponding change (e.g., a decrease) in the critical voltage Vt of NGD 102, which may lead to the development of a "hump" effect.

[0016] Figure 3 shows a graph of the current-voltage (IV) curves 300 of the NGD 102, which can exhibit a hump effect 302 at different bias voltages Vb according to the present disclosure. The hump effect 302 is characterized by a decrease in the critical voltage Vt at a lower drain current Id. As shown in Figure 3, the hump effect 302 can become more pronounced or enhanced with the presence or increase of a reverse bias voltage (e.g., Vb = Xb, as shown in Figure 3, where, in some embodiments, Xb can be in the range of 0.5 volts (V) to 5.0 V). A decrease in the critical voltage Vt may result in a reduction in the accuracy and repeatability of the reference voltage Vref provided by the reference voltage circuit 100. Additionally, as shown in Figure 3, in some embodiments, the voltage X1 can range from 0.5 V to 5.0 V, and the current Y1 can range from 1 nanoampere (nA) to 1 milliampere (mA), where the critical voltage Vt is shown on a linear scale and the drain current Id is expressed on a logarithmic scale.

[0017] To address these issues, this disclosure provides embodiments of integrated circuit (IC) devices including NGD transistor elements (e.g., NGD 102) that include gate inversion-doped regions that may be disposed above the gate oxide or other dielectric layer and at the edge of the STI structure (e.g., in the P-well region). As used herein, an "inversion" doped (e.g., implanted) region can be a region that is doped opposite to the surrounding region in its particular material or structure. In some embodiments, as described in more detail below, the gate inversion-doped region can reduce the channel current in the subcritical region, thereby reducing the effect of the STI structure recess feature 210 and the associated hump effect 302, thereby improving the performance of the reference voltage circuit 100. Furthermore, in some embodiments, as described more fully below, the addition of the gate inversion-doped region may not require any additional process steps related to minimal changes in the circuit layout associated with the creation of the reference voltage circuit 100.

[0018] In the various embodiments discussed below, although the inversion region is referred to as the implantation region, other doping methods (e.g., diffusion) can be used to generate the inversion region, as well as other N+ and P+ regions mentioned below.

[0019] Figures 4A and 4B respectively show a layout view 400A and a cross-sectional view 400B of an NGD 102 including a gate inversion doped (e.g., implanted) region (e.g., P+ region) 410 according to this disclosure. More specifically, the location of the cross-sectional view 400B in Figure 4B is indicated by the dashed line shown in Figure 4A. As shown in Figure 4B, in some embodiments, the NGD 102 may include a substrate in which a deep N-well region 408 is located below a P-well region 206, which may be laterally surrounded by the N-well region 402. In some embodiments, the P-well region 206 may provide a semiconductor channel through which current can flow between an N+ source region (or a first N+ source-drain region) 404 and an N+ drain region (or a second N+ source-drain region) 406, as shown in Figures 4A and 4B. In some embodiments, the substrate may include silicon (Si) or another semiconductor material.

[0020] In some embodiments, a dielectric structure (e.g., a shallow trench isolation (STI) structure) 204 may be formed in the substrate at the P-well region 206. More specifically, in some embodiments, the dielectric structure 204 may be formed on the surface of the substrate and extend at least partially downward into the substrate. Furthermore, in some embodiments, the dielectric structure 204 may be located at the lateral perimeter of the P-well region 206 (e.g., along the N-well region 402), as shown in FIG4B. Additionally, the dielectric structure 204 may be disposed partially or entirely along the lateral perimeter of the P-well region 206. In some embodiments, the dielectric structure 204 may include silicon oxide (SiO x) (e.g., silicon dioxide (SiO 2)), or another oxide or dielectric material (e.g., silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric material, etc.).

[0021] In some embodiments, a dielectric layer (e.g., a gate oxide, such as silicon oxide (SiO₂) (e.g., silicon dioxide (SiO₂)), or another oxide or dielectric material, as described above) 208 may be disposed over the P-well region 206 and at least a portion of the dielectric structure 204 (e.g., on top of the P-well region 206 and at least a portion of the dielectric structure 204). In some embodiments, the side edges of the dielectric layer 208 may be located above the dielectric structure 204. Furthermore, an N+ (n-doped) gate structure 202 may be disposed over the dielectric layer 208 (e.g., on top of the dielectric layer 208). In some embodiments, as shown in FIG4B, the lateral extent of the N+ gate structure 202 substantially matches the lateral extent of the dielectric layer 208.

[0022] In some embodiments, at least one P+ (p-doped) region 410 may be disposed within the N+ gate structure 202 as an inversion doped region, as described above. As shown in Figures 4A and 4B, two P+ regions 410 may exist, with each P+ region 410 disposed above the dielectric structure 204 and the P-well region 206. In some embodiments, one side of the P+ region 410 may exist above the dielectric structure 204, while the opposite side of the P+ region 410 may exist above the P-well region 206 but not above the dielectric structure 204. Furthermore, in some embodiments, each P+ region 410 may extend along a corresponding laterally-facing side of the dielectric structure 204 perpendicular to the first N+ source-drain region 404 and the second N+ source-drain region 406 and between the first N+ source-drain region 404 and the second N+ source-drain region 406. More specifically, the first P+ region 410 may extend over the middle portion of the first side edge of the dielectric structure 204 perpendicular to the first and second ends of the dielectric layer 208, and the second P+ region 410 may extend over the middle portion of the second side edge of the dielectric structure 204 opposite to the first side edge. Furthermore, in some embodiments, the length of the middle portion of the first and second side edges of the dielectric structure 204 may be at least 75% of the length of the corresponding first and second side edges. However, in other embodiments, other percentages of the length of the middle portion relative to the first and second side edges of the dielectric structure 204 may be used (e.g., 50%, 55%, 60%, 65%, or greater than 75%). Additionally, as shown in FIG4B, the first and second side edges of the dielectric structure 204 may face each other through the central portion of the P-well region 206. Furthermore, in some embodiments, each P+ region 410 may be completely laterally surrounded by the N+ gate structure 202. Additionally, in some embodiments, each P+ region 410 may extend from the top surface to the bottom surface of the N+ gate structure 202. Moreover, in some embodiments, as shown in FIG4B, each P+ region 410 may be narrower than dielectric structure 204 in a plan view or layout diagram.

[0023] Although Figures 4A and 4B show each P+ region 410 having a specific depth, width, and length relative to other structures of NGD 102, other relative dimensions for each P+ region 410 are also possible in other embodiments.

[0024] Figure 5, through layout diagram 500A, illustrates an exemplary current flow in an NGD 102 affected by a gate inversion doped region (e.g., P+ region 410) according to this disclosure. As indicated, most of the current can flow between the first N+ source-drain region 404 and the second N+ source-drain region 406 via a channel in the P-well region 206 beneath the N+ gate structure 202. Therefore, the amount of leakage current that might pass through the recessed feature 210 at the edge of the dielectric structure 204 beneath the N+ gate structure 202 can be reduced or minimized by the presence of the P+ region 410, which can be used to suppress any such leakage current through the relevant portion of the dielectric structure 204. In some embodiments, the P+ region 410 can alter the work function of the polysilicon at the location of the N+ gate structure 202. This altered work function can cause an increase in the critical voltage Vt at these locations, thereby reducing the gap between the critical voltage Vt at P+ region 410 and the critical voltage Vt at other locations along dielectric structure 204 near the first N+ source-drain region 404 and the second N+ source-drain region 406, resulting in a reduced hump effect 302 and lower associated leakage current.

[0025] Therefore, in some embodiments, when used in the NGD 102 of the reference voltage circuit 100, the use of one or more P+ regions 410 can produce a more accurate and stable reference voltage Vref. As discussed below, this accuracy and stability may be related to the "gamma" value associated with the NGD 102. Generally, the gamma value is used to quantify how the critical voltage Vt, represented in the gate-source voltage Vgs, is affected by the source-substrate reverse bias Vb. More specifically, for our purposes, Figure 6 shows Figure 600 of an exemplary IV curve illustrating the gamma value, which can be used to quantify the effect of the hump effect 302 of the NGD 102 on the critical voltage Vt.

[0026] As described above, the hump effect 302 caused by the dip feature 210 may affect the critical voltage Vt or gate-source voltage Vgs at the corresponding drain current Id. Figure 6 shows two IV curves: the first curve shows various drain currents Id at the gate-source voltage Vgs at a bias voltage Vb = 0, and the second curve shows the drain current Id at the gate-source voltage Vgs at a non-zero bias voltage Vb = x. Given these two curves, two gamma values ​​are defined: gamma 1 601 and gamma 2 602, which can provide some insights into the impact of the hump effect 302 on the accuracy and precision of the reference voltage Vref of the resulting reference voltage circuit 100.

[0027] Gamma (γ) can be the difference between the gate-source voltage Vgs at a given drain current Id for two different biases (e.g., zero bias Vb = 0 (or Vb0) and a non-zero bias (e.g., Vb in the range of -5 V to -0.5 V)). Mathematically, gamma can be defined as follows:

[0028]

[0029] In the gamma equation, 2ϕf is the surface potential or contact potential. Assuming a surface potential of 0.65, in some embodiments, the gamma can be as follows:

[0030]

[0031] Furthermore, as shown in Figure 6, Gamma 1 601 is the gamma value at the drain current Id = A (e.g., in some embodiments, in the range of 10-500 nA), and Gamma 2 602 is the gamma value at the drain current Id = B (e.g., in some embodiments, in the range of 0.5-5 nA). In some embodiments, Gamma 1 601 is within the range of the gate-source voltage Vgs affected by the hump effect 302, while Gamma 2 602 is outside the range of the gate-source voltage Vgs affected by the hump effect 302. For example, the gamma value associated with the drain current Id = C (e.g., in some embodiments, in the range of 0.05-0.5 nA) can be substantially the same as Gamma 2 602. Therefore, by comparing the differences between gamma 1 601 and gamma 2 602 of two different NGD 102 (e.g., one with P+ region 410 used as a gate inversion region and the other without), a judgment can be made regarding the relative effectiveness of P+ region 410.

[0032] Figure 7 shows the IV curves and associated gamma values ​​of NGD 102 with and without gate inversion doping or implantation regions (e.g., P+ region 410, as shown in Figures 4A and 4B) according to this disclosure. The drain current of NGD 102 including P+ region 410 is denoted as Id', and the drain current of NGD 102 without P+ region 410 is denoted as Id. Therefore, in the visual review of Figure 7, due to the significant hump effect 302 applied at a non-zero bias, the IV curves Id (Vb=0) 701 and Id (Vb=x) 702 associated with NGD 102 without P+ region 410 result in gamma 1 (Id) being significantly larger than gamma 2 (Id), as mentioned above in conjunction with Figure 3. Conversely, the IV curves Id'(Vb=0)703 (e.g., substantially overlapping Id(Vb=0)701) and Id'(Vb=x)704 associated with NGD 102, including P+ region 410, result in gamma 1 (Id') being only slightly larger than gamma 2 (Id'), thus showing a significant improvement in the hump effect 302. Additionally, as shown in Figure 7, in some embodiments, the voltage X2 can range from 0.5 V to 5.0 V, and the current Y2 can range from 1 nanoampere (nA) to 1 milliampere (mA), where the gate-source voltage Vgs is shown on a linear scale and the drain current Id is shown on a logarithmic scale.

[0033] In view of the reduced hump effect 302, a more accurate and precise reference voltage Vref can be generated by a reference voltage circuit 100 including an NGD 102 with a P+ region 410. To this end, Figure 800 shows an illustrative temperature coefficient Tc comparison of reference voltage performance for NGD 102 with and without a gate inversion doped region (e.g., P+ region 410) according to this disclosure. More specifically, Figure 8 shows several measurement points of the reference voltage Vref at some reference temperatures Tref (e.g., 25 degrees Celsius (°C) or some other temperature) and the corresponding temperature coefficient Tc (e.g., in parts per million per degree Celsius (ppm / °C)), representing the rate of change of the reference voltage Vref at the reference temperature Tref. Qualitatively, the white test points, unrelated to the use of an inversion doped region, are generally further away from the zero temperature coefficient Tc than the shaded test points associated with the use of an inversion doped region, indicating greater variability of the reference voltage Vref with respect to temperature. Furthermore, the white test points are more dispersed in both the vertical and horizontal directions compared to the shaded test points, indicating that the reference voltage Vref and temperature coefficient Tc are more variable when no inversion doped region (e.g., P+ region 410) is used in the NGD 102 of the reference voltage circuit 100.

[0034] As shown in Figure 800, the measurement point distribution of the NGD 102 with and without the gate inversion doped region (e.g., P+ region 410) thus indicates a small median temperature coefficient Tc (e.g., close to zero), and both the standard deviation of the reference voltage Vref at the reference temperature Tref and the temperature coefficient Tc of the reference voltage Vref at that temperature are small. Therefore, using the inversion doped region is expected to improve the accuracy and precision of the reference voltage Vref provided by the reference voltage circuit 100.

[0035] Additionally, while the use of an NGD 102 with an inversion-doped region (e.g., P+ region 410) is discussed herein with respect to a reference voltage circuit 100, in other embodiments such an NGD 102 may be employed outside the environment of the reference voltage circuit 100 to provide advantages related to reducing current leakage caused by the recessed features of the shallow trench isolation structure.

[0036] Figures 9A to 9F show cross-sectional views of some embodiments of an IC device including an NGD 102 and a corresponding FGD 104 with gate inversion doped regions (e.g., P+ regions 410) implemented at multiple manufacturing stages according to this disclosure. Although Figures 9A to 9F are described as a series of actions, it should be understood that these actions are not limiting, as the order of actions within each series may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some actions shown and / or described may be omitted in whole or in part.

[0037] For example, FIG9A illustrates a substrate 901 having doped (e.g., implanted or diffused) regions, including but not limited to a deep N-well region 408 on which a P-well region 206 is formed. As described in conjunction with FIGS9B to 9F, the left-handed P-well region 206 may form part of an FGD 104, while the right-handed P-well region 206 may form part of an NGD 102, as described above. Additionally, the substrate 901 may also include one or more N-well regions 402 that separate the respective P-well regions 206 from each other. In some embodiments, the respective regions of the substrate 901 may be formed by multiple implantation operations performed on relevant portions of the substrate 901. For example, in some embodiments, the deep N-well region 408 may be formed using implantation via the lower surface of the substrate 901, and the P-well regions 206 and N-well regions 402 may be formed using implantation via the upper surface of the substrate 901. In some embodiments, the substrate 901 may include silicon (Si) and / or other semiconductor materials.

[0038] Figure 9B illustrates trenches 902 formed (e.g., photolithography and associated etching) in the upper surface of the P-well region 206 of the substrate 901. In some embodiments, one or more trenches 902 may be formed within each P-well region 206 (e.g., adjacent to the N-well region 402). Furthermore, in some embodiments, each trench 902 may extend partially into its corresponding P-well region 206 (e.g., less than or equal to half). Additionally, as shown in Figures 4A and 4B, each trench 902 may be located at the lateral periphery of the upper surface of the corresponding P-well region 206.

[0039] Figure 9C illustrates the formation (e.g., deposition) of a dielectric material (e.g., silicon oxide (SiO₂), such as silicon dioxide (SiO₂), or another oxide or dielectric material) to produce one or more dielectric structures (e.g., shallow trench isolation (STI) structures) 204. Thus, the dielectric structure 204 can take the form of the trench 902 of Figure 9B, extending partially into the corresponding P-well region 206. Additionally, in some embodiments, each dielectric structure 204 can be located at a lateral periphery on the upper surface of the corresponding P-well region 206. Furthermore, in some embodiments, after depositing the dielectric material and after producing the dielectric structure 204, the P-well region 206, the N-well region 402, and the upper surface of the dielectric structure 204 can be planarized (e.g., using chemical mechanical planarization (CMP)).

[0040] Figure 9D illustrates the formation (e.g., deposition) of a dielectric layer 208 over the upper surface (e.g., on top) of the P-well region 206, the N-well region 402, and the dielectric structure 204. In some embodiments, a single dielectric layer 208 may be formed over multiple P-well regions 206, as shown in Figure 9D. As described more fully below, the dielectric layer 208 may form a gate oxide (e.g., silicon oxide (SiO₂), such as silicon dioxide (SiO₂), or another oxide or dielectric material) for the gate structure of each transistor device associated with each P-well region 206.

[0041] Figure 9E illustrates the formation (e.g., deposition) of a conductive layer (e.g., polysilicon or another metal and / or conductive material) on a dielectric layer 208, followed by the formation (e.g., doping, such as by implantation or diffusion) of various P+ and N+ regions within the conductive layer to produce, for example, an N+ gate structure 202 (e.g., for NGD 102) and a P+ gate structure 910 (e.g., for FGD 104), as well as a P+ region 410 (e.g., for NGD 102) and an N+ region 912 (e.g., for FGD 104). As described above, the P+ region 410 can be used as an inversion doped or implanted region, while the N+ region 912 can be used to provide a self-aligned n-doped source-drain region for FGD 104 (not explicitly shown in Figure 9E). In some embodiments, the n-type dopant used for the N+ gate structure 202 and the N+ region 912 may include arsenic (As), phosphorus (P), or another n-type dopant material. In addition, in some embodiments, the p-type dopant used for the P+ gate structure 910 and the P+ region 410 may include boron (B), boron trifluoride (BF3), or another p-type dopant material.

[0042] In some embodiments, assuming both p-type and n-type regions are used in both NGD 102 and FGD 104, the injection of P+ region 410 can be performed simultaneously with other P+ regions (e.g., the P+ gate structure 910 of FGD 104, or the P+ source-drain region of a pMOS transistor element not shown or discussed herein). Therefore, in some embodiments, P+ region 410 can be generated without adding any additional IC manufacturing steps.

[0043] Figure 9F illustrates the formation (e.g., photolithography and associated etching) of various trenches 914 (e.g., the region above the N-well region 402) to form the gate and associated dielectric (e.g., gate oxide) structures of NGD 102 and FGD 104. In some embodiments, the P+ gate structure 910 and N+ gate structure 202 are electrically connected together for use in a reference voltage circuit 100. In some embodiments, the formation of additional structures (e.g., additional dielectric layers, conductive (e.g., metallic) vias, conductive (e.g., metallic) layers, etc. (not shown in Figure 9F)) may occur after the formation of the trenches 914.

[0044] Figure 9G shows different cross-sectional views of the FGD 104 according to this disclosure, as indicated by the dashed arrows in Figure 9H. Furthermore, Figure 9H shows a plan view of the FGD 104, indicating the cross-section of Figure 9G. As shown, the N+ region 912 may be disposed along each upper edge of the P+ gate structure 910. In some embodiments, the N+ region 912 may be formed simultaneously with the first N+ source-drain region 404 and the second N+ source-drain region 406 (e.g., to facilitate the self-aligned formation of the first N+ source-drain region 404 and the second N+ source-drain region 406 of the FGD 104, as mentioned above). Furthermore, in some embodiments, as shown in Figures 9G and 9H, the N+ region 912 may extend along the entire P+ gate structure 910, the first N+ source-drain region 404, and / or the second N+ source-drain region 406.

[0045] Figure 10 illustrates a method 1000 for forming an IC device including an NGD 102 according to some embodiments of the present disclosure, the NGD 102 including the gate inversion doped (e.g., implanted) regions of Figures 9A to 9F (e.g., for reference voltage circuit 100). Although this and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, these actions may be performed in a different order than shown, and / or may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0046] At action 1002, for example, a substrate (e.g., substrate 901) including a P-well region (e.g., P-well region 206) may be provided. Figure 9A shows a cross-sectional view corresponding to some embodiments of action 1002.

[0047] At action 1004, at least one trench (e.g., trench 902 in FIG. 9B) may be formed in the upper surface of the P-trap region. FIG. 9B shows a cross-sectional view corresponding to some embodiments of action 1004.

[0048] At action 1006, a dielectric structure (e.g., dielectric structure 204 in FIG. 9C) may be formed in the trench. As described above, in some embodiments, the dielectric structure and the P-well region may be planarized (e.g., by CMP) after the dielectric structure is formed. FIG. 9C shows a cross-sectional view corresponding to some embodiments of action 1006.

[0049] At action 1008, a dielectric layer (e.g., dielectric layer 208 in FIG. 9D) may be formed over the P-well region and the dielectric structure. FIG. 9D shows a cross-sectional view corresponding to some embodiments of action 1008.

[0050] At action 1010, an N+ gate structure (e.g., N+ gate structure 202 in FIG. 9E) may be formed over the dielectric layer. Furthermore, at action 1012, at least one P+ region (e.g., P+ region 410 in FIG. 9E) may be formed in the N+ gate structure, wherein the at least one P+ region may be located over the P-well region and the dielectric structure. FIG. 9E shows cross-sectional views corresponding to some embodiments of actions 1010 and 1012. In some embodiments, the formation of the dielectric layer, the N+ gate structure, and at least one P+ region may also involve selective removal of material, as shown in FIG. 9F, to form individual NGD 102s including inversion-doped regions, as described in detail above.

[0051] Some embodiments relate to an integrated circuit (IC) device. The device includes: a substrate including a P-well region and a dielectric structure located at a surface of the substrate, extending downward into the substrate, and at a lateral perimeter of the P-well region; a dielectric layer located above the P-well region and laterally extending above the dielectric structure; and an N+ gate structure located above the dielectric layer and including at least one P+ region above the P-well region of the substrate and the dielectric structure.

[0052] In some embodiments, the N+ gate structure comprises an N+ polycrystalline silicon structure. In some embodiments, the dielectric layer comprises at least one of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), or undoped silicate glass (USG). In some embodiments, the dielectric structure is integrally disposed along the lateral perimeter of the P-well region. In some embodiments, the substrate further comprises: a first N+ source-drain region located near a first end of the dielectric layer, and a second N+ source-drain region located near a second end of the dielectric layer opposite to the first end. In some embodiments, at least one P+ region includes: a first P+ region extending above a middle portion of a first side edge of a dielectric structure, the first side edge being perpendicular to a first end and a second end of the dielectric layer; and a second P+ region extending above a middle portion of a second side edge of the dielectric structure, the second side edge being opposite to the first side edge. In some embodiments, the middle portion of the first side edge of the dielectric structure includes at least 75% of the length of the first side edge; and the middle portion of the second side edge of the dielectric structure includes at least 75% of the length of the second side edge. In some embodiments, the first side edge of the dielectric structure faces the central portion of the P-well region of the substrate; and the second side edge of the dielectric structure faces the first side edge of the dielectric structure. In some embodiments, at least one P+ region is completely laterally surrounded by an N+ gate structure. In some embodiments, at least one P+ region extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0053] Some embodiments relate to another type of IC device. The device includes a reference voltage circuit comprising a flip-gate element (FGD) and a normal gate element (NGD). The FGD includes a first P-well region located in a substrate; a first N+ source-drain region and a second N+ source-drain region located within the first P-well region; and a P+ gate structure located above the first P-well region and between the first N+ source-drain region and the second N+ source-drain region in a plan view of the IC device. The P+ gate structure includes a first N+ region aligned side-by-side with the first N+ source-drain region in a plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in a plan view. The NGD includes a second P-well region located in a substrate; a third N+ source-drain region and a fourth N+ source-drain region located in the second P-well region; and an N+ gate structure located above the second P-well region and between the third N+ source-drain region and the fourth N+ source-drain region in a plan view. The N+ gate structure includes at least one P+ region extending between the third N+ source-drain region and the fourth N+ source-drain region in a plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

[0054] In some embodiments, the reference voltage circuit further includes: a first current source coupling a first voltage terminal to the drain terminal of the FGD; and a second current source coupling a source terminal of the NGD to a second voltage terminal, wherein the source terminal provides a reference voltage. In some embodiments, at least one P+ region is located above a second P-well region disposed in the substrate and a dielectric structure disposed on the surface of the substrate, extending downward into the substrate, and located at the lateral perimeter of the P+ well region. In some embodiments, the NGD further includes: a dielectric layer located between the second P-well region and the N+ gate structure; wherein a third N+ source-drain region is located near a first end of the dielectric layer; wherein a fourth N+ source-drain region is located near a second end of the dielectric layer opposite to the first end; and wherein at least one P+ region includes: a first P+ region extending above a middle portion of a first side edge of the dielectric structure, the first side edge being perpendicular to the first and second ends of the dielectric layer; and a second P+ region extending above a middle portion of a second side edge of the dielectric structure, the second side edge being opposite to the first side edge. In some embodiments, the first side edge of the dielectric structure faces the central portion of the second P-well region of the substrate; and the second side edge of the dielectric structure faces the first side edge of the dielectric structure. In some embodiments, at least one P+ region is completely surrounded laterally by the N+ gate structure and extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0055] Some embodiments relate to a method. The method includes: providing a substrate including a P-well region; forming a trench in a top surface of the P-well region; forming a dielectric structure in the trench; forming a dielectric layer over the P-well region and the dielectric structure; forming an N+ gate structure over the dielectric layer; and implanting at least one P+ region in the N+ gate structure, the at least one P+ region being located over the P-well region and the dielectric structure.

[0056] In some embodiments, the method further includes: implanting a first N+ source-drain region in a substrate near a first end of the dielectric layer; and implanting a second N+ source-drain region in a substrate near a second end of the dielectric layer opposite to the first end, wherein implanting at least one P+ region includes: implanting the first P+ region to extend over a middle portion of a first side edge of the dielectric structure between the first and second ends of the dielectric layer; and implanting the second P+ region to extend over a middle portion of a second side edge of the dielectric structure opposite to the first side edge. In some embodiments, the method further includes simultaneously implanting a P+ region of a gate structure separate from the N+ gate structure while implanting at least one P+ region in the N+ gate structure. In some embodiments, each of the first P+ region and the second P+ region is completely laterally surrounded by the N+ gate structure and extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

[0057] It should be understood that in this written description and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used for convenience in describing and distinguishing different elements in a figure or series of figures. In themselves, these terms do not imply any temporal order or structural proximity of these elements, and are not intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with the first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in embodiments not shown.

[0058] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

[0059] 100: Reference Voltage Circuit 102: Standard gate transistor element / NGD 104: Flip-gate transistor / FGD 202: Gate Structure 204: Dielectric Structure 206: P-well region 208: Dielectric layer 210: Depression feature 300: Curve 302: Camel Hump Effect 400A, 500A: Layout Diagram 400B: Sectional View 402: N-well region 404: N+ source region / First N+ source-drain region 406: N+ drain region / Second N+ source-drain region 408: Deep N-well region 410:P+ area 600, 700, 800: Figure 601: Gamma 1 602: Gamma 2 701:I d(V b=0) 702:I d(V b=x) 703:I d'(V b=0) 704:I d'(V b=x) 901: Base 902, 914: Ditches 910: P+ gate structure 912: N+ area 1000: Method 1002~1012: Actions I 1: Current source / First current source I 2: Current source / Second current source VDD: Drain voltage V ref: Reference voltage

Claims

1. An integrated circuit device, comprising: The substrate includes a P-well region and a dielectric structure, wherein the dielectric structure is located on the surface of the substrate, extends downward into the substrate, and is located at the lateral perimeter of the P-well region; A dielectric layer is located above the P-well region and extends laterally above the dielectric structure; and an N+ gate structure is located above the dielectric layer and includes at least one P+ region located above the P-well region on the substrate and the dielectric structure, wherein the at least one P+ region is completely surrounded laterally by the N+ gate structure.

2. The integrated circuit arrangement as claimed in claim 1, wherein the dielectric structure is disposed integrally along the lateral perimeter of the P-well region.

3. The integrated circuit device as claimed in claim 1, wherein the substrate further comprises: The first N+ source-drain region is located near the first end of the dielectric layer; And a second N+ source-drain region, located near the second end of the dielectric layer opposite to the first end.

4. The integrated circuit arrangement as claimed in claim 1, wherein the at least one P+ region comprises: The first P+ region extends above the middle portion of the first side edge of the dielectric structure, and the first side edge is perpendicular to the first end and the second end of the dielectric layer. And a second P+ region, extending above the middle portion of the second side edge of the dielectric structure, the second side edge being opposite to the first side edge.

5. An integrated circuit device, comprising: A reference voltage circuit includes: a flip-gate element, including: a first P-well region located in a substrate; a first N+ source-drain region and a second N+ source-drain region located in the first P-well region; and a P+ gate structure located above the first P-well region, situated between the first N+ source-drain region and the second N+ source-drain region in a plan view of the integrated circuit arrangement, the P+ gate structure including a first N+ region aligned side-by-side with the first N+ source-drain region in the plan view and a second N+ region aligned side-by-side with the second N+ source-drain region in the plan view; and a regular gate element, including: a second P-well region located in the substrate; A third N+ source-drain region and a fourth N+ source-drain region are located within the second P-well region; and an N+ gate structure is located above the second P-well region, situated between the third N+ source-drain region and the fourth N+ source-drain region in the plan view, the N+ gate structure including at least one P+ region extending between the third N+ source-drain region and the fourth N+ source-drain region in the plan view, wherein the N+ gate structure is electrically connected to the P+ gate structure.

6. The integrated circuit arrangement as claimed in claim 5, wherein the reference voltage circuit further comprises: A first current source couples a first voltage terminal to the drain terminal of the flip-gate element; And a second current source, which couples the source terminal of the normal gate element to a second voltage terminal, wherein the source terminal provides a reference voltage.

7. A method of forming an integrated circuit device, comprising: Provide a substrate including the P-well region; A trench is formed on the upper surface of the P-well region; A dielectric structure is formed in the trench; A dielectric layer is formed above the P-well region and the dielectric structure; An N+ gate structure is formed above the dielectric layer; and at least one P+ region is formed in the N+ gate structure, the at least one P+ region being located above the P-well region and the dielectric structure, wherein implanting the at least one P+ region includes: implanting a first P+ region to extend between the first end and the second end of the dielectric layer above a middle portion of a first side edge of the dielectric structure. And inject a second P+ region to extend above the middle portion of the second side side opposite to the first side side of the dielectric structure, wherein each of the first P+ region and the second P+ region is completely surrounded laterally by the N+ gate structure.

8. The method as described in claim 7, further comprising: A first N+ source-drain region is implanted in the substrate near the first end of the dielectric layer; And a second N+ source-drain region is implanted in the substrate near the second end of the dielectric layer opposite to the first end.

9. The method as described in claim 8, further comprising: While injecting the at least one P+ region into the N+ gate structure, a P+ region of a gate structure separate from the N+ gate structure is also injected.

10. The method of claim 8, wherein each of the first P+ region and the second P+ region extends from the top surface of the N+ gate structure to the bottom surface of the N+ gate structure.

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