Projection image correction system and projection image correction method

Abstract

The projection image correction system includes a state control circuit and a data output circuit. The state control circuit sends a read request to the first memory to obtain first pixel information when no read request corresponding to the interpolation operation has been sent to the first memory, stores the first pixel information in a second memory, and counts the number of read requests sent to the first memory to generate a first count value. The data output circuit counts according to a write completion signal to generate a second count value, and when the second count value is the same as the first count value, obtains multiple second pixel information pieces used for the interpolation operation from the second memory and provides them to the interpolation device to perform the interpolation operation. The write completion signal indicates that the first pixel information has been stored in the second memory, and that the multiple second pixel information pieces include the first pixel information.

Description

Technical Field

[0001] This case relates to a projection image correction system, and in particular to a projection image correction system and method having a cache memory mechanism that can continuously receive and send read requests. Prior Technology

[0002] Projected images displayed by projectors often exhibit distortion (e.g., trapezoidal distortion). To correct these distortions, projection image correction systems typically obtain neighboring pixel information of the distorted image region for interpolation calculations, thereby correcting the distorted area. In existing technologies, line buffers or general-purpose cache control mechanisms are used to implement the data access mechanism of the projection image correction system. Line buffer setups require significant storage space and hardware costs to temporarily store pixel information used for image correction; while general-purpose cache setups only allow one read / write operation per cycle on a single cache line, and the next read / write request can only be processed after the previous one is completed. This results in the projection image correction system spending a considerable amount of time on data access, leading to significantly poor overall processing efficiency. Summary of the Invention

[0003] In some embodiments, one of the objectives of this invention is to provide a projection image correction system and projection image correction method with a cache memory mechanism that can continuously receive and send read requests, so as to improve the shortcomings of the prior art.

[0004] In some embodiments, the projection image correction system includes a state control circuit and a data output circuit. The state control circuit sends at least one read request to a first memory when no read request corresponding to an interpolation operation has been sent to a first memory, to obtain at least one first pixel information from the first memory, stores the at least one first pixel information in a second memory, and counts the number of times the at least one read request has been sent to the first memory to generate a first count value. The data output circuit counts according to at least one write completion signal to generate a second count value, and when the second count value is the same as the first count value, obtains a plurality of second pixel information to be used in the interpolation operation from the second memory and sends it to an interpolation device, so that the interpolation device performs the interpolation operation based on the plurality of second pixel information. The at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and that the plurality of second pixel information includes the at least one first pixel information.

[0005] In some embodiments, projection image correction performed by the projection image correction system includes the following operations: when at least one read request corresponding to an interpolation operation has not been sent to a first memory, the at least one read request is sent to the first memory to obtain at least one first pixel information from the first memory and store the at least one first pixel information to a second memory in the projection image correction system; the number of times the at least one read request is sent to the first memory is counted to generate a first count value; counting is performed according to at least one write completion signal to generate a second count value; and when the second count value is the same as the first count value, a plurality of second pixel information to be used in the interpolation operation is obtained from the second memory and given to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

[0006] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Simple Explanation of the Diagram

[0007] [Figure 1] is a schematic diagram of a projection image correction system according to some embodiments of this case; [Figure 2] is a schematic diagram of the memory in Figure 1 drawn according to some embodiments of this case; [Figure 3] is a schematic diagram of the state control circuit of Figure 1 according to some embodiments of this case; [Figure 4] is a schematic diagram of the reordering operation of the data sorting circuit of Figure 1 according to some embodiments of this case; [Figure 5] is a schematic diagram of the data output circuit of Figure 1 drawn according to some embodiments of this case; [Figure 6A] is a flowchart illustrating the first part of the operation of the projection image correction system of Figure 1 performing an interpolation operation according to some embodiments of this case; [Figure 6B] is a flowchart illustrating the second part of the operation of the projection image correction system of Figure 1 performing this interpolation operation according to some embodiments of the present invention; [Figure 7] is a timing diagram illustrating the execution of multiple read requests by the projection image correction system of Figure 1 according to some embodiments of this case; and [Figure 8] is a schematic diagram of a projection image correction method according to some embodiments of this case. Implementation

[0008] All terms used herein have their common meanings. The definitions of the terms mentioned above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not limit the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0009] As used herein, "coupling" or "connection" can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or moving together. As used herein, the term "circuit" can refer to a device in which at least one transistor and / or at least one active or passive component are connected in a certain manner to process signals.

[0010] Figure 1 is a schematic diagram of a projection image correction system 100 according to some embodiments of this invention. In some embodiments, the projection trapezoidal correction device 101 may output an address request signal add_req to the projection image correction system 100 based on an image correction algorithm (e.g., but not limited to, interpolation correction) performed on the distorted image, so that the projection image correction system 100 may provide all pixel information (hereinafter referred to as a plurality of second pixel information) to the interpolation device 102 for performing one interpolation operation, so that the interpolation device 102 may perform the interpolation operation based on the plurality of second pixel information, thereby correcting the distortion in the projection image.

[0011] The projection image correction system 100 includes an address decoding circuit 110, a memory 120, a confirmation circuit 130, a data sorting circuit 140, a first-in-first-out (FIFO) circuit 150, a status control circuit 160, a data output circuit 170, and a data writing circuit 180. The address decoding circuit 110 can receive an address request signal add_req from the projection keystone correction device 101, decode the address request signal add_req to obtain multiple address signals AddXX, and transmit these address signals AddXX to the memory 120.

[0012] Memory 120 includes memory banks 122, 124, 126, and 128. In some embodiments, memory banks 122, 124, 126, and 128 can store multiple pixel information of the original image data DIN in a preset order. For example, memory 120 is further coupled to memory 103 via data writing circuit 180, wherein memory 103 stores multiple original pixel information of the original image data DIN. Memory 120 can obtain the original image data DIN from memory 103 via data writing circuit 180 and store multiple original pixel information of the original image data DIN into memory banks 122, 124, 126, and 128 in a preset order. This will be explained later with reference to FIG2.

[0013] The verification circuit 130 can read multiple pixel information (hereinafter referred to as a plurality of third pixel information) from memory banks 122, 124, 126, and 128 according to the address signals AddXX. In some embodiments, memory 103 is dynamic random access memory, and memory 120 is static random access memory. The verification circuit 130 can verify whether each of the plurality of third pixel information meets a preset condition. For example, each third pixel information includes a tag value and a valid value. The verification circuit 130 compares the tag value of a corresponding one of the plurality of third pixel information with a target tag value TT to verify whether the tag value of the corresponding one is the same as the target tag value TT, and to verify whether the valid value of the corresponding one is a preset value. If the tag value of the corresponding one is the same as the target tag value and the valid value of the corresponding one is a preset value, the verification circuit 130 can verify that the corresponding one of the plurality of third pixel information meets the preset condition (equivalent to a read hit). Alternatively, if the tag value of the corresponding entity differs from the target tag value and / or the valid value of the corresponding entity is not the preset value, the verification circuit 130 can confirm that the corresponding entity of the plurality of third pixel information does not meet the preset condition (equivalent to a read miss). Similarly, the verification circuit 130 can confirm whether each of the plurality of third pixel information meets the preset condition.

[0014] In some embodiments, the aforementioned valid value is used to indicate whether the corresponding third pixel information is in a valid state (e.g., an available state). For example, when the valid value is a first logic value, the corresponding third pixel information is in a valid state; conversely, when the valid value is a second logic value, the corresponding third pixel information is in an invalid state and cannot be used for interpolation operations. In some embodiments, the address decoding circuit 110 can decode the address request signal add_req to obtain the aforementioned target tag value TT, and provide this target tag value TT to the confirmation circuit 130. In some embodiments, the confirmation circuit 130 can be implemented by a comparator circuit, but this invention is not limited thereto.

[0015] Data sorting circuit 140 is coupled to confirmation circuit 130 and, based on the confirmation result of confirmation circuit 130 (e.g., a read miss result), determines that memory 120 is missing at least one first pixel information and issues at least one read request Req to obtain the at least one first pixel information from memory 103 via status control circuit 160. The missing at least one first pixel information in memory 120 corresponds to at least one of the plurality of third pixel information that does not meet the aforementioned preset conditions. In addition, based on the confirmation result of confirmation circuit 130, data sorting circuit 140 further reorders each of the plurality of third pixel information that meets the aforementioned preset conditions and at least one first address signal (which corresponds to the aforementioned at least one first pixel information) among the plurality of address signals AddXX, and outputs the reordered each of the plurality of third pixel information that meets the aforementioned preset conditions and the at least one first address signal to first-in-first-out circuit 150. This will be explained later with reference to FIG4.

[0016] When at least one read request Req has not been sent to memory 103, the state control circuit 160 sends the at least one read request Req to memory 103 to obtain the at least one first pixel information from memory 103 and store the at least one first pixel information in memory 120. During this process, the state control circuit 160 also counts the number of times the at least one read request Req is sent to memory 103 to generate a count value CT1. The configuration of the state control circuit 160 will be described later with reference to FIG3.

[0017] Specifically, the state control circuit 160 sends at least one read request Req to the data writing circuit 180. The data writing circuit 180 can obtain at least one first address signal (which indicates the position information of the at least one first pixel information in the original image data DIN) based on the at least one read request Req, thereby reading the at least one first pixel information from the memory 103. Accordingly, the data writing circuit 180 can store the at least one first pixel information in the memory 120 and send at least one write completion signal SC to the data output circuit 170, wherein the at least one write completion signal SC is used to indicate that the at least one first pixel information has been stored in the memory 120. Accordingly, the data output circuit 170 can count according to at least one write completion signal SC to generate another count value (e.g., the count value CT2 in FIG5), and when the count value CT2 is the same as the count value CT1, within the same time period, obtain the plurality of second pixel information (which includes the aforementioned at least one first pixel information and each of the plurality of third pixel information that meets the aforementioned preset conditions) required to perform one interpolation operation from the memory 120 and the data sorting circuit 140 (via the first-in-first-out circuit 150). In this way, the data output circuit 170 can output the plurality of second pixel information to the interpolation device 102 to perform interpolation operation, thereby correcting the projected image.

[0018] Figure 2 is a schematic diagram of the memory 120 in Figure 1 drawn according to some embodiments of this case. As mentioned above, the memory banks 122, 124, 126, and 128 of the memory 120 can store multiple raw pixel information of the original image data DIN in a preset order. For example, based on the coordinate positions in the original image data DIN, multiple raw pixel information can be stored in memory banks 122, 124, 126, and 128 in the order of even rows and even columns, even rows and odd columns, odd rows and even columns, and odd rows and odd columns (i.e., the aforementioned preset order). Each piece of raw pixel information stored in the memory 120 can include a tag value, a valid value, and a pixel data value. Memory banks 122, 124, 126, and 128 can be accessed independently. In some related technologies, the projection image correction system can only read multiple pixel data sequentially from memory within multiple cycles, resulting in low overall processing efficiency. Unlike the aforementioned related technologies, with the above-described configuration, the projection image correction system 100 can obtain multiple pixel information from memory banks 122, 124, 126, and 128 within the same time cycle, thereby performing interpolation operations more efficiently.

[0019] Figure 3 is a schematic diagram of the state control circuit 160 of Figure 1 according to some embodiments of this invention. In some embodiments, the state control circuit 160 records at least one sent request Rreq and compares at least one read request Req with at least one sent request Rreq to confirm whether at least one read request Req has not been sent to memory 103. For example, as shown in Figure 3, the state control circuit 160 includes a controller 310, a register 320, a register 330, and a first-in-first-out circuit 340. The controller 310 receives at least one read request Req and at least one write completion signal SC. The register 320 stores information related to at least one sent request Rreq (which may be, for example, but is not limited to, the location information of the pixel information that the at least one sent request Rreq wants to access). The controller 310 can compare whether the received at least one read request Req is the same as the at least one sent request Rreq in the register 320. If at least one read request Req is the same as at least one sent request Rreq, it means that at least one read request Req has been sent to memory 103 by data write circuit 180. Under this condition, controller 310 will not send at least one read request Req to memory 103 again.

[0020] On the other hand, if at least one read request Req is different from at least one sent request Rreq, it means that at least one read request Req has not been sent to memory 103 by data write circuit 180. Under this condition, controller 310 will send at least one read request Req to memory 103 via data write circuit 180. For example, when at least one read request Req is different from at least one sent request Rreq, controller 310 can send at least one read request Req to FIFO circuit 340, thereby sending at least one read request Req to data write circuit 180 via FIFO circuit 340, and sending the at least one read request Req to memory 103 via data write circuit 180. At the same time, controller 310 will store at least one read request Req in register 320 to update at least one sent request Rreq (that is, record at least one read request Req as one of at least one sent request Rreq), and count the number of times the at least one read request Req is sent to memory 103 to generate a count value CT1. The temporary register 330 is used to store the count value CT1.

[0021] In some embodiments, the data sorting circuit 140 sends a flag signal (not shown) simultaneously with the last read request in at least one read request Req, thereby informing the controller 310 that the last read request corresponding to one interpolation operation has been sent. Accordingly, after the count value CT1 has been transmitted to the data output circuit 170, the controller 310 can reset the count value CT1 to 0 according to this flag signal, in preparation for counting the number of times the at least one read request Req corresponding to the next interpolation operation has been sent. In some embodiments, the controller 310 may be implemented via a microcontroller circuit or a digital signal processing circuit capable of executing a state machine, but this invention is not limited thereto.

[0022] In other embodiments, the state control circuit 160 may include more registers (not shown) for storing at least one first pixel information, allowing the data output circuit 170 to directly retrieve the first pixel information from these registers (rather than from memory 120). This reduces the waiting time for the data output circuit 170 to retrieve the first pixel information, thereby further improving overall data access efficiency.

[0023] Figure 4 is a schematic diagram illustrating the reordering operation of the data sorting circuit 140 of Figure 1 according to some embodiments of this invention. In some embodiments, each of the plurality of address signals Addxx may further include offset information. If the confirmation circuit 130 confirms that the third pixel information read from the memory 120 meets the preset conditions (i.e., read hit), the data sorting circuit 140 may read the corresponding number of bits from the pixel data value of the third pixel information according to the offset information corresponding to the third pixel information and reorder them. Alternatively, if the confirmation circuit 130 confirms that the third pixel information read from the memory 120 does not meet the preset conditions (i.e., read miss), the data sorting circuit 140 may reorder at least one address signal corresponding to the third pixel information that does not meet the preset conditions. In detail, the confirmation circuit 130 can retrieve one third pixel information from memory banks 122, 124, 126, and 128 within the same time period based on address signals Addxx corresponding to an address request signal add_req. The corresponding pixels are located in even-row, even-column, even-row, even-column, odd-row, and odd-row, odd-column positions in the original image data DIN, respectively. However, during interpolation, the positions of these pixels are classified as top-left, top-right, bottom-left, and bottom-right corners on the mapped coordinates. The reordering performed by the data sorting circuit 140 is to complete the aforementioned position transformation.

[0024] As shown in Figure 4, the third pixel information read from memory bank 122 is labeled as pixel information EE, the third pixel information read from memory bank 124 is labeled as pixel information EO, the third pixel information read from memory bank 126 is labeled as pixel information OE, and the third pixel information read from memory bank 128 is labeled as pixel information OO. These are arranged in a preset order: even rows, even columns; even rows, odd columns; odd rows, even columns; and odd rows, odd columns. During the reordering process, pixel information EE, pixel information EO, pixel information OE, and pixel information OO are rearranged according to the mapping coordinates of their corresponding pixels into top-left information UL, top-right information UR, bottom-left information DL, and bottom-right information DR, and then input to the first-in-first-out circuit 150 accordingly.

[0025] It should be understood that if pixel information OO, pixel information OE, pixel information EO, and pixel information If the corresponding pixel information in [EE] meets the aforementioned preset conditions, the content of the corresponding pixel information is the corresponding number of bits in the aforementioned pixel data value. Conversely, if the corresponding pixel information does not meet the aforementioned preset conditions (i.e., read miss), the content of the corresponding pixel information is... [This refers to] the address signal corresponding to the corresponding pixel information (i.e., the aforementioned at least one first address signal). In other words, the reordered data contains address signals corresponding to unread pixel information and read pixel information. Thus, the data output circuit 170 can, in subsequent operations, read the previously unread pixel information (i.e., at least one first pixel information) from the memory 120 based on the address signal, and read the corresponding number of bits from the pixel data value, replacing the data portion of the corresponding address signal in the reordered data with these bits, thereby providing the interpolation device 102 with multiple second pixel information required to perform this interpolation operation.

[0026] Figure 5 is a schematic diagram of the data output circuit 170 of Figure 1 according to some embodiments of this invention. The data output circuit 170 includes a counter 510, a first-in-first-out (FIFO) circuit 520, and an output circuit 530. The counter 510 receives at least one write completion signal SC from the data write circuit 180 and counts the received at least one write completion signal SC to generate a count value CT2. The FIFO circuit 520 receives the count value CT1 from the state control circuit 160. The output circuit 530 obtains the count value CT1 from the first-in-first-out circuit 520, and when the count value CT2 is the same as the count value CT1 (equivalent to at least one read request Req corresponding to an address request signal add_req being sent to memory 103, and memory 120 having completed obtaining all the missing at least one first pixel information from memory 103), it obtains at least one first pixel information from memory 120 and obtains each of the at least one first address signal and the plurality of third pixel information that meet the preset condition from the data sorting circuit 140 after reordering, and replaces the content of at least one first address signal with at least one first pixel information, thereby outputting each of the at least one first pixel information and the plurality of third pixel information that meet the preset condition as the plurality of second pixel information to provide the pixel information required by the interpolation device 102 to perform the interpolation operation.

[0027] Figure 6A is a flowchart illustrating the first part of the operation of the projection image correction system 100 of Figure 1 performing an interpolation operation according to some embodiments of this invention, and Figure 6B is a flowchart illustrating the second part of the operation of the projection image correction system 100 of Figure 1 performing the interpolation operation according to some embodiments of this invention. In operation S605, the self-projection trapezoidal correction device 101 receives an address request signal add_req. In operation S610, the address decoding circuit 110 decodes the address request signal add_req to obtain multiple address signals AddXX. For example, as shown in Figures 2 and 4, the third pixel information stored in memory banks 122, 124, 126, and 128 are pixel information EE, pixel information EO, pixel information OE, and pixel information OO, respectively. The address decoding circuit 110 can decode the address request signal add_req according to the pixel mapping coordinate relationship of the original image data DIN to obtain multiple address signals AddXX, where XX can correspond to the aforementioned multiple pixel information EE, EO, OE, and OO. For example, address signal AddEE can represent a corresponding storage address in memory bank 122, address signal AddEO can represent a corresponding storage address in memory bank 124, address signal AddOE can represent a corresponding storage address in memory bank 126, and address signal AddOO can represent a corresponding storage address in memory bank 128.

[0028] Referring again to Figure 6A, in operation S615, the verification circuit 130 reads a plurality of third pixel information from memory banks 122, 124, 126, and 128 according to the address signals AddXX. In operation S620, the verification circuit 130 verifies whether each of the plurality of third pixel information meets a preset condition (i.e., whether a read hit occurs), selectively generating a first or second verification result. If it meets the condition, the verification circuit 130 generates a first verification result to indicate that the third pixel information meets the preset condition; if it does not meet the condition, the verification circuit 130 generates a second verification result to indicate that the third pixel information does not meet the preset condition. In operation S625, the data sorting circuit 140 determines at least one missing first pixel information in memory 120 based on the second verification result of the verification circuit 130 and issues at least one read request Req accordingly, wherein the at least one first pixel information corresponds to each of the plurality of third pixel information that does not meet the preset condition. In operation S630, the data sorting circuit 140 reorders at least one first address signal corresponding to at least one first pixel information and each of the plurality of third pixel information that meets the preset condition in the plurality of address signals AddXX (as shown in FIG4), and transmits the reordered at least one first address signal and each of the plurality of third pixel information that meets the preset condition to the first-in-first-out circuit 150.

[0029] Referring to Figure 6B, in operation S635, the state control circuit 160 confirms whether the at least one read request Req has been sent to the memory 103, and if the at least one read request Req has not been sent to the memory 103, it sends the at least one read request Req to the memory 103 via the data writing circuit 180. In operation S640, the state control circuit 160 counts the number of times the at least one read request Req is sent to the memory 103 to generate a count value CT1. In operation S645, the data writing circuit 180 reads at least one first pixel information from the memory 103 according to the at least one read request Req, stores the read at least one first pixel information in the memory 120, and sends at least one write completion signal SC.

[0030] In operation S650, the data output circuit 170 counts according to at least one write completion signal SC to generate a count value CT2. When the count value CT2 is the same as the count value CT1, it reads at least one first pixel information from the memory 120 and reads at least one reordered first address signal and each of the plurality of third pixel information that meets the preset condition from the first-in-first-out circuit 150. It then replaces at least one first address signal with at least one first pixel information, so that each of the plurality of reordered third pixel information that meets the preset condition and at least one first pixel information are output as the plurality of second pixel information used by the interpolation device 102 to perform an interpolation operation.

[0031] The descriptions of the above operations can be found in the foregoing embodiments, and therefore will not be repeated here. The above operations are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation methods and scope of the embodiments of this case, these operations may be appropriately added, replaced, omitted, performed in a different order, or performed simultaneously or partially simultaneously.

[0032] Figure 7 is a timing diagram illustrating the execution of multiple read requests by the projection image correction system 100 of Figure 1 according to some embodiments of this invention. In some embodiments, the state control circuit 160 may temporarily store at least one read request Req of a preset number (greater than 1) via the first-in-first-out circuit 340, thereby enabling the continuous reception of multiple read requests (corresponding to at least one read request Req) and the continuous transmission of multiple read requests to the memory 103. Equivalently, the projection image correction system 100 can achieve continuous and partially parallel data access to reduce the impact of the latency Td of reading pixel information from the memory 120.

[0033] In some related technologies, the projection image correction system needs to process one read request (i.e., read the required pixel information from the cache in response to a read request) before it can process the next read request. This significantly reduces the overall processing efficiency. Unlike the aforementioned related technologies, as shown in Figure 7, the state control circuit 160 can continuously receive and send multiple read requests, thereby improving the overall processing efficiency.

[0034] Figure 8 is a schematic diagram of a projection image correction method 800 according to some embodiments of this invention. In some embodiments, the projection image correction method 800 may be performed by, but is not limited to, the projection image correction system 100 of Figure 1.

[0035] In operation S810, when at least one read request corresponding to an interpolation operation has not been sent to a first memory, the at least one read request is sent to the first memory to obtain at least one first pixel information from the first memory and store the at least one first pixel information in a second memory of the projection image correction system. In operation S820, the number of times the at least one read request is sent to the first memory is counted to generate a first count value. In operation S830, counting is performed according to at least one write completion signal to generate a second count value. In operation S840, when the second count value is the same as the first count value, a plurality of second pixel information to be used in the interpolation operation is obtained from the second memory and given to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

[0036] The description of the above-described projection image correction method 800 can be found in the foregoing embodiments, and therefore will not be repeated here. The above-described operations are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this invention, these operations may be appropriately added, replaced, omitted, performed in a different order, or performed simultaneously or partially simultaneously.

[0037] In summary, the projection image correction system and method provided in some embodiments of this case can realize the operation mode of continuously receiving read requests and sending read requests to memory, improve the efficiency of memory access to data and reduce the time loss of read data miss, thereby improving the overall system processing efficiency.

[0038] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make variations to the technical features of this case based on the express or implied content of this case. All such variations may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0039] 100: Projection Image Correction System 101: Projection trapezoidal correction device 102: Interpolation device 103: Memory 110: Address decoding circuit 120: Memory 122, 124, 126, 128: Memory bank 130: Confirmation Circuit 140: Data sorting circuit 150: First-In-First-Out (FIFO) circuit 160: State control circuit 170: Data Output Circuit 180: Data writing circuit 310: Controller 320, 330: Temporary registers 340, 520: First-In-First-Out (FIFO) circuit 510: Counter 530: Output Circuit 800: Projection Image Correction Method add_req: Address request signal AddXX: Address Signal CT1, CT2: Count values DIN: Original image data DL: Information in the lower left corner DR: Information in the bottom right corner EE: Pixel News EO: Pixel News OE: Pixel Information OO: Pixel News Req: at least one read request Rreq: At least one request has been sent. S605, S610, S615, S620, S625, S630, S635, S640, S645, S650: Operation S810, S820, S830, S840: Operation SC: At least one write completion signal TT: Target label value Td: Delay time UL: Top left corner information UR: Top right corner information

Claims

1. A projection image correction system, comprising: a state control circuit that sends at least one read request to the first memory when at least one read request corresponding to an interpolation operation has not been sent to the first memory, to obtain at least one first pixel information from the first memory, stores the at least one first pixel information to a second memory, and counts the number of times the at least one read request is sent to the first memory to generate a first count value; and a data output circuit that counts according to at least one write completion signal to generate a second count value, and when the second count value is the same as the first count value, obtains a plurality of second pixel information to be used in the interpolation operation from the second memory and sends it to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

2. The projection image correction system of claim 1, wherein the state control circuit is further configured to record at least one sent request and compare the at least one read request with the at least one sent request to confirm whether the at least one read request has not been sent to the first memory.

3. The projection image correction system of claim 1, wherein the state control circuit comprises: a first register storing at least one sent request; a second register storing the first count value; a first-in-first-out circuit that sends the at least one read request to the first memory; and a controller that compares the at least one read request with the at least one sent request to confirm whether the at least one read request has not been sent to the first memory, sends the at least one read request to the first-in-first-out circuit when the at least one read request is different from the at least one sent request, stores the at least one read request in the first register to update the at least one sent request, and counts the number of times the at least one read request is sent to the first memory to generate the first count value.

4. The projection image correction system of claim 1, wherein the data output circuit comprises: a counter for counting the at least one write completion signal to generate the second count value; a first-in-first-out circuit for receiving the first count value from the state control circuit; and an output circuit for obtaining the first count value from the first-in-first-out circuit and reading the plurality of second pixel information from the second memory when the second count value is the same as the first count value.

5. The projection image correction system of claim 1 further includes: a data writing circuit that reads the at least one first pixel information from the first memory according to the at least one read request, writes the at least one first pixel information to the second memory, and sends the at least one write completion signal accordingly.

6. The projection image correction system of claim 1, wherein the second memory includes a plurality of memory libraries, and the plurality of memory libraries store a plurality of original pixel information in an original image data in a preset order, the plurality of original pixel information including the at least one first pixel information.

7. The projection image correction system of claim 1 further comprises: an address decoding circuit, which decodes a received address request signal to obtain a plurality of address signals, and reads a plurality of third pixel information from a plurality of memory banks in the second memory according to the plurality of address signals; a confirmation circuit, which confirms whether each of the plurality of third pixel information meets a preset condition; and a data sorting circuit, which determines that the second memory is missing at least one first pixel information when at least one of the plurality of third pixel information does not meet the preset condition and issues the at least one read request accordingly, and reorders each of the plurality of third pixel information that meets the preset condition and at least one first address signal, wherein the at least one first address signal is the plurality of address signals corresponding to the at least one of the plurality of third pixel information that does not meet the preset condition.

8. The projection image correction system of claim 7, wherein each of the plurality of third pixel information includes a label value and a valid value, and if the valid value of one of the plurality of third pixel information is a preset value and the label value of the corresponding one is the same as a target label value, the confirmation circuit confirms that the corresponding one meets the preset condition.

9. The projection image correction system of claim 7 further includes: a first-in-first-out circuit that receives from the data sorting circuit each of the reordered plurality of third pixel information that meets the preset condition and the at least one first address signal, wherein the data output circuit further replaces the reordered at least one first address signal with the at least one first pixel information, and outputs each of the reordered plurality of third pixel information that meets the preset condition and the at least one first pixel information as the plurality of second pixel information.

10. A projection image correction method, performed by a projection image correction system, the projection image correction method comprising: issuing at least one read request to the first memory when no read request corresponding to an interpolation operation has been sent to the first memory, to obtain at least one first pixel information from the first memory, and storing the at least one first pixel information to a second memory in the projection image correction system; counting the number of times the at least one read request is sent to the first memory to generate a first count value; counting according to at least one write completion signal to generate a second count value; and when the second count value is the same as the first count value, obtaining a plurality of second pixel information to be used in the interpolation operation from the second memory and providing it to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

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