Package structure and manufacturing method thereof

Abstract

A packaging structure includes a substrate, an intermediate module, a chip module, and a first package. The intermediate module is disposed on the substrate. The chip module is disposed on the intermediate module. The chip module is electrically connected to the substrate through the intermediate module. The first package encapsulates the chip module and the intermediate module and directly contacts the substrate. The bottom surface of the first package is coplanar with the top surface of the substrate. A method for manufacturing the packaging structure is also provided.

Description

Technical Field

[0001] This invention relates to a packaging structure and its manufacturing method. Prior Technology

[0002] With the advancement of technology, the market demands for electronic products are increasing. For example, ensuring that the packaging structure has good quality has become a current research topic. Summary of the Invention

[0003] This invention provides a packaging structure and its manufacturing method, which effectively improves the yield and thus ensures good quality.

[0004] A packaging structure of the present invention includes a substrate, an intermediate module, a chip module, and a first package. The intermediate module is disposed on the substrate. The chip module is disposed on the intermediate module. The chip module is electrically connected to the substrate through the intermediate module. The first package encapsulates the chip module and the intermediate module and directly contacts the substrate. The bottom surface of the first package is coplanar with the top surface of the substrate.

[0005] A method for manufacturing a packaging structure according to the present invention includes at least providing a substrate; providing a cut-to-size intermediate module; disposing the intermediate module on the substrate; providing a wafer module; disposing the wafer module on the intermediate module such that the wafer module is electrically connected to the substrate through the intermediate module; and forming a first package to encapsulate the wafer module and the intermediate module and to directly contact the substrate.

[0006] In one embodiment of the present invention, after forming the first package described above, a planarization process is further performed to expose the top surface of the wafer module.

[0007] In one embodiment of the present invention, after the first package is formed, the order-cutting process is not performed.

[0008] In one embodiment of the present invention, the above-described manufacturing method further includes: joining the intermediate module and the substrate through a plurality of first conductive terminals; joining the wafer module and the intermediate module through a plurality of second conductive terminals; and covering the plurality of first conductive terminals and the plurality of second conductive terminals respectively with a first protective member and a second protective member.

[0009] In one embodiment of the present invention, the first protective member and the second protective member are formed by performing an adhesive dispensing process or a film lamination process, respectively.

[0010] In one embodiment of the present invention, the second protective member is formed before the aforementioned wafer module is disposed on the intermediate module, or the second protective member is formed after the wafer module is disposed on the intermediate module.

[0011] In one embodiment of the present invention, the first protective member and / or the second protective member described above are part of the first package.

[0012] In one embodiment of the present invention, the steps of forming the above-mentioned intermediate module include: placing a plurality of bridging chips on a carrier board; forming a second package to encapsulate the plurality of bridging chips; removing the carrier board; and performing a dicing process.

[0013] In one embodiment of the present invention, the first package body described above exposes a portion of the substrate.

[0014] In one embodiment of the present invention, the intermediate module is disposed on the substrate before the wafer module is disposed on the intermediate module.

[0015] Based on the above, since the number of process steps that the chip module goes through can be reduced, the risk of defect rate in the process can be reduced. At the same time, based on the protection of the package, the overall structural strength can be improved. Accordingly, the yield of the package structure of the present invention is effectively improved, thereby ensuring its good quality.

[0016] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0017] Figures 1A to 1G are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to an embodiment of the present invention. Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are partial cross-sectional schematic diagrams of the packaging structure according to some embodiments of the present invention. Implementation

[0018] The directional terms used in this article (e.g., up, down, right, left, front, back, top, bottom) are used for reference only and are not intended to imply absolute orientation.

[0019] Unless otherwise expressly stated, no method described herein is intended to be construed as requiring its steps to be performed in a particular order.

[0020] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness, dimensions, or size of layers or regions in the drawings are enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be described again in the following paragraphs.

[0021] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part.

[0022] Unless otherwise stated, the term "between" used in this specification to define numerical ranges is intended to cover the range equal to and between the endpoint values. For example, a size range between a first value and a second value means that the size range can cover the first value, the second value, and any value between the first value and the second value.

[0023] Figures 1A to 1G are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to an embodiment of the present invention. Referring to Figures 1A to 1E, the manufacturing process of the intermediate module 110 may include the following steps. First, a carrier 10 is provided. In some embodiments, the carrier 10 is, for example, a plate made of glass, wafer, metal or other suitable support material, so that the carrier 10 can be used to carry films or components formed thereon.

[0024] In this embodiment, a release layer 11 may optionally be formed on the carrier plate 10 to improve the releaseability of the structure (such as an intermediate structure in the process) and the carrier plate 10 in subsequent processes. For example, the release layer 11 may be a light-to-heat-conversion (LTHC) release layer or other suitable release layer, and the present invention is not limited thereto.

[0025] Next, a layered structure 111 is formed on the carrier 10. In this embodiment, the layered structure 111 is a single-layer structure. For example, the layered structure 111 can be an insulating layer deposited from polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or similar materials. However, the invention is not limited to this. In embodiments not shown, the layered structure 111 can be a suitable redistribution layer (RDL) structure, wherein the top and bottom layers of the RDL structure are insulating layers deposited from polyimide, polybenzoxazole, benzocyclobutene, or similar materials. Furthermore, multiple openings 111a can be formed in the layered structure 111 by a suitable method (such as an etching process).

[0026] Then, as shown in FIG1A, a plurality of bridging chips 112 are disposed on the carrier 10. In this embodiment, the bridging chip 112 has an active surface AS and a back surface BS opposite to the active surface AS, and the bridging chip 112 is disposed on the layered structure 111 with the active surface AS facing upward. For example, the back surface BS of the bridging chip 112 is attached to the layered structure 111 by an adhesive layer 12, and the adhesive layer 12 can directly contact the top surface of the layered structure 111.

[0027] In one embodiment, the adhesive layer 12 may be a die attach film (DAF). However, the invention is not limited thereto, and in other embodiments, the bridging wafer 112 may be configured on the carrier 10 in other ways. Furthermore, the bridging wafer 112 may be any suitable wafer type.

[0028] After configuring multiple bridging chips 112, a package 113 is formed to encapsulate the multiple bridging chips 112 (e.g., in direct contact with the silicon substrate of the bridging chips 112). In one embodiment, the package 113 may be formed by the following steps. First, a packaging material is formed to cover the conductive bumps 112a of the bridging chips 112, wherein the conductive bumps 112a may be disposed on pads 112b and surrounded by an insulating layer 112c. Next, the packaging material is planarized to form the package 113, so that the top surface of the package 113 may be substantially coplanar with the top surface of the conductive bumps 112a, but the invention is not limited thereto. Here, the package 113 is, for example, a second package.

[0029] In Figure 1A, a plurality of conductive connectors 114 may also be formed on the carrier 10, wherein the plurality of conductive connectors 114 may correspond to the plurality of openings 111a of the layered structure 111 and surround the bridging wafer 112, wherein the plurality of conductive connectors 114 and the plurality of openings 111a are arranged, for example, in a one-to-one manner. Furthermore, the top surfaces of the conductive connectors 114, the top surfaces of the package 113, and the top surfaces of the conductive bumps 112a may be substantially coplanar, but the present invention is not limited thereto.

[0030] In some embodiments, the conductive connector 114 may be made of copper, aluminum, nickel, or a combination thereof, and may be a conductive post formed, for example, by lithography, plating, or photoresist stripping. However, the invention is not limited thereto, and the conductive connector 114 may be formed of other suitable materials and forming methods depending on the actual design requirements.

[0031] In one embodiment, the conductive connector 114 is formed before the plurality of bridging wafers 112 are disposed and the package 113 is formed. In another embodiment, the conductive connector 114 is formed after the plurality of bridging wafers 112 are disposed and before the package 113 is formed. In yet another embodiment, the conductive connector 114 is formed after the plurality of bridging wafers 112 are disposed and the package 113 is formed.

[0032] Referring again to FIG1A, a wiring layer 115 is formed on the carrier 10 (for example, in direct contact with the package 113 and the conductive connector 114). In this embodiment, the wiring layer 115 may be a multilayer structure. For example, the wiring layer 115 may include multiple dielectric layers 115a stacked on top of each other and multiple patterned conductive layers 115b, wherein the patterned conductive layers 115b may reconfigure the conductors for signal transmission used in the package.

[0033] In some embodiments, the material of the dielectric layer 115a may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, polyimide, benzocyclobutene, and may be formed, for example, by spin-on coating, chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0034] In some embodiments, the material of the patterned conductive layer 115b may include copper, aluminum, nickel, gold, silver, tin, or a combination thereof, and may be formed, for example, by sputtering, vapor deposition, electroless plating, or electroplating. However, the invention is not limited thereto, and the dielectric layer 115a and the patterned conductive layer 115b may be formed by other suitable materials and forming methods according to actual design requirements.

[0035] Referring to Figure 1B, after forming the circuit layer 115, another carrier 20 and another release layer 21 are bonded to the circuit layer 115, wherein optionally a portion of the circuit layer 115 can be embedded in the release layer 21. Next, the carrier 10 is removed through the release layer 11 to expose the bottom surface 111b of the layered structure 111 and the bottom surface 114b of the conductive connector 114, wherein the carrier 20 and the release layer 21 are similar to the carrier 10 and the release layer 11, and will not be described again here. Here, exposure to a UV laser can be used to peel the release layer 11 and the carrier 10 away from the layered structure 111 and the conductive connector 114.

[0036] Referring to Figure 1C, flip the structure shown in Figure 1B vertically so that multiple bridging chips 112, packages 113, and conductive connectors 114 are displayed as disposed on the circuit layer 115. Then, multiple connection terminals 116 are formed on the bottom surface 114b of the conductive connectors 114 and the bottom surface 111b of the layered structure 111.

[0037] For example, as shown in FIG1C, the connection terminal 116 includes a plurality of conductive terminals 116a and a plurality of dummy terminals 116b, wherein the conductive terminals 116a can directly contact and be electrically connected to the conductive connector 114, while the dummy terminals 116b can directly contact and be electrically insulated from the layered structure 111. Here, the dummy terminal 116b can be a dummy bump. By designing these dummy terminals 116b, in embodiments where terminals are manufactured using an electroplating process, the terminals on the entire plane to be electroplated can be more evenly distributed, resulting in a more uniform electroplating current distribution. Consequently, the height of the terminals formed will also be more uniform, thus achieving good terminal co-planarity. Alternatively, the design of these dummy terminals 116b can disperse stress, preventing stress caused by thermal expansion coefficient (CTE) mismatch from acting entirely on the functional conductive terminal 116a under conditions of high and low temperature changes during subsequent component operation and / or temperature differences during reliability testing. This effectively improves the product's lifespan and performance, and also enhances the product's performance during reliability testing. However, the present invention is not limited to these limitations.

[0038] Referring to Figure 1D, after the connection terminal 116 is formed, the carrier 20 is removed through the release layer 21 to expose the other surface of the circuit layer 115 opposite to the surface on which the bridging wafer 112 is disposed. Here, exposure to a UV laser can be used to peel the release layer 21 and the carrier 20 away from the circuit layer 115.

[0039] Referring to Figure 1E, a singulation process is then performed to obtain multiple intermediate modules 110 (single-segment type), wherein the singulation process can be performed by a rotating blade or a laser beam. After performing the singulation process and before bonding to the substrate 120, inspection and testing steps can be performed on the singled intermediate modules 110 to reduce the probability that poor quality will adversely affect the subsequently bonded wafer modules 130, but the present invention is not limited thereto.

[0040] Referring to FIG1F, a substrate 120 is provided, and an intermediate module 110 (single-chip type) is disposed on the substrate 120. Next, a chip module 130 is disposed on the intermediate module 110, such that the chip module 130 is electrically connected to the substrate 120 through the intermediate module 110. In this embodiment, the chip module 130 is, for example, composed of multiple individual chiplets (FIG. 1F schematically illustrates three chips 131). Here, the three chips 131 may have the same or different functions depending on the actual design requirements; this invention is not limited thereto. For example, the chip 131 may be a logic chip, a memory chip, or a combination thereof.

[0041] In this embodiment, a plurality of external terminals 121 are further formed on the surface of the substrate 120 relative to the intermediate module 110 (such as the bottom surface) to connect with other components in subsequent processes (such as electrical connection or dummy connection).

[0042] In Figure 1F, the intermediate module 110 and the substrate 120 can be connected via multiple conductive terminals 116a and dummy terminals 116b, and the wafer module 130 and the intermediate module 110 can be connected via multiple conductive terminals 130a. The wafer module 130 is electrically connected to the substrate 120 via conductive terminals 130a, the circuit layer 115 in the intermediate module 110, the conductive connector 114 in the intermediate module 110, and the conductive terminals 116a. Here, the conductive terminal 116a is, for example, a first conductive terminal, and the conductive terminal 130a is, for example, a second conductive terminal.

[0043] It should be noted that both the conductive terminal 116a and the dummy terminal 116b are in direct contact with the top metal layer of the substrate 120 to achieve the effect of stress dispersion. The portion of the top metal layer to which the conductive terminal 116a is connected is a functional pad, which allows it to be electrically connected to the functional external terminal 121 below. The portion of the top metal layer to which the dummy terminal 116b is connected is a dummy pad, which prevents it from being electrically connected to the functional external terminal 121 below, or allows it to be connected to the dummy external terminal 121 below. However, the present invention is not limited to this.

[0044] In one embodiment, before bonding the intermediate module 110, an inspection and testing step may be performed on the substrate 120 to reduce the probability that its poor quality will adversely affect the subsequent bonding of the chip module 130 thereon, but the invention is not limited thereto.

[0045] In one embodiment, there is a gap between adjacent wafers 131 in the wafer module 130 and signal transmission can be performed by bridging wafers 112, but the present invention is not limited thereto.

[0046] In some embodiments, substrate 120 may be an ABF substrate or the like. However, it should be noted that the number of dielectric layers and conductive circuit design (such as vias) of substrate 120 in FIG1F are only schematic illustrations. The present invention does not limit the type of substrate 120. As long as substrate 120 can provide the signal transmission function required in the product, it falls within the protection scope of the present invention.

[0047] Referring to Figure 1G, a package 140 is formed to encapsulate the chip module 130 and the intermediate module 110 and directly contact the substrate 120. For example, the bottom surface 140b of the package 140 may be coplanar with the top surface 120t of the substrate 120. Here, the package 140 is, for example, a first package. Furthermore, the package 113 and the package 140 may be formed by a molding process using a liquid molding compound or a granule-type solid molding compound.

[0048] After the above-described process, the fabrication of the packaging structure PKG1 in this embodiment is largely complete. Since the chip module 130 is not initially placed on the wafer-level interposer module 110, and most of the processes in the packaging structure PKG1 have already been completed when it is placed, the number of process steps traversed by the chip module 130 can be reduced, lowering its yield loss risk during the process. Simultaneously, the overall structural strength can be improved based on the protection of the package 140. Therefore, the yield of the packaging structure PKG1 in this embodiment is effectively improved, thereby ensuring its good quality. Here, the wafer-level interposer module 110 is, for example, the uncut interposer module 110 shown in FIG. 1D.

[0049] Furthermore, when placing wafers on large-scale interposers at the wafer level without wafer dicing, warpage or surface unevenness is likely to occur. On the other hand, the conductive terminals on the wafer may not be effectively aligned with the underlying interposer, resulting in higher process risk and more difficult yield control. However, with the process step design shown in Figures 1A to 1G, the fine-pitch wafer bonding process can be limited to a smaller area (the size of the interposer module 110 in the wafer dicing type), thus providing a wider process tolerance / margin and reducing the probability of the aforementioned problems occurring.

[0050] In this embodiment, the package 140 covers the connection terminal 116 (including conductive terminal 116a and dummy terminal 116b) and the conductive terminal 130a, so that the connection terminal 116 (including conductive terminal 116a and dummy terminal 116b) and the conductive terminal 130a are recessed within the package 140. Furthermore, as shown in FIG1G, the protective element covering the connection terminal 116 (including conductive terminal 116a and dummy terminal 116b) and the conductive terminal 130a can be part of the package 140. In this way, protection can be provided simultaneously for components such as the intermediate module 110, the wafer module 130, and the connection terminal 116 (including conductive terminal 116a and dummy terminal 116b) and the conductive terminal 130a, thus significantly reducing material costs. However, the present invention is not limited to this.

[0051] In one embodiment, after forming the package 140, a planarization process is further performed, such as chemical-mechanical polishing (CMP), mechanical grinding process, or the like, to expose the top surface 130t of the wafer module 130 in the package 140, and to make the top surface 130t of the wafer module 130 coplanar with the top surface 140t of the package 140. In this way, the heat dissipation capacity of the wafer module 130 can be improved. Due to the design of the package 140, the wafer module 130 does not need to be pre-thinned. The thickness in the stacking direction (Z direction) can be effectively reduced in one step through the aforementioned planarization process, and the thickness can be more accurately controlled within the required range. However, the present invention is not limited to this.

[0052] In one embodiment, the thickness 140T of the package 140 is equal to the vertical distance from the top surface 130t of the wafer module 130 to the top surface 120t of the substrate 120, but the present invention is not limited thereto.

[0053] In one embodiment, after the package 140 is formed, no cut-off process is performed. Therefore, the package 140 can have different dimensions from the substrate 120. For example, the outer sidewall 140s of the package 140 can be located between the outer sidewall 110s of the intermediate module 110 and the outer sidewall 120s of the substrate 120. That is, the package 140 will expose a portion of region A on the substrate 120 to facilitate the subsequent configuration of other components. However, the present invention is not limited to this.

[0054] In one embodiment, since the package 113 of the intermediate module 110 is exposed after the cut-off process, the package 140 formed in this step can physically cover part of the package 113 of the intermediate module 110 (e.g., in direct contact). However, the present invention is not limited to this. In other embodiments, the package 140 can be the package 113 of the intermediate module 110 that indirectly covers it, such as by sandwiching other films or components therein.

[0055] In one embodiment, the chip module 130 is composed of multiple individual chips 131. Since the cost of chips 131 is relatively high, a probe card test can be performed on the chips 131 before they are placed on the intermediate module 110 to select known good dies (KGD). This avoids the situation where damage to some chips 131 in the chip module 130 causes other chips 131 to malfunction. However, the invention is not limited to this. Here, a known good die can be a semiconductor chip that has been tested, inspected, and passed in terms of functionality and reliability, and is known to achieve all designed properties and operating states after a power supply potential is applied.

[0056] In one embodiment, the substrate 120 may have a groove (not shown) formed on its top surface 120t (such as the green paint of the top insulating layer) during the manufacturing process, and the package 140 may be filled into the groove to improve the adhesion between the package 140 and the substrate 120 and reduce the probability of peeling, but the present invention is not limited thereto.

[0057] In some embodiments, the conductive bump 112a, the connecting terminal 116, and the conductive terminal 130a may each comprise a conductive post, a conductive plug solder ball, or a combination thereof, made of materials such as copper or the like. The solder balls may be formed by a ball placement process and / or a reflow process, but the invention is not limited thereto. In some alternative embodiments, the conductive bump 112a, the connecting terminal 116, and the conductive terminal 130a may use other possible forms or shapes based on design requirements, and may have the same or different appearances from each other.

[0058] In some embodiments, the encapsulation 113 and encapsulation 140 may be formed of insulating materials such as epoxy resin or other suitable resins. For example, they may be molding compounds formed by a molding process. However, the invention is not limited thereto; the encapsulation 113 and encapsulation 140 may be formed of other suitable materials and methods, and may have the same or different forms.

[0059] It must be noted that the following embodiments use the component references and some contents of the above embodiments, wherein the same or similar references are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the foregoing embodiments. The following embodiments will not repeat the description.

[0060] Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13 are partial cross-sectional schematic diagrams of the packaging structure according to some embodiments of the present invention.

[0061] Referring to Figure 2, in this embodiment, the packaging structure PKG2 is similar to the packaging structure PKG1, except that: the connecting terminal 116 (including the conductive terminal 116a and the dummy terminal 116b) is covered by a protective element 151A, and the conductive terminal 130a is covered by a protective element 152A. The protective elements 151A and 152A are formed before the packaging body 140 is formed. In other words, the protective elements 151A and 152A in this embodiment are not part of the packaging body 140.

[0062] Furthermore, as shown in Figure 2, the materials of protective element 151A and protective element 152A are different. For example, the material of protective element 151A is selected from capillary bottom filler material (CUF), while the material of protective element 152A is selected from non-conductive film (NCF). For example, in Figure 2, since the capillary bottom filler material is formed by performing a dispensing process, it fills the gap between the connecting terminals 116 by means of the fluidity of the adhesive and capillary phenomenon, and also overflows upward to form on the sidewall of the intermediate module 110. Therefore, protective element 151A has a trapezoidal profile. On the other hand, since the non-conductive film is formed by performing a film lamination process, before the wafer module 130 is bonded to the intermediate module 110, the conductive terminals 130a on the wafer 131 are first attached to the sheet-like dry film material, and then the flip-chip bonding of the wafer 131 is performed by heat and pressure. At the same time, the conductive terminals 130a are protected by the protective member 152A. Therefore, the flip-chip bonding method when using the non-conductive film is thermal compression bond (TCB). The protective member 152A can form an arc-shaped edge caused by the compression of the dry film material, and in this way, it will not cover the sidewall of the wafer 131 (e.g., the upper half). That is, based on the selection of different materials, the protective member 151A and the protective member 152A can have different shapes, but the present invention is not limited to this.

[0063] In one embodiment, the capillary bottom filler material and the non-conductive film can each have their advantages under different circumstances. For example, when there is a high aspect ratio between the wafers 131, such as large wafer size and / or small spacing between wafers 131 (e.g., 50 micrometers to 150 micrometers), the capillary bottom filler material can easily cover the sidewalls between the wafers 131 and have a large area of ​​contact with the substrate material (e.g., silicon) in the wafers 131. As a result, poor adhesion, trapped voids, and / or insufficient strength of the capillary bottom filler material itself can easily occur between the capillary bottom filler material and the substrate material, which may lead to adverse effects such as delamination and cracking during reliability testing, reducing product reliability. In this case, the non-conductive film has its advantages because it can avoid the aforementioned risks. On the other hand, since it is difficult for non-conductive films to cover higher conductive terminals, when the height of the conductive terminal 130a after the bonding of the wafer 131 is high (e.g., greater than 40 micrometers), the capillary bottom filling material has its advantages. Therefore, the present invention does not limit the material of the protective component, which can be determined according to the actual design requirements.

[0064] In this embodiment, the use of a non-conductive film between the wafer 131 and the intermediate module 110 can reduce the size of the intermediate module 110. However, the present invention is not limited to this. In other embodiments, when the non-conductive film is used between the intermediate module 110 and the substrate 120, the size of the substrate 120 can be reduced.

[0065] Referring to Figure 3, in this embodiment, the packaging structure PKG3 is similar to the packaging structure PKG2, except that: the protective element 151B is selected from a non-conductive film, while the protective element 152B is selected from a capillary underfill material. Therefore, the protective element 151B has an arc-shaped edge, while the protective element 152B has a trapezoidal contour. Furthermore, in this embodiment, the flip-chip bonding method using the capillary underfill material can be to first place the wafer 131 in position, then bond it through reflow, and then form the capillary underfill material through a dispensing process. That is, the protective element 152B can be formed after the wafer module 130 is bonded to the intermediate module 110. In addition, in this embodiment, because the spacing between the wafers 131 is small, the capillary effect is more significant. Therefore, the protective elements 152B between the wafers 131 will rise higher than the protective elements 152B on both sides, but the invention is not limited to this.

[0066] Referring to Figure 4, in this embodiment, the encapsulation structure PKG4 is similar to the encapsulation structures PKG2 and PKG3, except that: a protective element 151B selected from a non-conductive film is used to cover the connecting terminal 116, and a protective element 152A selected from a non-conductive film is used to cover the conductive terminal 130a.

[0067] Referring to Figure 5, in this embodiment, the packaging structure PKG5 is similar to the packaging structures PKG2 and PKG3, except that: a protective element 151A selected from the capillary bottom filling material is used to cover the connecting terminal 116, and a protective element 152B selected from the capillary bottom filling material is used to cover the conductive terminal 130a.

[0068] Referring to Figure 6, in this embodiment, the encapsulation structure PKG6 is similar to the encapsulation structures PKG1 and PKG3, except that: the encapsulation body 140 is used to cover the connecting terminal 116, and the protective element 152B selected from the capillary bottom filling material is used to cover the conductive terminal 130a.

[0069] Referring to Figure 7, in this embodiment, the encapsulation structure PKG7 is similar to the encapsulation structures PKG1 and PKG2, except that: a protective element 151A selected from the capillary bottom filling material is used to cover the connecting terminal 116, and an encapsulation body 140 is used to cover the conductive terminal 130a.

[0070] Referring to Figure 8, in this embodiment, the encapsulation structure PKG8 is similar to the encapsulation structures PKG1 and PKG2, except that: the encapsulation body 140 is used to cover the connecting terminal 116, and the protective element 152A selected from the non-conductive film is used to cover the conductive terminal 130a.

[0071] Referring to Figure 9, in this embodiment, the encapsulation structure PKG9 is similar to the encapsulation structures PKG1 and PKG3, except that: a protective element 151B selected from a non-conductive film is used to cover the connecting terminal 116, and an encapsulation body 140 is used to cover the conductive terminal 130a.

[0072] Please refer to Figure 10. In this embodiment, the packaging structure PKG10 is similar to the packaging structure PKG3, except that a protective element 152B selected from the capillary bottom filling material is used to simultaneously cover the connecting terminal 116 and the conductive terminal 130a.

[0073] Referring to Figure 11, in this embodiment, the packaging structure PKG11 is similar to the packaging structure PKG2, except that the package 140 includes an overflow portion, which makes the junction between the outer wall of the package 140 and the substrate 120 curved (e.g., the junction between the outer wall of the package 140 and the substrate 120 is not perpendicular). In this way, the adhesion between the package 140 and the substrate 120 can be improved.

[0074] Referring to Figure 12, in this embodiment, the packaging structure PKG12 is similar to the packaging structure PKG2, except that the packaging structure PKG12 further includes a cover 160, wherein the cover 160 at least covers the back side of the chip module 130 relative to the active side. Therefore, the cover 160 can protect the electronic components in the packaging structure PKG12, and it can also serve as a heat sink to provide additional heat dissipation. In one embodiment, the cover 160 can form multiple cavities with the package body 140.

[0075] Referring to Figure 13, in this embodiment, the packaging structure PKG13 is similar to the packaging structure PKG2, except that the packaging structure PKG13 further includes a metal ring 170, wherein the metal ring 170 can be located on the top surface 120t of the substrate 120 and surround the chip module 130. Therefore, the metal ring 170 can protect the electronic components in the packaging structure PKG13 and can also provide additional support as a reinforcing member.

[0076] In the above embodiments, the backside 130t of the wafer module 130 may be further deposited to form a backside metal (BSM) or a thermal interface material (TIM) (not shown). The backside metal can be continuously formed on the coplanar surface formed by the package 140 and the wafer module 130 to further improve heat dissipation capability, but the present invention is not limited thereto. Here, the material of the backside metal can be any suitable metal material with excellent heat dissipation efficiency, and the present invention is not limited thereto.

[0077] In summary, by reducing the number of process steps the chip module passes through, the risk of defect rate during the process is reduced. At the same time, the overall structural strength can be improved based on the protection of the package. Accordingly, the yield of the package structure in this embodiment is effectively improved, thereby ensuring its good quality.

[0078] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0079] 10, 20: Carrier board 11, 21: Release layer 12: Adhesive layer 110: Intermediary Module 110s, 120s, 140s: outer wall 111: Layered structure 111a: Opening 111b, 114b, 140b: Bottom surface 112: Bridge chip 112a: Conductive bump 112b: Connector 112c: Insulation layer 113, 140: Package 114: Conductive connectors 115: Line Layer 115a: Dielectric layer 115b: Patterned conductive layer 116: Connecting terminal 116a, 130a: Conductive terminals 116b: Dummy Terminal 120:Substrate 120t, 130t, 140t: Top surface 121: External terminal 130: Chip Module 131: Chip 140T: Thickness 151A, 151B, 152A, 152B: Protective components 160: Capping 170: Metal Ring A: Area AS: Active Face BS: Back PKG1, PKG2, PKG3, PKG4, PKG5, PKG6, PKG7, PKG8, PKG9, PKG10, PKG11, PKG12, PKG13: Package Structure

Claims

1. A packaging structure, comprising: substrate; An intermediate module is disposed on the substrate; a wafer module is disposed on the intermediate module, wherein the wafer module is electrically connected to the substrate through the intermediate module; and a first package encapsulates the intermediate module and the wafer module disposed thereon and directly contacts the substrate, wherein the bottom surface of the first package is coplanar with the top surface of the substrate, wherein a portion of the first package extends from above the substrate to above the intermediate module.

2. The packaging structure as claimed in claim 1, wherein the first package exposes the top surface of the wafer module.

3. The packaging structure as claimed in claim 1, wherein the outer sidewall of the first package is located between the outer sidewall of the intermediate module and the outer sidewall of the substrate.

4. The packaging structure as claimed in claim 1, wherein the thickness of the first package is equal to the vertical distance from the top surface of the wafer module to the top surface of the substrate.

5. The packaging structure as described in claim 1, wherein the first package covers a portion of the second package of the intermediate module.

6. The packaging structure as claimed in claim 1, wherein the substrate and the intermediate module further include a plurality of first conductive terminals, and the intermediate module and the wafer module further include a plurality of second conductive terminals, wherein the plurality of first conductive terminals and the plurality of second conductive terminals are recessed within the first package body.

7. The packaging structure as claimed in claim 6, wherein the plurality of first conductive terminals and the plurality of second conductive terminals are respectively covered by a first protective member and a second protective member.

8. The packaging structure as claimed in claim 7, wherein the material of the first protective member and the material of the second protective member are respectively selected from a non-conductive film, a capillary bottom filling material, the first package body, or a combination thereof, and the materials of the first protective member and the second protective member are the same or different.

9. The packaging structure as claimed in claim 1, wherein the first package includes an overflow portion such that the junction between the outer wall of the first package and the substrate is curved.

10. A method for manufacturing a packaging structure, comprising: Provide substrate; Provide an intermediary module, wherein the intermediary module is of the single-slice type; The intermediate module is disposed on the substrate; Provide a chip module; dispose of the chip module on the intermediate module, wherein the chip module is electrically connected to the substrate through the intermediate module; and form a first package to encapsulate the chip module and the intermediate module and directly contact the substrate.

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