Optical device and method of manufacture

Abstract

This disclosure presents an optical device and a manufacturing method, wherein a protective layer is formed over a support substrate, a first semiconductor die, and an optical interposer. The optical interposer and a second semiconductor die are encapsulated together with a sealant. The sealant and the second semiconductor die are planarized, and after planarization, the sealant is removed to expose the protective layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to optical devices and manufacturing methods. Prior Technology

[0002] Electronic communication and processing is a technology used for signal transmission and processing. In recent years, optical communication and processing has been used in an increasing number of applications, especially for signal transmission using fiber optics. [, , ]

[0003] Optical communication and processing are often combined with electronic communication and processing to provide sophisticated applications. For example, optical fibers can be used for long-distance signal transmission, while electrical signals can be used for short-distance signal transmission, processing, and control. Therefore, devices integrating long-distance optical elements and short-distance electronic elements are formed for converting between optical and electrical signals and for processing both. The package can thus contain both: an optical (photonic) die including the optical components and an electronic die including the electronic components. Summary of the Invention

[0004] In one embodiment, a method of manufacturing an optical device includes: forming a protective layer on a support substrate, a first semiconductor die, and an optical interposer; encapsulating the optical interposer and a second semiconductor die with a sealant; and removing the sealant to expose the protective layer.

[0005] In another embodiment, a method of manufacturing an optical device includes: bonding a first optical package to an intermediate substrate, the first optical package including a protective layer over a support substrate, the support substrate being located over a first semiconductor die, the first semiconductor die being bonded to the optical intermediate layer; bonding a second semiconductor die to the intermediate substrate; encapsulating the second semiconductor die and the first optical package with a sealant; and removing a portion of the sealant to expose at least a portion of the protective layer.

[0006] In another embodiment, the optical device includes: a first optical package bonded to an intermediate substrate; a first semiconductor die bonded to the intermediate substrate; a sealant surrounding the first semiconductor die and the first optical package; and a protective layer covering the first optical package and exposed by the sealant. Simple Explanation of the Diagram

[0007] The best understanding of all aspects of this disclosure can be obtained from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration. Figures 1 to 6 illustrate the steps for forming a first optical package according to some embodiments. Figures 7A to 7E illustrate an additional support substrate with a protective layer according to some embodiments. Figures 8 and 9 illustrate additional steps in the formation of the first optical package according to some embodiments. Figure 10 illustrates an intermediate substrate according to some embodiments. Figure 11 illustrates the bonding of a first optical package to an intermediate substrate according to some embodiments. Figure 12 illustrates the thinning of the sealant according to some embodiments. Figure 13 illustrates the removal of sealant according to some embodiments. Figure 14 illustrates the bonding of an intermediate substrate to a second substrate according to some embodiments. Figure 15 illustrates the placement of fiber optic array units according to some embodiments. Figure 16 illustrates the placement of a heat sink according to some embodiments. Figure 17 illustrates the use of a second anti-reflective coating according to some embodiments. Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify the content of this disclosure. Of course, these examples are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments where the first feature and the second feature are in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0009] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and other elements or features. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0010] Embodiments will now be discussed with reference to certain examples, in which the use of a protective layer on the first optical package helps to form a flatter surface for receiving and transmitting optical signals. However, the embodiments presented are intended to be illustrative and are not intended to limit the presented ideas to the precise embodiments described. Rather, the presented ideas can be incorporated into a wide variety of embodiments, and all such embodiments are included within the overall scope of the disclosure.

[0011] Referring to FIG1, an initial structure of an optical interposer 100 (see FIG5) is shown according to some embodiments. In the specific embodiment shown in FIG1, the optical interposer 100 is a photonic integrated circuit (PIC) and at this stage includes a first substrate 101, a first insulating layer 103, and a layer of material 105 for a first active layer 201 for a first optical element 203 (not shown separately in FIG1, but further shown and discussed in FIG2). In one embodiment, at the start of the fabrication process of the optical interposer 100, the first substrate 101, the first insulating layer 103, and the layer of material 105 for the first active layer 201 for the first optical element 203 may together be part of a silicon-on-insulator (SOI) substrate. First, consider the first substrate 101, which may be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material capable of providing structural support for the upper-layer device.

[0012] The first insulating layer 103 may be a dielectric layer separating the first substrate 101 from the upper first active layer 201, and in some embodiments, it may also be part of a covering material surrounding a subsequently fabricated first optical element 203 (discussed further below). In one embodiment, the first insulating layer 103 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations thereof, or the like, formed using methods such as implantation (e.g., forming a buried oxide layer, BOX layer), or deposited over the first substrate 101 using methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. However, any suitable materials and manufacturing methods may be used.

[0013] The material 105 of the first active layer 201 is initially (before patterning) a conformal layer that will be used to begin fabricating the first active layer 201 of the first optical element 203. In one embodiment, the material 105 of the first active layer 201 can be a translucent material that can be used as the core material of the desired first optical element 203, such as a semiconductor material like silicon, germanium, silicon-germanium, combinations thereof, or the like. In other embodiments, the material 105 of the first active layer 201 can be a dielectric material, such as silicon nitride or the like. Although in other embodiments, the material 105 of the first active layer 201 can be a group III-V material, lithium niobate, or a polymer. In embodiments where the material 105 of the first active layer 201 is deposited, the material 105 of the first active layer 201 can be deposited using methods such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or similar methods. In other embodiments where the first insulating layer 103 is formed using an implantation method, the material 105 of the first active layer 201 may initially be part of the first substrate 101 prior to the implantation process that forms the first insulating layer 103. However, the material 105 of the first active layer 201 can be formed using any suitable material and manufacturing method.

[0014] Figure 2 illustrates the fabrication of a first optical element 203 of the first active layer 201 using the material 105 of the first active layer 201 once the material 105 of the first active layer 201 is ready. In embodiments, the first optical element 203 of the first active layer 201 may include optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), couplers (e.g., grating couplers, edge couplers, etc., for narrowed waveguides with widths between about 1 nanometer and about 200 nanometers), directional couplers, optical modulators (e.g., Mach-Zehnder silicon-optical switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optic converters, lasers, combinations thereof, or similar elements. However, any suitable first optical element 203 may be used.

[0015] In order to begin forming the first active layer 201 of the first optical element 203 from initial material, the material 105 of the first active layer 201 may be patterned into the desired shape of the first active layer 201 of the first optical element 203. In one embodiment, the material 105 of the first active layer 201 may be patterned using, for example, one or more lithography and etching processes. However, any suitable method may be used to pattern the material 105 of the first active layer 201. For some first optical elements 203, such as waveguides or edge couplers, the patterning process may be all or at least most of the fabrication used to form these first optical elements 203.

[0016] Figure 3 illustrates that for components requiring further fabrication processes, such as Mach-Zehnder silicon optical switches using resistive heating elements, additional processing can be performed before or after the patterning of the material of the first active layer 201. For example, implantation processes, other deposition and patterning processes of different materials (e.g., resistive heating elements, III-V materials for converters), combinations of all these processes, or the like, can be used to aid in the further fabrication of various desired first optical elements 203. In one particular embodiment, as specifically shown in Figure 3, epitaxial deposition of a semiconductor material 301, such as germanium (e.g., for electro / optical signal modulation and conversion), can be performed on the patterned portion of the material 105 of the first active layer 201. In such embodiments, epitaxial growth of the semiconductor material 301 can be performed to assist in the fabrication of, for example, photodiodes for photoelectric converters. All such fabrication processes, and all suitable first optical elements 203 and their various combinations that can be fabricated, are fully encompassed within the scope of this embodiment.

[0017] Figure 4 illustrates that once the individual first optical elements 203 in the first active layer 201 are formed, a second insulating layer 401 can be deposited to cover the first optical elements 203 and provide additional encapsulation material. In one embodiment, the second insulating layer 401 may be a dielectric layer that separates the individual elements of the first active layer 201 from each other and from the overlying structure, and may additionally serve as another portion of the encapsulation material surrounding the first optical elements 203. In one embodiment, the second insulating layer 401 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, or a combination thereof, or the like. The deposition method used to form it may include chemical vapor deposition, atomic layer deposition, physical vapor deposition, or a combination thereof, or the like. Once the material of the second insulating layer 401 has been deposited, the material may be planarized using, for example, a chemical mechanical polishing process to planarize the top surface of the second insulating layer 401 (in embodiments where the second insulating layer 401 is intended to completely cover the first optical element 203), or to planarize the second insulating layer 401 with the top surface of the first optical element 203. However, any suitable materials and manufacturing methods can be used.

[0018] Figure 5 illustrates that once the first optical element 203 of the first active layer 201 is fabricated and the second insulating layer 401 is formed, a first metallization layer 501 is formed to electrically connect the first active layer 201 of the first optical element 203 to the control circuitry, to each other, and to subsequently attached devices (not shown in Figure 5, but further illustrated and described below with reference to Figure 6). In one embodiment, the first metallization layer 501 is formed from alternating layers of dielectric and conductive materials and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In certain embodiments, multiple metallization layers can be used to interconnect various first optical elements 203, but the exact number of first metallization layers 501 depends on the design of the optical interposer 100.

[0019] Furthermore, during the fabrication of the first metallization layer 501, one or more second optical elements 503 may be formed as part of the first metallization layer 501. In some embodiments, the second optical element 503 of the first metallization layer 501 may include elements such as couplers (e.g., edge couplers, grating couplers, etc.) for connection to external signals, optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffused waveguides, etc.), optical modulators (e.g., Mach-Zehnder silicon photonic switches, microelectromechanical switches, microring resonators, etc.), amplifiers, multiplexers, demultiplexers, photoelectric converters (e.g., PN junctions), electro-optic converters, lasers, combinations thereof, or the like. However, any suitable optical element may be used as one or more second optical elements 503.

[0020] In one embodiment, one or more second optical elements 503 may be formed by first depositing material for one or more second optical elements 503. In one embodiment, the material for one or more second optical elements 503 may be a dielectric material, such as silicon nitride, silicon oxide, combinations thereof, or the like, or a semiconductor material, such as silicon, and the deposition method used for deposition may be chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or the like. However, any suitable material and any suitable deposition method may be used.

[0021] Once the material of one or more second optical elements 503 has been deposited or otherwise formed, the material can be patterned into the desired shape of the one or more second optical elements 503. In one embodiment, the material of one or more second optical elements 503 may be patterned using, for example, one or more lithography masks and etching processes. However, any suitable method may be used to pattern the material of one or more second optical elements 503.

[0022] For certain elements of one or more second optical elements 503, such as waveguides or edge couplers, the patterning process may be all or at least most of the fabrication used to form these elements. Furthermore, for elements utilizing further fabrication processes, such as Mach-Zehnder silicon photonic switches utilizing resistance-heated elements, additional processing may be performed before or after the material patterning of one or more second optical elements 503. For example, implantation processes, additional deposition and patterning processes of different materials, combinations of all these processes, or the like, may be used to aid in the further fabrication of various desired one or more second optical elements 503. All such fabrication processes, and all suitable one or more second optical elements 503 and their various combinations that can be fabricated, are fully encompassed within the scope of this embodiment.

[0023] Once one or more second optical elements 503 of the first metallization layer 501 are fabricated, a first bonding layer 505 is formed on the first metallization layer 501. In one embodiment, the first bonding layer 505 can be used for dielectric-to-dielectric and metal-to-metal bonding. According to some embodiments, the first bonding layer 505 is formed of a first dielectric material 509, such as silicon oxide, silicon nitride, or the like. The first dielectric material 509 can be deposited using any suitable method, such as CVD, high-density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. However, any suitable materials and deposition processes can be used.

[0024] Once the first dielectric material 509 is formed, a first opening is formed in the first dielectric material 509 to expose the conductive portion of the underlying layer, in preparation for forming a first bonding pad 507 within the first bonding layer 505. Once the first opening is formed in the first dielectric material 509, a seed layer and electroplated metal can be filled into the first opening to form the first bonding pad 507 within the first dielectric material 509. The seed layer can be deposited blanket-deposited on the top surface of the first dielectric material 509, the exposed conductive portion of the underlying layer, and the sidewalls of the opening. The seed layer may comprise a copper layer. The seed layer can be deposited using methods such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), or similar methods, depending on the desired material. Electroplated metal can be deposited on the seed layer via electroplating processes such as electroplating or electroless plating. The electroplated metal may comprise copper, copper alloys, or the like. The electroplated metal can be a filler material. Prior to the seed layer, a barrier layer (not shown separately) may be deposited over the entire surface of the top surface and opening sidewalls of the first dielectric material 509. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0025] After filling the first opening, a planarization process such as chemical mechanical polishing (CMP) is performed to remove excess portions of the seed layer and electroplated metal, forming a first bonding pad 507 within the first bonding layer 505. In some embodiments, bonding pad vias (not shown separately) may also be used to connect the first bonding pad 507 to the underlying conductive portion, and the first bonding pad 507 to the first metallization layer 501 through the underlying conductive portion.

[0026] Furthermore, the first bonding layer 505 may also include one or more third optical elements 511 integrated within the first bonding layer 505. In this embodiment, before depositing the first dielectric material 509, one or more third optical elements 511 may be fabricated using methods and materials similar to those used for one or more second optical elements 503 (as described above), such as waveguides and other structures at least partially formed by deposition and patterning processes. However, any suitable structure, material, and manufacturing method may be used.

[0027] Figure 6 illustrates the bonding of the first semiconductor device 601 to the first bonding layer 505 of the optical interposer 100. In some embodiments, the first semiconductor device 601 is an electronic integrated circuit (EIC; e.g., a device without optical components), which may have a semiconductor substrate 603, a layer of active device 605, an overlying interconnect structure 607, a second bonding layer 609, and an associated third bonding pad 611. In one embodiment, the semiconductor substrate 603 may be similar to the first substrate 101 (e.g., a semiconductor material such as silicon or silicon-germanium), the active device 605 may be a transistor, capacitor, resistor, or the like formed on the semiconductor substrate 603, the interconnect structure 607 may be similar to the first metallization layer 501 (without optical components), the second bonding layer 609 may be similar to the first bonding layer 505, and the third bonding pad 611 may be similar to the first bonding pad 507. However, any suitable device may be used.

[0028] In one embodiment, the first semiconductor device 601 may be configured to work in conjunction with the optical interposer 100 to achieve the desired functionality. In some embodiments, the first semiconductor device 601 may be a high bandwidth memory (HBM) module, xPU, logic die, three-dimensional integrated circuit (3DIC) die, central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC) die, microelectromechanical system (MEMS) die, a combination of the above, or the like. Any device with any suitable functionality may be used, all of which are fully encompassed within the scope of the embodiments.

[0029] In one embodiment, the first semiconductor device 601 and the first bonding layer 505 can be bonded using dielectric-to-dielectric and metal-to-metal bonding processes. In specific embodiments using dielectric-to-dielectric and metal-to-metal bonding processes, the process can be initiated by activating the surfaces of the second bonding layer 609 and the first bonding layer 505. Activating the top surfaces of the first bonding layer 505 and the second bonding layer 609 can include dry treatment, wet treatment, plasma treatment, exposure to inert gas plasma, exposure to H2, exposure to N2, exposure to O2, combinations thereof, or similar methods, as examples. In embodiments using wet treatment, RCA cleaning can be used, for example. In another embodiment, the activation process can include other types of treatments. The activation process facilitates the bonding of the first bonding layer 505 and the second bonding layer 609.

[0030] After the activation process, the optical interposer 100 and the first semiconductor device 601 can be cleaned using, for example, a chemical cleaning agent. The first semiconductor device 601 is then aligned and positioned to physically contact the optical interposer 100. Heat treatment and contact pressure are then applied to the optical interposer 100 and the first semiconductor device 601 to bond the optical interposer 100 to the laser die 600. For example, the optical interposer 100 and the first semiconductor device 601 can be subjected to pressures of about 200 kPa or less, and temperatures between about 25°C and about 250°C to fuse the optical interposer 100 and the first semiconductor device 601. The optical interposer 100 and the first semiconductor device 601 can then be subjected to temperatures at or above the eutectic point of the materials of the first bonding pad 507 and the third bonding pad 611, for example, between about 150°C and about 650°C, to melt the metal. In this way, the optical interposer 100 and the first semiconductor device 601 form a dielectric-to-dielectric and metal-to-metal bonding device. In some embodiments, the bonded grains are baked, tempered, pressed, or otherwise treated to strengthen or complete the bond.

[0031] Furthermore, while specific processes for initiating and strengthening the bond have been described, these descriptions are illustrative and not intended to limit the embodiments. Instead, any suitable combination of baking, tempering, pressing, or other processes can be utilized. All of these processes are fully intended to be included within the scope of the embodiments.

[0032] Figure 6 further illustrates that once the first semiconductor device 601 is bonded, a first gap filler material 613 is deposited to fill the space around the first semiconductor device 601 and provide additional support. In one embodiment, the first gap filler material 613 may be a material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like, deposited to fill and overfill the space around the first semiconductor device 601. However, any suitable material and deposition method may be used.

[0033] Once the first gap filler material 613 has been deposited, it can be planarized to expose the first semiconductor device 601. In one embodiment, the planarization process can be a chemical mechanical planarization process, a polishing process, or the like. However, any suitable planarization process can be used.

[0034] Figures 7A to 7E illustrate the formation of a support substrate 701 and its attachment to a first semiconductor device 601 and a first gap-filling material 613. Referring first to Figure 7A, it shows that in one embodiment, the support substrate 701 may be a support material transparent to the desired wavelength of light, such as silicon. However, any suitable material may be used.

[0035] Figure 7A further illustrates that the support substrate 701 may further include one or more first coupling lenses 703, which are positioned to facilitate operation from the fiber array unit 1501 (not shown in Figure 7A, but further shown and described below with reference to Figure 15). In one embodiment, the first coupling lens 703 can be formed by shaping the material of the support substrate (e.g., silicon) using a photomask and etching process. However, any suitable process can be used.

[0036] Furthermore, if desired, a first anti-reflective coating (ARC) (not shown separately in FIG. 7A) may be formed on the first coupling lens 703. In one embodiment, the first ARC may be one or more layers of material that helps prevent unwanted reflections when light is focused through the first coupling lens 703. In a particular embodiment, the one or more layers of material may be a material such as silicon oxide, silicon nitride, combinations thereof, or the like, using methods such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, oxidation, nitridation, combinations thereof, or the like.

[0037] In one particular embodiment, the first ARC may use a first layer of silicon oxide and a first layer of silicon nitride formed on the first layer of silicon oxide. A second layer of silicon oxide and a second layer of silicon nitride are deposited on the first layer of silicon oxide and the first layer of silicon nitride, forming an alternating stack of silicon oxide and silicon nitride. Once all the desired layers have been deposited, these layers can be patterned using, for example, lithography and etching processes. However, any suitable combination of materials and processes can be used.

[0038] Optionally, if the groove formed by the first coupling lens 703 is not filled by other means, a filler material may be deposited to fill the groove formed by the first coupling lens 703. In one embodiment, the filler material may be an encapsulating material, such as silicon oxide deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, or similar methods. Once the groove has been filled, a process such as chemical mechanical polishing may be used to planarize the filler material to remove portions of the filler material outside the groove.

[0039] Figure 7B illustrates a protective layer 707 formed over the support substrate 701, the first coupling lens 703, and the anti-reflective layer, within the groove created by the formation of the first coupling lens 703 if no filler material is present. In one embodiment, the protective layer 707 serves to provide an anti-reflective coating, which also provides additional protection to the underlying structure during the removal of the sealant 1109 (not shown in Figure 7B but shown and described in Figure 11), and also helps ensure that the surface after the sealant 1109 is removed is smoother than in other cases. Maintaining this surface smoothness facilitates the transmission of the optical signal 1503 (not shown in Figure 7B but shown in Figure 15) between the fiber array unit 1501 and the first optical package 900.

[0040] In one particular embodiment, the protective layer 707 may be formed of a protective material such as silicon oxide; however, other suitable materials may also be selected, such as silicon nitride, oxynitride, or dielectric materials including oxides, nitrides, polyimides, photoresists, polymer materials, or combinations thereof or the like. The protective material may use methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, combinations thereof, or the like, with a thickness between about 50 Å and about 3000 Å. However, any suitable material, process, or thickness may be used.

[0041] Alternatively, once the protective layer 707 is deposited, it can be planarized to provide a flat, smooth surface. In one embodiment, a planarization process, such as chemical mechanical polishing, can be used to planarize the protective layer 707. However, any suitable planarization process can be used.

[0042] Of course, while the precise steps described above can be used to form the first coupling lens 703 and the protective layer 707, these precise steps are merely illustrative and not intended to limit the embodiments. Rather, any suitable combination or order of steps can be used. For example, in some embodiments, the filler material and the first antireflective coating may be omitted, and the material of the protective layer 707 may be used to fill the remaining portion of the groove used to form the first coupling lens 703. Any suitable combination of steps can be used, and all such modifications are fully intended to be included within the scope of the embodiments.

[0043] Figure 7C illustrates one such modification of the protective layer 707. In the embodiment shown in Figure 7C, the protective layer 707 is deposited in a manner that conforms to the underlying shape of one or more first coupling lenses 703. The shape of the protective layer 707 can be controlled by using conformal deposition methods such as chemical vapor deposition, atomic layer deposition, combinations thereof, or similar methods. However, any suitable method can be used.

[0044] Figure 7D illustrates another embodiment of the protective layer 707. In this embodiment, the protective layer 707 is a multilayer structure comprising a bottom layer 711, an intermediate layer 713, and a top layer 715. In one embodiment, the bottom layer 711 may be formed using similar materials and methods as described above with respect to the protective layer 707 in Figure 7C, such as depositing a material such as silicon oxide conforming to the shape of the bottom layer. However, any suitable materials and methods may be used.

[0045] Intermediate layer 713 may be deposited on top of bottom layer 711. In one embodiment, intermediate layer 713 may be a material such as silicon nitride, silicon oxide, a combination thereof, or the like, deposited using a deposition process such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, a combination thereof, or the like. However, any suitable material and deposition method may be used.

[0046] The top layer 715 may be deposited on top of the intermediate layer 713. In one embodiment, the top layer 715 may be formed using similar materials and methods as described above with respect to the protective layer 707 in FIG. 7B, for example, depositing a material such as silicon oxide, which is deposited in a blanket-like manner and then planarized. However, any suitable materials and methods may be used.

[0047] Figure 7E illustrates that once the protective layer 707 is formed (using any of the embodiments described above with respect to Figures 7A to 7D), the support substrate 701 can be attached to the first semiconductor device 601 and the first gap filler material 613. In one embodiment, an adhesive (not shown separately in Figure 7E) can be used to attach the support substrate 701. However, in other embodiments, a bonding process such as a melt bonding process can be used to bond the support substrate 701 to the first semiconductor device 601 and the first gap filler material 613. Any suitable method can be used to attach the support substrate 701.

[0048] Figure 8 illustrates the removal of the first substrate 101 and the selective removal of the first insulating layer 103, thereby exposing the first active layer 201 of the first optical element 203. In one embodiment, planarization processes such as chemical mechanical polishing, grinding, one or more etching processes, combinations thereof, or the like can be used to remove the first substrate 101 and the first insulating layer 103. However, any suitable method can be used to remove the first substrate 101 and / or the first insulating layer 103.

[0049] Once the first substrate 101 and the first insulating layer 103 are removed, a second active layer 801 of the fourth optical element 803 can be formed on the back side of the first active layer 201. In one embodiment, the second active layer 801 of the fourth optical element 803 can be formed using similar materials and similar processes to those used for the second optical element 503 (as described above with respect to FIG. 5) of the first metallization layer 501. For example, the second active layer 801 of the fourth optical element 803 can be formed from alternating layers of a coating material such as silicon oxide and a core material such as silicon nitride, using deposition and patterning processes to form optical elements such as waveguides and the like.

[0050] Figure 9 illustrates the formation of a first through-device via (TDV) 901 and a third bonding layer 903 to form a first optical package 900, which in some embodiments is a photonic engine. In one embodiment, the first TDV 901 penetrates the second active layer 801 and the first active layer 201 to provide a fast path for power, data, and ground through the optical interposer 100. In one embodiment, the first TDV 901 can be formed by first forming the TDV opening in the optical interposer 100. The TDV opening can be formed by coating and developing a suitable photoresist (not shown) and removing exposed portions of the second active layer 801 and the optical interposer 100.

[0051] Once the device via opening is formed in the optical interposer 100, a liner can be used to cover the device via opening. The liner can be, for example, an oxide or silicon nitride formed from tetraethylorthosilicate (TEOS), although any suitable dielectric material can be used instead. The liner can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or thermal processes, can also be used.

[0052] Once a liner is formed on the sidewalls and bottom of the device via opening, a barrier layer (not shown separately) can be formed, and the remainder of the device via opening can be filled with a first conductive material. The first conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polycrystalline silicon, combinations thereof, and the like can be used. The first conductive material can be formed by electroplating copper onto a seed layer (not shown), filling and overfilling the device via opening. Once the device via opening is filled, excess liner, barrier layer, seed layer, and first conductive material outside the device via opening can be removed by a planarization process such as chemical mechanical polishing, although any suitable removal process can be used.

[0053] In some embodiments, optionally, once the first device via 901 is formed, a second metallization layer (not shown separately in FIG. 9) electrically connected to the first device via 901 may be formed. In one embodiment, the second metallization layer may be formed as described above with respect to the first metallization layer 501, for example, by using a damascene process, a dual damascene process, or the like to form alternating layers of dielectric and conductive materials. In other embodiments, an electroplating process may be used to form and shape the conductive material, and then the conductive material may be covered with a dielectric material to form the second metallization layer. However, any suitable structure and manufacturing method may be used.

[0054] A third bonding layer 903 is formed to provide an electrical connection between the optical interposer 100 and subsequent additional devices. In one embodiment, the third bonding layer 903 may be similar to the first bonding layer 505, for example having a third bonding pad 909 (similar to the first bonding pad 507) or even a fifth optical element 911 (similar to the third optical element 511). However, any suitable device may be used.

[0055] Figure 9 further illustrates the placement of a first external connector 913, which can be formed to provide a conductive area for contact between the third bonding pad 909 and other external devices. The first external connector 913 can be a conductive bump (e.g., a controlled collapse chip connection (C4) bump, ball grid array, microbump, etc.) or a conductive pillar using materials such as solder and copper. In embodiments where the first external connector 913 is a contact bump, it can contain materials such as tin or other suitable materials, such as silver, lead-free tin, or copper. In embodiments where the first external connector 913 is a solder bump, it can be formed by first forming a tin layer using common methods such as vapor deposition, electroplating, printing, solder transfer, balling, etc. Once the tin layer is structurally formed, reflow can be performed to shape the material into the desired bump shape.

[0056] Of course, while the use of the first external connector 913 is one embodiment that can be used to provide a connection for the first optical package 900, this is merely illustrative and not intended to limit the embodiments. Rather, any suitable method can be used to physically, electrically, and in some cases, optically connect the first optical package 900, such as dielectric-to-dielectric and metal-to-metal bonding. Any suitable method can be used to bond the first optical package 900.

[0057] Figure 10 illustrates an interposer substrate 1001 for coupling a first optical package 900 with other devices to form, for example, a chip-on-wafer-on-substrate device. In one embodiment, the interposer substrate 1001 includes a semiconductor substrate 1003, a third metallization layer 1005, a third device via (TDV) 1007, a fourth metallization layer 1009, and a second external connector 1013. The semiconductor substrate 1003 may include an active layer of doped or undoped bulk silicon or a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes layers of semiconductor material such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0058] Optionally, a first active device (not shown separately) may be added to the semiconductor substrate 1003. The first active device includes various active and passive devices, such as capacitors, resistors, inductors, etc., and can be used to generate the structural and functional requirements necessary for the design of the semiconductor substrate 1003. The first active device can be formed within or on the semiconductor substrate 1003 using any suitable method.

[0059] An opening may be formed in the semiconductor substrate 1003 to accommodate the first bridging die 1004, wherein the opening may be formed using, for example, one or more lithography masks and etching processes. In one embodiment, the first bridging die 1004 may be a local silicon interconnect (LSI) die for bridging and electrically connecting subsequently placed means, and may be placed using, for example, a pick and place process. However, any suitable means and methods may be used.

[0060] A third metallization layer 1005 is formed over the semiconductor substrate 1003 and the first active device on the interposer substrate 1001 and is designed to connect various devices to form a functional circuit. In one embodiment, the third metallization layer 1005 of the interposer substrate 1001 is formed of alternating layers of dielectric material (e.g., low-k dielectric material, very low-k dielectric material, ultra-low-k dielectric material, combinations thereof, or the like) and conductive material, and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). However, any suitable materials and processes can be used.

[0061] The fourth bonding pad 1011 may be formed on the third metallization layer 1005. In one embodiment, the fourth bonding pad 1011 may be formed using a method and materials similar to those used for the third bonding pad 909 discussed above with respect to FIG9. However, any suitable method and materials may be used.

[0062] Furthermore, at any desired point in the manufacturing process, the second device via 1007 may be formed within one or more layers of the semiconductor substrate 1003 and (if desired) the third metallization layer 1005 to provide an electrical connection from the front side of the semiconductor substrate 1003 to the back side of the semiconductor substrate 1003. In one embodiment, the second device via 1007 may be formed by first forming a via (TDV) opening in either the semiconductor substrate 1003 or (if desired) the overlying third metallization layer 1005 (e.g., after the desired third metallization layer 1005 is formed, but before the formation of the next overlying third metallization layer 1005). The TDV opening may be formed by coating and developing a suitable photoresist and removing the exposed portion of the underlying material to the desired depth. The TDV opening may be formed to extend into the semiconductor substrate 1003 to a depth greater than the final desired height of the semiconductor substrate 1003.

[0063] Once the TDV opening is formed in the semiconductor substrate 1003 and / or any third metallization layer 1005, a liner can be used to line the TDV opening. The liner can be, for example, an oxide formed of tetraethylorthosilicate (TEOS) or silicon nitride, although any suitable dielectric material can also be used. The liner can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or thermal processes, can also be used.

[0064] Once the liner is formed along the sidewalls and bottom of the TDV opening, a barrier layer can be formed, and the remainder of the TDV opening can be filled with a first conductive material. The first conductive material may include copper, although other suitable materials may be used alternatively, such as aluminum, alloys, doped polycrystalline silicon, combinations thereof, etc. The first conductive material can be formed by electroplating copper onto the seed layer, filling and overfilling the TDV opening. Once the TDV opening is filled, any excess liner, barrier layer, seed layer, and first conductive material outside the TDV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0065] Once the TDV opening is filled, the semiconductor substrate 1003 can be thinned until the second device via 1007 is exposed. In one embodiment, a chemical mechanical polishing process, a polishing process, or the like can be used to thin the semiconductor substrate 1003. Furthermore, once exposed, one or more etching processes, such as a wet etching process, can be used to recess the second device via 1007 to recess the semiconductor substrate 1003 such that the second device via 1007 extends out of the semiconductor substrate 1003.

[0066] Once the second device via 1007 is formed, a fourth metallization layer 1009 can be formed on the side of the semiconductor substrate 1003 opposite to the third metallization layer 1005. The fourth metallization layer 1009 can be formed using methods and materials similar to those used for the third metallization layer 1005. However, any suitable method can be used.

[0067] In one embodiment, the second external connector 1013 may be placed and may be, for example, a ball grid array (BGA) comprising a eutectic material such as solder, although any suitable material may be used. Alternatively, under-bump metallization or an additional metallization layer may be used between the fourth metallization layer 1009 and the second external connector 1013. In embodiments where the second external connector 1013 is a solder bump, a drop ball method may be used to form the second external connector 1013, such as a direct drop ball process. In another embodiment, the solder bump may be manufactured by first forming a layer of tin, which may be formed by any suitable method, such as vapor deposition, electroplating, printing, or solder transfer, and then tempering to shape the material into the desired bump shape. Once the second external connector 1013 is formed, testing may be performed to ensure that the structure is suitable for subsequent processing.

[0068] Of course, while the above process is one method of forming the intermediate substrate 1001, this description is intended to illustrate and not limit the embodiments. Instead, any suitable method can be used to form the intermediate substrate 1001. For example, in another embodiment, a second device via 1007 may be formed first, followed by placing a first bridging die 1004 and encapsulating it with a sealant (instead of the semiconductor substrate 1003), and then forming a metallization layer. Any suitable processes and apparatus can be used, all of which are fully encompassed within the scope of the embodiments.

[0069] Figure 11 illustrates that once the intermediate substrate 1001 is formed, the first optical package 900 (shown in a very simplified form in Figure 11 for clarity) can be attached to the intermediate substrate 1001. In one embodiment, the first optical package 900 is attached to the intermediate substrate 1001 by aligning the first external connector 913 with the fourth bonding pad 1011 of the intermediate substrate 1001. Once aligned and in physical contact, the first external connector 913 is tempered by raising its temperature above its eutectic point, thereby transforming the material of the first external connector 913 into a liquid phase. Once tempered, the temperature is lowered to transform the material of the first external connector 913 back into a solid phase, thereby bonding the first optical package 900 to the intermediate substrate 1001.

[0070] Optionally, a first underfill material 1101 may be placed. The first underfill material reduces stress and protects the joint created by tempering the first external connector 913. The first underfill material may be formed by a capillary process after the first optical package 900 is attached.

[0071] Figure 11 further illustrates the second semiconductor device 1105 and the third semiconductor device 1107 bonded to the intermediate substrate 1001. In some embodiments, the second semiconductor device 1105 and the third semiconductor device 1107 are electronic integrated circuits (EICs), such as ASIC devices. In a particular embodiment, the second semiconductor device 1105 and the third semiconductor device 1107 include system-on-a-chip (SoC) devices and high-bandwidth memory (HBM) devices. Of course, although in one embodiment the second semiconductor device 1105 and the third semiconductor device 1107 are SOC and HBM devices, the embodiments do not limit the second semiconductor device 1105 and the third semiconductor device 1107 to be SOC and HBM devices. Rather, the second semiconductor device 1105 and the third semiconductor device 1107 can be any suitable semiconductor device, such as a processor die, a memory die, or other type of functional die. In a particular embodiment, the second semiconductor device 1105 may be a logic die, a 3DIC die, a CPU, a GPU, a micro-electro-mechanical systems (MEMS) die, an XPU die, a combination of the like, or the like. Any device with any suitable function may be used, and all such devices are fully included within the scope of the embodiments.

[0072] In one embodiment, the second semiconductor device 1105 and the third semiconductor device 1107 may be bonded to the intermediate substrate 1001 using, for example, a third external connector 1108. The third external connector 1108 may be a conductive bump (e.g., a ball grid array, microbumps, etc.) or a conductive pillar using materials such as solder and copper. In embodiments where the third external connector 1108 is a contact bump, the third external connector 1108 may contain materials such as tin, or other suitable materials, such as silver, lead-free tin, or copper. In embodiments where the third external connector 1108 is a solder bump, the third external connector 1108 may be formed by first forming a tin layer using common methods such as vapor deposition, electroplating, printing, solder transfer, balling, etc. Once the tin layer is structurally formed, tempering may be performed to shape the material into the desired bump shape.

[0073] Furthermore, once the third external connector 1108 is placed, the second semiconductor device 1105 and the third semiconductor device 1107 are aligned with the intermediate substrate 1001. Once aligned and in physical contact, the third external connector 1108 is tempered by raising its temperature above its eutectic point, thereby transforming the material of the third external connector 1108 into a liquid phase. After tempering, the temperature is lowered to transform the material of the third external connector 1108 back into a solid phase, thereby bonding the second semiconductor device 1105 and the third semiconductor device 1107 to the intermediate substrate 1001.

[0074] Optionally, a second underfill material 1110 may be placed. The second underfill material 1110 can reduce stress and protect the contacts created by tempering the third external connector 1108. The second underfill material 1110 can be formed by a capillary process after the second semiconductor device 1105 and the third semiconductor device 1107 are attached.

[0075] Once the second semiconductor device 1105, the third semiconductor device 1107, and the first optical package 900 are bonded to the intermediate substrate 1001, the second semiconductor device 1105, the third semiconductor device 1107, and the first optical package 900 are encapsulated with a sealant 1109. In one embodiment, the sealant 1109 may be a material such as a molding compound placed using an injection molding process. Once placed, the molding compound can be cured. However, any suitable material and process can be used.

[0076] Figure 12 illustrates that once the sealant 1109 is placed and cured, it can be planarized. In one embodiment, a planarization process such as chemical mechanical polishing can be used to planarize the sealant 1109 until the sealant 1109 is coplanar with one or both of the second semiconductor device 1105 and the third semiconductor device 1107. However, any suitable planarization process can be used.

[0077] Furthermore, given the potential for damage during the planarization process, it is advantageous to keep the planarization process away from the first optical package 900. Therefore, to prevent damage to the sealant 1109 during the planarization process, the height of the second semiconductor device 1105 and / or the third semiconductor device 1107 is intentionally made higher than the height of the first optical package 900. Thus, after the sealant 1109 is planarized, it remains above the first optical package 900.

[0078] However, since the height of the first optical package 900 differs from at least one of the second semiconductor device 1105 and the third semiconductor device 1107, the planarization process exposing the second semiconductor device 1105 and / or the third semiconductor device 1107 may not necessarily expose the first optical package 900. Therefore, once the sealant 1109 is planarized, a portion of the sealant 1109 may still remain above the first optical package 900.

[0079] Figure 13 illustrates the removal of sealant 1109 from above the first optical package 900 to facilitate the transmission of optical signal 1503 to the first optical package 900. In one embodiment, one or more lithography masks and etching processes, such as dry etching or wet etching processes, can be used to remove the sealant 1109. For example, photoresist can be placed and patterned on the sealant 1109, and one or more directional etching processes, such as reactive ion etching, can be used to remove the sealant 1109 above the first optical package 900 using the photoresist as a mask. However, any suitable method can be used.

[0080] In one embodiment, the sealant 1109 can be removed from above the first optical package 900, and simultaneously all sealant 1109 can be removed from the sidewalls of the second semiconductor device 1105. In other embodiments, the sealant 1109 can be removed from above the first optical package 900, while retaining sealant 1109 along all sidewalls of the second semiconductor device 1105 and the third semiconductor device 1107 (illustrated by dashed line 1301 in FIG. 13). Any suitable pattern can be used.

[0081] However, due to the presence of protective layer 707, it is more resistant to damage caused by the removal of sealant 1109. Less damage allows for a higher transmission rate of optical signal 1503 transmitted through protective layer 707. Furthermore, this damage reduction solution is practically feasible for photonic engines in co-packaged optics (CPO) systems. These solutions are also highly compatible with current manufacturing benchmark processes.

[0082] Figure 14 illustrates that once the second semiconductor device 1105, the third semiconductor device 1107, and the first optical package 900 are bonded to the intermediate substrate 1001, the intermediate substrate 1001 can be bonded to the second substrate 1401, for example, using a second external connector 1013. In one embodiment, the second substrate 1401 can be a package substrate, which can be a printed circuit board (PCB) or the like. The second substrate 1401 may include one or more dielectric layers and conductive features, such as conductive lines and vias. In some embodiments, the second substrate 1401 may include through-holes, active devices, passive devices, etc. The second substrate 1401 may also have conductive pads formed on its upper and lower surfaces.

[0083] The second external connector 1013 can be aligned with a corresponding conductive connection on the second substrate 1401. Once aligned, the second external connector 1013 can be tempered to bond the second substrate 1401 to the intermediate substrate 1001. However, any suitable bonding process can be used to connect the intermediate substrate 1001 to the second substrate 1401.

[0084] Furthermore, an external connection (not described separately) may be placed on the side of the second substrate 1401 opposite to the intermediate substrate 1001 to prepare for further connection. In one embodiment, the external connection may be formed using a process and materials similar to those used for the second external connector 1013. However, any suitable materials and processes may be used.

[0085] Figure 15 illustrates a fiber optic array unit (FAU) 1501 positioned above a first optical package 900. In one embodiment, the fiber optic array unit 1501 provides an entry and exit point for an optical signal 1503. In one embodiment, the fiber optic array unit assembly 1501 receives optical fibers (not shown separately in Figure 15), arranges the fibers through fiber sheaths, and guides the optical signal 1503 from the optical fibers to the first optical package 900. Support materials such as glass portions and / or silicon substrates support the various elements of the fiber optic array unit 1501 and can be fixed together using a refractive index matching gel.

[0086] By utilizing the protective layer 707 as described above, which protects the top surface of the underlying device, it helps to allow for a high transmission rate of the optical signal 1503. Furthermore, this solution is practically feasible for photonic engines in co-packaged optics (CPO) systems. These solutions are also highly compatible with current manufacturing baseline processes.

[0087] Figure 16 illustrates another embodiment in which a heat sink 1601 can be used to help dissipate heat from the second semiconductor device 1105 and / or the third semiconductor device 1107. In one embodiment, the heat sink 1601 can be formed using a material with high thermal conductivity, such as aluminum, copper, other metals, alloys, combinations thereof, etc., and assists in cooling other devices by increasing the surface area exposed to the surrounding coolant (such as air). Heat transfer mechanisms occur through convection of the surrounding air, conduction in the air, and radiation. For example, the heat sink 1601 can be formed by employing a large number of geometrically shaped needle-like matrix fins, or an array of straight or outwardly flared fins. In another instance, such as in cases of low convection, a matte black surface color can radiate more effectively than a shiny metallic color in the visible spectrum. Any suitable form of heat sink can be used.

[0088] Figure 16 further illustrates another embodiment of removing the sealant 1109 covering the first optical package 900. In this embodiment, only the sealant 1109 directly above the first optical package 900 is removed, while the sealant 1109 laterally away from the first optical package 900 remains in place. However, any suitable sealant 1109 can be patterned.

[0089] Figure 17 illustrates another embodiment using a second antireflective coating 1701 located between the support substrate 701 and the first semiconductor device 601. In one embodiment, the second antireflective coating 1701 may be a single-layer or multi-layer structure, similar to the protective layer 707, and may be formed using similar materials and methods as described in Figures 7A to 7D. Furthermore, the second antireflective coating 1701 may be formed on either the support substrate 701 or the first semiconductor device 601. However, any suitable materials and methods may be used.

[0090] In one embodiment, a method of manufacturing an optical device includes: forming a protective layer on a support substrate, a first semiconductor die, and an optical interposer; encapsulating the optical interposer and a second semiconductor die with a sealant; planarizing the sealant and the second semiconductor die; and removing the sealant after planarizing the sealant to expose the protective layer. In one embodiment, the protective layer is formed of silicon oxide. In one embodiment, the method further includes attaching the optical interposer to the interposer substrate prior to encapsulation. In one embodiment, the method further includes attaching the second semiconductor die to the interposer substrate prior to encapsulation. In one embodiment, the protective layer is generally formed to form at least a portion of the protective layer. In one embodiment, the protective layer is formed to form a multilayer structure. In one embodiment, the method further includes planarizing the sealant and the second semiconductor die.

[0091] In another embodiment, a method of manufacturing an optical device includes: bonding a first optical package to an intermediate substrate, the first optical package including a protective layer over a support substrate, the support substrate being located over a first semiconductor die, the first semiconductor die being bonded to the optical intermediate layer; bonding a second semiconductor die to the intermediate substrate; encapsulating the second semiconductor die and the first optical package with a sealant; and removing a portion of the sealant to expose at least a portion of the protective layer. In one embodiment, after removing a portion of the sealant, the sidewalls of the second semiconductor die are exposed. In one embodiment, after removing a portion of the sealant, each sidewall of the second semiconductor die remains covered by the sealant. In one embodiment, the protective layer includes silicon oxide. In one embodiment, the protective layer is conformally fitted to a coupling lens in the support substrate. In one embodiment, the protective layer includes multiple layers of different materials. In one embodiment, the support substrate has an anti-reflective layer on the side opposite to the protective layer.

[0092] In another embodiment, the optical device includes: a first optical package bonded to an intermediate substrate; a first semiconductor die bonded to the intermediate substrate; a sealant surrounding the first semiconductor die and the first optical package; and a protective layer covering the first optical package and exposed by the sealant. In one embodiment, the protective layer comprises silicon oxide. In one embodiment, the protective layer comprises multiple layers of different materials. In one embodiment, the protective layer is conformal to the underlying lens. In one embodiment, the sealant has a stepped height change between the first semiconductor device and the first optical package. In one embodiment, at least a portion of the sidewall of the first semiconductor device is exposed by the sealant.

[0093] The features of the above embodiments are designed to facilitate understanding of this disclosure by those skilled in the art. Those skilled in the art should understand that this disclosure can be used as a basis to design and modify other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the spirit and scope of this disclosure, and changes, substitutions, or modifications can be made without departing from the spirit and scope of this disclosure.

[0094] 100: Optical Intermediate Layer 101: First basement 103: First insulating layer 105: Materials 201: First Active Layer 203: First optical element 301: Semiconductor Materials 401: Second Insulation Layer 501: First metallization layer 503: Second optical element 505: First bonding layer 507: First bonding pad 509: First Dielectric Material 511: Third optical element 600: Laser Grain 601: First Semiconductor Device 603, 1003: Semiconductor substrate 605: Active device 607: Interconnection Structure 609: Second bonding layer 611,909: Third joint pad 613: First gap filling material 701: Supporting substrate 703: First coupling lens 707: Protective Layer 711: The Bottom 713: Intermediate Layer 715: Top Floor 801: Second Active Layer 803: Fourth Optical Element 900: First Optical Package 901: Through hole of the first device 903: Third bonding layer 911: The Fifth Optical Element 913: First external connector 1001: Intermediate Basis 1004: First bridging grain 1005: Third metallization layer 1007: Second device through hole 1009: Fourth metallization layer 1011: Fourth joint pad 1013: Second external connector 1101: First bottom filling material 1105: Second Semiconductor Device 1107: Third Semiconductor Device 1108: Third external connector 1109: Sealant 1110: Second bottom filling material 1301: Marked by dashed line 1401: Second basement 1501: Fiber optic array unit 1503: Optical Signal 1601: Radiator 1701: Second anti-reflective coating

Claims

1. A method for manufacturing an optical device, comprising: An optical package is provided comprising a support substrate, a first semiconductor die, an optical interposer, and a protective layer, wherein the protective layer is formed over the support substrate, the first semiconductor die, and the optical interposer; the optical interposer, the optical package, and the second semiconductor die are encapsulated with a sealant; and the sealant is removed to expose the protective layer.

2. The method of claim 1, further comprising attaching the optical interposer and the second semiconductor die to the interposer substrate prior to the encapsulation.

3. A method for manufacturing an optical device, comprising: A first optical package is bonded to an interposer substrate, the first optical package including a protective layer over a support substrate, the support substrate being over a first semiconductor die bonded to the optical interposer layer; a second semiconductor die is bonded to the interposer substrate; The second semiconductor die and the first optical package are encapsulated with a sealant; and a portion of the sealant is removed to expose at least a portion of the protective layer.

4. The method of claim 3, wherein the sidewalls of the second semiconductor die are exposed after the removal of the portion of the sealant.

5. The method of claim 3, wherein after the removal of the portion of the sealant, each sidewall of the second semiconductor die remains covered by the sealant.

6. The method of claim 3, wherein an anti-reflective layer is provided on the side of the supporting substrate opposite to the protective layer.

7. An optical device, comprising: An optical package bonded to an interposer substrate, wherein the optical package includes: an optical interposer layer; a first semiconductor die located above the optical interposer layer; a support substrate located above the first semiconductor die; a protective layer covering the support substrate; a second semiconductor die bonded to the interposer substrate; and a sealant surrounding the second semiconductor die and the optical package, wherein the protective layer is exposed by the sealant.

8. The optical device as claimed in claim 7, wherein the protective layer comprises multiple layers of different materials.

9. The optical device as claimed in claim 7, wherein the protective layer is conformal to the underlying lens.

10. The optical device as claimed in claim 7, wherein the sealant has a stepped height variation between the second semiconductor die and the optical package.

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