Manufacturing method for dicing a wafer
The wafer dicing method aligns non-perpendicular edges of non-rectangular dies with calibration objects and markers to facilitate traditional dicing, addressing inefficiencies and costs in existing methods, enhancing accuracy and yield.
Patent Information
- Application Number
- TW113143410
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2026-07-11
- Estimated Expiration
- 2044-11-11
AI Technical Summary
Traditional methods for dicing wafers with non-rectangular dies, such as hexagonal chips, are inefficient and costly, requiring plasma etching due to the inability to form straight lines, leading to high costs, time consumption, and low yield.
A wafer dicing method that aligns non-perpendicular edges of non-rectangular dies to form straight lines, using calibration objects and markers to ensure accurate image recognition and cutting, allowing traditional dicing processes to be used.
Enables efficient and accurate dicing of non-rectangular dies using traditional methods, reducing costs and improving yield by ensuring consistent image recognition and angle judgment during the dicing process.
Smart Images
Figure IMG-2_DRAW_113143410-A0101-14-0001-1 
Figure IMG-2_DRAW_113143410-A0101-14-0002-2 
Figure IMG-2_DRAW_113143410-A0101-14-0003-3
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing wafers, and more particularly to a method for manufacturing wafers into non-rectangular dies. Prior Technology
[0002] A photosensitive chip is a photoelectric conversion element that generates a change in current or voltage when light shines on it. Photosensitive chips are widely used in various optical instruments such as optical communication, photoelectric detection, automatic brightness adjustment, spectral analysis, photosensitive circuits, photodetectors, and cameras. They are typically used to detect light intensity, measure spectra, or detect light signals. As shown in Figure 1, a wafer is linearly cut using a dicing saw, resulting in a common rectangular chip shape. However, using this type of rectangular chip in the photosensitive modules of recently popular wearable devices cannot meet the requirement of maximizing the distribution area. Therefore, to meet the requirement of maximizing the distribution area of photosensitive chips, various chip shapes have been developed, the most common being hexagonal chips, as shown in Figure 2.
[0003] Figure 2 shows a hexagonal die layout on a wafer 1 in the prior art. The die 10 layout shown in the figure is a dense layout, which maximizes the usable area of the wafer. However, because the hexagonal die outlines cannot form a long straight line, after the die 10 growth process is completed, the wafer cannot be diced using the traditional low-cost dicing method shown in Figure 1. Even after laser dicing, the wafer cannot be divided using the traditional cleaving process. Instead, dicing can only be performed using a plasma etching process. However, plasma etching of wafers with a thickness of 100 to 300 micrometers (μm) has disadvantages such as high cost, time consumption, and low yield. These disadvantages urgently need to be improved. Summary of the Invention
[0004] The main objective of this invention is to provide an innovative wafer dicing manufacturing method, particularly suitable for dicing non-rectangular dies on wafers. This manufacturing method not only allows for wafer dicing using traditional linear dicing processes, but also ensures consistent image recognition from different angles by setting calibration objects in the separation areas between dies on the wafer. This improves the image positioning accuracy of the wafer dicing equipment and ensures the correctness of angle judgment by different dicing devices, thereby increasing the accuracy of wafer dicing.
[0005] To achieve the above objectives, the present invention provides a method for manufacturing a wafer dicing method, wherein the wafer has a plurality of non-perpendicular interior corners. The manufacturing method includes the following steps: First, arranging the wafer dices such that the edges of each die are aligned in a straight line, wherein a separation region surrounds adjacent dices. Second, setting a plurality of markers in each separation region. Next, after initially image positioning each marker, cutting the wafer in a straight line along the aligned edges of the dices. After rotating the wafer by an angle and image positioning each marker, cutting the wafer in a straight line along the aligned but uncut edges of the dices. Finally, repeating the previous steps until all edges of each die are cut in a straight line.
[0006] In one embodiment of the present invention, in the wafer cutting manufacturing method, when each grain is a grain with an interior angle of 120°, the edges of the grains on the wafer are aligned and arranged to form a complex first slope line, a complex second slope line, and a complex third slope line.
[0007] In one embodiment of the present invention, the wafer cutting manufacturing method involves arranging each first slope line on the wafer in a horizontal state after the initial positioning of each calibration system in the image is completed.
[0008] In one embodiment of the present invention, the wafer cutting manufacturing method involves rotating the wafer by an angle and positioning each calibration system: rotating the wafer by 60°, positioning each second slope line in a horizontal state, and then cutting each second slope line on the wafer with a straight line; rotating the wafer by 60° again, positioning each third slope line in a horizontal state, and then cutting each third slope line on the wafer with a straight line.
[0009] In one embodiment of the present invention, the wafer cutting method involves cutting the wafer in a straight line using a cutting blade.
[0010] In one embodiment of the present invention, the step of setting a plurality of calibration objects in each of the separation regions in the wafer dicing manufacturing method is to form each calibration object in each separation region by an exposure and development process.
[0011] In one embodiment of the present invention, the step of arranging the grains on the wafer to form a separation region between adjacent grains is to arrange the adjacent grains on the wafer to form a triangular region.
[0012] To achieve the above objectives, the present invention provides a method for manufacturing a wafer dicing method, wherein the wafer has a plurality of hexagonal grains, comprising the following steps: arranging the hexagonal grains on the wafer such that one edge of each hexagonal grain is aligned and arranged to form a plurality of first slope lines, a plurality of second slope lines, and a plurality of third slope lines, wherein a partition region surrounds each adjacent hexagonal grain, and the area of each partition region is smaller than that of each hexagonal grain; setting a plurality of markers in each partition region; initially image positioning each marker to position the first slope lines to a horizontal state, and then dicing the wafer along each first slope line; rotating the wafer by 60° and image positioning each marker to position the second slope lines to a horizontal state, and then dicing the wafer along each second slope line; and rotating the wafer by 60° and image positioning each marker to position the third slope lines to a horizontal state, and then dicing the wafer along each third slope line.
[0013] In one embodiment of the present invention, the wafer cutting method involves cutting the wafer in a straight line using a cutting blade.
[0014] In one embodiment of the present invention, the step of setting a plurality of calibration objects in each separation region in the wafer dicing manufacturing method is to form each calibration object in each separation region by an exposure and development process.
[0015] In one embodiment of the present invention, the step of arranging hexagonal grains on the wafer to form a separation region between adjacent hexagonal grains is to arrange adjacent hexagonal grains on the wafer to form a triangular region.
[0016] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the drawings and the embodiments described below. Simple Explanation of the Diagram
[0017] Figure 1 is a top view of a traditional wafer layout with rectangular grains; Figure 2 is a top view of a traditional wafer layout with hexagonal grains; Figure 3 is a top view schematic diagram of the wafer layout of hexagonal grains in one embodiment of the present invention; Figure 4 is a partially enlarged schematic diagram of Figure 3; Figures 5A to 5C are enlarged schematic diagrams of parts of Figure 4 under different rotation angles; Figure 6 is a top view schematic diagram of the wafer layout of hexagonal grains in another embodiment of the present invention; Figures 7A to 7C are enlarged schematic diagrams of parts of Figure 6 rotated at different angles; and Figure 8 is a schematic diagram of the wafer cutting process of the present invention. Implementation
[0018] The present invention will be explained below through embodiments. These embodiments are not intended to limit the implementation of the invention to any specific environment, application, or special method as described in the embodiments. Therefore, the descriptions of the embodiments are for illustrative purposes only and are not intended to limit the invention. It should be noted that in the following embodiments and drawings, elements not directly related to the present invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.
[0019] Please refer to Figure 3, which shows a top view of a wafer 50. The wafer 50 has a plurality of pre-diced photosensitive grains, with a separating region 30 surrounding adjacent grains 20. The area of this separating region 30 is smaller than that of each grain 20. In terms of grain appearance, each grain 20 is a hexagonal grain with non-perpendicular interior angles; more precisely, each grain 20 has an interior angle of 120°. The separating region 30 surrounded by the hexagonal grains is a triangular region. Furthermore, two electrodes 22 are provided at the upper edge of each grain 20 as the contact points for positive and negative electrodes, as shown in a partially enlarged schematic diagram in Figure 4. Although the arrangement of the grains 20 on the wafer 50 shown in Figure 3 is not the densest arrangement, its characteristic is that the six sides of each hexagonal grain are aligned with each other to form a plurality of straight lines, facilitating subsequent straight-line dicing of the wafer with a dicing blade. These lines are classified by their slope and can be divided into three categories: the first slope line L1, the second slope line L2, and the third slope line L3. Specifically, as shown in Figure 3, the first slope line L1 has a slope of 0, the second slope line L2 has a slope of... The slope of the third slope line L3 is - .
[0020] The die arrangement shown in Figure 3 allows the edges of each die to be connected into long straight lines, facilitating straight cutting on the wafer by the dicing blade and reducing the process costs required for laser or plasma cutting. It should be noted that before cutting the wafer with the dicing blade, the cutting equipment must use image positioning to identify the orientation of the die edges. Cutting can only proceed after the image confirms the die edge orientation is correct, to avoid incorrect cutting and resulting die failure and damage. Please refer to Figures 4, 5A to 5C. When using image positioning to locate the die edge, one of the two electrodes 22 of the die 20 can be used as a reference positioning point, as shown in the box in Figure 4.
[0021] Specifically, during initial image positioning, one of the electrodes 22 of the die 20 is selected as the positioning reference point. After the image confirms that the die edge orientation is correct, horizontal straight-line cutting is performed. That is, after the image positioning is correct, the first slope line L1 is in a horizontal state with a slope of 0, and the cutting equipment can perform straight-line cutting, aligning and connecting each die 20 on the wafer 50 to form the edges of the first slope line L1, as shown in Figure 5A. Next, the entire wafer 50 is rotated by an angle, for example, 60°, so that the slope of the second slope line L2 changes from the original... After the wafer is horizontalized and the image positioning is confirmed to be correct, it is cut into straight sections again using the dicing equipment. The individual dies 20 of the cut wafer 50 are aligned and connected to form the edges of the second slope line L2, as shown in Figure 5B. Similarly, the wafer is rotated 60° again so that the third slope line L3 is horizontal after the second rotation. After the image positioning is confirmed to be correct, the wafer is cut into straight sections again using the dicing equipment. The individual dies 20 of the cut wafer 50 are aligned and connected to form the edges of the third slope line L3, as shown in Figure 5C.
[0022] While the aforementioned wafer dicing method overcomes the drawback of traditional wafer dicing requiring laser or plasma methods for non-rectangular dies, the method of using one electrode on the die as a positioning reference point for image recognition still carries the possibility of image recognition failure. Specifically, as shown in Figures 5A to 5C, after calibrating an electrode 22 as a positioning reference point, the orientation of each die 20 on the wafer 50 will change when the wafer rotates at three different angles: 0°, 60°, and 120°. This orientation difference will cause difficulties in image recognition; that is, the die will produce three different images at three different orientations, causing confusion in the grayscale values of the image recognition, leading to misidentification and affecting the accuracy of wafer dicing.
[0023] In view of this, please refer to Figure 6, which shows a method for dicing a wafer in a preferred embodiment of the present invention. In this preferred embodiment, a marker 40 is provided in the separation region 30 between adjacent dies 20 on the wafer 50 to assist in image positioning and identification during wafer dicing. The marker 40 is formed in each separation region 30 during the wafer fabrication process using an exposure and development process. Specifically, referring to Figure 6, since the marker 40 in the center of the separation region 30 between adjacent dies 20 can serve as a positioning reference point for image identification, when performing a wafer dicing process similar to the aforementioned method, the image identification images at various angles will be substantially consistent. This avoids the disadvantage of grayscale value confusion and difficulty in identification in the aforementioned image identification, improving the image positioning accuracy. It also increases the accuracy of the wafer rotation angle in image identification, thereby improving the accuracy of wafer dicing.
[0024] Specifically, similar to the above, when initial image positioning is performed, a calibrator 40 is selected between the dies 20 as a positioning reference point. After the image confirms that the die edge orientation is correct, a horizontal straight line cut is performed. That is, at this point, the first slope line L1 is in a horizontal state with a slope of 0. The dies 20 are cut on the wafer 50 and aligned to form the edges of the first slope line L1, as shown in Figure 7A. Next, the entire wafer is rotated 60° to make the second slope line L2 horizontal. After the image positioning is correct, the wafer is cut again with a cutting device to align the dies 20 on the wafer 50 to form the edges of the second slope line L2, as shown in Figure 7B. Similarly, the wafer is rotated 60° again, so that the third slope line L3 becomes horizontal after the second rotation. After the image positioning and recognition are correct, the wafer is cut again using a cutting device. The cut wafer 50 and each die 20 are aligned and connected to form the edges of the third slope line L3, as shown in Figure 7C. After three cuts, the edges of each die 20 on the wafer 50 can be smoothly cut with a cutting blade. Subsequently, the non-rectangular die can be easily separated using the traditional wafer cleaving method. Moreover, the above example of a hexagonal die is only for illustrating the wafer cutting manufacturing method of the present invention, and is not intended to limit the present invention to the manufacturing method of cutting hexagonal dies. In fact, the present invention can also be applied to the cutting of other die shapes, such as parallelogram or octagonal dies.
[0025] Please refer to Figure 8, which shows a schematic flowchart of the wafer dicing process of the present invention. First, in step S01, a plurality of dies on the wafer are arranged such that one edge of each die is aligned in a straight line, wherein a separation region surrounds each adjacent die, and the area of each separation region is smaller than that of each die. In step S02, a plurality of markers are placed in each separation region. Next, in step S03, after initial image positioning of each marker, the wafer is linearly diced along the edge of the straight line formed by the dies. In step S04, after rotating the wafer by an angle and image positioning of each marker, the wafer is linearly diced along the edge of the straight line formed by the dies that has not yet been diced. Finally, in step S05, the previous steps are repeated until all edges of each die are linearly diced. The descriptions of the relevant components in the aforementioned process steps can be found above and will not be repeated here.
[0026] The above embodiments are merely illustrative of the implementation of the present invention and to explain its technical features, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention shall be determined by the scope of the patent application.
[0027] 1: Wafer 10: Grain 20: Grain 22: Electrode 30: Separator 40: Calibration material 50: Wafer L1: Line with first slope L2: The line with the second slope L3: The line with the third slope
Claims
1. A method for manufacturing a wafer dicing, the wafer having a plurality of non-perpendicular interior corners, the method comprising: arranging the wafer dices such that one edge of each of the dices is aligned in a straight line, wherein a separation region surrounds each adjacent dice, and the area of each separation region is smaller than that of each dice; setting a plurality of markers in each separation region using an exposure and development process; initially image-positioning each of the markers, and then linearly dicing the wafer along the edge of the aligned dices; rotating the wafer by an angle and image-positioning each of the markers, and then linearly dicing the wafer along the edge of the aligned dices that has not yet been diced; and repeating the previous step until all edges of each dice are linearly diced.
2. The wafer dicing manufacturing method as claimed in claim 1, wherein when each of the grains is a grain with an interior angle of 120°, the edges of the grains on the wafer are aligned to form a plurality of first slope lines, a plurality of second slope lines and a plurality of third slope lines.
3. The wafer dicing manufacturing method as described in claim 2, wherein after the image initial positioning of each of the calibration systems positions each of the first slope lines in a horizontal state, the first slope lines on the wafer are diced in a straight line.
4. The wafer dicing manufacturing method as described in claim 3, wherein the wafer is rotated by an angle and each of the calibration systems is image-positioned: the wafer is rotated by 60°, and after positioning each of the second slope lines to the horizontal state, the second slope lines on the wafer are diced in a straight line; and the wafer is rotated by 60° again, and after positioning each of the third slope lines to the horizontal state, the third slope lines on the wafer are diced in a straight line.
5. The wafer dicing method as described in claim 1, wherein the step of dicing the wafer in a straight line is performed using a dicing blade.
6. The method of manufacturing a wafer dicing as claimed in claim 2, wherein the step of arranging the grains on the wafer such that a separation region is formed between adjacent grains is to arrange the adjacent grains on the wafer to form a triangular region.
7. A method for manufacturing a wafer dicing, the wafer having a plurality of hexagonal grains, the method comprising: arranging the hexagonal grains on the wafer such that one edge of each hexagonal grain is aligned to form a plurality of first slope lines, a plurality of second slope lines, and a plurality of third slope lines, wherein a partition region surrounds adjacent hexagonal grains, and the area of each partition region is smaller than that of each hexagonal grain; setting a plurality of markers in each partition region using an exposure and development process; initially positioning each marker to position the first slope lines in a horizontal state, and then dicing the wafer along each of the first slope lines; After rotating the wafer by 60° and positioning each of the markers to make the second slope lines horizontal, the wafer is cut in a straight line along each of the second slope lines; and after rotating the wafer by 60° and positioning each of the markers to make the third slope lines horizontal, the wafer is cut in a straight line along each of the third slope lines.
8. The method of manufacturing a wafer as described in claim 7, wherein the step of cutting the wafer in a straight line is performed using a dicing blade.
9. The method of manufacturing a wafer dicing as claimed in claim 7, wherein the step of arranging the hexagonal grains on the wafer such that a separation region is formed between adjacent hexagonal grains is to arrange adjacent hexagonal grains on the wafer to form a triangular region.