Electrostatic discharge protection circuit

Abstract

An electrostatic discharge protection circuit is coupled between a first voltage terminal and a second voltage terminal, and includes first and second bipolar junction transistors. The first terminals of the first and second bipolar junction transistors are respectively coupled to the first and second voltage terminals. The second terminals of the first and second bipolar junction transistors are mutually coupled. The control terminals of the first and second bipolar junction transistors are mutually coupled. The breakdown voltage of the junction between the first terminal and the control terminal of the first bipolar junction transistor is greater than the breakdown voltage of the junction between the second terminal and the control terminal of the first bipolar junction transistor. The breakdown voltage of the junction between the first terminal and the control terminal of the second bipolar junction transistor is greater than the breakdown voltage of the junction between the second terminal and the control terminal of the second bipolar junction transistor.

Description

Technical Field

[0001] This invention relates to a circuit design technique, and more particularly to an electrostatic discharge (ESD) protection circuit. Prior Technology

[0002] Electrostatic discharge (ESD) protection circuits are primarily designed to prevent damage to circuit systems caused by the current generated during ESD events, such as human body mannequin (HBM), systemic ESD, surge surges, etc. ESD protection circuits are widely used in various integrated circuits. Depending on the specific technical application, ESD protection circuits can employ different types of transistors and diverse circuit structures. Summary of the Invention

[0003] This invention provides an electrostatic discharge protection (ESD) circuit that increases the overall anti-interference capability of the ESD circuit by using the base (B)-collector (C) junction in a heterogeneous bipolar junction transistor.

[0004] The electrostatic discharge protection circuit of this embodiment is coupled between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first bipolar junction transistor (BJT) and a second BJT. The first BJT has a first terminal, a second terminal, and a control terminal, and the first terminal of the first BJT is coupled to the first voltage terminal. The second BJT has a first terminal, a second terminal, and a control terminal, the second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to the second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. A first breakdown voltage at a first junction between the first terminal of the first BJT and the control terminal is greater than a second breakdown voltage at a second junction between the second terminal of the first BJT and the control terminal. Furthermore, the third breakdown voltage of a third junction between the first terminal of the second bipolar junction transistor and the control terminal is greater than the fourth breakdown voltage of a fourth junction between the second terminal of the second bipolar junction transistor and the control terminal.

[0005] The electrostatic discharge protection circuit of this invention is coupled between a first voltage terminal and a second voltage terminal. The electrostatic discharge protection circuit includes a first bipolar junction transistor (BJT) and a second BJT. The first BJT has a first terminal, a second terminal, and a control terminal, and the first terminal of the first BJT is coupled to the first voltage terminal. The second BJT has a first terminal, a second terminal, and a control terminal; the second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to the second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. A first doping concentration of the semiconductor material at the first end of the first bipolar junction transistor is less than a second doping concentration of the semiconductor material at the second end of the first bipolar junction transistor, and a third doping concentration of the semiconductor material at the first end of the second bipolar junction transistor is less than a fourth doping concentration of the semiconductor material at the second end of the second bipolar junction transistor.

[0006] Based on the above, the electrostatic discharge protection circuit of this embodiment of the invention uses a specific circuit structure to couple the base (B)-collector (C) junction of a heterojunction transistor to the corresponding voltage terminal, instead of using the base (B)-emitter (E) junction with a lower breakdown voltage. Therefore, in the event of a voltage electrostatic discharge (ESD) event, the ESD protection circuit can increase its anti-interference capability based on the BC junction with a higher breakdown voltage. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of an electrostatic discharge (ESD) protection circuit according to an embodiment of the present invention. Figures 2A to 2H are schematic diagrams of ESD protection circuits according to the first to eighth embodiments of the present invention. Figure 3 is a circuit diagram of an impedance circuit according to various embodiments of the present invention. Figures 4A to 4B are schematic diagrams of ESD protection circuits according to the ninth to tenth embodiments of the present invention. Figures 5A to 5G are schematic diagrams of ESD protection circuits according to the eleventh to seventeenth embodiments of the present invention. Implementation

[0008] Figure 1 is a schematic diagram of an electrostatic discharge (ESD) protection circuit 100 according to an embodiment of the present invention. The ESD protection circuit 100 is coupled between voltage terminals VN1 and VN2. The ESD protection circuit 100 can be disposed at the input or output terminal of an electronic circuit (e.g., a high-power radio frequency signal processing circuit). The aforementioned high-power radio frequency signal processing circuit is, for example, an amplifier circuit, where voltage terminal VN1 is used to input a radio frequency signal, the power of which can be greater than or equal to 30 dBm.

[0009] Under normal operating voltage conditions, the ESD protection circuit 100 will not affect the operation of the electronic circuit. Conversely, when a surge occurs at either voltage terminal VN1 or VN2 due to electrostatic discharge, the ESD protection circuit 100 can divert the surge to the other voltage terminal, thereby protecting the input or output terminal of the electronic circuit from the impact of the surge. It is assumed here that the voltage value at voltage terminal VN1 is higher than the voltage value at voltage terminal VN2.

[0010] Although ESD protection circuits can be implemented using a single heterojunction bipolar transistor (HBT), the emitter (E) of the HBT is heavily doped with semiconductor material, making it highly conductive. This results in a low breakdown voltage at the base (B)-emitter (E) junction. Therefore, during positive / negative voltage ESD events—that is, when the voltage at terminal VN1 is higher / lower than the voltage at terminal VN2 for a certain period—the base (B)-emitter (E) junction of the HBT is prone to conduction due to its low breakdown voltage, leading to a decrease in the ESD protection circuit's immunity to these events. To achieve better immunity, a larger circuit layout area is required to house the HBT within the ESD protection circuit.

[0011] This invention employs a specific circuit structure to couple the base (B)-collector (C) junction of a heterojunction bipolar junction transistor to the corresponding voltage terminals VN1 and VN2. Therefore, in the event of the aforementioned positive / negative voltage ESD events, the ESD protection circuit can increase its anti-interference capability by utilizing the BC junction, which possesses a higher breakdown voltage.

[0012] Figures 2A to 2H are schematic diagrams of ESD protection circuits 100-1 to 100-8 according to the first to eighth embodiments of the present invention. The ESD protection circuit 100-1 in Figure 2A is coupled between voltage terminals VN1 and VN2. In this embodiment, voltage terminal VN1 is exemplified by the voltage input terminal VDD, and the voltage value of voltage terminal VN1 can be positive or negative. Voltage terminal VN2 is exemplified by the reference voltage terminal GND. Users of this embodiment can adjust the voltage values ​​on voltage terminals VN1 and VN2 according to their needs.

[0013] The ESD protection circuit 100-1 in Figure 2A includes bipolar junction transistors HBT1 and HBT2 (hereinafter referred to as transistors HBT1 and HBT2). Transistors HBT1 and HBT2 are disposed on the same integrated circuit board. In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction transistors (HBTs). The materials of transistors HBT1 and HBT2 may include, for example, silicon germanium, gallium arsenide, or silicon. Transistor HBT1 has a terminal HBN11 (e.g., collector terminal), a terminal HBN12 (e.g., emitter terminal), and a control terminal HBN1C (e.g., base terminal). Terminal HBN11 of transistor HBT1 is coupled to a voltage terminal VN1.

[0014] Transistor HBT2 has terminals HBN21 (e.g., collector), HBN22 (e.g., emitter), and a control terminal HBN2C (e.g., base). Terminal HBN22 (e.g., emitter) of transistor HBT2 is coupled to terminal HBN12 (e.g., emitter) of transistor HBT1. Terminal HBN21 of transistor HBT2 is coupled to voltage terminal VN2. The control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2.

[0015] In this embodiment, the breakdown voltage of the junction between terminal HBN11 and control terminal HBN1C of transistor HBT1 (referred to as the first junction) is greater than the breakdown voltage of the junction between terminal HBN12 and control terminal HBN1C of transistor HBT1 (referred to as the second junction). Furthermore, the breakdown voltage of the junction between terminal HBN21 and control terminal HBN2C of transistor HBT2 (referred to as the third junction) is greater than the breakdown voltage of the junction between terminal HBN22 and control terminal HBN2C of transistor HBT2 (referred to as the fourth junction).

[0016] In Figure 2A, transistors HBT1 and HBT2 are NPN type heterojunction bipolar transistors. The terminal HBN11 of transistor HBT1 in Figure 2A is formed of semiconductor material M1, and the control terminal HBN1C of transistor HBT1 is formed of semiconductor material M2. The terminal HBN21 of transistor HBT2 is formed of semiconductor material M3, and the control terminal HBN2C of transistor HBT2 is formed of semiconductor material M4. The terminals HBN12 of transistor HBT1 and HBN22 of transistor HBT2 are both formed of semiconductor material M5.

[0017] Semiconductor materials M1, M3, and M5 in Figure 2A have the same conductivity type, such as N-type or P-type conductivity. Semiconductor materials M2 and M4 have the same conductivity type, but different conductivity types from the aforementioned semiconductor materials M1, M3, and M5. That is, as in the embodiment of Figure 2A, semiconductor materials M1, M3, and M5 are N-type conductivity semiconductor materials, while semiconductor materials M2 and M4 are P-type conductivity semiconductor materials. On the other hand, in the similar embodiment of Figure 2C described later, semiconductor materials M1, M3, and M5 are P-type conductivity semiconductor materials, while semiconductor materials M2 and M4 are N-type conductivity semiconductor materials.

[0018] In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction bipolar junction transistors. Therefore, semiconductor material M5 is different from semiconductor material M1 or semiconductor material M3.

[0019] In Figure 2A, semiconductor materials M1 and M3 are each lightly doped N-type semiconductor materials. Semiconductor materials M2 and M4 are each P-type semiconductor materials. Semiconductor material M5 is a heavily doped N-type semiconductor material. Therefore, it is possible to achieve a situation where the breakdown voltage of the first junction in transistor HBT1 is greater than the breakdown voltage of the second junction in transistor HBT1, and the breakdown voltage of the third junction in transistor HBT2 is greater than the breakdown voltage of the fourth junction in transistor HBT2. In other words, the doping concentration of semiconductor material M1 forming terminal HBN11 of transistor HBT1 will be less than the doping concentration of semiconductor material M5 forming terminal HBN12 of transistor HBT1, and the doping concentration of semiconductor material M3 forming terminal HBN21 of transistor HBT2 will be less than the doping concentration of semiconductor material M5 forming terminal HBN22 of transistor HBT2. The doping concentration of semiconductor material M1 is, for example, equivalent to the doping concentration of semiconductor material M3.

[0020] In this embodiment, both transistors HBT1 and HBT2 are designed as identical NPN or PNP heterojunction bipolar transistors. Therefore, the breakdown voltage of the first junction is equal to the breakdown voltage of the third junction, and the breakdown voltage of the second junction is equal to the breakdown voltage of the fourth junction.

[0021] The ESD protection circuit 100-1 in Figure 2A further includes an impedance circuit 210. The impedance circuit 210 is coupled between the control terminal HBN1C of transistor HBT1 and the control terminal HBN2C of transistor HBT2. The detailed circuit structure of the impedance circuit 210 can be found in Figure 3 and the corresponding embodiment description below.

[0022] Impedance circuit 210 provides a bias voltage to turn on transistors HBT1 and HBT2 when an ESD event occurs, thereby allowing transistors HBT1 and HBT2 to discharge ESD current. In this embodiment, the product of the impedance value of impedance circuit 210 and the breakdown current of the first junction in transistor HBT1 is greater than or equal to the turn-on voltage of the second junction in transistor HBT1. Referring to FIG2A, an ESD event occurs when the voltage value of voltage terminal VN1 is greater than the voltage value of voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the first junction in transistor HBT1 (the junction between terminal HBN11 and control terminal HBN1C). At this time, since terminal HBN11 of transistor HBT1 is formed of a lightly doped semiconductor material, the breakdown voltage of the first junction of transistor HBT1 is high, thus resulting in higher anti-interference capability. Therefore, the first junction of transistor HBT1 will not be damaged, and a breakdown current will be generated. The breakdown current can flow through the impedance circuit 210 along the path indicated by the dashed arrow 215 in Figure 2A. When the product of the impedance value of the impedance circuit 210 and the breakdown current at the first junction of transistor HBT1 is greater than the turn-on voltage of the second junction (the junction between terminal HBN12 and control terminal HBN1C) of transistor HBT1, transistor HBT1 can be turned on, and the aforementioned breakdown current can turn on transistor HBT2, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN1 through transistors HBT1 and HBT2 to voltage terminal VN2. On the other hand, when the voltage value at voltage terminal VN1 is less than the voltage value at voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the third junction (the junction between terminal HBN21 and control terminal HBN2C) of transistor HBT2, an ESD event occurs. At this time, since the HBN21 terminal of transistor HBT2 is formed of a lightly doped semiconductor material, the breakdown voltage of the third junction of transistor HBT2 is relatively high, resulting in higher anti-interference capability. Therefore, the third junction of transistor HBT2 will not be damaged, and a breakdown current will be generated. The breakdown current can flow through the impedance circuit 210 along the path indicated by the dashed arrow 225 shown in Figure 2A. When the product of the impedance value of the impedance circuit 210 and the breakdown current of the third junction in transistor HBT2 is greater than the conduction voltage of the fourth junction in transistor HBT2 (the junction between terminal HBN22 and control terminal HBN1C), transistor HBT2 can be turned on, and the aforementioned breakdown current can turn on transistor HBT1, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from the voltage terminal VN2 through transistors HBT2 and HBT1 to the voltage terminal VN1.

[0023] In Figures 2A and 2B, transistors HBT1 and HBT2 are both NPN type heterojunction bipolar transistors. The difference between the ESD protection circuit 100-2 in Figure 2B and the ESD protection circuit 100-1 in Figure 2A is that in ESD protection circuit 100-2, terminal HBN12 of transistor HBT1 is coupled to the control terminal HBN1C of transistor HBT1, and terminal HBN22 of transistor HBT2 is coupled to the control terminal HBN2C of transistor HBT2. Furthermore, terminal HBN22 of transistor HBT1 is coupled to terminal HBN22 of transistor HBT2. On the other hand, the ESD protection circuit 100-2 in Figure 2B includes impedance circuits 210 and 220. Impedance circuit 210 is coupled between the control terminal HBN1C and terminal HBN12 of transistor HBT1. Impedance circuit 220 is coupled between the control terminal HBN2C and terminal HBN22 of transistor HBT2. For detailed circuit structures of impedance circuits 210 and 220, please refer to Figure 3 and the corresponding embodiment description below.

[0024] Impedance circuits 210 and 220 can provide bias voltage to turn on transistors HBT1 and HBT2 when an ESD event occurs, thereby allowing transistors HBT1 and HBT2 to discharge ESD current. In this embodiment, the sum of the impedance values ​​of impedance circuit 210 and impedance circuit 220 is the comprehensive impedance value. The product of the comprehensive impedance value and the breakdown current of the first junction in transistor HBT1 is greater than or equal to the turn-on voltage of the second junction in transistor HBT1. Referring to FIG2B, when the voltage value of voltage terminal VN1 is greater than the voltage value of voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the first junction (the junction between terminal HBN11 and control terminal HBN1C) in transistor HBT1, an ESD event occurs. At this time, since terminal HBN11 of transistor HBT1 is formed of a lightly doped semiconductor material, the breakdown voltage of the first junction of transistor HBT1 is higher, thereby improving the anti-interference capability. Therefore, the first junction of transistor HBT1 will not be damaged, and a breakdown current will be generated. The breakdown current can flow through impedance circuits 210 and 220 along the path indicated by dashed arrow 215 in Figure 2B. When the product of the combined impedance of impedance circuits 210 and 220 and the breakdown current of the first junction of transistor HBT1 is greater than the on-state voltage of the second junction of transistor HBT1 (the junction between terminal HBN12 and control terminal HBN1C), transistor HBT1 can be turned on, and the aforementioned breakdown current can turn on transistor HBT2, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN1 through transistors HBT1 and HBT2 to voltage terminal VN2. On the other hand, an ESD event occurs when the voltage value at voltage terminal VN1 is less than the voltage value at voltage terminal VN2, and the voltage difference between voltage terminals VN1 and VN2 is greater than the breakdown voltage of the third junction (the junction between terminal HBN21 and control terminal HBN2C) in transistor HBT2. At this time, since terminal HBN21 of transistor HBT2 is formed of a lightly doped semiconductor material, the breakdown voltage of the third junction of transistor HBT2 is relatively high, resulting in higher anti-interference capability. Therefore, the third junction of transistor HBT2 will not be damaged, and a breakdown current is generated. The breakdown current can flow through impedance circuit 210 along the path indicated by dashed arrow 225 shown in Figure 2B. When the combined impedance of impedance circuits 210 and 220, plus the breakdown current at the third junction of transistor HBT2, exceeds the turn-on voltage at the fourth junction of transistor HBT2 (the junction between terminal HBN22 and control terminal HBN1C), transistor HBT2 can be turned on. Furthermore, the aforementioned breakdown current can turn on transistor HBT1, thus forming an ESD current discharge path. In this way, the ESD current can be conducted from voltage terminal VN2 through transistors HBT2 and HBT1 to voltage terminal VN1.

[0025] Compared to Figures 2A and 2B, ESD protection circuit 100-3 in Figure 2C and ESD protection circuit 100-4 in Figure 2D use different types of heterojunction bipolar transistors to implement transistors HBT1 and HBT2. In both Figures 2C and 2D, transistors HBT1 and HBT2 are PNP type heterojunction bipolar transistors. That is, the coupling relationship of the circuit structures in Figures 2A and 2C is the same; the only difference is whether transistors HBT1 and HBT2 are NPN or PNP type heterojunction bipolar transistors. Similarly, the coupling relationship of the circuit structures in Figures 2B and 2D is the same; the only difference is whether transistors HBT1 and HBT2 are NPN or PNP type heterojunction bipolar transistors. In Figures 2C and 2D, the semiconductor materials M1 and M3 of transistors HBT1 and HBT2 are both low-doped P-type semiconductor materials, M2 and M4 are both N-type semiconductor materials, and M5 is a high-doped P-type semiconductor material.

[0026] Compared to Figures 2A to 2D, the transistors HBT1 and HBT2 in the ESD protection circuits 100-5 to 100-8 in Figures 2E to 2H are implemented using different types of heterojunction bipolar transistors. For example, Figures 2E and 2F use PNP and NPN transistors to implement transistors HBT1 and HBT2 respectively; Figures 2G and 2H use NPN and PNP transistors to implement transistors HBT1 and HBT2 respectively. In Figures 2E to 2G, the terminal HBN11 of transistor HBT1 is formed of semiconductor material M1, and the control terminal HBN1C of transistor HBT1 is formed of semiconductor material M2. The terminal HBN21 of transistor HBT2 is formed of semiconductor material M3, and the control terminal HBN2C of transistor HBT2 is formed of semiconductor material M4. The HBN12 terminal of transistor HBT1 is formed of semiconductor material M5, and the HBN22 terminal of transistor HBT2 is formed of semiconductor material M6. The doping concentration of semiconductor material M1 forming the HBN11 terminal of transistor HBT1 will be less than the doping concentration of semiconductor material M5 forming the HBN12 terminal of transistor HBT1, and the doping concentration of semiconductor material M3 forming the HBN21 terminal of transistor HBT2 will be less than the doping concentration of semiconductor material M6 forming the HBN22 terminal of transistor HBT2. The doping concentration of semiconductor material M1 is, for example, equivalent to the doping concentration of semiconductor material M3. The doping concentration of semiconductor material M5 is, for example, equivalent to the doping concentration of semiconductor material M6.

[0027] Semiconductor materials M1, M4, and M5 in Figures 2E and 2F have the same conductivity type, such as N-type or P-type conductivity. Semiconductor materials M2, M3, and M6 have the same conductivity type, but different conductivity types from those of the aforementioned semiconductor materials M1, M4, and M5. That is, as in the embodiments of Figures 2E and 2F, semiconductor materials M1, M4, and M5 are P-type conductivity semiconductor materials, while semiconductor materials M2, M3, and M6 are N-type conductivity semiconductor materials. On the other hand, in the similar embodiments Figures 2G and 2H described later, semiconductor materials M1, M4, and M5 are N-type conductivity semiconductor materials, while semiconductor materials M2, M3, and M6 are P-type conductivity semiconductor materials.

[0028] In this embodiment, transistors HBT1 and HBT2 are implemented using heterojunction bipolar junction transistors. Therefore, semiconductor material M1 is different from semiconductor material M5, and semiconductor material M3 is different from semiconductor material M6.

[0029] In the ESD protection circuit 100-5 of Figure 2E and the ESD protection circuit 100-6 of Figure 2F, transistor HBT1 is a PNP type heterojunction bipolar transistor, and transistor HBT2 is an NPN type heterojunction bipolar transistor. Specifically, semiconductor material M1 is a lightly doped P-type semiconductor material, semiconductor material M2 is an N-type semiconductor material, and semiconductor material M3 is a lightly doped N-type semiconductor material. Semiconductor material M4 is a P-type semiconductor material, semiconductor material M5 is a heavily doped P-type semiconductor material, and semiconductor material M6 is a heavily doped N-type semiconductor material.

[0030] In Figure 2E, the control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2 through impedance circuit 210.

[0031] In Figure 2F, the control terminal HBN1C of transistor HBT1 is coupled to terminal HBN12 of transistor HBT1 through impedance circuit 210. The control terminal HBN2C of transistor HBT2 is coupled to terminal HBN22 of transistor HBT2 through impedance circuit 220. Furthermore, terminal HBN12 of transistor HBT1 is coupled to terminal HBN22 of transistor HBT2.

[0032] In the ESD protection circuit 100-7 of Figure 2G and the ESD protection circuit 100-8 of Figure 2H, transistor HBT1 is an NPN heterojunction bipolar transistor, and transistor HBT2 is a PNP heterojunction bipolar transistor. Specifically, semiconductor material M1 is a lightly doped N-type semiconductor material, semiconductor material M2 is a P-type semiconductor material, and semiconductor material M3 is a lightly doped P-type semiconductor material. Semiconductor material M4 is an N-type semiconductor material, semiconductor material M5 is a heavily doped N-type semiconductor material, and semiconductor material M6 is a heavily doped P-type semiconductor material.

[0033] In Figure 2G, the control terminal HBN1C of transistor HBT1 is coupled to the control terminal HBN2C of transistor HBT2 through impedance circuit 210.

[0034] In Figure 2H, the control terminal HBN1C of transistor HBT1 is coupled to terminal HBN12 of transistor HBT1 through impedance circuit 210. The control terminal HBN2C of transistor HBT2 is coupled to terminal HBN22 of transistor HBT2 through impedance circuit 220. Furthermore, terminal HBN12 of transistor HBT1 is coupled to terminal HBN22 of transistor HBT2.

[0035] Figure 3 is a circuit diagram of impedance circuit 210 according to various embodiments of the present invention. Impedance circuits 210 and 220 of various embodiments of the present invention can be implemented by impedance circuits 211-1 to 211-9 in Figure 3 or other circuit structures. Impedance circuits 210, 220, 210-1 to 210-M (representing 210-1, 210-2, 210-3, and so on up to 210-M) and 220-1 to 220-N (representing 220-1, 220-2, 220-3, and so on up to 220-N) in various embodiments of the present invention can be the same circuit structure, or can be arbitrarily selected from impedance circuits 211-1 to 211-9 in Figure 3.

[0036] The various impedance circuits 211-1 to 211-9 in Figure 3 may include one or a combination of a resistor R1 (impedance circuit 211-1), a capacitor C1 (impedance circuit 211-2), an inductor L1 (impedance circuit 211-3), at least one diode (e.g., diodes D1 and D2), at least one first field-effect transistor (e.g., field-effect transistors FET1 and FET2), and at least one first metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., metal-oxide-semiconductor field-effect transistors M1 and M2). Impedance circuits 211-4 and 211-5 respectively include one or more diodes D1 and D2 connected in series. In other words, impedance circuits 211-4 and 211-5 are formed by stacking multiple diodes D1 and D2.

[0037] Impedance circuits 211-6 and 211-7 are each composed of multiple field-effect transistors (FETs) 1 or 2 connected in series. The control terminal of each FET 1 or FET 2 is coupled to its source or drain terminal. The FET 1 or FET 2 can be N-type or P-type FETs. In other words, impedance circuits 211-6 and 211-7 are formed by stacking multiple FETs 1 and FET 2.

[0038] Impedance circuits 211-8 and 211-9 are each composed of multiple MOSFETs M1 or M2 connected in series, with the control terminal of each MOSFET M1 or M2 coupled to its source or drain terminal. MOSFETs M1 or M2 can be N-type or P-type field-effect transistors. In other words, impedance circuits 211-8 and 211-9 are formed by stacking multiple MOSFETs M1 and M2, respectively.

[0039] In Figures 2A to 2H, the terminal HBN12 of transistor HBT1 is directly coupled to the terminal HBN22 of transistor HBT2. In this embodiment, the terminal HBN12 of transistor HBT1 can be coupled to the terminal HBN22 of transistor HBT2 through one or more intermediate transistors, as shown in Figures 4A-4B and 5A-5G.

[0040] Figures 4A to 4B are circuit diagrams of ESD protection circuits 100-9 to 100-10 according to the ninth to tenth embodiments of the present invention. The transistors HBT1, HBT2, and HBTM1 and HBTM2 in Figures 4A to 4B are all based on NPN heterojunction bipolar transistors. The terminal (e.g., emitter terminal) of transistor HBT1 is coupled to the terminal (e.g., emitter terminal) of transistor HBT2 through one or more intermediate transistors (e.g., one or more transistors HBTM1 and HBTM2 in Figures 4A-4B and 5A-5G). An impedance circuit 210-1 to 210-M (representing 210-1, 210-2, 210-3, and so on up to 210-M) can be provided between the control terminal of transistor HBT1 and the control terminal of the next stage transistor (e.g., transistor HBTM1) in Figure 4A. It is worth noting that, in the variant embodiment of Figure 4A, the impedance circuit can use only the impedance circuit 210-M closest to the middle (this impedance circuit 210-M is coupled to the control terminal of transistor HBTM1 and the control terminal of transistor HBTM2), and the impedance circuits 210-1, 210-2, 210-3...210-(M-1) can be omitted. Figure 4B further shows that impedance circuits 220-1 to 220-N (represented as arranged from 220-1, 220-2, 220-3 to 220-N) can be additionally provided between the control terminal of transistor HBT2 and the control terminal of the next stage transistor (e.g., transistor HBTM2). It is worth noting that, in the variant embodiment of Figure 4B, the impedance circuit can use only the impedance circuit 210-M closest to the middle and the impedance circuit 220-N (this impedance circuit 210-M is directly coupled to this impedance circuit 220-N), and the impedance circuits 210-1, 210-2, 210-3…210-(M-1) and the impedance circuits 220-1, 220-2, 220-3…220-(N-1) can be omitted.

[0041] The control terminals of the transistors HBTM1 and HBTM2 closest to the center may not be coupled to their emitter terminals (as shown in Figure 4A), or the control terminals of the transistors HBTM1 and HBTM2 closest to the center may be coupled to their emitter terminals (as shown in Figure 4B). The transistors HBT1 and HBT2 will be coupled to the voltage terminals VN1 and VN2 via BC junctions with high breakdown voltages.

[0042] On the other hand, the series connection method of each junction between transistors (e.g., transistors HBTM1 and HBTM2) located between transistors HBT1 and HBT2 is not limited to the embodiments of the present invention. Figures 5A to 5G are circuit diagrams of ESD protection circuits 100-11 to 100-17 according to the eleventh to seventeenth embodiments of the present invention, respectively. The difference between Figure 5A and Figure 4B is that the coupling method between the emitter and collector terminals of the transistor HBTM1 closest to the middle in ESD protection circuit 100-11 in Figure 5A is different from that of transistor HBTM1 in ESD protection circuit 100-10 in Figure 4B.

[0043] The difference between Figure 5B and Figure 4B is that the coupling method between the emitter and collector terminals of the transistor HBTM2, which is closest to the middle in the ESD protection circuit 100-12 in Figure 5B, is different from that of the transistor HBTM2 in the ESD protection circuit 100-10 in Figure 4B.

[0044] In Figures 5C to 5E, the transistors HBT1 and HBT2 in ESD protection circuits 100-13 to 100-15 are PNP type heterojunction bipolar transistors, which are different from ESD protection circuit 100-10 in Figure 4B. Furthermore, the transistors HBTM1 and HBTM2 in ESD protection circuit 100-13 in Figure 5C are NPN type heterojunction bipolar transistors.

[0045] In Figure 5D, the ESD protection circuit 100-14 uses a PNP type heterojunction bipolar transistor HBTM1 and an NPN type heterojunction bipolar transistor HBTM2.

[0046] In Figure 5E, the ESD protection circuit 100-15 uses an NPN type heterojunction bipolar transistor HBTM1 and a PNP type heterojunction bipolar transistor HBTM2.

[0047] In Figure 5F, the ESD protection circuit 100-16 uses a PNP type heterojunction bipolar transistor HBT1, and NPN type heterojunction bipolar transistors HBTM1, HBTM2 and HBT2.

[0048] In Figure 5G, the transistors HBT1 and HBTM2 in the ESD protection circuit 100-17 are NPN type heterojunction bipolar transistors, and the transistors HBTM1 and HBT2 are PNP type heterojunction bipolar transistors.

[0049] In summary, the electrostatic discharge protection circuit of this invention, through a specific circuit structure, utilizes the base (B)-collector (C) junction of a heterojunction transistor to couple to the corresponding voltage terminal, instead of using the base (B)-emitter (E) junction with a lower breakdown voltage. Therefore, in the event of a voltage electrostatic discharge (ESD) event, the ESD protection circuit can increase its anti-interference capability based on the BC junction with a higher breakdown voltage.

[0050] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0051] 100, 100-1~100-17: Electrostatic discharge protection circuit 210, 220, 210-1~210-M, 220-1~220-N, 211-1~211-9: Impedance circuits 215, 225: Dashed arrows HBT1, HBT2, HBTM1, HBTM2: Bipolar Junction Transistor / Transistor HBN11, HBN12, HBN21, HBN22: Terminals of bipolar junction transistors HBN1C, HBN2C: Control terminals of bipolar junction transistors VN1, VN2: Voltage terminals M1~M6: Semiconductor materials VDD: Voltage input terminal GND: Reference voltage terminal R1: Resistor C1: Capacitor L1: Inductor D1, D2: Diodes FET1, FET2: Field-Effect Transistors M1, M2: Metal-oxide-semiconductor field-effect transistors

Claims

1. An electrostatic discharge protection circuit, coupled between a first voltage terminal and a second voltage terminal, the electrostatic discharge protection circuit comprising: A first bipolar junction transistor has a first terminal, a second terminal and a control terminal, and the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal. The system also includes a second bipolar junction transistor (BJT), having a first terminal, a second terminal, and a control terminal. The second terminal of the second BJT is coupled to the second terminal of the first BJT, the first terminal of the second BJT is coupled to the second voltage terminal, and the control terminal of the first BJT is coupled to the control terminal of the second BJT. A first breakdown voltage at a first junction between the first terminal and the control terminal of the first BJT is greater than a second breakdown voltage at a second junction between the second terminal and the control terminal of the first BJT. Furthermore, a third breakdown voltage at a third junction between the first terminal and the control terminal of the second BJT is greater than a fourth breakdown voltage at a fourth junction between the second terminal and the control terminal of the second BJT. The first end of the first bipolar junction transistor is a first collector, the second end of the first bipolar junction transistor is a first emitter, the first end of the second bipolar junction transistor is a second collector, and the second end of the second bipolar junction transistor is a second emitter.

2. The electrostatic discharge protection circuit as claimed in claim 1, wherein the first terminal of the first bipolar junction transistor is formed of a first type semiconductor material, the control terminal of the first bipolar junction transistor is formed of a second type semiconductor material, the first terminal of the second bipolar junction transistor is formed of a third type semiconductor material, the control terminal of the second bipolar junction transistor is formed of a fourth type semiconductor material, and the second terminals of both the first and second bipolar junction transistors are formed of a fifth type semiconductor material. The first type semiconductor material, the third type semiconductor material, and the fifth type semiconductor material have the same conductivity type, and the fifth type semiconductor material is different from the first type semiconductor material or the third type semiconductor material. The second type semiconductor material and the fourth type semiconductor material have the same conductivity type.

3. The electrostatic discharge protection circuit as claimed in claim 2, wherein the first type semiconductor material and the third type semiconductor material are each a lightly doped N-type semiconductor material, the second type semiconductor material and the fourth type semiconductor material are each a P-type semiconductor material, and the fifth type semiconductor material is a heavily doped N-type semiconductor material.

4. The electrostatic discharge protection circuit as claimed in claim 2, wherein the first type semiconductor material and the third type semiconductor material are each a lightly doped P-type semiconductor material, the second type semiconductor material and the fourth type semiconductor material are each an N-type semiconductor material, and the fifth type semiconductor material is a heavily doped P-type semiconductor material.

5. The electrostatic discharge protection circuit as claimed in claim 1, wherein the first terminal of the first bipolar junction transistor is formed of a first type semiconductor material, the control terminal of the first bipolar junction transistor is formed of a second type semiconductor material, the first terminal of the second bipolar junction transistor is formed of a third type semiconductor material, the control terminal of the second bipolar junction transistor is formed of a fourth type semiconductor material, the second terminal of the first bipolar junction transistor is formed of a fifth type semiconductor material, and the second terminal of the second bipolar junction transistor is formed of a sixth type semiconductor material, wherein... The first type semiconductor material, the fourth type semiconductor material, and the fifth type semiconductor material have the same conductivity type, and the second type semiconductor material, the third type semiconductor material, and the sixth type semiconductor material have the same conductivity type.

6. The electrostatic discharge protection circuit as described in claim 5, wherein: The first type of semiconductor material is a lightly doped P-type semiconductor material, the second type of semiconductor material is an N-type semiconductor material, the third type of semiconductor material is a lightly doped N-type semiconductor material, the fourth type of semiconductor material is a P-type semiconductor material, the fifth type of semiconductor material is a heavily doped P-type semiconductor material, and the sixth type of semiconductor material is a heavily doped N-type semiconductor material; or, the first type of semiconductor material is a lightly doped N-type semiconductor material, the second type of semiconductor material is a P-type semiconductor material, the third type of semiconductor material is a lightly doped P-type semiconductor material, the fourth type of semiconductor material is an N-type semiconductor, the fifth type of semiconductor material is a heavily doped N-type semiconductor material, and the sixth type of semiconductor material is a heavily doped P-type semiconductor material.

7. The electrostatic discharge protection circuit as claimed in claim 1, wherein the first breakdown voltage is equal to the third breakdown voltage, and the second breakdown voltage is equal to the fourth breakdown voltage.

8. The electrostatic discharge protection circuit as claimed in claim 1, wherein the first emitter is coupled to the second emitter.

9. The electrostatic discharge protection circuit as claimed in claim 1, wherein the second terminal of the first bipolar junction transistor is coupled to the second terminal of the second bipolar junction transistor via one or more intermediate transistors.

10. The electrostatic discharge protection circuit as claimed in claim 1 further includes a first impedance circuit and a second impedance circuit, the first impedance circuit being coupled between the control terminal and the second terminal of the first bipolar junction transistor, the second impedance circuit being coupled between the control terminal and the second terminal of the second bipolar junction transistor, and the second terminal of the first bipolar junction transistor being coupled to the second terminal of the second bipolar junction transistor.

11. The electrostatic discharge protection circuit of claim 10, wherein the first impedance circuit includes one or a combination of a first resistor, a first capacitor, a first inductor, a first diode, at least one first field-effect transistor and at least one first metal-oxide-semiconductor field-effect transistor, and the second impedance circuit includes one or a combination of a second resistor, a second capacitor, a second inductor, a second diode, at least one second field-effect transistor and at least one second metal-oxide-semiconductor field-effect transistor.

12. The electrostatic discharge protection circuit as claimed in claim 10, wherein the sum of the impedance values ​​of the first impedance circuit and the second impedance circuit is a composite impedance value; when the voltage value of the first voltage terminal is greater than the voltage value of the second voltage terminal and an electrostatic discharge event occurs, the product of the composite impedance value and a first breakdown current of the first junction of the first bipolar junction transistor is greater than or equal to a first on-state voltage of the second junction of the first bipolar junction transistor; and when the voltage value of the second voltage terminal is greater than the voltage value of the first voltage terminal and an electrostatic discharge event occurs, the product of the composite impedance value and a third breakdown current of the third junction of the second bipolar junction transistor is greater than or equal to a second on-state voltage of the fourth junction of the second bipolar junction transistor.

13. The electrostatic discharge protection circuit as claimed in claim 1 further includes a first impedance circuit coupled between the control terminal of the first bipolar junction transistor and the control terminal of the second bipolar junction transistor.

14. The electrostatic discharge protection circuit as claimed in claim 13, wherein the first impedance circuit comprises one or a combination of a resistor, a capacitor, an inductor, a diode, a field-effect transistor, and a metal-oxide-semiconductor field-effect transistor.

15. The electrostatic discharge protection circuit as claimed in claim 13, wherein when the voltage value of the first voltage terminal is greater than the voltage value of the second voltage terminal and an electrostatic discharge event occurs, the product of the impedance value of the first impedance circuit and a first breakdown current of the first bipolar junction transistor at the first junction is greater than or equal to a first on-state voltage of the second junction of the first bipolar junction transistor; and when the voltage value of the second voltage terminal is greater than the voltage value of the first voltage terminal and an electrostatic discharge event occurs, the product of the impedance value of the first impedance circuit and a third breakdown current of the third junction of the second bipolar junction transistor is greater than or equal to a second on-state voltage of the fourth junction of the second bipolar junction transistor.

16. The electrostatic discharge protection circuit as claimed in claim 1, wherein both the first bipolar junction transistor and the second bipolar junction transistor are heterojunction bipolar transistors.

17. The electrostatic discharge protection circuit as claimed in claim 1, wherein the first voltage terminal is a voltage input terminal and the second voltage terminal is a reference voltage terminal.

18. The electrostatic discharge protection circuit as claimed in claim 1, wherein the electrostatic discharge protection circuit is used in a high-power radio frequency signal processing circuit.

19. An electrostatic discharge protection circuit, coupled between a first voltage terminal and a second voltage terminal, the electrostatic discharge protection circuit comprising: A first bipolar junction transistor has a first terminal, a second terminal and a control terminal, and the first terminal of the first bipolar junction transistor is coupled to the first voltage terminal. The second bipolar junction transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the second bipolar junction transistor is coupled to the second terminal of the first bipolar junction transistor. The first terminal of the second bipolar junction transistor is coupled to the second voltage terminal, and the control terminal of the first bipolar junction transistor is coupled to the control terminal of the second bipolar junction transistor. A first doping concentration of the semiconductor material forming the first terminal of the first bipolar junction transistor is less than a second doping concentration of the semiconductor material forming the second terminal of the first bipolar junction transistor. A third doping concentration of the semiconductor material forming the first terminal of the second bipolar junction transistor is less than a fourth doping concentration of the semiconductor material forming the second terminal of the second bipolar junction transistor.

20. The electrostatic discharge protection circuit as claimed in claim 19, wherein the first doping concentration is equal to the third doping concentration, and the second doping concentration is equal to the fourth doping concentration.

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