Circuit substrate and manufacturing method thereof

Abstract

A circuit board includes a dielectric layer, a first conductor layer, a first ground element, and a plurality of signal lines. The first conductor layer is disposed on one side of the dielectric layer. The first ground element protrudes from the first conductor layer and is disposed within the dielectric layer. The signal lines are disposed within the dielectric layer and located on one side of the first ground element. The projection of each signal line onto the first conductor layer is adjacent to the projection of the first ground element onto the first conductor layer, but the projections of each signal line onto the first conductor layer do not contact the projection of the first ground element onto the first conductor layer.

Description

Technical Field

[0001] This invention relates to a circuit board, and more particularly to a circuit board with a prominent grounding barrier. The invention also relates to a method for manufacturing this circuit board. Prior Technology

[0002] Due to technological advancements, the demand for integrated circuit boards (ICBs) has increased significantly. Therefore, improving the performance of ICBs has become an important issue.

[0003] Existing integrated circuit boards primarily reduce crosstalk by minimizing coupling (e.g., reducing the coupling coefficient or the coupling length). Specifically, there are two methods: reducing the coupling coefficient and reducing the coupling length.

[0004] However, for D2D (Die-to-Die) connection structures in modern 2.XD (such as 2.1D, 2.3D, 2.5D) or 3D packaging architectures, the coupling length has been reduced to near the technical limit, making it difficult to reduce crosstalk by reducing the coupling length.

[0005] Existing integrated circuit boards primarily reduce coupling coefficients using two methods. One method is to significantly increase the pitch of signal lines to reduce coupling coefficients. The other method is to add a ground wire between two signal lines. Summary of the Invention

[0006] According to one embodiment of the present invention, a circuit board is provided, comprising a dielectric layer, a first conductor layer, a first ground element, and a plurality of signal lines. The first conductor layer is disposed on one side of the dielectric layer. The first ground element protrudes from the first conductor layer and is disposed within the dielectric layer. The signal lines are disposed within the dielectric layer and located on one side of the first ground element. The projection of each signal line onto the first conductor layer is adjacent to the projection of the first ground element onto the first conductor layer, but the projections of each signal line onto the first conductor layer do not contact the projection of the first ground element onto the first conductor layer.

[0007] According to another embodiment of the present invention, a circuit board is provided, comprising a dielectric layer, a first conductor layer, a plurality of first ground elements, and a plurality of signal lines. The first conductor layer is disposed on one side of the dielectric layer. The first ground elements protrude from the first conductor layer and are disposed within the dielectric layer. The signal lines are disposed within the dielectric layer and located on one side of the first ground elements. The projection of each signal line onto the first conductor layer is adjacent to the projection of at least one first ground element onto the first conductor layer, but the projection of each signal line onto the first conductor layer does not contact the projection of any first ground element onto the first conductor layer.

[0008] According to another embodiment of the present invention, a method for manufacturing a circuit board is provided, comprising the following steps: providing an insulating substrate; performing a first metal layer coating process to form a first metal layer on the insulating substrate; performing a first photolithography process on the first metal layer to form a first ground element and a first conductor layer; performing a dielectric layer formation process to form a dielectric layer covering the first conductor layer and the first ground element; performing an aperture forming process to form an opening in the dielectric layer and expose the first ground element through the opening; performing a second metal layer coating process to form a second metal layer on the dielectric layer; performing a polishing process to remove the second metal layer outside the opening in the dielectric layer; performing a third metal layer coating process to form a third metal layer on the dielectric layer; and performing a second photolithography process on the third metal layer to form a plurality of signal lines.

[0009] As described above, the circuit board has a first grounding element, which protrudes from the first conductive layer of the circuit board and is disposed within the dielectric layer of the circuit board. The signal lines of the circuit board are disposed within the dielectric layer and located on one side of the first grounding element. The projection of each signal line onto the first conductive layer is adjacent to the projection of the first grounding element onto the first conductive layer, but the projections of each signal line onto the first conductive layer do not contact the projection of the first grounding element onto the first conductive layer. The aforementioned first grounding element protrudes from the first conductive layer to form a protruding grounding barrier, which can effectively isolate electromagnetic fields to reduce crosstalk between signal lines. Therefore, the circuit board can effectively solve the problem of crosstalk generated under high-speed signal transmission and high-frequency operation conditions to meet the needs of various applications.

[0010] Furthermore, each signal line on the circuit board is extremely close to at least one first grounding element but does not make contact with it. Therefore, the first grounding element not only acts as a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines, but also prevents micro-short circuits and leakage current. Thus, the reliability of the circuit board can be significantly improved, meeting the requirements of practical applications.

[0011] Furthermore, the circuit board's structural design is scalable, allowing integration with existing processes and applicability to various heterogeneous packaging structures. This significantly reduces the circuit board's area while achieving high signal density. Consequently, the circuit board's computing power and processing time can be greatly improved to meet the demands of high-performance computing (HPC) and artificial intelligence (AI) fields. Therefore, the circuit board truly aligns with future development trends. Simple Explanation of the Diagram

[0012] Figure 1 is a cross-sectional view of the circuit board of the first embodiment of the present invention. Figure 2 is a first schematic diagram of the circuit board according to the first embodiment of the present invention. Figure 3 is a second schematic diagram of the circuit board of the first embodiment of the present invention. Figure 4 is a cross-sectional view of the circuit board according to the second embodiment of the present invention. Figure 5 is a first schematic diagram of the circuit board according to the second embodiment of the present invention. Figure 6 is a second schematic diagram of the circuit board according to the second embodiment of the present invention. Figure 7 is a cross-sectional view of the circuit board according to the third embodiment of the present invention. Figure 8 is a cross-sectional view of the circuit board according to the fourth embodiment of the present invention. Figure 9 is a cross-sectional view of the circuit board according to the fifth embodiment of the present invention. Figure 10 is a cross-sectional view of the circuit board according to the sixth embodiment of the present invention. Figure 11 is a cross-sectional view of the circuit board according to the seventh embodiment of the present invention. Figure 12 is a cross-sectional view of the circuit board according to the eighth embodiment of the present invention. Figure 13 is a cross-sectional view of the circuit board according to the ninth embodiment of the present invention. Figure 14 is a first graph showing the electromagnetic simulation results of the circuit board of several embodiments of the present invention. Figure 15 is a second graph showing the electromagnetic simulation results of the circuit board of several embodiments of the present invention. Figures 16A to 16H are the first to eighth schematic diagrams of the manufacturing method of the circuit board according to the tenth embodiment of the present invention. Figure 17 is a flowchart of the manufacturing method of the circuit board according to the eleventh embodiment of the present invention. Implementation

[0013] The following description, with reference to the accompanying drawings, illustrates embodiments of the circuit board and its manufacturing method according to the present invention. For clarity and ease of illustration, the dimensions and proportions of the components in the drawings may be exaggerated or reduced. In the following description and / or the claims, when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to that other element or there may be an intervening element; when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intervening element. Other terms used to describe the relationship between elements or layers should be interpreted in the same manner. For ease of understanding, the same elements in the following embodiments are indicated by the same symbols.

[0014] Please refer to Figures 1, 2, and 3, which are cross-sectional views, a first schematic diagram, and a second schematic diagram of the circuit board according to the first embodiment of the present invention. As shown in Figure 1, the circuit board 1 includes an insulating substrate 10, a dielectric layer 11, a first conductor layer 12, a first grounding element G1, and two signal lines St. The circuit board 1 may be a multilayer board.

[0015] A first conductive layer 12 is disposed on an insulating substrate 10 and on one side of a dielectric layer 11. In this embodiment, the first conductive layer 12 is disposed below the dielectric layer 11. The first conductive layer 12 may be copper or other suitable metal material. The dielectric layer 11 may be made of a dielectric material, such as a PI film or other suitable dielectric material. In this embodiment, the insulating substrate 10 is a glass substrate. In another embodiment, the insulating substrate 10 may also be a dielectric layer.

[0016] The first grounding element G1 protrudes from the first conductor layer 12 and is disposed within the dielectric layer 11. The first grounding element G1 may be a metal via. In another embodiment, the first grounding element G1 may also be a grounding trace.

[0017] The signal lines St are disposed within the dielectric layer 11 and located on the upper left and upper right sides of the first grounding element G1. That is, the dielectric layer 11 has a signal layer and a ground layer, with the signal lines St disposed on the signal layer and the grounding element G1 disposed on the ground layer. The signal layer is located above the ground layer, and the ground layer is located above the first conductor layer 12. The signal lines St can be metallic wires, such as copper wire or other suitable metallic wires.

[0018] As described above, in this embodiment, as shown in Figure 1, the first grounding element G1 is disposed below the two signal lines St and located between them to provide electromagnetic wave isolation. The first grounding element G1 is close to the two signal lines St but does not contact them. The first grounding element G1 has a left corner t1 and a right corner t2 on its top surface, while the two signal lines St have two inner corners t3 on their bottom surfaces near the first grounding element G1, so that the left corner t1 and right corner t2 on the top surface of the first grounding element G1 are very close to but do not contact the two inner corners t3 on the bottom surfaces of the two signal lines St. The same applies to the following embodiments. The first grounding element G1 can be inverted trapezoidal in shape, and the signal lines St can be rectangular. In another embodiment, the first grounding element G1 can be trapezoidal, rectangular, pentagonal, other polygonal shapes, or other suitable shapes. The signal lines St can also be trapezoidal, inverted trapezoidal, pentagonal, other polygonal shapes, or other suitable shapes. This embodiment is not limited thereto. The following embodiments are the same.

[0019] As shown in Figure 2, the projections SP of each signal line St on the first conductor layer 12 are adjacent to the projection GP of the first grounding element G1 on the first conductor layer 12. However, the projections of each signal line St on the first conductor layer 12 do not contact the projection GP of the first grounding element G1 on the first conductor layer 12. The projections SP of each signal line St on the first conductor layer 12 can be very close to the projection GP of the first grounding element G1 on the first conductor layer 12, but do not contact the projection GP of the first grounding element G1 on the first conductor layer 12. The signal lines St will also not contact the first grounding element G1. The distance between the projections SP of each signal line St on the first conductor layer 12 and the projection GP of the first grounding element G1 on the first conductor layer 12 (the shortest distance between the signal line St and the first grounding element G1) can be 1µm to 10µm, such as 3µm, 5µm, etc., and can be adjusted according to actual needs.

[0020] Furthermore, the plane P1 passing through the top surface of the first grounding member G1 and the plane P2 passing through the bottom surface of the signal lines St can coincide with each other.

[0021] As described above, the first grounding element G1 protrudes from the first conductor layer 12, while the two signal lines St are positioned above and on either side of the first grounding element G1, very close but not in contact. The first grounding element G1, protruding from the first conductor layer 12, can form an effective protruding grounding barrier to isolate electromagnetic fields. Therefore, the first grounding element G1 can significantly reduce crosstalk between the signal lines St.

[0022] Furthermore, since each signal line St on the circuit board 1 is very close to the first grounding element G1 but does not make contact with it, the first grounding element G1 can not only form a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines St, but also prevent micro-short circuits and leakage current.

[0023] As shown in Figure 3, there can also be a gap between the plane P1 of the top surface of the first grounding member G1 and the plane P2 of the bottom surface of the signal lines St.

[0024] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0025] Please refer to Figures 4, 5, and 6, which are cross-sectional views, a first schematic diagram, and a second schematic diagram of the circuit board according to the second embodiment of the present invention. As shown in Figure 4, the circuit board 2 includes a first insulating substrate 20A, a second insulating substrate 20B, a dielectric layer 21, a first conductor layer 22, a first grounding element G1, and two signal lines St. That is, the dielectric layer 21 has a signal layer and a ground layer, wherein the signal line St is disposed on the signal layer, and the grounding element G1 is disposed on the ground layer. The ground layer is located above the signal layer, and the ground layer is located below the first conductor layer 22. The circuit board 2 can be a multilayer board.

[0026] A first conductive layer 22 is disposed on one side of the dielectric layer 21. In this embodiment, the first conductive layer 22 is disposed on the upper side of the dielectric layer 21. The dielectric layer 21 is disposed on the first insulating substrate 20A. A second insulating substrate 20B is disposed on the first conductive layer 22A. In this embodiment, the first insulating substrate 20A and the second insulating substrate 20B are glass substrates. In another embodiment, the first insulating substrate 20A and the second insulating substrate 20B may also be dielectric layers.

[0027] The first grounding element G1 protrudes from the first conductor layer 22 and is disposed within the dielectric layer 21.

[0028] The signal lines St are disposed within the dielectric layer 21 and located on one side of the first grounding member G1. These signal lines St can be metallic conductors, such as copper wire or other suitable metallic wires. The first grounding member G1 is close to but does not contact the two signal lines St. The first grounding member G1 has a left end corner t4 and a right end corner t5 on its bottom surface, while the two signal lines St have two inner end corners t6 on their top surfaces near the first grounding member G1, such that the left end corner t4 and the right end corner t5 on the bottom surface of the first grounding member G1 are close to but do not contact the two inner end corners t6 on the top surfaces of the two signal lines St. The following embodiments are similar.

[0029] As can be seen from the above, in this embodiment, the first grounding element G1 is disposed above the two signal lines St and located between the signal lines St to provide electromagnetic wave isolation.

[0030] As shown in Figure 5, the projections SP of each signal line St on the first conductor layer 22 are adjacent to the projection GP of the first grounding element G1 on the first conductor layer 22. However, the projections of each signal line St on the first conductor layer 22 do not contact the projection GP of the first grounding element G1 on the first conductor layer 22. The projections SP of each signal line St on the first conductor layer 22 can be very close to the projection GP of the first grounding element G1 on the first conductor layer 22, but do not contact the projection GP of the first grounding element G1 on the first conductor layer 22. The signal lines St will also not contact the first grounding element G1. Similarly, the distance between the projections SP of each signal line St on the first conductor layer 22 and the projection GP of the first grounding element G1 on the first conductor layer 22 (the shortest distance between the signal line St and the first grounding element G1) can be adjusted according to actual needs.

[0031] Furthermore, the plane P3 passing through the bottom surface of the first grounding member G1 and the plane P4 passing through the top surface of the signal lines St can coincide with each other.

[0032] Similar to the previous embodiment, the first grounding element G1 protrudes from the first conductor layer 22, while the two signal lines St are disposed below the first grounding element G1 and located on both sides of the first grounding element G1. The first grounding element G1, protruding from the first conductor layer 22, can form an effective protruding grounding barrier to isolate electromagnetic fields. Therefore, the first grounding element G1 can significantly reduce crosstalk between the signal lines St.

[0033] Similarly, since each signal line St on the circuit board 2 is very close to the first grounding element G1 but does not contact it, the first grounding element G1 can not only form a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines St, but also prevent micro-short circuits and leakage current.

[0034] As shown in Figure 6, there can also be a gap between the plane P3 of the bottom surface of the first grounding member G1 and the plane P4 of the top surface of the signal lines St.

[0035] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0036] Please refer to Figure 7, which is a cross-sectional view of the circuit board according to the third embodiment of the present invention. As shown in the figure, the circuit board 3 includes a first insulating substrate 30A, a second insulating substrate 30B, a dielectric layer 31, a first conductor layer 32, a second conductor layer 33, a first grounding element G1, a second grounding element G2, and two signal lines St. The structure is similar to the above embodiments, and the detailed structure will not be described in detail.

[0037] The first conductor layer 32 is disposed on the first insulating substrate 30A and on one side of the dielectric layer 31. In this embodiment, the first conductor layer 32 is disposed on the underside of the dielectric layer 31.

[0038] The first grounding element G1 protrudes from the first conductor layer 32 and is disposed within the dielectric layer 31.

[0039] These signal lines St are disposed within the dielectric layer 31 and located on one side of the first grounding element G1.

[0040] The second conductor layer 33 is disposed on the other side of the dielectric layer 31. In this embodiment, the second conductor layer 33 is disposed on the upper side of the dielectric layer 31. The second insulating substrate 30B is disposed on the second conductor layer 33A. In this embodiment, the first insulating substrate 30A and the second insulating substrate 30B are glass substrates. In another embodiment, the first insulating substrate 30A and the second insulating substrate 30B may also be dielectric layers.

[0041] The second grounding element G2 protrudes from the second conductor layer 33 and is disposed within the dielectric layer 31. The second grounding element G2 may be a metal via. In another embodiment, the second grounding element G2 may also be a grounding trace.

[0042] As described above, in this embodiment, the first grounding element G1 is disposed below the two signal lines St, while the second grounding element G2 is disposed above the two signal lines St. The first grounding element G1 is located between the signal lines St, and the second grounding element G2 is also located between the signal lines St to provide electromagnetic wave isolation.

[0043] The projections of each signal line St on the first conductor layer 32 are adjacent to the projection of the first grounding element G1 on the first conductor layer 32. However, the projections of each signal line St on the first conductor layer 32 do not contact the projection of the first grounding element G1 on the first conductor layer 32. The projections of each signal line St on the second conductor layer 33 are also adjacent to the projection of the second grounding element G2 on the second conductor layer 33, but they do not contact the projection of the second grounding element G2 on the second conductor layer 33. The signal lines St do not contact the first grounding element G1 or the second grounding element G2. The distance between the projections of each signal line St on the first conductor layer 32 and the projections of the first grounding element G1 on the first conductor layer 32 (the shortest distance between the signal line St and the first grounding element G1) can be 1µm to 10µm, such as 3µm, 5µm, etc., and can be adjusted according to actual needs. Similarly, the distance between the projection of each signal line St onto the second conductor layer 33 and the projection of the second grounding component G2 onto the second conductor layer 33 (the shortest distance between the signal line St and the second grounding component G2) can also be 1µm to 10µm, such as 3µm, 5µm, etc., which can be adjusted according to actual needs.

[0044] Furthermore, the plane passing through the top surface of the first grounding member G1 and the plane passing through the bottom surface of the signal lines St can coincide with each other. There can also be a gap between the plane passing through the top surface of the first grounding member G1 and the plane passing through the bottom surface of the signal lines St. Similarly, the plane passing through the bottom surface of the second grounding member G2 and the plane passing through the top surface of the signal lines St can coincide with each other. There can also be a gap between the plane passing through the bottom surface of the second grounding member G2 and the plane passing through the top surface of the signal lines St.

[0045] As described above, the first grounding element G1 protrudes from the first conductor layer 32, while the two signal lines St are positioned above and on either side of the first grounding element G1. The first grounding element G1, protruding from the first conductor layer 32, forms an effective protruding grounding barrier to isolate electromagnetic fields. The second grounding element G2 protrudes from the second conductor layer 33, while the two signal lines St are positioned below and on either side of the second grounding element G2. The second grounding element G2, protruding from the second conductor layer 33, forms an effective protruding grounding barrier to isolate electromagnetic fields. Therefore, the combination of the first grounding element G1 and the second grounding element G2 can significantly reduce crosstalk between the signal lines St.

[0046] Furthermore, since each signal line St on the circuit carrier board 3 is extremely close to the first grounding element G1 and the second grounding element G2 but does not contact them, the first grounding element G1 and the second grounding element G2 can not only form a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines St, but also prevent micro-short circuits and leakage current.

[0047] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0048] Please refer to Figure 8, which is a cross-sectional view of the circuit board according to the fourth embodiment of the present invention. As shown in the figure, the circuit board 4 includes an insulating substrate 40, a dielectric layer 41, a first conductor layer 42, two first grounding elements G1, and two signal lines St. The structure is similar to the above embodiments, and the detailed structure will not be described in detail.

[0049] The first conductor layer 42 is disposed on the insulating substrate 40 and on one side of the dielectric layer 41. In this embodiment, the first conductor layer 42 is disposed on the underside of the dielectric layer 41.

[0050] These first grounding elements G1 protrude from the first conductor layer 42 and are disposed within the dielectric layer 41.

[0051] These signal lines St are disposed within the dielectric layer 41 and located on one side of the first grounding element G1.

[0052] As can be seen from the above, in this embodiment, the two first grounding elements G1 are disposed below the two signal lines St, and the signal lines St are located between the first grounding elements G1 to provide electromagnetic wave isolation.

[0053] The projections of each signal line St on the first conductor layer 42 are adjacent to the projections of at least one first grounding element G1 on the first conductor layer 42. However, the projections of each signal line St on the first conductor layer 42 do not contact the projections of any first grounding element G1 on the first conductor layer 42. In this embodiment, the projections of the signal lines St on the first conductor layer 42 are between the projections of the first grounding elements G1 on the first conductor layer 42. The projections of each signal line St on the first conductor layer 42 may be very close to the projections of at least one first grounding element G1 on the first conductor layer 42, but do not contact the projections of any first grounding element G1 on the first conductor layer 42. The signal lines St will not contact the first grounding element G1. The distance between the projections of each signal line St on the first conductor layer 42 and the projections GP of the first grounding element G1 on the first conductor layer 42 (the shortest distance between the signal line St and the first grounding element G1) is as described in the previous embodiment.

[0054] Furthermore, the plane passing through the top surface of the first grounding elements G1 and the plane passing through the bottom surface of the signal lines St can coincide with each other. There can also be a gap between the plane passing through the top surface of the first grounding elements G1 and the plane passing through the bottom surface of the signal lines St.

[0055] As described above, the first grounding elements G1 protrude from the first conductor layer 42, and two signal lines St are positioned above and between the first grounding elements G1. This structure can significantly reduce crosstalk between the signal lines St. The number of first grounding elements G1 and the number of signal lines St can be varied according to actual needs. The positions of the first grounding elements G1 and the signal lines St can also be varied according to actual needs.

[0056] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0057] Please refer to Figure 9, which is a cross-sectional view of the circuit board according to the fifth embodiment of the present invention. As shown in the figure, the circuit board 5 includes a first insulating substrate 50A, a second insulating substrate 50B, a dielectric layer 51, a first conductor layer 52, a second conductor layer 53, two first grounding elements G1, two signal lines St, and two second grounding elements G2. The structure is similar to that of the above embodiments, and the detailed structure will not be described in detail.

[0058] The first conductor layer 52 is disposed on the first insulating substrate 50A and on one side of the dielectric layer 51. In this embodiment, the first conductor layer 52 is disposed on the underside of the dielectric layer 51.

[0059] These first grounding elements G1 protrude from the first conductor layer 52 and are disposed within the dielectric layer 51.

[0060] These signal lines St are disposed within the dielectric layer 51 and located on one side of the first grounding element G1.

[0061] Unlike the fourth embodiment, in this embodiment, two second grounding elements G2 and a second conductor layer 53 may be disposed above the signal lines St. The second grounding elements G2 are disposed above the signal lines St and located on both sides of the signal lines St, symmetrically opposite to the first grounding elements G1. The second conductor layer 53 is disposed above the dielectric layer 51, and the second grounding elements G2 protrude from the second conductor layer 53. A second insulating substrate 50B is disposed on the second conductor layer 53. In this embodiment, the first insulating substrate 50A and the second insulating substrate 50B are glass substrates. In another embodiment, the first insulating substrate 50A and the second insulating substrate 50B may also be dielectric layers.

[0062] As described above, in this embodiment, the two first grounding elements G1 are disposed below the two signal lines St, and the two second grounding elements G2 are disposed above the two signal lines St. The signal lines St are located between the first grounding elements G1 and the second grounding elements G2 to provide electromagnetic wave isolation.

[0063] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0064] Please refer to Figure 10, which is a cross-sectional view of the circuit board according to the sixth embodiment of the present invention. As shown in the figure, the circuit board 6 includes an insulating substrate 60, a dielectric layer 61, a first conductor layer 62, two first grounding elements G1', and two signal lines St. The structure is similar to that of the above embodiments, and the detailed structure will not be described in detail.

[0065] Unlike the fourth embodiment, these first grounding elements G1' are grounding traces.

[0066] As can be seen from the above, in this embodiment, the two first grounding elements G1' are disposed below the two signal lines St, and the signal lines St are located at the first grounding elements G1' to provide electromagnetic wave isolation.

[0067] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0068] Please refer to Figure 11, which is a cross-sectional view of the circuit board according to the seventh embodiment of the present invention. As shown in the figure, the circuit board 7 includes an insulating substrate 70, a dielectric layer 71, a first conductor layer 72, three first grounding elements G1, and two signal lines St. The structure is similar to the above embodiments, and the detailed structure will not be described in detail.

[0069] The first conductor layer 72 is disposed on the insulating substrate 70 and on one side of the dielectric layer 71. In this embodiment, the first conductor layer 72 is disposed on the underside of the dielectric layer 71.

[0070] These first grounding elements G1 protrude from the first conductor layer 72 and are disposed within the dielectric layer 71.

[0071] These signal lines St are disposed within the dielectric layer 71 and located on one side of the first grounding elements G1.

[0072] As described above, in this embodiment, the three first grounding elements G1 are disposed below the two signal lines St. Furthermore, each signal line St is located between two adjacent first grounding elements G1 to achieve an interleaved arrangement, thereby providing electromagnetic wave isolation.

[0073] The projections of each signal line St onto the first conductor layer 72 are adjacent to the projections of at least one first grounding element G1 onto the first conductor layer 72. However, the projections of each signal line St onto the first conductor layer 72 do not contact the projections of any first grounding element G1 onto the first conductor layer 72. In this embodiment, the projections of the signal lines St onto the first conductor layer 72 are interleaved with the projections of the first grounding elements G1 onto the first conductor layer 72. The projections of each signal line St onto the first conductor layer 72 may be very close to the projections of at least one first grounding element G1 onto the first conductor layer 72, but do not contact the projections of any first grounding element G1 onto the first conductor layer 72. The signal lines St will not contact the first grounding element G1. The distance between the projections of each signal line St onto the first conductor layer 72 and the projections GP of the first grounding element G1 onto the first conductor layer 72 (the shortest distance between the signal line St and the first grounding element G1) is as described in the previous embodiment.

[0074] Furthermore, the plane passing through the top surface of the first grounding elements G1 and the plane passing through the bottom surface of the signal lines St can coincide with each other. There can also be a gap between the plane passing through the top surface of the first grounding elements G1 and the plane passing through the bottom surface of the signal lines St.

[0075] As described above, the first grounding elements G1 protrude from the first conductor layer 72, and two signal lines St are positioned above and interleaved with the first grounding elements G1. This structure can significantly reduce crosstalk between the signal lines St. The number of first grounding elements G1 and the number of signal lines St can be varied according to actual needs. The positions of the first grounding elements G1 and the signal lines St can also be varied according to actual needs.

[0076] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0077] Please refer to Figure 12, which is a cross-sectional view of the circuit board according to the eighth embodiment of the present invention. As shown in the figure, the circuit board 8 includes a first insulating substrate 80A, a second insulating substrate 80B, a dielectric layer 81, a first conductor layer 82, a second conductor layer 83, three first grounding elements G1, two signal lines St, and three second grounding elements G2. The structure is similar to the above embodiments, and the detailed structure will not be described in detail.

[0078] The first conductor layer 82 is disposed on the first insulating substrate 80A and on one side of the dielectric layer 51. In this embodiment, the first conductor layer 82 is disposed on the underside of the dielectric layer 81.

[0079] These first grounding elements G1 protrude from the first conductor layer 82 and are disposed within the dielectric layer 81.

[0080] These signal lines St are disposed within the dielectric layer 81 and located on one side of the first grounding element G1.

[0081] Unlike the seventh embodiment, in this embodiment, three second grounding elements G2 and a second conductor layer 83 may be disposed above the signal lines St. The second grounding elements G2 are disposed above the signal lines St and intersect with them, and are symmetrical to the first grounding elements G1. The second conductor layer 83 is disposed above the dielectric layer 81, and the second grounding elements G2 protrude from the second conductor layer 83. A second insulating substrate 80B is disposed on the second conductor layer 83. In this embodiment, the first insulating substrate 80A and the second insulating substrate 80B are glass substrates. In another embodiment, the first insulating substrate 80A and the second insulating substrate 80B may also be dielectric layers.

[0082] As described above, in this embodiment, the three first grounding elements G1 are disposed below the two signal lines St. Furthermore, each signal line St is located between two adjacent first grounding elements G1 to achieve an interleaved arrangement, thereby providing electromagnetic wave isolation. The three second grounding elements G2 are disposed above the two signal lines St. Furthermore, each signal line St is located between two adjacent second grounding elements G2 to achieve an interleaved arrangement, thereby providing electromagnetic wave isolation.

[0083] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0084] Please refer to Figure 13, which is a cross-sectional view of the circuit board according to the ninth embodiment of the present invention. As shown in the figure, the circuit board 9 includes a first insulating substrate 90A, a second insulating substrate 90B, a dielectric layer 91, a first conductor layer 92, three first grounding elements G1, and two signal lines St. The structure is similar to another embodiment of the above embodiments, and the detailed structure will not be described in detail.

[0085] The first conductive layer 92 is disposed on one side of the dielectric layer 91. In this embodiment, the first conductive layer 92 is disposed on the upper side of the dielectric layer 91. The dielectric layer 91 is disposed on the first insulating substrate 90A.

[0086] These first grounding elements G1 protrude from the first conductor layer 92 and are disposed within the dielectric layer 91.

[0087] The signal lines St are disposed within the dielectric layer 91 and located on one side of the first grounding elements G1. A second insulating substrate 90B is disposed on the first conductor layer 92. In this embodiment, the first insulating substrate 90A and the second insulating substrate 90B are glass substrates. In another embodiment, the first insulating substrate 90A and the second insulating substrate 90B may also be dielectric layers.

[0088] As described above, in this embodiment, the three first grounding elements G1 are disposed above the two signal lines St. Furthermore, each signal line St is located between two adjacent first grounding elements G1 to achieve an interleaved arrangement, thereby providing electromagnetic wave isolation.

[0089] The projections of each signal line St on the first conductor layer 92 are adjacent to the projections of at least one first grounding element G1 on the first conductor layer 92. However, the projections of each signal line St on the first conductor layer 92 do not contact the projections of any first grounding element G1 on the first conductor layer 92. In this embodiment, the projections of the signal lines St on the first conductor layer 92 are interleaved with the projections of the first grounding elements G1 on the first conductor layer 92. The projections of each signal line St on the first conductor layer 92 can be very close to the projections of at least one first grounding element G1 on the first conductor layer 92, but do not contact the projections of any first grounding element G1 on the first conductor layer 92. The signal lines St will not contact the first grounding element G1. The distance between the projections of each signal line St on the first conductor layer 92 and the projections GP of the first grounding element G1 on the first conductor layer 92 (the shortest distance between the signal line St and the first grounding element G1) is as described in the previous embodiment.

[0090] Furthermore, the plane passing through the bottom surface of the first grounding elements G1 and the plane passing through the top surface of the signal lines St can coincide with each other. There can also be a gap between the plane passing through the bottom surface of the first grounding elements G1 and the plane passing through the top surface of the signal lines St.

[0091] As described above, the first grounding elements G1 protrude from the first conductor layer 92, while two signal lines St are positioned below and interleaved with the first grounding elements G1. This structure can significantly reduce crosstalk between the signal lines St. The number of first grounding elements G1 and the number of signal lines St can be varied according to actual needs. The positions of the first grounding elements G1 and the signal lines St can also be varied according to actual needs.

[0092] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the circuit board based on this embodiment should still be included within the patent scope of the invention.

[0093] The above embodiments detail the structural design of the protruding grounding barrier. Taking the first embodiment as an example, the circuit board 1 has a first grounding element G1, which protrudes from the first conductor layer 12 of the circuit board 1 and is disposed within the dielectric layer 11 of the circuit board 12. The signal lines St of the circuit board 1 are disposed within the dielectric layer 11 and located on one side of the first grounding element G1. The projection of each signal line St on the first conductor layer 12 is adjacent to the projection of the first grounding element G1 on the first conductor layer 12, but the projection of each signal line St on the first conductor layer 12 does not contact the projection of the first grounding element G1 on the first conductor layer. The first grounding element G1 protruding from the first conductor layer 12 can form a protruding grounding barrier that can effectively isolate electromagnetic fields. This protruding grounding barrier can reduce crosstalk between signal lines, effectively solving the problem of crosstalk generated in high-speed signal transmission and high-frequency operation, to meet the needs of various applications.

[0094] Furthermore, each signal line St on the circuit board 1 is extremely close to at least one first grounding element G1 but not in contact with it. Therefore, the first grounding element G1 not only serves as a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines St, but also avoids micro-short circuits and leakage current. Thus, the reliability of the circuit board 1 can be significantly improved, meeting the requirements of practical applications.

[0095] Furthermore, the circuit board 1 is designed with an expandable architecture, allowing integration with existing processes and applicability to various heterogeneous packaging structures, such as 2.XD IC packaging, 3D IC packaging, SiP (System in Package), PoP (Package on Package), and Fanout packaging. Therefore, the area of ​​the circuit board 1 can be significantly reduced while achieving high signal transmission density. Consequently, the computing power and processing time of the circuit board 1 can be greatly improved to meet the demands of high-performance computing (HPC) and artificial intelligence (AI) fields. Therefore, the circuit board truly aligns with future development trends.

[0096] Please refer to Figure 14, which is a first graph showing the electromagnetic simulation results of circuit boards according to several embodiments of the present invention. Figure 14 shows the electromagnetic simulation results of near-end crosstalk (NEXT). As shown in the figure, curve C0 represents the electromagnetic simulation results of the circuit board without a prominent grounding barrier (with the first grounding element G1 of the first embodiment removed). Curve C1 represents the electromagnetic simulation results of circuit board 1 of the first embodiment. Curve C2 represents the electromagnetic simulation results of circuit board 4 of the fourth embodiment. Curve C3 represents the electromagnetic simulation results of circuit board 7 of the seventh embodiment. As can be seen from the figure, circuit boards 1, 4, and 8 can all effectively reduce near-end crosstalk and are all superior to the circuit board without a prominent grounding barrier. Circuit board 1 has the best effect in reducing near-end crosstalk.

[0097] Please refer to Figure 15, which is a second graph showing the electromagnetic simulation results of circuit boards according to several embodiments of the present invention. Figure 15 shows the electromagnetic simulation results of far-end crosstalk (FEXT). As shown in the figure, curve C0' represents the electromagnetic simulation result of the circuit board without a prominent grounding barrier (with the first grounding element G1 of the first embodiment removed). Curve C1' represents the electromagnetic simulation result of circuit board 1 of the first embodiment. Curve C2' represents the electromagnetic simulation result of circuit board 4 of the fourth embodiment. Curve C3' represents the electromagnetic simulation result of circuit board 7 of the seventh embodiment. As can be seen from the figure, circuit boards 1, 4, and 8 can all effectively reduce far-end crosstalk and are all superior to the circuit board without a prominent grounding barrier. Circuit board 1 also has the best effect in reducing far-end crosstalk.

[0098] Please refer to Figures 16A to 16H, which are the first to eighth schematic diagrams of the manufacturing method of the circuit board according to the tenth embodiment of the present invention. This embodiment uses the circuit board 1 of the first embodiment as an example to illustrate its manufacturing method. As shown in Figure 16A, firstly, an insulating substrate 10 (such as a glass substrate) is provided, and a release film coating process is performed to form a release film Rm on the insulating substrate 10.

[0099] As shown in Figure 16B, a first metal layer coating process is then performed to form a first metal layer M1. The first metal layer coating process includes two steps. The first step is to form a first seed layer on the insulating substrate 10. The second step is to perform a first metal electroplating process to form the aforementioned first metal layer M1 on the first seed layer.

[0100] Then, as shown in Figure 16C, a first lithography process is performed on the first metal layer M1 to form the first grounding element G1 and the first conductor layer 12, followed by a photoresist stripping process.

[0101] As shown in Figure 16D, a dielectric layer formation process is performed to form a dielectric layer 11 covering the first conductor layer 12 and the first grounding element G1. Then, an aperture process is performed to form an opening PN on the dielectric layer 11, exposing the first grounding element G1 through the opening PN.

[0102] As shown in Figure 16E, a second metal layer coating process is performed to form a second conductor layer M2 on the dielectric layer 11. The second metal layer coating process includes two steps. The first step is to form a second seed layer on the dielectric layer 11. The second step is to perform a second metal electroplating process to form the aforementioned second metal layer M2 on the second seed layer, followed by a photoresist stripping process.

[0103] Next, as shown in Figure 16F, a polishing process is performed to remove the second metal layer M2 outside the opening PN in the dielectric layer 11. Therefore, one side of the first grounding member G1 is not in contact with any metal layer.

[0104] Then, as shown in Figure 16G, a third metal layer coating process is performed to form a third metal layer M3 on the dielectric layer 11. The third metal layer coating process includes two steps. The first step is to form a third seed layer on the dielectric layer 11. The second step is to perform a third metal electroplating process to form the aforementioned third metal layer M3 on the third seed layer.

[0105] Next, as shown in Figure 16H, a second photolithography process is performed on the third metal layer M3 to form two signal lines St, followed by a photoresist stripping process.

[0106] The structure of any of the above embodiments can be achieved by selectively performing the above steps.

[0107] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the manufacturing method of the circuit board according to this embodiment should still be included within the patent scope of the invention.

[0108] Please refer to Figure 17, which is a flowchart of the manufacturing method of the circuit board according to the eleventh embodiment of the present invention. As shown in the figure, the manufacturing method of the circuit board in this embodiment may include the following steps:

[0109] Step 171: Provide an insulating substrate.

[0110] Step 172: Perform a first metal layer coating process to form a first metal layer on the insulating substrate.

[0111] Step 173: Perform a first photolithography process on the first metal layer to form the first grounding element and the first conductor layer.

[0112] Step 174: Perform a dielectric layer formation procedure to form a dielectric layer covering the first conductor layer and the first grounding element.

[0113] Step 175: Perform an opening procedure to form an opening in the dielectric layer and expose the first grounding element through the opening.

[0114] Step 176: Perform a second metal layer coating procedure to form a second metal layer on the dielectric layer.

[0115] Step 177: Perform a polishing procedure to remove the second metal layer outside the opening in the dielectric layer.

[0116] Step 178: Perform a third metal layer coating procedure to form a third metal layer on the dielectric layer.

[0117] Step 179: Perform a second photolithography process on the third metal layer to form a plurality of signal lines.

[0118] The resulting structure is similar to the above embodiments, and the detailed structure will not be described in detail.

[0119] Of course, this embodiment is only for illustrative purposes and is not intended to limit the scope of the invention. Equivalent modifications or alterations made to the manufacturing method of the circuit board according to this embodiment should still be included within the patent scope of the invention.

[0120] Although the steps of the methods described in this invention are shown and described in a specific order, the order of operation of each method may be changed, some steps may be performed in reverse order, or some steps may be performed simultaneously with other steps. In another embodiment, different steps may be implemented intermittently and / or alternately.

[0121] In summary, according to embodiments of the present invention, the circuit board has a first grounding element, which protrudes from the first conductor layer of the circuit board and is disposed within the dielectric layer of the circuit board. Signal lines of the circuit board are disposed within the dielectric layer and located on one side of the first grounding element. The projections of each signal line onto the first conductor layer are adjacent to the projections of the first grounding element onto the first conductor layer, but the projections of each signal line onto the first conductor layer do not contact the projections of the first grounding element onto the first conductor layer. The aforementioned first grounding element protrudes from the first conductor layer to form a protruding grounding barrier, which can effectively isolate electromagnetic fields to reduce crosstalk between signal lines. Therefore, the circuit board can effectively solve the problem of crosstalk generated under high-speed signal transmission and high-frequency operation conditions to meet the needs of various applications.

[0122] Furthermore, according to embodiments of the present invention, each signal line of the circuit board is extremely close to at least one first grounding element but does not contact this first grounding element. Therefore, the first grounding element not only serves as a prominent grounding barrier to effectively isolate electromagnetic fields and reduce crosstalk between signal lines, but also avoids micro-short circuits and leakage current. Thus, the reliability of the circuit board can be significantly improved, thereby meeting the requirements of practical applications.

[0123] Furthermore, according to embodiments of the present invention, the circuit board is designed with an scalable architecture that can be integrated with existing processes and applied to various heterogeneous packaging structures. Therefore, the area of ​​the circuit board can be significantly reduced while achieving high signal transmission density. Consequently, the computing power and processing time of the circuit board can be significantly improved to meet the needs of high-performance computing (HPC) and artificial intelligence (AI) fields. Therefore, the circuit board truly aligns with future development trends.

[0124] The above description is illustrative only and not restrictive. Any equivalent modifications or alterations made without departing from the spirit and scope of this invention should be included in the appended claims.

[0125] 1, 2, 3, 4, 5, 6, 7, 8, 9: Circuit board 10, 20, 40, 60, 70, 90: Insulating substrate 20A, 30A, 50A, 80A, 90A: First insulating substrate 20B, 30B, 50B, 80B, 90B: Second insulating substrate 11, 21, 31, 41, 51, 61, 71, 81, 91: Dielectric layers 12, 22, 32, 42, 52, 62, 72, 82, 92: First conductor layer 33, 83: Second conductor layer G1: First grounding component G2: Second grounding component St: Signal Line Rm: Release film M1: First metal layer M2: Second metal layer M3: Third metal layer t1: Left corner of the top surface of the first grounding component t2: Right corner of the top surface of the first grounding element t3: Inner corner of the bottom surface of the signal line t4: Left corner of the bottom surface of the first grounding component t5: The right corner of the bottom surface of the first grounding component t6: Inner corner of the top surface of the signal line PN: Opening SP, GP: Projection P1, P2, P3, P4: Planes C0, C0', C1, C1', C2, C2', C3, C3': Curves

Claims

1. A circuit board comprising: One dielectric layer; A first conductive layer is disposed on one side of the dielectric layer; A first grounding element protrudes from the first conductor layer and is disposed within the dielectric layer; and a plurality of signal lines are disposed within the dielectric layer and located on one side of the first grounding element; wherein the projection of each signal line on the first conductor layer is adjacent to the projection of the first grounding element on the first conductor layer but does not contact the projection of the first grounding element on the first conductor layer, and the projection of the first grounding element on the first conductor layer is between the projections of the signal lines on the first conductor layer.

2. The circuit board as described in claim 1, wherein the first grounding element is a metal via.

3. The circuit board as described in claim 1, wherein the first grounding element is a grounding trace.

4. The circuit board as claimed in claim 1, wherein the first conductor layer is disposed below the dielectric layer, the signal lines are located above the first grounding member, and the plane passing through the top surface of the first grounding member coincides with the plane passing through the bottom surface of the signal lines.

5. The circuit board as claimed in claim 1, wherein the first conductor layer is disposed below the dielectric layer, the signal lines are located above the first ground member, and there is a gap between the plane passing through the top surface of the first ground member and the plane passing through the bottom surface of the signal lines.

6. The circuit board as claimed in claim 1, wherein the first conductor layer is disposed on the upper side of the dielectric layer, the signal lines are located on the lower side of the first ground member, and the plane passing through the bottom surface of the first ground member coincides with the plane passing through the top surface of the signal lines.

7. The circuit board as claimed in claim 1, wherein the first conductor layer is disposed below the dielectric layer, the signal lines are located below the first ground member, and there is a gap between the plane passing through the bottom surface of the first ground member and the plane passing through the top surface of the signal lines.

8. The circuit board as claimed in claim 1 further includes a second conductor layer and a second grounding member, the second conductor layer being disposed on the other side of the dielectric layer, the second grounding member protruding from the second conductor layer and disposed within the dielectric layer, wherein the projection of each signal line on the second conductor layer is adjacent to the projection of the second grounding member on the second conductor layer but does not contact the projection of the second grounding member on the second conductor layer.

9. The circuit board as described in claim 8, wherein the second grounding element is a metal via.

10. The circuit board as described in claim 8, wherein the second grounding element is a grounding trace.

11. A circuit board comprising: One dielectric layer; A first conductive layer is disposed on one side of the dielectric layer; The first grounding element protrudes from the first conductor layer and is disposed within the dielectric layer, wherein the first grounding element is a metal via; and a plurality of signal lines are disposed within the dielectric layer and located on one side of the first grounding elements; wherein the projection of each signal line on the first conductor layer is adjacent to the projection of at least one first grounding element on the first conductor layer but does not contact the projection of any of the first grounding elements on the first conductor layer.

12. The circuit board as described in claim 11, wherein the first grounding element is a grounding trace.

13. The circuit board as claimed in claim 11, wherein the projections of the signal lines on the first conductor layer are between the projections of the first grounding elements on the first conductor layer.

14. The circuit board as claimed in claim 11, wherein the projections of the signal lines on the first conductor layer and the projections of the first ground elements on the first conductor layer are interleaved.

15. The circuit board as claimed in claim 11, wherein the first conductor layer is disposed below the dielectric layer, the signal lines are located above the first grounding elements, and the plane passing through the top surface of the first grounding elements coincides with the plane passing through the bottom surface of the signal lines.

16. The circuit board as claimed in claim 11, wherein the first conductor layer is disposed below the dielectric layer, the signal lines are located above the first ground members, and there is a gap between the plane passing through the top surface of the first ground members and the plane passing through the bottom surface of the signal lines.

17. The circuit board as claimed in claim 11, wherein the first conductor layer is disposed on the upper side of the dielectric layer, the signal lines are located on the lower side of the first ground members, and the plane passing through the bottom surface of the first ground members coincides with the plane passing through the top surface of the signal lines.

18. The circuit board as claimed in claim 11, wherein the first conductor layer is disposed on the upper side of the dielectric layer, the signal lines are located on the lower side of the first ground members, and there is a gap between the plane passing through the bottom surface of the first ground members and the plane passing through the top surface of the signal lines.

19. The circuit board as claimed in claim 11 further includes a second conductor layer and a plurality of second grounding elements, the second conductor layer being disposed on the other side of the dielectric layer, the second grounding elements protruding from the second conductor layer and disposed within the dielectric layer, wherein the projection of each signal line on the second conductor layer is adjacent to the projection of at least one of the second grounding elements on the second conductor layer but does not contact the projection of any of the second grounding elements on the second conductor layer.

20. The circuit board as claimed in claim 19, wherein the second grounding element is a metal via.

21. The circuit board as described in claim 19, wherein the second grounding element is a grounding trace.

22. A method for manufacturing a circuit board, comprising: Provide an insulating substrate; Perform a first metal layer coating process to form a first metal layer on the insulating substrate; A first photolithography process is performed on the first metal layer to form a first ground element and a first conductor layer; a dielectric layer formation process is performed to form a dielectric layer covering the first conductor layer and the first ground element; an aperture process is performed to form an opening in the dielectric layer and expose the first ground element through the opening; a second metal layer coating process is performed to form a second metal layer on the dielectric layer; a polishing process is performed to remove the second metal layer outside the opening in the dielectric layer; a third metal layer coating process is performed to form a third metal layer on the dielectric layer; and a second photolithography process is performed on the third metal layer to form a plurality of signal lines.

23. The method of manufacturing a circuit board as described in claim 22 further includes: Perform a release film coating process to form a release film on the insulating substrate.

24. A method for manufacturing a circuit board as claimed in claim 22, wherein the step of performing the first metal layer coating process to form the first metal layer on the insulating substrate includes: A first seed layer is formed on the insulating substrate; And perform a first metal electroplating process to form the first metal layer on the first seed layer.

25. A method for manufacturing a circuit board as claimed in claim 22, wherein the step of performing the second metal layer coating process to form the second metal layer on the dielectric layer includes: A second seed layer is formed on the dielectric layer; And perform a second metal electroplating process to form the second metal layer on the second seed layer.

26. A method for manufacturing a circuit board as claimed in claim 22, wherein the step of performing the third metal layer coating process to form the third metal layer on the dielectric layer includes: A third seed layer is formed on the dielectric layer; And perform a third metal electroplating process to form the third metal layer on the third seed layer.

27. A method for manufacturing a circuit board as described in claim 22, wherein the insulating substrate is a glass substrate.

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