Semiconductor device

Abstract

This disclosure provides a semiconductor device including a bottom electrode, a top electrode, and a phase-change memory structure. The top electrode is disposed on the bottom electrode. The phase-change memory structure is disposed between the top electrode and the bottom electrode.

Description

Technical Field

[0001] This disclosure pertains to a semiconductor device. Prior Technology

[0002] Phase-change memory (PCM) is a non-volatile memory technology that utilizes the unique properties of chalcogenide glasses to store data. The operating principle of PCM involves switching the phase of the chalcogenide material between an amorphous and crystalline state. The amorphous state has high resistance, while the crystalline state has low resistance, thus enabling binary data storage. PCM is known for its high durability, fast read / write speeds, and good scalability, making it a promising alternative to traditional flash memory. However, challenges such as high power consumption and low charge transfer speeds have limited its integration into mainstream memory solutions. Summary of the Invention

[0003] According to one or more embodiments of this disclosure, a semiconductor device includes a bottom electrode, a top electrode, and a phase-change memory structure. The top electrode is disposed on the bottom electrode. The phase-change memory structure is disposed between the top electrode and the bottom electrode.

[0004] In one or more embodiments disclosed herein, the top electrode comprises graphene.

[0005] In one or more embodiments disclosed herein, the bottom electrode and the top electrode each comprise nitrogen-doped graphene.

[0006] In one or more embodiments disclosed herein, the phase change memory structure includes germanium-antimony-tellurium, germanium-antimony-silicon, antimony tritelluride, germanium-hexatelluride-chromium, germanium telluride, vanadium dioxide, molybdenum dioxide, vanadium trioxide, cerium dioxide, iron tetroxide, ferrous sulfide, titanium pentoxide, lanthanum cobaltate, samarium nickelate, titanium trioxide, tantalum pentoxide, or combinations thereof.

[0007] In one or more embodiments disclosed herein, the phase change memory structure extends from the top electrode to the bottom electrode in a length of 100 nanometers to 200 nanometers.

[0008] In one or more embodiments disclosed herein, the phase change memory structure extends parallel to the top surface of the bottom electrode with a width of 50 nanometers to 100 nanometers.

[0009] In one or more embodiments disclosed herein, the width of the bottom electrode extending along the top surface of the bottom electrode is greater than the width of the phase change memory structure extending along the top surface of the bottom electrode.

[0010] In one or more embodiments disclosed herein, the semiconductor device further includes a first insulating structure disposed on a bottom electrode and a second insulating structure disposed thereon, wherein the phase change memory structure is laterally sandwiched between the first insulating structure and the second insulating structure from the cross-section of the semiconductor device.

[0011] In one or more embodiments disclosed herein, the first insulating structure and the second insulating structure respectively contact the opposite sidewalls of the phase change memory structure.

[0012] According to one or more embodiments of this disclosure, a semiconductor device includes two electrodes, a plurality of phase-change memory (PCM) structures, and an insulating structure. At least one of the two electrodes comprises graphene. The plurality of PCM structures are disposed between the two electrodes and contact different portions of at least one of the two electrodes. The insulating structure laterally surrounds each of the PCM structures.

[0013] In one or more embodiments disclosed herein, the other of the two electrodes comprises nitrogen-doped graphene.

[0014] In one or more embodiments disclosed herein, each of the phase change memory structures includes chromium germanium telluride, germanium antimony telluride, silicon germanium antimony, antimony telluride, germanium telluride, iron sulfide, vanadium dioxide, molybdenum dioxide, vanadium trioxide, niobium dioxide, iron tetroxide, tantalum pentoxide, titanium pentoxide, lanthanum cobaltate, samarium nickelate, titanium trioxide, or combinations thereof.

[0015] In one or more embodiments disclosed herein, the cross-sectional shape of each phase change memory structure is a regular hexagon.

[0016] In one or more embodiments disclosed herein, the distance between any two adjacent phase change memory structures is 50 nanometers to 100 nanometers.

[0017] In one or more embodiments disclosed herein, each of the phase change memory structures extends from the inner surface of one of the two electrodes to the inner surface of the other of the two electrodes, and the sidewalls of each of the phase change memory structures are straight.

[0018] According to one or more embodiments disclosed above, a semiconductor device includes a bottom electrode, a top electrode, and at least one phase-change memory structure, and can be applied in the field of phase-change memory. Since at least the bottom electrode used to trigger the phase change of the phase-change memory structure contains graphene, a material with high carrier mobility, low resistance, excellent thermal conductivity, and flexible electronic properties, power consumption can be reduced and charge transfer speed can be increased, thereby providing application potential for high-density semiconductor devices. Simple Explanation of the Diagram

[0019] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below: Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure; Figure 2 shows the state of the semiconductor device in Figure 1 when it is first triggered by a voltage pulse; Figure 3 shows the state of the semiconductor device in Figure 1 when it is continuously triggered by a voltage pulse; Figure 4 is a schematic cross-sectional view of a semiconductor device according to some other embodiments of this disclosure; Figures 5A, 5B, and 5C are schematic cross-sectional views of phase-change memory structures according to different embodiments of this disclosure; and Figures 6A and 6B are schematic cross-sectional views of the phase change memory structure arrangement according to different embodiments of this disclosure. Implementation

[0020] The following drawings will disclose several embodiments of this disclosure. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit this disclosure. That is, in some embodiments of this disclosure, these practical details are not essential and therefore should not be used to limit this disclosure. In addition, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner. Furthermore, for the convenience of the reader, the dimensions of the components in the drawings are not drawn to scale.

[0021] It should be understood that although the terms "first," "second," and "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, "first element," "component," "region," "layer," or "part" as used below may also be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0022] It should be understood that relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another, as illustrated in the figures. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in a figure is flipped, an element described as being "below" the other element will be oriented "above" the other element. Thus, the exemplary term "below" can include both "below" and "above" orientations, depending on the specific orientation of the figure. Similarly, if a device in a figure is flipped, an element described as being "below" or "below" the other element will be oriented "above" the other element. Thus, the exemplary term "below" or "below" can include both "above" and "below" orientations.

[0023] Referring to Figure 1, which is a schematic cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure, the semiconductor device 100 includes two electrodes (i.e., a bottom electrode 110 and a top electrode 120) and a phase-change memory structure 130. The top electrode 120 is disposed above the bottom electrode 110, and the phase-change memory structure 130 is disposed between and in contact with the top electrode 120 and the bottom electrode 110. The semiconductor device 100 can be applied in the field of phase-change memory, for example, as a memory device. During use, current flows through the bottom electrode 110 and the top electrode 120. By controlling the intensity and duration of the voltage pulse, data storage and retrieval in the semiconductor device 100 can be achieved. Specifically, when the phase-change memory structure 130 is subjected to a low-power, long-duration voltage pulse, its material crystallizes to form an ordered lattice structure, exhibiting a highly conductive crystalline state; when the phase-change memory structure 130 is subjected to a high-power, short-duration voltage pulse, the atoms of its material randomly arrange themselves, forming a low-conductivity amorphous state.

[0024] In this disclosure, the bottom electrode 110 comprises graphene. Choosing graphene as the material for the bottom electrode 110 allows for effective control of the phase transition between amorphous and crystalline states in the phase-change memory structure 130, thereby significantly improving the read / write performance of the semiconductor device 100. Therefore, the semiconductor device 100 can be scaled down to the nanometer scale, thereby increasing the integration density of various electronic components within the semiconductor device 100. Specifically, graphene's superior conductivity at the nanometer scale stems from its ballistic transport properties, meaning electrons move with minimal scattering, resulting in extremely low resistance. Its atomic-scale thickness and two-dimensional lattice structure provide ideal channels for electrons, reducing interference and energy loss. Furthermore, strong carbon-carbon bonds and minimal defects further enhance its conductive pathways, enabling efficient electron flow even at extremely small scales. These properties make graphene outstanding in nanometer-scale applications requiring precise and efficient conductivity.

[0025] In some embodiments, the top electrode 120 also comprises graphene. In other words, the bottom electrode 110 and the top electrode 120 are made of the same material. This further enhances the electrical efficiency provided by graphene. Furthermore, using the same material for both the top electrode 120 and the bottom electrode 110 simplifies the manufacturing process, reduces variability, and thus improves production yield and consistency. This consistency also improves interface compatibility, minimizing defects and instabilities at the interface between the electrode and the memory material, thereby improving device performance. In addition, consistency ensures symmetrical electrical properties, enhancing read / write performance and reducing variability. Furthermore, the matched coefficients of thermal expansion between the same materials reduce stress caused by thermal cycling, improving device stability and lifespan. In summary, overall chemical stability is improved by reducing the risk of unwanted reactions or diffusion between different materials, thus promoting long-term reliability.

[0026] In some embodiments, the phase change memory structure 130 may comprise germanium-antimony-tellurium alloys (e.g., germanium-antimony-tellurium (GeSbTe)), germanium-antimony-silicon (SiGeSb), antimony tritelluride (Sb₂Te₃), germanium telluride (GeTe), digermonium-hexatellurium-chromium (Cr₃Ge₂Te₆), vanadium dioxide (VO₂), molybdenum dioxide (MoO₂), vanadium trioxide (V₂O₃), cerium dioxide (NbO₂), iron tetroxide (Fe₃O₄), titanium trioxide (Ti₃O₅), titanium trioxide (Ti₂O₃), ferrous sulfide (FeS), tantalum pentoxide (Ta₂O₅), lanthanum cobalt oxide (LaCoO₃), samarium nickelate (SmNiO₃), or combinations thereof. In some embodiments, the bottom electrode 110 and the top electrode 120 may each comprise nitrogen-doped graphene, while the phase-change memory structure 130 may comprise GeSbTe. Nitrogen-doped graphene offers significant advantages when paired with GeSbTe. First, it enhances conductivity, improving charge transfer efficiency and resulting in faster switching speeds and lower power consumption. Second, it provides greater stability, maintaining the integrity of GeSbTe during phase transitions due to its superior thermal and chemical stability. Third, it reduces contact resistance, minimizing energy loss at the electrode-memory material interface and improving memory cell efficiency. Furthermore, nitrogen-doped graphene ensures a uniform interface with GeSbTe, promoting consistent switching behavior among memory cells. Moreover, its high-temperature tolerance further supports stable performance at high temperatures and extends device lifespan by reducing degradation at the electrode-memory material interface. In summary, these characteristics highlight the suitability of nitrogen-doped graphene for optimizing the performance, efficiency, and durability of GeSbTe-based memory devices (semiconductor device 100).

[0027] Overall, compared with traditional electrode materials such as silver and copper, the combination of nitrogen-doped graphene electrodes and GeSbTe phase-change memory structure 130 can significantly reduce the power consumption of semiconductor device 100 and significantly improve the charge transfer speed, thereby providing applicability for high-density semiconductor devices.

[0028] Referring to Figures 2 and 3, Figure 2 shows the state of the semiconductor device 100 in Figure 1 when it is initially triggered by a voltage pulse, while Figure 3 shows the state of the semiconductor device 100 in Figure 1 when it is continuously triggered by a voltage pulse. Specifically, the material of the phase-change memory structure 130 can initially be an ordered lattice structure (crystalline state) 130a (see Figure 1). When the phase-change memory structure 130 is subjected to a high-power and short-duration pulse, the atoms in its material begin to randomly arrange themselves near the bottom electrode 110 and the top electrode 120, forming a low-conductivity amorphous state 130b (see Figure 2). Furthermore, when the phase-change memory structure 130 is continuously subjected to a high-power and short-duration pulse, the entire phase-change memory structure 130 transforms into the amorphous state 130b (see Figure 3). Because the combination of (nitrogen-doped) graphene electrodes with the GeSbTe phase change memory structure 130 significantly improves the charge transfer speed, the phase transition time of the phase change memory structure 130 from crystalline to amorphous (or from amorphous to crystalline) can range from milliseconds to sub-nanoseconds, thereby greatly reducing power consumption.

[0029] Referring again to Figure 1. In some implementations, the phase-change memory structure 130 can be scaled down to the nanoscale. For example, the phase change memory structure 130 can extend from the bottom surface 121 (inner surface) of the top electrode 120 to the top surface 111 (inner surface) of the bottom electrode 110, wherein the length L of the phase change memory structure 130 from the top electrode 120 to the bottom electrode 110 (i.e., the distance D from the bottom surface 121 of the top electrode 120 to the top surface 111 of the bottom electrode 110) is 100 nm to 200 nm (e.g., 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm), and the width W is the width of the phase change memory structure 130 in the direction perpendicular to the length L (extending in the direction parallel to the top surface 111 of the bottom electrode 110) is 50 nm to 100 nm (e.g., 60 nm, 70 nm, 80 nm, 90 nm). Because the phase-change memory structure 130 disclosed herein can be scaled down to the nanometer scale, it offers numerous advantages, such as shorter electron paths leading to increased speed, reduced power consumption, higher storage density, lower manufacturing costs, improved thermal management, and greater possibilities for innovative designs. These advantages make memory technology faster, more efficient, and more cost-effective.

[0030] Furthermore, since the width W of the phase-change memory structure 130 is relatively small, the contact area with the electrodes (i.e., the top electrode 120 and the bottom electrode 110) can be minimized. This reduces the energy required for read / write operations by concentrating heat in a smaller area and improves read / write speeds by inducing phase transitions (phase switching) more quickly. Additionally, thermal control is improved by limiting heat diffusion, leakage current is reduced, and the durability of the phase-change memory structure 130 is increased by reducing thermal stress and material degradation.

[0031] In some embodiments, the semiconductor device 100 further includes a first insulating structure 140 and a second insulating structure 150 disposed on the bottom electrode 110, wherein the phase-change memory structure 130, viewed from a side cross-sectional view of the semiconductor device (view shown in Figure 1), is located between and laterally sandwiched between the first insulating structure 140 and the second insulating structure 150. In some embodiments, the first insulating structure 140 and the second insulating structure 150 are disposed (sandwiched) between and contact the top electrode 120 and the bottom electrode 110. In some embodiments, the top surface 131 of the phase-change memory structure 130, the top surface 141 of the first insulating structure 140, and the top surface 151 of the second insulating structure 150 are coplanar and contact the top electrode 120; similarly, the bottom surface 132 of the phase-change memory structure 130, the bottom surface 142 of the first insulating structure 140, and the bottom surface 152 of the second insulating structure 150 are coplanar and contact the bottom electrode 110. Therefore, the phase change memory structure 130, the first insulating structure 140 and the second insulating structure 150 have the same length (i.e., length L), which can improve the durability of the semiconductor device 100.

[0032] The first insulating structure 140 and the second insulating structure 150 protect the phase-change memory structure 130 from current leakage, thereby ensuring data integrity and confining heat within the phase-change region, improving thermal efficiency and reducing the energy required for phase switching. Furthermore, the first insulating structure 140 and the second insulating structure 150 protect the semiconductor device 100 from external interference and damage, thereby improving its durability and maintaining the stability and performance of the semiconductor device 100 by preventing unwanted chemical reactions and element diffusion. In some embodiments, the first insulating structure 140 and the second insulating structure 150 may comprise materials such as Al₂O₃, ZrO₂, or combinations thereof, to better achieve the above effects. In some embodiments, the first insulating structure 140 and the second insulating structure 150 respectively contact the opposite sidewalls of the phase-change memory structure 130 (i.e., the entire first sidewall 133 and the entire second sidewall 134), such that there is no gap between the insulating structures (i.e., the first insulating structure 140 and the second insulating structure 150) and the phase-change memory structure 130. In this way, the first insulation structure 140 and the second insulation structure 150 can provide better protection for the phase change memory structure 130.

[0033] In some embodiments, the width W1 of the bottom electrode 110 (extending parallel to the top surface 111 of the bottom electrode 110) is greater than the width W of the phase-change memory structure 130 (extending parallel to the top surface 111 of the bottom electrode 110). This allows for the provision of multiple phase-change memory structures 130 on the bottom electrode 110, which helps to increase the integration density of various electronic components in the semiconductor device 100. More specifically, refer to Figure 4, which is a schematic cross-sectional view of a semiconductor device 100a according to some other embodiments of this disclosure. The semiconductor device 100a differs from the semiconductor device 100 in that it includes multiple phase-change memory structures 130 disposed between the top electrode 120 and the bottom electrode 110, respectively contacting different portions of the bottom electrode 110 (top electrode 120), and an insulating structure 160 is disposed on the bottom electrode 110 and tightly surrounds each phase-change memory structure 130 from the side. It should be understood that, apart from the number of phase change memory structures 130, other features (e.g., materials) and configurations of the phase change memory structures 130 and the insulation structure 160 can be referred to the phase change memory structure 130, the first insulation structure 140 and the second insulation structure 150 described above, and will not be repeated here.

[0034] Referring to Figures 5A, 5B, and 5C, these figures are schematic cross-sectional views of a phase-change memory structure 130 according to different embodiments of this disclosure. Specifically, the cross-sections shown in Figures 5A, 5B, and 5C are cross-sections along the width W direction of the phase-change memory structure 130. In other words, the cross-sections shown in Figures 5A, 5B, and 5C can be considered top views of the phase-change memory structure 130. As shown in Figures 5A, 5B, and 5C, the cross-sectional shape of the phase-change memory structure 130 can be square, circular, or regular hexagonal. Since the sidewalls of the phase-change memory structure 130 (e.g., first sidewall 133 or second sidewall 134, see Figure 1) are straight, the phase-change memory structure 130 can be prism or cylinder. These shapes facilitate manufacturing. In some preferred embodiments, the cross-sectional shape of the phase-change memory structure 130 is regular hexagonal. This shape can provide a higher packing density of the phase-change memory structure 130.

[0035] Meanwhile, when the cross-sectional shape of the phase-change memory structure 130 is square, the width W of the phase-change memory structure 130 is the diagonal length of the square; when the cross-sectional shape of the phase-change memory structure 130 is circular, the width W of the phase-change memory structure 130 is the diameter of the circle; when the cross-sectional shape of the phase-change memory structure 130 is hexagonal, the width W of the phase-change memory structure 130 is the diagonal length of the hexagon. In some embodiments, the corner R of the phase-change memory structure 130 can be sharp corners for ease of manufacturing. In some preferred embodiments, the corner R of the phase-change memory structure 130 can be rounded corners to manage heat accumulation. Specifically, rounded corners can distribute heat more evenly, reduce stress, and improve thermal stability, which helps to enhance the performance and lifespan of the device.

[0036] Referring to Figures 6A and 6B, these figures are schematic cross-sectional views (cross-sectional views) of the arrangement of phase-change memory structures 130 according to different embodiments of this disclosure. In some embodiments, the phase-change memory structures 130 may be arranged at intervals. As shown in Figure 6A, in some embodiments, the phase-change memory structures 130 may be arranged in an array. Array arrangement improves scalability, thereby achieving higher storage density. Furthermore, array arrangement enhances performance through parallel processing, improves reliability, and manages heat more effectively. As shown in Figure 6B, in some other embodiments, the phase-change memory structures 130 may be arranged in a staggered manner. Staggered arrangement improves thermal management by better heat dissipation and reducing crosstalk between the phase-change memory structures 130, thereby enhancing the reliability of the phase-change memory structures 130 and extending their lifespan.

[0037] In some implementations, the distance between any two phase change memory structures 130 is 50 to 100 nanometers (e.g., 60, 70, 80, or 90 nanometers). Here, "distance" refers to the minimum distance from one sidewall of a phase change memory structure 130 to the sidewall of an adjacent phase change memory structure 130. Excessive distance between phase change memory structures 130 can pose challenges in achieving precise and uniform heating during the phase change process. This can lead to variability in the crystallization or amorphization processes of different phase change memory structures 130, resulting in decreased consistency in data storage and retrieval. Conversely, if the distance between phase change memory structures 130 is too small, it may restrict heat dissipation between the phase change memory structures 130, leading to localized overheating, potentially causing premature wear or degradation of the material. Therefore, maintaining the optimal distance between phase change memory structures 130 is crucial for ensuring consistent and reliable phase change behavior, and equally important for the efficient operation and durability of phase change memory technology.

[0038] According to the above embodiments, the semiconductor device disclosed herein can be applied to the field of phase-change memory and can be a memory device. The semiconductor device includes a bottom electrode, a top electrode, and at least one phase-change memory structure, and can be applied to the field of phase-change memory. Since at least the bottom electrode used to trigger the phase switching of the phase-change memory structure contains graphene, and graphene has high carrier mobility, low resistance, excellent thermal conductivity, and flexible electronic properties, power consumption can be reduced and charge transfer speed can be increased, thereby providing the possibility of high-density semiconductor device applications.

[0039] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art may make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

[0040] 100, 100a: Semiconductor devices 110: Bottom electrode 111: Top surface 120: Top electrode 121: Bottom surface 130: Phase Change Memory Structure 130a: Crystalline 130b: Amorphous state 131: Top surface 132: Bottom surface 133: First sidewall 134: Second sidewall 140: First insulation structure 141: Top surface 142: Bottom surface 150: Second insulation structure 151: Top surface 152: Bottom 160: Insulation structure L: Length D: Distance W: Width W1: Width R: Corner

[0041] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: A bottom electrode comprising graphene; a top electrode disposed on the bottom electrode; A phase-change memory structure is disposed between the top electrode and the bottom electrode and in contact with the top electrode and the bottom electrode; and a first insulating structure and a second insulating structure are disposed on the bottom electrode, wherein the phase-change memory structure is laterally sandwiched between the first insulating structure and the second insulating structure from the cross-section of the semiconductor device.

2. The semiconductor device as claimed in claim 1, wherein the top electrode comprises graphene.

3. The semiconductor device of claim 2, wherein the bottom electrode and the top electrode each comprise nitrogen-doped graphene.

4. The semiconductor device as claimed in claim 1, wherein the phase-change memory structure comprises germanium antimony tellurium, germanium antimony silicon, antimony tritelluride, germanium hexatelluride trichromium, germanium telluride, vanadium dioxide, molybdenum dioxide, vanadium trioxide, cerium dioxide, iron tetroxide, ferrous sulfide, titanium pentoxide, titanium trioxide, tantalum pentoxide, lanthanum cobaltate, samarium nickelate, or combinations thereof.

5. The semiconductor device of claim 1, wherein the phase-change memory structure extends from the top electrode to the bottom electrode in a length of 100 nanometers to 200 nanometers.

6. The semiconductor device of claim 1, wherein the phase-change memory structure extends parallel to a top surface of the bottom electrode with a width of 50 nanometers to 100 nanometers.

7. The semiconductor device of claim 1, wherein the width of the bottom electrode extending along a top surface of the bottom electrode is greater than the width of the phase-change memory structure extending along the top surface of the bottom electrode.

8. The semiconductor device of claim 1, wherein the first insulating structure and the second insulating structure respectively contact opposite sidewalls of the phase change memory structure.

9. A semiconductor device, comprising: Two electrodes, wherein at least one of the two electrodes comprises graphene; a plurality of phase change memory structures disposed between the two electrodes and respectively contacting different portions of at least one of the two electrodes, wherein each of the phase change memory structures extends from the inner surface of one of the two electrodes to the inner surface of the other of the two electrodes, and the sidewalls of each of the phase change memory structures are straight; and an insulating structure laterally surrounding each of the phase change memory structures.

10. The semiconductor device of claim 9, wherein the other of the two electrodes comprises nitrogen-doped graphene.

11. The semiconductor device of claim 9, wherein each of the phase-change memory structures comprises chromium germanium telluride, germanium antimony telluride, silicon germanium antimony, antimony telluride, germanium telluride, iron sulfide, vanadium dioxide, molybdenum dioxide, vanadium trioxide, niobium dioxide, iron tetroxide, tantalum pentoxide, titanium pentoxide, titanium trioxide, lanthanum cobaltate, samarium nickelate, or combinations thereof.

12. The semiconductor device of claim 9, wherein each of the phase-change memory structures has a cross-sectional shape of a regular hexagon.

13. The semiconductor device of claim 9, wherein the distance between any two adjacent phase-change memory structures is 50 nanometers to 100 nanometers.

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