Defect detection method memory device

Abstract

This invention provides a defect detection method for a memory device. The memory device includes a memory array. The memory array performs access operations based on a reference voltage. The defect detection method includes: dividing the memory array into multiple memory blocks; adjusting the voltage value of the reference voltage to sequentially perform access operations on the multiple memory blocks, and receiving multiple defect counts of the multiple memory blocks after the access operations; and determining the defect type of the memory blocks based on the multiple defect counts.

Description

Technical Field

[0001] This invention relates to a method for electronic devices, and more particularly to a method for detecting defects in memory devices. Prior Technology

[0002] Current testing methods for memory devices can determine the number of defects in the memory array. However, when the number of defects in the memory array is large, it becomes difficult to determine the type of defect. Summary of the Invention

[0003] This invention provides a defect detection method for memory devices, which can determine the type of defect in a memory array.

[0004] The defect detection method of the present invention is used in a memory device. The memory device includes a memory array. The memory array performs access operations based on a reference voltage. The defect detection method includes: dividing the memory array into multiple memory blocks; adjusting the voltage value of the reference voltage to sequentially perform access operations on the multiple memory blocks, and receiving multiple defect counts of the multiple memory blocks after the access operations; and determining the defect type of the memory blocks based on the multiple defect counts.

[0005] Based on the above, this invention divides the memory array into multiple memory blocks to obtain multiple defect counts for the multiple memory blocks after the aforementioned access operations. It should be noted that the defect count of a single memory block will be lower than the defect count of the memory array. In this way, the defect type of the memory block can be easily determined. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic diagram of the operation of a memory device according to an embodiment of the present invention. Figure 2 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 3 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 4 is a defect statistics chart drawn according to an embodiment of the present invention. Figure 5 is a statistical chart of the number of memory blocks according to an embodiment of the present invention. Figure 6 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 7 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 8 is a schematic diagram illustrating a method for determining a reference voltage range according to an embodiment of the present invention. Figure 9 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 10 is a defect statistics chart illustrated according to an embodiment of the present invention. Implementation

[0007] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description are considered to be the same or similar components when they appear in different drawings. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0008] Please refer to Figures 1 and 2. Figure 1 is a schematic diagram of the operation of a memory device according to an embodiment of the present invention. Figure 2 is a flowchart of a defect detection method according to an embodiment of the present invention. In this embodiment, the memory device 100 includes a memory array 110. For example, the memory device 100 may be a static random-access memory (SRAM) device, but the present invention is not limited thereto. In this embodiment, the memory array 110 includes a plurality of memory cells. The memory array 110 performs access operations based on reference voltages VCC1 and VCC2. For example, the access operations include write operations and read operations. The memory array 110 performs a write operation based on reference voltage VCC1. The memory array 110 performs a read operation based on reference voltage VCC2. The defect detection method S100 may be executed, for example, by a controller 200. For example, the controller 200 may be a memory controller in the memory device 100 or a test circuit located outside the memory device 100.

[0009] In this embodiment, the defect detection method S100 includes steps S110 to S130. In step S110, the memory array 110 is divided into memory blocks BK1 to BKn. For example, taking a memory array 110 with 64 Mb as an example, the memory array 110 can be divided into 256 memory blocks BK1 to BKn (that is, n equals "256").

[0010] In step S120, the controller 200 adjusts the voltage values ​​of reference voltages VCC1 and VCC2 to sequentially access memory blocks BK0~BKn, and receives the defect counts DFI1~DFIn of memory blocks BK1~BKn after the access operations.

[0011] The defect count DFI1 of memory block BK1 may change with changes in the reference voltages VCC1 and VCC2. The defect count DFI2 of memory block BK2 may change with changes in the reference voltages VCC1 and VCC2, and so on.

[0012] In step S130, the controller 200 determines the defect type of memory blocks BK1 to BKn based on defect counts DFI1 to DFIn. For example, the controller 200 can define the defect type of memory block BK1 based on the content of defect count DFI1. The controller 200 can define the defect type of memory block BK2 based on the content of defect count DFI2, and so on.

[0013] It is worth mentioning that the memory array 110 is divided into memory blocks BK1~BKn to obtain defect counts DFI1~DFIn. The defect count DFI1 of memory block BK1 will be lower than the defect count of the entire memory array 110. In this way, the defect type of memory block BK1 can be easily determined. Similarly, the defect type of each of memory blocks BK1~BKn can be easily determined.

[0014] In this embodiment, the defect counts DFI1 to DFIn each include a failed bit count (FBC) and a failed bit line count (FBL). Taking defect count DFI1 as an example, defect count DFI1 includes a failed bit count FBC1 and a failed bit line count FBL1. The controller 200 can define the defect type of memory block BK1 based on the failed bit count FBC1 and the failed bit line count FBL1.

[0015] For example, when the error bit count FBC1 corresponding to memory block BK1 is "0" and the error bit line count FBL1 corresponding to memory block BK1 is "0", the controller 200 determines that memory block BK1 is a qualified (pass) memory block. That is to say, based on the corresponding reference voltages VCC1 and VCC2, memory block BK1 has no defects.

[0016] For example, when the error bit count FBC1 corresponding to memory block BK1 is greater than "0" and the error bit line count FBL1 corresponding to memory block BK1 is equal to "1", the controller 200 determines that memory block BK1 has a bit line failure. That is, the error bits are all concentrated on the same bit line.

[0017] For example, when the error bit count FBC1 corresponding to memory block BK1 is equal to a and the error bit line count FBL1 corresponding to memory block BK1 is greater than "1", the controller 200 determines that memory block BK1 has a bit defects.

[0018] For another example, when the error bit line count FBL1 corresponding to memory block BK1 is greater than a set value (such as "40"), the controller 200 determines that memory block BK1 has a data failure (DQ failure).

[0019] Furthermore, in some embodiments, the controller 200 can be operated to define different defect types based on a specific range of error bit count FBC1 and error bit line count FBL1. For example, when the error bit count FBC1 equals "1", the controller 200 determines that memory block BK1 has a first defect type. When the error bit count FBC1 is less than or equal to "2" (i.e., FBC1 ≤ 2), the controller 200 determines that memory block BK1 has a second defect type. When the error bit count FBC1 is less than or equal to "4" (i.e., FBC1 ≤ 4), the controller 200 determines that memory block BK1 has a third defect type. When the error bit count FBC1 is less than or equal to "100" (i.e., FBC1 ≤ 100), the controller 200 determines that memory block BK1 has a fourth defect type. The fourth defect type may include bit line failure and / or word line failure in memory block BK1. When the error bit count FBC1 is less than or equal to 1000 (i.e., FBC1 ≤ 1000), the controller 200 determines that memory block BK1 has a fifth defect type. The fifth defect type may include bit line failure and / or word line failure in memory block BK1.

[0020] Furthermore, when the error bit count FBC1 equals "2" and the error bit line count FBL1 is less than or equal to "2" (i.e., FBC1=2 and FBL1≤2), the controller 200 determines that memory block BK1 has a sixth defect type. When the error bit count FBC1 equals "3" and the error bit line count FBL1 is less than or equal to "3" (i.e., FBC1=3 and FBL1≤3), the controller 200 determines that memory block BK1 has a seventh defect type. When the error bit count FBC1 equals "4" and the error bit line count FBL1 is less than or equal to "4" (i.e., FBC1=4 and FBL1≤4), the controller 200 determines that memory block BK1 has an eighth defect type.

[0021] Therefore, controller 200 records at least one defect type of the selected memory block. Controller 200 is also capable of displaying or listing at least one defect type of the selected memory block. Controller 200 records at least one defect type and defect address of the selected memory block. Controller 200 is also capable of displaying or listing at least one defect type and defect address of the selected memory block.

[0022] Similarly, the controller 200 can also use the same method described above to define the defect types of memory blocks BK2~BKn.

[0023] In this embodiment, the defect detection method S100 can be executed during the testing phase of the memory array 110.

[0024] In this embodiment, the controller 200 can select functional test items to perform tests on memory blocks BK1~BKn to record the error bit count and error bit line count of memory blocks BK1~BKn. The controller 200 can use other functional test items to display the defect type and defect address of memory blocks BK1~BKn.

[0025] In this embodiment, the controller 200 generates different status flags according to different defect types of the memory blocks BK1 to BKn, and determines whether to display the defect addresses corresponding to the defect types according to the status flags. For example, the status flags can be determined according to the error bit counts of the memory blocks BK1 to BKn. For example, when the error bit count of the memory block BK1 is greater than 0 and less than or equal to 100 (i.e., 1 < FBC ≤ 100), the controller 200 can display the defect type and the defect address of the memory block BK1. For example, when the error bit count of the memory block BK1 is greater than 100 (i.e., FBC ≥ 100), the controller 200 displays the defect type of the memory block BK1 without displaying the defect address of the memory block BK1. The defect addresses include memory array addresses, memory block addresses, word line addresses, memory row addresses, and data pin addresses.

[0026] In this embodiment, the error bit count and the order of the memory blocks BK1 to BKn can be used to determine whether to display the defect addresses corresponding to the defect types and the display address order.

[0027] Taking the memory block BK1 as an example, when the error bit count is equal to 0, the controller 200 can determine that the memory block BK1 is a qualified memory block and generate a flag indicating that the memory block BK1 is in a qualified memory block state. In some embodiments, when the error bit count is equal to 0, the controller 200 can generate a flag indicating that the memory block BK1 is in a qualified memory block state and record the qualified address (i.e., the address of the memory block BK1).

[0028] [[ID=J11]] In some embodiments, when the total error bit count of the defect counts of the memory array is greater than a critical value (such as 100 or 1000), the controller 200 stops recording the defect addresses. Therefore, when the total error bit count of the defect counts of the memory array is greater than a critical value (such as 100 or 1000), the controller 200 stops recording the defect addresses of the subsequent memory blocks.

[0029] Please refer to Figures 1 and 3. Figure 3 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. In this embodiment, the defect detection method S200 is used to record defect counts DFI1~DFIn. The defect detection method S200 includes steps S210~S260. In step S210, the controller 200 sets reference voltages VCC1 and VCC2. In step S220, the controller 200 initializes "i". "i" can represent memory block BK(i). That is, "i" can represent the number of one of the memory blocks BK1~BKn. In this embodiment, the controller 200 sets "i" to "1" in step S220. Therefore, in step S220, "i" indicates memory block BK1.

[0030] In step S230, the controller 200 receives the defect count DFI1 (i.e., the defect count generated by memory block BK1 after performing an access operation) and determines whether the defect count DFI1 matches the observed defect type. When the defect count DFI1 matches the observed defect type, the controller 200 records the defect address of the defect count DFI1 in step S240. For example, the defect address includes the word line address, memory row address, and data (DQ) pin address. Next, the controller 200 increments "i" (e.g., i = i + 1) in step S250. For example, the controller 200 can record the defect count DFI1 and the defect address of the defect count DFI1 in a memory circuit.

[0031] In step S260, the controller 200 determines whether "i" has reached the set value. If "i" has not yet reached the set value, the controller 200 returns to the operation in step S230. Therefore, the controller 200 determines whether the defect count DFI2 matches the defect type to be observed. When "i" reaches the set value, the controller 200 terminates the defect detection method S200.

[0032] In step S230, when the defect count DFI1 does not match the defect type to be observed, the controller 200 increments "i" (e.g., i=i+1) in step S250 and performs the operation in step S260.

[0033] In this embodiment, the controller 200 may adjust at least one of the reference voltages VCC1 and VCC2 in step S210. For example, the controller 200 may increase or decrease at least one of the reference voltages VCC1 and VCC2 in step S210.

[0034] In this embodiment, during or before executing the defect detection method S200, the controller 200 counts the total number of defect counts DFI1 to DFIn of the memory array 110. The controller 200 can decide whether to record the defect address based on the total number of defect counts DFI1 to DFIn. For example, when the total number of error bits in the defect counts DFI1 to DFIn of the memory array 110 is less than or equal to a threshold value (e.g., "500" or "1000"), the controller 200 records the defect address. For example, when the total number of error bits in the defect counts DFI1 to DFIn of the memory array 110 is greater than the threshold value, the controller 200 stops recording the defect address. The aforementioned threshold value can be adjusted based on actual needs.

[0035] Please refer to Figures 1, 3, and 4. Figure 4 is a defect statistics chart illustrated according to an embodiment of the present invention. In this embodiment, after the defect detection method S200 ends, the controller 200 can generate the defect statistics chart shown in Figure 4 based on reference voltages VCC1 and VCC2. Column L1 of the statistics chart records memory blocks with defect counts. Column L2 of the statistics chart records the defect addresses of each memory block where defects occur.

[0036] Taking memory block BK29 as an example, a defect matching the observed defect type occurs at defect address ADDR0 in memory block BK29. Taking memory block BK161 as an example, defects matching the observed defect type occur at defect addresses ADDR1 and ADDR12 in memory block BK161.

[0037] Taking Figure 4 as an example, memory array 110 has 15 memory blocks with defects matching the defect type to be observed. Memory array 110 has 16 defect addresses. In addition, controller 200 can also use other functional test items to display the defect type and defect address of the same 15 memory blocks matching the defect type to be observed.

[0038] Generally, current memory array defect detection methods count defects on a per-array basis. Once the number of defects exceeds a threshold (e.g., "500" or "1000"), the defect address counting becomes invalid or erroneous. It should be noted that this embodiment counts defects on a per-block basis. The number of defects in each memory block is less than the total number of defects in the memory array 110. Therefore, the number of defects is less likely to exceed the threshold. This significantly reduces the risk of defect address counting becoming invalid or erroneous.

[0039] This invention is not limited to the form or content of the defect statistics chart in this embodiment.

[0040] Please refer to Figures 1 and 5. Figure 5 is a statistical chart illustrating the number of memory blocks according to an embodiment of the present invention. In this embodiment, the controller 200 can generate the number of memory blocks corresponding to different defect types by using multiple statistical results of defects of different defect types. As shown in Figure 5, column L3 of the statistical chart records the memory array number. Column L4 of the statistical chart records the defect type. Column L5 of the statistical chart records the number of memory blocks corresponding to different defect types.

[0041] Taking memory array 100_1 as an example, memory array 100_1 has 123 memory blocks with a fault bit count of "0" (i.e., FBC=0) and 62 memory blocks with a fault bit count of "1" (i.e., FBC=1), and so on.

[0042] This invention is not limited to the form or content of the statistical charts in this embodiment.

[0043] Please refer to Figures 1 and 6. Figure 6 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. In this embodiment, defect detection method S300 is used to read the error bit counts and defect addresses of memory blocks BK1~BKn corresponding to different reference voltages VCC1. The error bit counts and defect addresses are recorded in defect detection method S200. Defect detection method S300 includes steps S301~S30x. In step S301, controller 200 sets the voltage value of reference voltage VCC1 to a first voltage value. Controller 200 reads the error bit counts and defect addresses of memory blocks BK1~BKn based on access operations of the first voltage value.

[0044] In step S302, the controller 200 increments the reference voltage VCC1 from a first voltage value to a second voltage value. The controller 200 reads the error bit count and defect address of memory blocks BK1~BKn based on the access operation of the second voltage value.

[0045] In step S303, the controller 200 increments the reference voltage VCC1 from a second voltage value to a third voltage value. The controller 200 reads the error bit count and defect address of memory blocks BK1~BKn based on the access operation of the third voltage value, and so on.

[0046] Similarly, in step S30x, the controller 200 increments the reference voltage VCC1 to the x-th voltage value. The controller 200 reads the error bit count and defect address of memory blocks BK1~BKn based on the access operation at the x-th voltage value.

[0047] Please refer to Figures 1, 7, and 8. Figure 7 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. Figure 8 is a schematic diagram illustrating a method for determining a reference voltage range according to an embodiment of the present invention. In this embodiment, the controller 200 obtains at least one of the defect counts DFI1 to DFIn corresponding to at least one of the voltage values ​​of the reference voltages VCC1 and VCC2. The controller 200 sorts the error bit counts of at least one of the defect counts DFI1 to DFIn according to the voltage value of at least one of the reference voltages VCC1 and VCC2.

[0048] In this embodiment, the defect detection method S400 includes steps S401 to S412. In step S401, the controller 200 initializes the voltage value of the reference voltage VCC1(x) and the target memory block Unit[m] (i.e., x=1, m=1). In this embodiment, the initialized voltage value of the reference voltage VCC1(x) is the voltage value V1 (e.g., the lowest voltage value of the reference voltage VCC1).

[0049] In step S402, memory array 110 is accessed based on reference voltages VCC1(x) and VCC2. In this embodiment, the voltage value of reference voltage VCC2 is fixed.

[0050] In step S403, the controller 200 initializes the selected memory block BK(i) (i.e., i=1). Therefore, in step S403, the initial selected memory block BK(i) is memory block BK1.

[0051] In step S404, the controller 200 determines whether the selected memory block BK(i) is the previously recorded target memory block Unit[m]. Initially, the target memory block Unit[m] is not set. The selected memory block BK(i) is not the previously recorded target memory block Unit[m]. Therefore, in step S405, the controller 200 determines whether the selected memory block BK(i) matches the observed defect type and whether "m" is less than or equal to the first maximum value.

[0052] In this embodiment, the defect type to be observed is, for example, an error bit count of "1" (i.e., FBC=1). The first maximum value is set to "3". Therefore, this embodiment will observe three memory blocks that meet the defect type to be observed.

[0053] In step S405, when the selected memory block BK(i) matches the observed defect type and "m" is less than or equal to the first maximum value, the controller 200 records the defect address of the selected memory block BK(i) in step S406 and sets the selected memory block BK(i) as the target memory block Unit[m]. Next, the controller 200 increments "m" in step S407 (e.g., m = m + 1) and proceeds to step S408 to increment "i" (e.g., i = i + 1).

[0054] In step S405, when the selected memory block BK(i) does not meet the observed defect type and / or “m” is greater than the first maximum value, the controller 200 does not set the target memory block Unit[m] and does not increment “m”, and proceeds to step S408 to increment “i”.

[0055] In step S404, when the selected memory block BK(i) is the previously recorded target memory block Unit[m], it indicates that the target memory block Unit[m] has been set. That is, the controller 200 knows that the selected memory block BK(i) matches the defect type to be observed and the defect address of the selected memory block BK(i). Therefore, the controller 200 will record the defect address of the selected memory block BK(i) again in step S409 and proceed to step S408 to increment "i".

[0056] After step S408, in step S410, controller 200 determines whether "i" is greater than the second maximum value (e.g., "256"). When "i" is less than or equal to the second maximum value, controller 200 returns to the operation of step S404. When "i" is greater than the second maximum value, controller 200 increments "x" in step S411 (e.g., x = x + 1). Therefore, the reference voltage VCC1(x) is also incremented. In step S411, controller 200 determines whether "x" is greater than the third maximum value. When "x" is less than or equal to the third maximum value, controller 200 returns to the operation of step S402. When "x" is greater than the third maximum value, controller 200 terminates the defect detection method S400.

[0057] Based on the defect detection method S400, the controller 200 can obtain tables TB1, TB2, and TB3 as shown in Figure 8. For example, table TB1 records the defect address of the error bit count of memory block BK173 (e.g., target memory block Unit[1]). The defect address includes the word line address WL, the memory row address Col, and the data (DQ) pin address DQp. When the reference voltage VCC1 is equal to 0.99V, 0.96V, 0.94V, 0.86V, 0.81V, 0.765V, and 0.72V, memory block BK173 has the same defect address. For example, table TB2 records the defect address of the error bit count of memory block BK231 (e.g., target memory block Unit[2]). When the reference voltage VCC1 is between 0.99V and 0.765V, memory block BK231 has the same defect address. However, when the reference voltage VCC1 is 0.72V, memory block BK231 has 8 defect addresses. For example, Table TB3 records the defect addresses of the error bit count for memory block BK75 (e.g., target memory block Unit[3]). When the reference voltage VCC1 is between 0.81V and 0.765V, memory block BK75 has the same defect address. However, when the reference voltage VCC1 is 0.72V, memory block BK75 has 3 defect addresses.

[0058] Based on the error bit count and the reference voltage VCC1, tables TB1, TB2, and TB3 can be organized into table TB4.

[0059] In this embodiment, the controller 200 sets an error bit count range based on the defect type. The controller 200 obtains a voltage value range corresponding to the reference voltage within the error bit count range.

[0060] In this embodiment, for example, the defect type is an error bit count of "1" (i.e., FBC=1). Therefore, the error bit count range can be FBC=1. In Table TB4, the controller 200 can subtract the reference voltage VCC1 from its maximum voltage value (e.g., 0.99V) to obtain a first voltage value that initially corresponds to the error bit count range and a second voltage value that ultimately corresponds to the error bit count range. The controller 200 subtracts the second voltage value from the first voltage value to obtain the voltage value range.

[0061] Taking memory block BK173 as an example, the first voltage value is 0.99V. The second voltage value is 0.72V. Therefore, the controller 200 obtains a voltage range VR1 equal to 0.27V (i.e., 0.99V-0.72V). Taking memory block BK231 as an example, the first voltage value is 0.99V. The second voltage value is 0.765V. Therefore, the controller 200 obtains a voltage range VR2 equal to 0.225V (i.e., 0.99V-0.765V). Taking memory block BK75 as an example, the first voltage value is 0.81V. The second voltage value is 0.765V. Therefore, the controller 200 obtains a voltage range VR3 equal to 0.045V (i.e., 0.81V-0.765V).

[0062] In some embodiments, the controller 200 can increment the reference voltage VCC1 from its minimum value (e.g., 0.72V) to obtain a first voltage value that initially corresponds to the error bit count range and a second voltage value that ultimately corresponds to the error bit count range. The controller 200 subtracts the first voltage value from the second voltage value to obtain the voltage range.

[0063] Please refer to Figures 1, 8, and 9. Figure 9 is a flowchart illustrating a defect detection method according to an embodiment of the present invention. In this embodiment, the controller 200 can use the defect detection method S500 to obtain a first voltage value and a second voltage value. The defect detection method S500 can be executed after the defect detection method S400 is completed. The defect detection method S500 includes steps S501 to S510. In step S501, the controller 200 selects a first target memory block Unit[m] (i.e., m=1).

[0064] In step S502, the controller 200 initializes the voltage value of the reference voltage VCC1(x), the first flag, and the second flag. It should be noted that in this embodiment, the initialized voltage value of the reference voltage VCC1(x) is the maximum voltage value. The voltage value of the reference voltage VCC2 is fixed. In this embodiment, both the first flag and the second flag are initialized to a first value (e.g., "0").

[0065] In step S503, the controller 200 determines whether the error bit count of the target memory block Unit[m] is equal to "k" and whether the first flag is a first value. "k" can be the maximum value of the error bit count range for the defect type. When the error bit count of the target memory block Unit[m] is equal to "k" (i.e., FBC=k) and the first flag is a first value, this indicates that the controller 200 has found the first voltage value corresponding to the error bit count range. That is, the current voltage value of the reference voltage VCC1(x) is the first voltage value. Therefore, the controller 200 obtains the first voltage value in step S504 and sets the first flag to a second value (e.g., "1"). Next, the controller 200 increments "x" in step S505 (e.g., x=x+1). It should be noted that the reference voltage VCC1(x) is decremented.

[0066] In step S506, controller 200 determines whether "x" is greater than the third maximum value. When "x" is less than or equal to the third maximum value, controller 200 returns to step S503. When "x" is greater than the third maximum value, controller 200 increments "m" in step S507 (e.g., m = m + 1). In step S508, controller 200 determines whether "m" is greater than the first maximum value (e.g., "3"). When "m" is less than or equal to the first maximum value, controller 200 returns to step S502. Therefore, controller 200 determines the next target memory block Unit[m]. When "m" is greater than the first maximum value, controller 200 terminates defect detection method S500.

[0067] In step S503, when the error bit count of the target memory block Unit[m] is not equal to "k" and / or the first flag is the second value, this indicates that the error bit count of the target memory block Unit[m] corresponding to the voltage value of the reference voltage VCC1(x) does not conform to the defect type and / or the current voltage value of the reference voltage VCC1(x) is not the voltage value that begins to correspond to the error bit count range. Therefore, in step S509, the controller 200 determines whether the error bit count of the target memory block Unit[m] is greater than "k", whether the first flag is the second value, and whether the second flag is the first value. When the error bit count of the target memory block Unit[m] is greater than "k", the first flag is the second value, and the second flag is the first value, this indicates that after finding the first voltage value, the controller 200 obtains the second voltage value in step S510 and sets the second flag to the second value. That is, the controller 200 uses the previous voltage value of the reference voltage VCC1(x) as the second voltage value. Next, the controller 200 proceeds to step S507.

[0068] In step S509, under other circumstances, the controller 200 proceeds to the operation of step S505. For example, when the error bit count of the target memory block Unit[m] is less than "k", the first flag is the first value and / or the second flag is the second value, the controller 200 will proceed to the operation of step S505.

[0069] Taking memory block BK231 (e.g., target memory block Unit[2]) as an example, steps S502~S506, S509, and S510 are explained. The defect type is, for example, the error bit count is equal to "1" (i.e., FBC=1). In step S502, the voltage value of the reference voltage VCC1(x) is equal to 1.2V. The first flag and the second flag are initialized to the first value. In step S503, the controller 200 determines that the error bit count of memory block BK231 is not equal to "0". Therefore, the controller 200 enters step S509 to determine the error bit count, the first flag, and the second flag of memory block BK231. The defect type is, for example, the error bit count is less than "1" and the first flag is the first value. Therefore, the controller 200 increments "x" in step S509 and enters step S503 through the determination in step S506.

[0070] When the reference voltage VCC1(x) is equal to 0.99V, the controller 200 determines in step S503 that the error bit count of memory block BK231 is equal to "1". Therefore, the controller 200 obtains the first voltage value in step S504 and sets the first flag to the second value. Next, the controller 200 increments "x" in step S505 (e.g., x = x + 1), and proceeds to step S503 after the determination in step S506.

[0071] Next, in step S503, when the error bit count of memory block BK231 is equal to "1", the controller 200 will loop through steps S504, S505, S506, and S503, and so on.

[0072] Next, in step S503, when the error bit count of memory block BK231 is equal to "0", the controller 200 will loop through steps S509, S505, S506, and S503, and so on.

[0073] When the reference voltage VCC1(x) is 0.72V, the error bit count of memory block BK231 is "8". The controller 200 proceeds to step S509 to determine if the error bit count of memory block BK231 is greater than "1", setting the first flag to the second value and the second flag to the first value. Therefore, in step S510, the controller 200 uses the previous voltage value of the reference voltage VCC1(x) (i.e., 0.765V) as the second voltage value and sets the second flag to the second value. Thus, the controller 200 obtains a voltage range VR2 equal to 0.225V.

[0074] For example, in memory block BK173, in step S510, the controller 200 uses the current voltage value of the reference voltage VCC1(x) (i.e., 0.72V) as the second voltage value.

[0075] Please refer to Figures 1 and 10. Figure 10 is a defect statistics chart illustrated according to an embodiment of the present invention. In this embodiment, the controller 200 can use memory test items T1 and T2 to execute the defect detection method S100, thereby obtaining defect counts DFI1~DFIn corresponding to different memory test items. Column L1 of the statistics chart records memory blocks with defects. Column L2 of the statistics chart records the defect address of each memory block where a defect occurs. Column L6 of the statistics chart records the defect count of each memory block where a defect occurs in test items T1 and T2.

[0076] For example, test item T1 is different from test item T2. Therefore, the defect count for defects occurring in test item T1 may differ from the defect count for defects occurring in test item T2. Testers or R&D personnel can analyze the defects based on Figure 10.

[0077] In summary, the defect detection method of the present invention divides the memory array into multiple memory blocks to obtain multiple defect counts for the multiple memory blocks after the aforementioned access operations. The defect type of the multiple memory blocks can be determined based on the multiple defect counts. The defect count of a single memory block will be lower than the defect count of the memory array. In this way, the defect type of the memory block is easily determined.

[0078] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0079] 100, 100_1, 100_2, 100_3: Memory devices 110: Memory Array 200: Controller ADDR0~ADDR4, ADDR10~ADDR12, ADDR14, ADDR15: Defective addresses BK1~BKn: Memory blocks BK(i): Select memory block Col: Memory line address DFI1~DFIn: Defect Count DQp: Data pin address FBC1: Error Bit Count FBL1: Error Bit Line Count L1, L2, L3, L4, L5, L6: Fields S100, S200, S300, S400, S500: Defect Detection Methods S110~S130, S210~S260, S301~S30x, S401~S412, S501~S510: Steps T1, T2: Memory Test Items TB1, TB2, TB3, TB4: Table Unit[m]: Target memory block VCC1, VCC1(x), VCC2: Reference voltages VR1~VR3: Voltage range WL: Character line address

Claims

1. A defect detection method for a memory device, wherein the memory device includes a memory array, wherein the memory array performs an access operation based on a reference voltage, wherein the defect detection method includes: The memory array is divided into multiple memory blocks; The reference voltage is adjusted to sequentially perform the access operation on the memory blocks, and multiple defect counts of the memory blocks after the access operation are received; and a defect type of the memory blocks is determined based on the defect counts, wherein each defect count includes an error bit count and an error bit line count, and determining the defect type of the memory blocks based on the defect counts includes: defining one of a bit line failure and a data failure of the memory blocks based on the error bit count and the error bit line count.

2. The defect detection method as described in claim 1, wherein the step of defining the defect type of the memory blocks based on the error bit count and the error bit line count includes: When the error bit count of a first memory block corresponding to these memory blocks is equal to 0 and the error bit line count of the first memory block is equal to 0, the first memory block is determined to be a qualified memory block.

3. The defect detection method as described in claim 2, wherein the step of defining the defect type of the memory blocks based on the error bit count and the error bit line count further includes: When the error bit count corresponding to the first memory block is greater than 0 and the error bit line count corresponding to the first memory block is equal to 1, it is determined that the first memory block has a bit line failure.

4. The defect detection method as described in claim 2, wherein the step of defining the defect type of the memory blocks based on the error bit count and the error bit line count further includes: When the error bit count corresponding to the first memory block is equal to a and the error bit line count corresponding to the first memory block is greater than 1, it is determined that the first memory block has a bit defects, where a is a positive integer.

5. The defect detection method as described in claim 2, wherein the step of defining the defect type of the memory blocks based on the error bit count and the error bit line count further includes: When the error bit line count corresponding to the first memory block is greater than a set value, it is determined that the first memory block has data failure.

6. The defect detection method as described in claim 1 further includes: The error bit counts of at least one of the defect counts are sorted according to the voltage value of the reference voltage.

7. The defect detection method as described in claim 6 further includes: A range of error bit counts is set based on the defect type; And obtain a voltage value range corresponding to the reference voltage for the range of error bit counts.

8. The defect detection method as described in claim 7, wherein the step of obtaining the voltage value range corresponding to the reference voltage of the error bit count range includes: The reference voltage is subtracted from a maximum voltage value to obtain a first voltage value that initially corresponds to the error bit count range and a second voltage value that ultimately corresponds to the error bit count range. And subtract the second voltage value from the first voltage value to obtain the voltage range.

9. The defect detection method as claimed in claim 7, wherein the step of obtaining the voltage value range corresponding to the reference voltage of the error bit count range includes: The reference voltage is incremented by a minimum voltage value to obtain a first voltage value that initially corresponds to the error bit count range and a second voltage value that ultimately corresponds to the error bit count range; And subtract the first voltage value from the second voltage value to obtain the voltage range.

10. The defect detection method as described in claim 1 further includes: When the sum of the error bit counts of the plurality of defect counts of the memory array is less than or equal to a threshold value, the addresses of the plurality of defects of the memory array are recorded. And when the sum of the error bit counts of the plurality of defect counts of the memory array exceeds the threshold, the recording of the defect addresses is stopped.

11. The defect detection method as described in claim 10, wherein each of the defect addresses includes a word line address, a memory line address, and a data pin address.

12. The defect detection method as described in claim 11, wherein each of the defect addresses further includes a memory array address and a memory block address.

13. The defect detection method as claimed in claim 1, wherein the defect detection method is performed based on a plurality of different memory test items to obtain defect counts corresponding to the different memory test items.

14. The defect detection method as described in claim 1 further includes: A status flag is generated based on the defect type; And based on the status flag, determine whether to display the defect address corresponding to the defect type.

15. The defect detection method as described in claim 14, wherein the multiple error bit counts of the memory blocks and the order of the memory blocks are used to determine whether to display a defect address corresponding to a defect type and the order in which the addresses are displayed.

16. The defect detection method as described in claim 15 further includes: When the error bit count of a first memory block corresponding to these memory blocks is equal to 0, the first memory block is determined to be a qualified memory block, and a flag indicating that the first memory block is a qualified memory block is generated and a qualified address is recorded.

17. The defect detection method as described in claim 15 further includes: When the sum of the counts of these faulty bits in the memory array exceeds a threshold, recording of defective addresses stops.

18. The defect detection method as described in claim 1 further includes: Select a first functional test item to perform the test on these memory blocks to record the error bit count and error bit line count of these memory blocks; And a second functional test item is used to display the error bit count and error bit line count of these memory blocks.

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