Overvoltage protection circuit

Abstract

This invention provides an overvoltage protection circuit. The overvoltage protection circuit includes a main control transistor, a first resistance circuit, and a second resistance circuit. The first resistance circuit has a first resistance value, and the second resistance circuit has a second resistance value. The first terminal of the main control transistor is coupled to the input voltage and connected to the first terminal of the first resistance circuit. The second terminal of the main control transistor serves as the output terminal of the overvoltage protection circuit. The first terminal of the second resistance circuit is connected to the second terminal of the first resistance circuit. The control node between the first terminal of the second resistance circuit and the second terminal of the first resistance circuit is connected to the control terminal of the main control transistor.

Description

Technical Field

[0001] This invention relates to overvoltage, and more particularly to an overvoltage protection circuit. Prior Technology

[0002] Load dump, also known as a load slip, refers to the sudden disconnection of a power load. Load switching transients are a serious electrical hazard that requires close monitoring, as sudden load disconnection can primarily cause power supply or other equipment on the main line to malfunction, and may also cause a sudden voltage surge in inductive generators.

[0003] In automotive electronics, a battery connects various electronic control units (ECUs) and the alternator. Normally, the alternator charges the battery, but when the wiring harness ages or has poor contact, the battery may disconnect from the circuit. This causes a surge voltage at the alternator output. Because this surge voltage is very high and lasts for a very long time, it can cause significant damage to the various ECUs. This condition is called load dump. The peak voltage of a typical surge can reach 120V and can last up to 400 milliseconds. Typically, 12V automotive electrical systems have load dump protection up to 40V, and 24V automotive electrical systems have load dump protection up to 60V. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an overvoltage protection circuit. The overvoltage protection circuit of this invention includes a main control transistor, a first resistance circuit, and a second resistance circuit. The first terminal of the main control transistor is coupled to the input voltage. The second terminal of the main control transistor serves as the output terminal of the overvoltage protection circuit. The first resistance circuit has a first resistance value. The first terminal of the first resistance circuit is connected to the first terminal of the main control transistor. The second resistance circuit has a second resistance value. The first terminal of the second resistance circuit is connected to the second terminal of the first resistance circuit. The second terminal of the second resistance circuit is coupled to a reference potential. A control node between the first terminal of the second resistance circuit and the second terminal of the first resistance circuit is connected to the control terminal of the main control transistor.

[0005] As described above, this invention provides an overvoltage protection circuit. When various application scenarios, such as load dumping in the vehicle-mounted device, coupling at the input power supply harness, power grid surges, or lightning strikes, cause a surge / instantaneous high voltage in the output voltage, this invention's overvoltage protection circuit can immediately clamp the output voltage to prevent it from exceeding the rated voltage of the circuit components and burning them out. Compared to traditional overvoltage protection circuits, this invention's overvoltage protection circuit does not use large inductors, surge protection devices (SPDs), or transient voltage suppressors (TVS), thus significantly reducing heat generation and space occupation.

[0006] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Simple Explanation of the Diagram

[0007] Figure 1 is a circuit diagram of the overvoltage protection circuit of the first embodiment of the present invention.

[0008] Figure 2 is a circuit diagram of the overvoltage protection circuit of the second embodiment of the present invention.

[0009] Figure 3 is a circuit diagram of the overvoltage protection circuit of the third embodiment of the present invention.

[0010] Figure 4 is a circuit diagram of the overvoltage protection circuit of the fourth embodiment of the present invention.

[0011] Figure 5 is a circuit diagram of the overvoltage protection circuit according to the fifth embodiment of the present invention.

[0012] Figure 6 is a circuit diagram of the overvoltage protection circuit of the sixth embodiment of the present invention.

[0013] Figure 7 is a circuit diagram of the overvoltage protection circuit of the seventh embodiment of the present invention.

[0014] Figure 8 is a circuit diagram of the bias circuit of the overvoltage protection circuit of the eighth embodiment of the present invention.

[0015] Figure 9 is a circuit diagram of the bandgap reference circuit of the overvoltage protection circuit of the ninth embodiment of the present invention.

[0016] Figure 10 is a circuit diagram of the comparator in the overvoltage protection circuit of the tenth embodiment of the present invention.

[0017] Figure 11 shows the waveforms of the overvoltage protection circuits in the first to tenth embodiments of the present invention.

[0018] Figure 12 shows the waveforms of the overvoltage protection circuits in the first to tenth embodiments of the present invention. Implementation

[0019] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0020] Please refer to Figure 1, which is a circuit diagram of the overvoltage protection circuit of the first embodiment of the present invention.

[0021] As shown in Figure 1, in the first embodiment, the overvoltage protection circuit of the present invention includes a main control transistor Q1, a first resistance circuit RES10 and a second resistance circuit RES20.

[0022] The first terminal (e.g., the source) of the master control transistor Q1 is coupled to an input voltage VIN. The second terminal (e.g., the drain) of the master control transistor Q1 serves as an output terminal of the overvoltage protection circuit of this invention. The voltage at the second terminal of the master control transistor Q1 serves as the output voltage VOUT of the overvoltage protection circuit of this invention.

[0023] It is worth noting that the first resistance circuit RES10 and the second resistance circuit RES20 are configured between the input voltage VIN and a reference potential VSS, wherein the first resistance circuit RES10 is connected in parallel to the parasitic capacitance Cgs of the main control transistor Q1.

[0024] The first resistance circuit RES10 is a circuit having a first resistance value, which can be a fixed resistance value or a variable resistance value. The first resistance circuit RES10 includes one or more circuit elements, and the first resistance value of the first resistance circuit RES10 is the total resistance value of these one or more circuit elements.

[0025] The second resistance circuit RES20 is a circuit having a second resistance value, which can be a fixed resistance value or a variable resistance value. The second resistance circuit RES20 includes one or more circuit elements, and the second resistance value of the second resistance circuit RES20 is the total resistance value of these one or more circuit elements. The second resistance value of the second resistance circuit RES20 is different from the first resistance value of the first resistance circuit RES10.

[0026] The first terminal of the first resistance circuit RES10 is connected to an input node between the first terminal of the main control transistor Q1 and the input voltage VIN, or to an input node between the first terminal of the main control transistor Q1 and the input power supply used to supply the input voltage VIN. The first terminal of the second resistance circuit RES20 is connected to the second terminal of the first resistance circuit RES10. The second terminal of the second resistance circuit RES20 is coupled to a reference potential VSS.

[0027] The node between the first terminal of the second resistance circuit RES20 and the second terminal of the first resistance circuit RES10 serves as a control node, connected to the control terminal (e.g., the gate) of the main control transistor Q1. The voltage input of this control node to the control terminal of the main control transistor Q1 serves as the voltage VG of the control terminal (e.g., the gate) of the main control transistor Q1.

[0028] In other words, the overvoltage protection circuit of the present invention includes a first resistance circuit RES10 and a second resistance circuit RES20 configured with a main control transistor Q1. Thus, by appropriately setting or adjusting the first resistance value of the first resistance circuit RES10 and the second resistance value of the second resistance circuit RES20, the equivalent impedance of the parasitic capacitance Cgs of the main control transistor Q1 connected in parallel with the first resistance circuit RES10 can be appropriately set, as can the proportion of the second resistance value to the sum of the first and second resistance values. This allows for appropriate control or adjustment of the voltage VG at the control terminal (e.g., the gate) of the main control transistor Q1. Before the voltage at the second terminal of the main control transistor Q1, i.e., the output voltage VOUT of the overvoltage protection circuit of the present invention, rises to an excessively high voltage value, the output voltage VOUT is clamped, ensuring it does not exceed the operating voltage / rated voltage of the overvoltage protection circuit of the present invention and the load or other downstream circuits connected to its output terminal, preventing the overvoltage protection circuit of the present invention and its load or other downstream circuits from burning out due to overvoltage.

[0029] Please refer to Figure 2, which is a circuit diagram of the overvoltage protection circuit of the second embodiment of the present invention.

[0030] As shown in Figure 2, in the second embodiment, the overvoltage protection circuit of the present invention includes a main control transistor Q1, a first resistance circuit RES11, and a second resistance circuit RES21.

[0031] The first resistance circuit RES11, as shown in Figure 2, includes a resistor R11. The first resistance value of the first resistance circuit RES11 includes the resistance value of resistor R11. In practice, the first resistance circuit RES11 may include multiple resistors R11 with the same or different resistance values ​​connected in series or in parallel. The first resistance value of the first resistance circuit RES11 includes the total resistance value of the multiple resistors R11 connected in series or in parallel.

[0032] The second resistance circuit RES21, as shown in Figure 2, includes a resistor R21. The second resistance value of the second resistance circuit RES21 includes the resistance value of resistor R21. In practice, the second resistance circuit RES21 may include multiple resistors R21 with the same or different resistance values ​​connected in series or in parallel. The second resistance value of the second resistance circuit RES21 includes the total resistance value of the multiple resistors R21 connected in series or in parallel.

[0033] The first terminal of resistor R11 is coupled to the input voltage VIN. The second terminal of resistor R11 is connected to the first terminal of resistor R21. The second terminal of resistor R21 is coupled to the reference potential VSS. A control node between the second terminal of resistor R11 and the first terminal of resistor R21 is connected to the control terminal of the master transistor Q1.

[0034] In the time domain, the voltage at the control terminal of the master transistor Q1 is expressed by the following formula: VG(t)=VIN×(δ(t)–1 / Cgs×R2×e^-((R1+R2) / (Cgs×R1×R2))t); Where VG is the voltage at the control terminal of the main control transistor Q1 as shown in Figures 1 to 5, or the voltage at the control terminal of the main control transistor Q2 as shown in Figures 6 and 7; VIN is the input voltage; Cgs represents the capacitance value of the parasitic capacitance Cgs of the main control transistor Q1; R1 represents the first resistance value of the first resistance circuit RES10 as shown in Figure 1, the first resistance circuit RES11 as shown in Figure 2 or 3, the first resistance circuit RES12 as shown in Figure 4, or the first resistance circuit RES13 as shown in Figures 5 to 7; R2 represents the second resistance value of the second resistance circuit RES20 as shown in Figure 1, the second resistance circuit RES21 as shown in Figure 2 or 3, the first resistance circuit RES22 as shown in Figure 4, the second resistance circuit RES23 as shown in Figure 5, or the second resistance circuit RES24 as shown in Figure 6 or 7.

[0035] When a surge occurs in the output voltage VOUT of the second terminal of the master control transistor Q1, and time t is 0, the voltage VG at the control terminal of the master control transistor Q1 is equal to VIN[1-(1 / Cgs×R2)]. When VIN×(1 / Cgs×R2)<|Vth|, the master control transistor Q1 will turn off.

[0036] Therefore, by setting up second resistance circuits RES21 with different second resistance values, or by connecting the parasitic capacitance Cgs of the main control transistor Q1 in parallel with first resistance circuits RES1 with different first resistance values ​​to obtain different equivalent impedances, the turn-off time of the main control transistor Q1 will be different. In particular, when a surge occurs in the output voltage VOUT of the second terminal of the main control transistor Q1, the main control transistor Q1 is controlled to turn off instantaneously to clamp the output voltage VOUT of the overvoltage protection circuit of the present invention, preventing the output voltage VOUT of the overvoltage protection circuit of the present invention from continuing to rise to the overvoltage value, which would cause the overvoltage protection circuit of the present invention and its connected subsequent circuits to burn out due to overvoltage.

[0037] Please refer to Figure 3, which is a circuit diagram of the overvoltage protection circuit of the third embodiment of the present invention.

[0038] The third embodiment of the present invention is identical to the second embodiment and will not be described again in this document.

[0039] The difference between the third embodiment and the second embodiment of the present invention is that, as shown in FIG3, the overvoltage protection circuit of the third embodiment of the present invention further includes an output capacitor Cout.

[0040] The first terminal of the output capacitor Cout is connected to the second terminal of the main control transistor Q1, and the second terminal of the output capacitor Cout is coupled to the reference potential VSS.

[0041] The second terminal of the main control transistor Q1 or the second terminal of the output capacitor Cout included in the overvoltage protection circuit of this invention serves as the output terminal of the overvoltage protection circuit of this invention and is connected to the first terminal of the load RL. The second terminal of the load RL can be coupled to the reference potential VSS.

[0042] When the main control transistor Q1 is off, the smaller the resistance of the load RL and the capacitance of the output capacitor Cout, the faster the output voltage VOUT decreases. Conversely, when the main control transistor Q1 is off, the larger the resistance of the load RL and the capacitance of the output capacitor Cout, the slower the output voltage VOUT decreases.

[0043] Conversely, when the master transistor Q1 is in the ON state, the smaller the on-resistance (denoted as Rds hereinafter) between the first terminal (e.g., source) and the second terminal (e.g., drain) of the master transistor Q1, and the smaller the output capacitor Cout and the larger the load RL, the faster the output voltage VOUT rises. Therefore, by switching the master transistor Q1 between the ON and OFF states, the output voltage VOUT can be controlled to remain stable within an operating voltage range.

[0044] Since the load RL changes unpredictably, the only adjustments can be made to the switching speed of the main control transistor Q1, the capacitance value of the output capacitor Cout, and the resistance value Rds. To make the switching speed of the main control transistor Q1 slower and the ripple in the output voltage VOUT smaller, the output capacitor Cout can be set to have a larger capacitance value, and the main control transistor Q1 can be selected with a smaller resistance value Rds.

[0045] In practice, the output capacitor Cout and the load RL shown in Figure 3 can also be configured in the same way in the overvoltage protection circuit of the present invention as shown in Figures 1, 2, 4 to 7.

[0046] Please refer to Figure 4, which is a circuit diagram of the overvoltage protection circuit of the fourth embodiment of the present invention.

[0047] As shown in Figure 4, in the fourth embodiment, the overvoltage protection circuit of the present invention includes a main control transistor Q1, a first resistance circuit RES12 and a second resistance circuit RES22.

[0048] As shown in Figures 2 and 3, the resistor R11 in the first resistance circuit RES11 and the resistor R21 in the second resistance circuit RES21 of the overvoltage protection circuit of the second and third embodiments of the present invention are both fixed resistors with fixed resistance values.

[0049] In contrast, the resistor R12 in the first resistance circuit RES12 and the resistor R22 in the second resistance circuit RES21 of the overvoltage protection circuit of the fourth embodiment of the present invention shown in FIG4 are both variable resistors with variable resistance values.

[0050] In practice, one of resistors R11 and R21 can be a fixed resistor and the other can be a variable resistor.

[0051] In the overvoltage protection circuit of the fourth embodiment of the present invention, the voltage VG of the control terminal (e.g., gate) of the main control transistor Q1 can be adjusted at any time by appropriately adjusting the first resistance value, the second resistance value, or both, so as to appropriately control the operating state of the main control transistor Q1 and maintain the voltage of the second terminal of the main control transistor Q1 (i.e., the output voltage VOUT of the overvoltage protection circuit of the present invention) within the operating voltage range of the overvoltage protection circuit and its subsequent circuits of the present invention.

[0052] Please refer to Figure 5, which is a circuit diagram of the overvoltage protection circuit of the fifth embodiment of the present invention.

[0053] As shown in Figure 5, in the fifth embodiment, the overvoltage protection circuit of the present invention includes a main control transistor Q1, a first resistance circuit RES13 and a second resistance circuit RES23.

[0054] The first resistance circuit RES13 includes a transistor as the first transistor Tr1. The first resistance circuit RES13 is a circuit with a first resistance value, which includes the internal resistance of the first transistor Tr1.

[0055] The second resistance circuit RES23 includes a transistor as a control-side transistor Tr2. The second resistance circuit RES23 is a circuit with a second resistance value, which includes the internal resistance of the control-side transistor Tr2.

[0056] The first terminal of the first transistor Tr1 is connected to an input node between the first terminal of the master transistor Q1 and the input voltage VIN. A control node between the second terminal of the first transistor Tr1 and the first terminal of the control-side transistor Tr2 is connected to the control terminal of the master transistor Q1. The control terminal of the master transistor Q1 has a voltage VG.

[0057] The control terminal of the first transistor Tr1 is coupled to the first upper bias voltage VH1. The control terminal of the control-side transistor Tr2 is coupled to the first lower bias voltage VL1. Both the first upper bias voltage VH1 and the first lower bias voltage VL1 can be variable voltages.

[0058] In the overvoltage protection circuit of the fifth embodiment of the present invention, the operating states of the first transistor Tr1, the first control-side transistor Tr2, or both can be appropriately controlled by setting or adjusting the first upper bias voltage VH1 coupled to the control terminal of the first transistor Tr1, the first lower bias voltage VL1 coupled to the control terminal of the control-side transistor Tr2, or both. This controls the first resistance value and the second resistance value of the second resistance circuit RES23, thereby appropriately controlling the voltage VG of the control terminal (e.g., the gate) of the main control transistor Q1. Thus, the voltage at the second terminal of the main control transistor Q1 (i.e., the output voltage VOUT of the overvoltage protection circuit of the present invention) can be maintained within the operating voltage range of the overvoltage protection circuit and its subsequent circuits.

[0059] Please refer to Figure 6, which is a circuit diagram of the overvoltage protection circuit of the sixth embodiment of the present invention.

[0060] As shown in Figure 6, in the sixth embodiment, the overvoltage protection circuit of the present invention includes a main control transistor Q2, a first resistance circuit RES13, and a second resistance circuit RES24, and further includes a comparator CMP1 and a voltage divider circuit DIV. In practice, the voltage divider circuit DIV can be omitted.

[0061] It is worth noting that in the overvoltage protection circuit of the sixth embodiment of the present invention, the second resistance circuit RES24 includes a resistance element RET, a transistor circuit ARY, and a bypass switch Te. In practice, the resistance element RET can be expanded or omitted.

[0062] The first terminal of the first transistor Tr1 is connected to an input node between the first terminal of the master control transistor Q2 and the input voltage VIN. The control terminal of the first transistor Tr1 is coupled to the first upper bias voltage VH1.

[0063] A resistance element RET comprises one or more circuit elements having a resistance value. For example, as shown in Figure 6, the resistance element RET includes a transistor as a control-side transistor Tr2. The first terminal of the control-side transistor Tr2 is connected to the second terminal of the first transistor Tr1. The control terminal of the control-side transistor Tr2 is coupled to a first lower bias voltage VL1. In practice, the control-side transistor Tr2 can be replaced by a resistor R21 as shown in Figure 2, a resistor R22 as shown in Figure 4, or other circuit elements having a resistance value.

[0064] The control terminal of the master transistor Q2 is connected to a control node between the first terminal of the control-side transistor Tr2 and the second terminal of the first transistor Tr1.

[0065] A transistor circuit ARY contains multiple transistors, which are respectively used as multiple array transistors Ta. In practice, a transistor circuit ARY may also contain only a single transistor. The number and type of the multiple array transistors Ta contained in the transistor circuit ARY depend on the actual application requirements. Figure 6 is only an example for illustration, and the present invention is not limited thereto.

[0066] The first terminal of each of the multiple array transistors Ta is connected to the second terminal of the control-side transistor Tr2. The second terminal of each of the multiple array transistors Ta is coupled to the reference potential VSS. The control terminal of each of the multiple array transistors Ta is coupled to a switching control voltage or connected to the output of comparator CMP1 as shown in Figure 6.

[0067] The bypass switch Te can be a transistor. The first terminal of the bypass switch Te is connected to the second terminal of the control-side transistor Tr2 and the first terminal of each of the multiple array transistors Ta. The second terminal of the bypass switch Te is coupled to a reference potential VSS. The control terminal of the bypass switch Te is coupled to a variable command voltage VE, or practically connected to an external control circuit to receive this variable command voltage VE from the external control circuit.

[0068] The voltage divider circuit DIV includes a first voltage divider resistor Rd1 and a second voltage divider resistor Rd2. The first terminal of the first voltage divider resistor Rd1 is connected to the second terminal of the main control transistor Q2 (this is the output terminal of the overvoltage protection circuit of this invention). The second terminal of the first voltage divider resistor Rd1 is connected to the first terminal of the second voltage divider resistor Rd2. The second terminal of the second voltage divider resistor Rd2 is coupled to a reference potential VSS.

[0069] As shown in Figure 6, the first input terminal of comparator CMP1, for example the inverting input terminal, is connected to a feedback node between the second terminal of the first voltage divider resistor Rd1 and the first terminal of the second voltage divider resistor Rd2, to obtain a voltage at this feedback node as a feedback voltage VFB. In practice, if the voltage divider circuit DIV is omitted, the first input terminal of comparator CMP1 can be directly connected to the second terminal of the main control transistor Q2 (which is the output terminal of the overvoltage protection circuit of this invention) to obtain the output voltage VOUT.

[0070] The second input of comparator CMP1, such as the inverting input, can be coupled to a reference voltage VREF. The output of comparator CMP1 is connected to the control terminal of each of the plurality of array transistors Ta. Comparator CMP1 is configured to compare the feedback voltage VFB with the reference potential VSS to determine the level of a comparison signal CMS, and outputs this comparison signal CMS to the control terminal of each of the plurality of array transistors Ta.

[0071] The higher the output voltage VOUT of the overvoltage protection circuit of this invention, the higher the voltage division voltage of the output voltage VOUT, i.e., the feedback voltage VFB.

[0072] When the feedback voltage VFB of the overvoltage protection circuit of the present invention is not higher than a reference voltage VREF, no overvoltage event occurs in the overvoltage protection circuit of the present invention, and therefore no overvoltage protection is required. At this time, the comparator CMP1 outputs a comparison signal CMS with a first level, such as a high level, to the control terminal of each of the plurality of array transistors Ta, so as to turn on the plurality of array transistors Ta of the transistor circuit ARY. At the same time, the control terminal of the control-side transistor Tr2 included in the resistive element RET receives a first upper bias voltage VH1 with a first level, such as a high level, causing the control-side transistor Tr2 to turn on. At the same time, the bypass switch Te turns on according to a received variable command voltage VE with a first level (e.g., a high level), thereby reducing the leakage current of the overvoltage protection circuit of the present invention.

[0073] It is worth noting that when the voltage at the second terminal of the main control transistor Q2 of the overvoltage protection circuit of the present invention (which is the output voltage VOUT of the overvoltage protection circuit of the present invention) is too high, causing the feedback voltage VFB to be higher than a reference voltage VREF, the overvoltage protection circuit of the present invention will experience an overvoltage event, and overvoltage protection is required at this time.

[0074] In the frequency domain, the voltage at the control terminal of the master transistor Q1 is expressed by the following formula: VG=VIN×((sCgs×R1×R2+R2) / (sCgs×R1×R2+R1+R2)), s = j×ω = j×2×π×f, Where VG is the voltage at the control terminal of the main control transistor Q1 as shown in Figures 1 to 5, or the voltage at the control terminal of the main control transistor Q2 as shown in Figures 6 and 7, VIN is the input voltage, f is the frequency of the waveform of the input voltage VIN signal, R1 represents the first resistance value of the first resistance circuit RES10 as shown in Figure 1, the first resistance circuit RES11 as shown in Figure 2 or 3, the first resistance circuit RES12 as shown in Figure 4, or the first resistance circuit RES13 as shown in Figures 5 to 7, and R2 represents the second resistance value of the second resistance circuit RES20 as shown in Figure 1, the second resistance circuit RES21 as shown in Figure 2 or 3, the first resistance circuit RES22 as shown in Figure 4, the second resistance circuit RES23 as shown in Figure 5, or the second resistance circuit RES24 as shown in Figure 6 or 7.

[0075] The higher the frequency of the input voltage VIN, the smaller sCgs will be, thus reducing the parallel equivalent impedance of resistor R11. Conversely, the lower the parallel equivalent impedance of resistor R11, the closer the voltage VG at the control terminal of the main control transistor Q1 will be to the input voltage VIN.

[0076] When the voltage difference obtained by subtracting the voltage VG at the control terminal of the main control transistor Q1 from the input voltage VIN is less than the absolute value of the critical voltage Vth of the main control transistor Q1, that is, VIN–VG < |Vth|, the main control transistor Q1 will turn off.

[0077] As described above, when overvoltage protection is to be implemented, the ratio of the second resistance value of the second resistance circuit RES24 to the sum of the first resistance value of the first resistance circuit RES13 and the second resistance value of the second resistance circuit RES24 needs to be increased to increase the voltage VG at the control terminal of the main control transistor Q1, so that the condition VIN–VG < |Vth| is met, thereby turning off the main control transistor Q2.

[0078] When the output voltage VOUT of the overvoltage protection circuit of this invention is too high, causing the voltage division voltage VFB of the output voltage VOUT, i.e., the feedback voltage, to be higher than the reference voltage VREF, an overvoltage event is about to occur or has already occurred, thus requiring overvoltage protection. At this time, the bypass switch Te is turned off based on a received variable command voltage VE with an initial level (low level). Simultaneously, the control terminal of the control-side transistor Tr2 included in the resistive element RET receives a first upper bias voltage VH1 with an initial level, for example, a low level, causing the control-side transistor Tr2 to turn off. Simultaneously, the comparator CMP1 outputs a comparison signal CMS with an initial level, for example, a low level, to the control terminal of each of the plurality of array transistors Ta, thereby turning off the plurality of array transistors Ta of the transistor circuit ARY. Thus, the absolute value of the difference between the input voltage VIN and the voltage VG is less than the critical voltage of the main control transistor Q2, i.e., VIN–VG < |Vth|, causing the main control transistor Q2 to turn off. This prevents the voltage at the second terminal of the main control transistor Q2 (i.e., the output voltage VOUT of the overvoltage protection circuit of the present invention) from continuously increasing to the overvoltage value, which would cause the overvoltage protection circuit of the present invention and its connected subsequent circuits to burn out.

[0079] Please refer to Figure 7, which is a circuit diagram of the overvoltage protection circuit of the seventh embodiment of the present invention.

[0080] The seventh embodiment of the present invention is the same as the sixth embodiment and will not be repeated here.

[0081] The difference between the seventh embodiment and the sixth embodiment of the present invention is that the overvoltage protection circuit of the seventh embodiment further includes a bias circuit BAS, a bandgap reference circuit GRE, and a resistor Rs.

[0082] The input terminal of the bias circuit BAS can be directly coupled to the input voltage VIN. Alternatively, the bias circuit BAS can be coupled to the input voltage VIN through a resistor Rs.

[0083] The first output terminal of the bias circuit BAS is connected to the control terminal of the first transistor Tr1. The bias circuit BAS sets and modulates the first upper bias voltage VH1. The second output terminal of the bias circuit BAS outputs the first upper bias voltage VH1 to the control terminal of the first transistor Tr1.

[0084] The second output of the bias circuit BAS is connected to the control terminal of the control-side transistor Tr2. The second output of the bias circuit BAS sets and modulates the first lower bias voltage VL1. The third output of the bias circuit BAS outputs the first lower bias voltage VL1 to the control terminal of the control-side transistor Tr2.

[0085] The first, second, and fourth output terminals of the bias circuit BAS are connected to the input terminals of the bandgap reference circuit GRE. The first output terminal of the bias circuit BAS outputs an initial upper bias voltage VH0, the second output terminal of the bias circuit BAS outputs a first upper bias voltage VH1, and the fourth output terminal of the bias circuit BAS outputs an initial upper bias voltage VL0 to the bandgap reference circuit GRE.

[0086] The output of the bandgap reference circuit GRE is connected to the second input of comparator CMP1, such as the non-inverting input. Based on the initial upper bias voltage VH0, the first upper bias voltage VH1, and the initial upper bias voltage VL0 received from the bias circuit BAS, the bandgap reference circuit GRE sets the reference voltage VREF and outputs the reference voltage VREF to the second input of comparator CMP1, such as the non-inverting input.

[0087] If necessary, the control terminal of each of the multiple array transistors Ta can be further coupled to a variable switching voltage CT as shown in Figure 7, or connected to an external control circuit to receive a variable switching voltage CT from the external control circuit, and switch the multiple array transistors Ta through this variable switching voltage CT.

[0088] Please refer to Figure 8, which is a circuit diagram of the overvoltage protection circuit of the eighth embodiment of the present invention.

[0089] The overvoltage protection circuit of this invention may include a bias circuit BAS as shown in Figure 8. The bias circuit BAS shown in Figure 7 can be replaced with the bias circuit BAS shown in Figure 8.

[0090] As shown in Figure 8, the bias circuit BAS includes a bias start-up circuit BA1 and a bias supply circuit BA2.

[0091] The bias start-up circuit BA1 includes a first start-up transistor Ts1 and a second start-up transistor Ts2, while the bias supply circuit BA2 includes a first bias transistor Tb1, a second bias transistor Tb2, a third bias transistor Tb3, a fourth bias transistor Tb4, a fifth bias transistor Tb5, a sixth bias transistor Tb6, a seventh bias transistor Tb7, and an eighth bias transistor Tb8.

[0092] The first terminal of resistor Rs is coupled to the input voltage VIN. The first terminal of the first startup transistor Ts1 and the control terminal are connected to the second terminal of resistor Rs to obtain a voltage Vs from the second terminal of resistor Rs. This resistor Rs can have a high resistance value to protect the bias startup circuit BA1. The first terminal of the second startup transistor Ts2 is connected to the first terminal of the first startup transistor Ts1 and the control terminal. The second terminal of the second startup transistor Ts2 is coupled to the reference potential VSS.

[0093] The first terminal of the first bias transistor Tb1 and the first terminal of the second bias transistor Tb2 are coupled to the input voltage VIN. The first terminal of the third bias transistor Tb3, the second terminal and control terminal of the first bias transistor Tb1, and the control terminal of the second bias transistor Tb2 are connected to an initial upper bias node, which has an initial upper bias voltage VH0.

[0094] The first terminal of the fourth bias transistor Tb4 is connected to the second terminal of the second bias transistor Tb2. The first terminal of the fifth bias transistor Tb5, the second terminal and control terminal of the third bias transistor Tb3, and the control terminal of the fourth bias transistor Tb4 are connected to the first upper bias node, which has a first upper bias VH1.

[0095] The first terminal and control terminal of the sixth bias transistor Tb6, the control terminal of the fifth bias transistor Tb5, and the second terminal of the first start transistor Ts1 are connected to the first lower bias node, which has a first lower bias VL1.

[0096] The first terminal of the seventh bias transistor Tb7 is connected to the second terminal of the fifth bias transistor Tb5. The second terminals of the seventh bias transistor Tb7 and the eighth bias transistor Tb8 are coupled to a reference potential VSS. The first and control terminals of the eighth bias transistor Tb8, the second terminal of the sixth bias transistor Tb6, the control terminal of the seventh bias transistor Tb7, and the control terminal of the second start-up transistor Ts2 are connected to an initial lower bias node, which has an initial lower bias VL0.

[0097] The input voltage VIN, as shown in Figure 7, flows through resistor Rs to the first input current inside the bias circuit BAS, as shown in Figures 7 and 8. It then flows through the first transistor Tr1, as shown in Figure 8, turning Tr1 on. Next, it flows through the sixth bias transistor Tb6, and a spur of this first input current flows to the control terminal of the second start-up transistor Ts2. Simultaneously, the second bias transistor Tb2 and the fourth bias transistor Tb4 remain on. The second input current flows directly from the input voltage VIN through the second bias transistor Tb2 and the fourth bias transistor Tb4 to the sixth bias transistor Tb6, and then a spur of this second input current flows to the control terminal of the second start-up transistor Ts2.

[0098] The startup transistor Ts2 switches from the off state to the on state when the initial lower bias voltage VL0 at an initial lower bias node between the second terminal of the sixth bias transistor Tb6 and the first terminal of the eighth bias transistor Tb8 gradually increases to a level higher than the voltage difference between the control terminal (e.g., gate) and the second terminal (e.g., source) of the second startup transistor Ts2 (e.g., VGS = VG - VS, where VG is the gate voltage and VS is the source voltage). At this time, because the resistor Rs divides the voltage and bears a portion of the input voltage VIN, the first startup transistor Ts1 and the second startup transistor Ts2 inside the bias circuit BAS are protected from burning out due to the voltage exceeding their respective rated voltages.

[0099] As shown in Figure 8, the bias start-up circuit BA1 is configured to start the operation of the bias supply circuit BA2, so that the bias supply circuit BA2 can smoothly supply a first upper bias voltage VH1 with an appropriate voltage value to the control terminal of the first transistor Tr1 and the bandgap reference circuit GRE as shown in Figure 7, smoothly supply a first lower bias voltage VL1 with an appropriate voltage value to the control terminal of the control transistor Tr2, and smoothly supply an initial upper bias voltage VH0 and an initial lower bias voltage VL0 with appropriate voltage values ​​to the bandgap reference circuit GRE.

[0100] For example, the initial upper bias voltage VH0 is equal to the input voltage VIN minus the first voltage difference (e.g., 1V), the first upper bias voltage VH1 is equal to the input voltage VIN minus the second voltage difference (e.g., 2V), this second voltage difference is higher than the first voltage difference, the first lower bias voltage VL1 is equal to the second voltage difference (e.g., 2V), and the initial lower bias voltage VL0 is equal to the first voltage difference (e.g., 1V).

[0101] Please refer to Figure 9, which is a circuit diagram of the bias circuit of the overvoltage protection circuit of the ninth embodiment of the present invention.

[0102] The overvoltage protection circuit of this invention may include a bandgap reference circuit GRE as shown in Figure 9. The bandgap reference circuit GRE shown in Figure 7 can be replaced with the bandgap reference circuit GRE shown in Figure 9.

[0103] As shown in Figure 9, the bandgap reference circuit GRE includes a reference voltage supply circuit RFU. If necessary, the bandgap reference circuit GRE can also include a current limiting circuit LM, a voltage drop receiving circuit DRP, or a combination thereof, as shown in Figure 9.

[0104] In other words, a current-limiting circuit LM and a voltage drop receiving circuit DRP can be configured between the input voltage VIN and the reference potential VSS to protect the reference voltage supply circuit RFU.

[0105] The voltage drop receiving circuit (DRP) is configured to absorb a portion of the voltage drop between the input voltage VIN and the reference potential VSS, thereby reducing the voltage drop across the reference voltage supply circuit (RFU) and preventing the RFU from burning out due to overvoltage.

[0106] The current limiting circuit LM is configured to limit the amount of input current flowing from the input voltage VIN through the voltage drop receiver circuit DRP to the reference voltage supply circuit RFU, in order to prevent the instantaneous excessive current from burning out the reference voltage supply circuit RFU.

[0107] It is worth noting that the reference voltage supply circuit RFU includes a temperature sensing circuit RF1 and a reference voltage supply circuit RF2. The reference voltage supply circuit RF2 is connected to the temperature sensing circuit RF1. The temperature sensing circuit RF1 is configured to sense temperature. The reference voltage supply circuit RF2 is configured to output a reference voltage VREF to the second input terminal, such as the inverting input terminal, of the comparator CMP1 based on the temperature sensed by the temperature sensing circuit RF1.

[0108] For example, the temperature sensing circuit RF1 of the reference voltage supply circuit RFU includes one or more temperature sensing elements whose output changes with temperature. For instance, Figure 9 shows a first temperature sensing transistor Tp1 and a second temperature sensing transistor Tp2, both bipolar transistors (BJTs). The voltage level of the bipolar transistor (BJT) changes with temperature, exhibiting a low voltage value at low temperatures and a high voltage value at high temperatures.

[0109] For example, the reference voltage supply circuit RF2 includes an initial reference transistor Tf0, a first reference transistor Tf1, a second reference transistor Tf2, a third reference transistor Tf3, and a fourth reference transistor Tf4. If necessary, the reference voltage supply circuit RF2 may further include a Zener diode Dz1, a Zener diode Dz2, or a combination thereof.

[0110] The initial reference transistor Tf0, the first reference transistor Tf1, the second reference transistor Tf2, the third reference transistor Tf3, and the fourth reference transistor Tf4 form a current mirror circuit.

[0111] For example, the current limiting circuit LM includes a first current limiting transistor Tm1 and a second current limiting transistor Tm2. The first terminal of the first current limiting transistor Tm1 and the first terminal of the second current limiting transistor Tm2 are coupled to the input voltage VIN.

[0112] As shown in Figure 9, the control terminals of the first current-limiting transistor Tm1 and the second current-limiting transistor Tm2 in the current-limiting circuit LM of the bandgap reference circuit GRE are each coupled to an initial upper bias voltage VH0, or connected to the output terminal of the bias circuit BAS as shown in Figure 7 to receive an initial upper bias voltage VH0 from the bias circuit BAS, or connected to an initial upper node of the bias circuit BAS as shown in Figure 8 to receive an initial upper bias voltage VH0 from the initial upper node.

[0113] For example, the voltage drop receiving circuit DRP includes a first piezoelectric transistor Td1, a second piezoelectric transistor Td2, and a third piezoelectric transistor Td3.

[0114] The first terminal of the first piezoelectric transistor Td1 is connected to the second terminal of the first current-limiting transistor Tm1. The first terminal of the second piezoelectric transistor Td2 is connected to the second terminal of the second current-limiting transistor Tm2. The control terminals of the first piezoelectric transistor Td1, the second piezoelectric transistor Td2, and the third piezoelectric transistor Td3 are coupled to the first upper bias voltage VH1, or connected to the output terminal of the bias circuit BAS as shown in Figure 7 to receive the first upper bias voltage VH1 from the bias circuit BAS, or connected to the first upper node of the bias circuit BAS as shown in Figure 8 to receive the first upper bias voltage VH1 from the first upper node.

[0115] The second terminal of the first piezoelectric transistor Td1 is connected to the first terminal of the first temperature-sensing transistor Tp1 in the temperature-sensing circuit RF1 and the control terminal. The second terminal of the second piezoelectric transistor Td2 is connected to the first terminal of the second temperature-sensing transistor Tp2 in the temperature-sensing circuit RF1. The second terminal of the third piezoelectric transistor Td3 is connected to the first terminal of the first reference transistor Tf1 and the first terminal of the third reference transistor Tf3.

[0116] The second terminal of the first thermoelectric transistor Tp1 is coupled to the reference potential VSS.

[0117] The control terminal of the second temperature-sensing transistor Tp2 is connected to the node between the first terminal of the first temperature-sensing transistor Tp1 and the second terminal of the first voltage-bearing transistor Td1. The second terminal of the second temperature-sensing transistor Tp2 is connected to the first terminal of the initial reference transistor Tf0. The second terminal of the initial reference transistor Tf0 is coupled to the reference potential VSS.

[0118] As shown in Figure 9, the control terminal of the initial reference transistor Tf0 in the reference voltage supply circuit RFU is coupled to an initial lower bias voltage VL0, or connected to the output terminal of the bias circuit BAS as shown in Figure 7 to receive the initial lower bias voltage VL0 from the bias circuit BAS, or connected to an initial lower bias node of the bias circuit BAS as shown in Figure 8 to receive an initial lower bias voltage VL0 from this initial lower bias node. The initial reference transistor Tf0 can operate in the linear region and can have very high impedance.

[0119] The cathode of the Zener diode Dz1 is connected to the first terminal of the second thermoelectric transistor Tp2. The anode of the Zener diode Dz1 is coupled to the reference potential VSS.

[0120] The control terminal of the second reference transistor Tf2 is connected to the node between the first terminal of the first temperature-sensing transistor Tp1 and the second terminal of the first voltage-bearing transistor Td1. The first terminal of the first reference transistor Tf1 and the first terminal of the third reference transistor Tf3 are connected to the second terminal of the third voltage-bearing transistor Td3. The control terminal of the third reference transistor Tf3 is connected to the control terminal and the second terminal of the first reference transistor Tf1.

[0121] The first terminal of the second reference transistor Tf2 is connected to the second terminal of the first reference transistor Tf1 and the control terminal. The second terminal of the second reference transistor Tf2 and the second terminal of the fourth reference transistor Tf4 are coupled to the reference potential VSS.

[0122] The first terminal of the fourth reference transistor Tf4 is connected to the second terminal of the third reference transistor Tf3. The control terminal of the fourth reference transistor Tf4 is connected to the node between the first terminal of the initial reference transistor Tf0 and the second terminal of the second temperature-sensing transistor Tp2.

[0123] The cathode of the Zena diode Dz2 is connected to the first terminal of the first reference transistor Tf1 and the first terminal of the first reference transistor Tf3. The anode of the Zena diode Dz2 is coupled to the reference potential VSS.

[0124] As shown in Figure 9, a node between the first terminal of the fourth reference transistor Tf4 and the second terminal of the third reference transistor Tf3 in the reference voltage supply circuit RFU of the bandgap reference circuit GRE serves as the output terminal of the bandgap reference circuit GRE. This node is connected to the second input terminal, such as the inverting input terminal, of the comparator CMP1 shown in Figure 7, to supply the reference voltage VREF to the second input terminal, such as the inverting input terminal, of the comparator CMP1.

[0125] It is worth noting that the overvoltage protection circuit of the present invention includes a bandgap reference circuit GRE as shown in FIG. 9, which can stably supply a reference voltage VREF with a fixed voltage value to the second input terminal, such as the non-inverting input terminal, of the comparator CMP1 as shown in FIG. 6 or FIG. 7, at any ambient temperature. Thus, the overvoltage protection circuit of the present invention is unaffected by temperature and can stably and appropriately switch the main control transistor Q2, clamping the output voltage VOUT of the second terminal of the main control transistor Q2 at an appropriate voltage to cut off surges, ensuring that the output voltage VOUT does not exceed the operating voltage of the overvoltage protection circuit of the present invention and the load or other downstream circuits connected to its output terminal. Therefore, the overvoltage protection circuit of the present invention can stably provide an appropriate output voltage VOUT to the load, preventing the load or other downstream circuits of the overvoltage protection circuit of the present invention from burning out due to overvoltage.

[0126] Please refer to Figure 10, which is a circuit diagram of the comparator of the overvoltage protection circuit of the eleventh embodiment of the present invention.

[0127] The overvoltage protection circuit of the present invention includes a comparator CMP1 as shown in FIG10. The comparator CMP1 shown in FIG7 can be replaced with the comparator CMP1 shown in FIG10.

[0128] As shown in Figure 10, comparator CMP1 includes an initial comparator transistor Tc0, a first comparator transistor Tc1, a second comparator transistor Tc2, a third comparator transistor Tc3, and a fourth comparator transistor Tc4. If necessary, comparator CMP1 may also include a Zener diode Dz3.

[0129] The first terminal of the initial comparator transistor Tc0 is coupled to the input voltage VIN. As shown in Figure 10, the control terminal of the initial comparator transistor Tc0 inside the comparator CMP1 is connected to the bias circuit BAS as shown in Figure 7 to receive the first upper bias voltage VH1 from the bias circuit BAS, or connected to the first upper bias node of the bias circuit BAS as shown in Figure 8 to receive the first upper bias voltage VH1 from this first upper bias node.

[0130] The first terminal of the first comparator transistor Tc1 is connected to the second terminal of the initial comparator transistor Tc0. As shown in Figure 10, the control terminal of the first comparator transistor Tc1 inside the comparator CMP1 serves as the second input terminal of the comparator CMP1, for example, a non-inverting input terminal, and is connected to the bandgap reference circuit GRE shown in Figure 7 to receive a reference voltage VREF from the bandgap reference circuit GRE.

[0131] As shown in Figure 10, the first terminal of the second comparator transistor Tc2 inside the comparator CMP1 is connected to the second terminal of the initial comparator transistor Tc0. The control terminal of the second comparator transistor Tc2 serves as the first input terminal of the comparator CMP1, such as the inverting input terminal, and is connected to the output terminal of the voltage divider circuit DIV shown in Figure 6 or Figure 7 (i.e., a feedback node between the second terminal of the first voltage divider resistor Rd1 and the first terminal of the second voltage divider resistor Rd2) to receive a feedback voltage VFB from the output terminal of the voltage divider circuit DIV.

[0132] The first terminal and the control terminal of the third comparator transistor Tc3 are connected to the second terminal of the first comparator transistor Tc1. The second terminal of the third comparator transistor Tc3 is coupled to the reference potential VSS.

[0133] The first terminal of the fourth comparator transistor Tc4 is connected to the second terminal of the second comparator transistor Tc2. The control terminal of the fourth comparator transistor Tc4 is connected to the control terminal of the third comparator transistor Tc3. The second terminal of the fourth comparator transistor Tc4 is coupled to the reference potential VSS.

[0134] The cathode of the Zinodia diode Dz3 is connected to the second terminal of the initial comparator transistor Tc0. The anode of the Zinodia diode Dz3 is coupled to the reference potential VSS.

[0135] As shown in Figure 10, the node between the first end of the fourth comparator transistor Tc4 and the second end of the second comparator transistor Tc2 inside the comparator CMP1 serves as an output terminal of the comparator CMP1 and is connected to the control terminal of each of the multiple array transistors Ta shown in Figure 7.

[0136] It is worth noting that, since the overvoltage protection circuit of the present invention includes the first resistance circuits RES10, RES11, RES12 or RES13 and the second resistance circuits RES20, RES21, RES22, RES23 or RES24, and is configured with the main control transistor Q1 or Q2, it can clamp the output voltage VOUT within the operating voltage range of the overvoltage protection circuit of the present invention and its connected subsequent circuits when a momentary high voltage occurs.

[0137] Therefore, compared to traditional overvoltage protection circuits, the overvoltage protection circuit of this invention does not require a high-bandwidth, fast-response comparator CMP1, and can be made of low-cost materials. The comparator CMP1 does not require a large number of internal circuit components. In other words, the overvoltage protection circuit of this invention can achieve the effect of preventing the overvoltage protection circuit and its connected downstream circuits from burning out due to overvoltage while reducing the cost and space occupied by the comparator CMP1.

[0138] Please refer to Figures 11 and 12, which are waveform diagrams of the overvoltage protection circuits of the first to tenth embodiments of the present invention.

[0139] When the input voltage VIN of the overvoltage protection circuit of this invention experiences a sudden high voltage (e.g., reaching a maximum of 40.5V as shown in Figures 11 and 12), causing a surge in the voltage VG at the control terminal of the main control transistor Q1 or Q2 (e.g., reaching a maximum of 36V as shown in Figures 11 and 12), the output voltage VOUT (i.e., the source voltage of the main control transistor Q1) of the overvoltage protection circuit of this invention can be quickly clamped (e.g., clamped at 28V as shown in Figures 11 and 12). This prevents the overvoltage protection circuit of this invention and its connected downstream circuits from burning out due to voltage exceeding the rated voltage of their components.

[0140] In summary, this invention provides an overvoltage protection circuit. When various application scenarios, such as load dumping of the vehicle device, coupling at the input power supply harness, power grid surges, or lightning strikes, cause surges / instantaneous high voltage in the output voltage, this invention's overvoltage protection circuit can immediately clamp the output voltage to prevent it from exceeding the rated voltage of the circuit components and burning them out. Compared to traditional overvoltage protection circuits, this invention's overvoltage protection circuit does not use large inductors, surge protection devices (SPDs), or transient voltage suppressors (TVS), thus significantly reducing heat generation and space occupation.

[0141] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0142] VIN: Input voltage VOUT: Output voltage Q1, Q2: Main control transistors Cgs: Parasitic capacitance VG, Vs: Voltage VSS: Reference potential RES10, RES11, RES12, RES13: First resistance circuit RES20, RES21, RES22, RES23, RES24: Second resistance circuit R11, R21, R12, R22, Rs: Resistors Cout: Output capacitor RL: Load Tr1: First transistor Tr2: Control-side transistor VH1: First upper bias voltage VL1: First lower bias voltage RET: Resistance element ARY: Transistor circuit Ta: Arrayed transistor Te: Bypass switch VE: Variable command voltage DIV: Voltage divider circuit Rd1: First voltage divider resistor Rd2: Second voltage divider resistor VFB: Feedback Voltage CMP1: Comparator VREF: Reference Voltage CMS: Comparison Signal CT: Variable Switching Voltage GRE: Bandgap Reference Circuit BAS: Bias circuit VH0: Initial upper bias voltage VL0: Initial upper bias BA1: Bias-driven startup circuit Ts1: First start-up transistor Ts2: Second start-up transistor BA2: Bias supply circuit Tb1: First bias transistor Tb2: Second bias transistor Tb3: Third bias transistor Tb4: Fourth bias transistor Tb5: Fifth bias transistor Tb6: Sixth bias transistor Tb7: Seventh bias transistor Tb8: Eighth bias transistor LM: Current limiting circuit Tm1: First current-limiting transistor Tm2: Second current-limiting transistor DRP: Voltage Drop Receiver Circuit Td1: First piezoelectric transistor Td2: Second piezoelectric transistor Td3: Third piezoelectric transistor RFU: Reference Voltage Supply Circuit RF1: Temperature sensing circuit Tp1: First thermoelectric transistor Tp2: Second thermoelectric transistor RF2: Reference voltage supply circuit Tf0: Initial reference transistor Tf1: First reference transistor Tf2: Second reference transistor Tf3: Third reference transistor Tf4: Fourth Reference Transistor Dz1, Dz2, Dz3: Kinna Diode Tc0: Initial Comparison Transistor Tc1: First Comparison Transistor Tc2: Second Comparison Transistor Tc3: Third Comparison Transistor Tc4: Fourth Comparison Transistor

Claims

1. An overvoltage protection circuit, comprising: a master control transistor, a first terminal of which is coupled to an input voltage, and a second terminal of which serves as an output terminal of the overvoltage protection circuit; and a first resistance circuit having a first resistance value, the first terminal of which is connected to the first terminal of the master control transistor. The system also includes a second resistance circuit having a second resistance value, a first terminal of which is connected to a second terminal of the first resistance circuit, and a second terminal of which is coupled to a reference potential; wherein a control node between the first terminal of the second resistance circuit and the second terminal of the first resistance circuit is connected to the control terminal of the main control transistor; wherein the second resistance circuit includes: a resistance element, the first terminal of which is connected to the control terminal of the main control transistor; and a transistor circuit including at least one array transistor, the first terminal of which is connected to the second terminal of the resistance element, the second terminal of which is connected to and coupled to the reference potential, and the control terminal of which is coupled to a switching control voltage. And a bypass switch, the first end of which is connected to the second end of the resistive element, the second end of which is coupled to the reference potential, and the control end of which is coupled to a variable command voltage.

2. The overvoltage protection circuit as claimed in claim 1, wherein the first resistance circuit includes a resistor.

3. The overvoltage protection circuit as claimed in claim 1, wherein the second resistance circuit includes a resistor.

4. The overvoltage protection circuit as claimed in claim 1, wherein the first resistance circuit includes a first transistor, a first terminal of the first transistor being coupled to the input voltage, a second terminal of the first transistor being connected to the control terminal of the master control transistor, and the control terminal of the first transistor being coupled to a first upper bias voltage.

5. The overvoltage protection circuit as claimed in claim 1, wherein the second resistance circuit includes a control-side transistor, a first terminal of the control-side transistor being connected to the control terminal of the master control transistor, a second terminal of the control-side transistor being coupled to the reference potential, and the control terminal of the control-side transistor being coupled to a first lower bias voltage.

6. The overvoltage protection circuit as claimed in claim 5, wherein the resistive element comprises: a control-side transistor, a first terminal of which is connected to the control terminal of the master control transistor, and the control terminal of which is coupled to a first lower bias voltage.

7. The overvoltage protection circuit as claimed in claim 1 further comprises: a comparator, a first input terminal of the comparator being connected to a second terminal of the master control transistor, a second input terminal of the comparator being coupled to a reference voltage, and an output terminal of the comparator being connected to a control terminal of at least one of the array transistors.

8. The overvoltage protection circuit as claimed in claim 7 further comprises: a voltage divider circuit including a first voltage divider resistor and a second voltage divider resistor, a first terminal of the first voltage divider resistor being connected to a second terminal of the master control transistor, a second terminal of the first voltage divider resistor being connected to a first terminal of the second voltage divider resistor, a second terminal of the second voltage divider resistor being coupled to the reference potential, and a feedback node between the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor being connected to the first input terminal of the comparator.

9. The overvoltage protection circuit as claimed in claim 7, wherein the comparator comprises: an initial comparator transistor, a first terminal of which is coupled to the input voltage, and a control terminal of which is coupled to a first upper bias voltage; a first comparator transistor, a first terminal of which is connected to a second terminal of which is connected to the initial comparator transistor, and a control terminal of which serves as a second input terminal of the comparator; and a second comparator transistor, a first terminal of which is connected to the second terminal of which is connected to the initial comparator transistor, and a control terminal of which serves as a first input terminal of the comparator. A third comparator transistor, wherein a first terminal and a control terminal of the third comparator transistor are connected to a second terminal of the first comparator transistor, and the second terminal of the third comparator transistor is coupled to the reference potential; And a fourth comparator transistor, wherein a first end of the fourth comparator transistor is connected to a second end of the second comparator transistor, a control end of the fourth comparator transistor is connected to a control end of the third comparator transistor, and a second end of the fourth comparator transistor is coupled to the reference potential; wherein the node between the first end of the fourth comparator transistor and the second end of the second comparator transistor serves as the output terminal of the comparator.

10. The overvoltage protection circuit as claimed in claim 9, wherein the comparator further comprises: a Zener diode, the cathode of which is connected to a second terminal of the initial comparator transistor, and the anode of which is coupled to the reference potential.

11. The overvoltage protection circuit as claimed in claim 7 further comprises: a bandgap reference circuit connected to the second input of the comparator and configured to supply the reference voltage to the second input of the comparator.

12. The overvoltage protection circuit of claim 11, wherein the bandgap reference circuit includes a reference voltage supply circuit, the reference voltage supply circuit comprising: a first thermoelectric transistor, a first terminal of the first thermoelectric transistor being coupled to the input voltage and connected to a control terminal of the first thermoelectric transistor, and a second terminal of the first thermoelectric transistor being coupled to the reference potential; a second thermoelectric transistor, a first terminal of the second thermoelectric transistor being coupled to the input voltage, and a control terminal of the second thermoelectric transistor being connected to the first terminal of the first thermoelectric transistor; an initial reference transistor, a first terminal of the initial reference transistor being connected to the second terminal of the second thermoelectric transistor, the second terminal of the initial reference transistor being coupled to the reference potential, and a control terminal of the initial reference transistor being coupled to an initial lower bias voltage; a first reference transistor, a first terminal of the first reference transistor being coupled to the input voltage; and a second reference transistor, a first terminal of the second reference transistor being connected to the second terminal of the first reference transistor and a control terminal, the second terminal of the second reference transistor being coupled to the reference potential, and a control terminal of the second reference transistor being connected to the control terminal of the second thermoelectric transistor. A third reference transistor, the first terminal of which is coupled to the input voltage, and the control terminal of which is connected to the control terminal of the first reference transistor; and a fourth reference transistor, the first terminal of which is connected to the second terminal of the third reference transistor, the second terminal of which is coupled to the reference potential, and the control terminal of which is connected to the first terminal of the initial reference transistor.

13. The overvoltage protection circuit as claimed in claim 12, wherein the reference voltage supply circuit further comprises: a Zener diode, the cathode of which is connected to a first end of the second thermosensitive transistor, and the anode of which is coupled to the reference potential.

14. The overvoltage protection circuit of claim 12, wherein the reference voltage supply circuit further comprises: a Zener diode, the cathode of which is connected to a first terminal of the first reference transistor and a first terminal of the third reference transistor, and the anode of which is coupled to the reference potential.

15. The overvoltage protection circuit of claim 12, wherein the bandgap reference circuit further comprises: a current limiting circuit, a first terminal of the current limiting circuit being coupled to the input voltage, and a second terminal of the current limiting circuit being connected to the reference voltage supply circuit via a voltage drop receiving circuit, the current limiting circuit being configured to limit the amount of an input current flowing from the input voltage through the voltage drop receiving circuit to the reference voltage supply circuit, wherein the voltage drop receiving circuit is configured to receive a portion of a voltage drop between the input terminal of the overvoltage protection circuit and the reference potential.

16. The overvoltage protection circuit of claim 15, wherein the current limiting circuit includes a first current limiting transistor and a second current limiting transistor, and the voltage drop receiving circuit includes a first piezoelectric transistor, a second piezoelectric transistor, and a third piezoelectric transistor; wherein a first terminal of the first current limiting transistor and a first terminal of the second current limiting transistor are coupled to the input voltage, and a control terminal of the first current limiting transistor and a control terminal of the second current limiting transistor are coupled to an initial upper bias voltage; wherein a first terminal of the first piezoelectric transistor is connected to a second terminal of the first current limiting transistor, a first terminal of the second piezoelectric transistor is connected to a second terminal of the second current limiting transistor, and a first terminal of the third piezoelectric transistor is coupled to the input voltage; wherein a second terminal of the first piezoelectric transistor is connected to a first terminal of the first temperature-sensing transistor, a second terminal of the second piezoelectric transistor is connected to a first terminal of the second temperature-sensing transistor, and a second terminal of the third piezoelectric transistor is connected to a first terminal of the first reference transistor and a first terminal of the third reference transistor; wherein the control terminals of the first piezoelectric transistor, the second piezoelectric transistor, and the third piezoelectric transistor are coupled to a first upper bias voltage.

17. The overvoltage protection circuit of claim 11 further comprises: a bias circuit, the bias circuit comprising: a first startup transistor, a first terminal of the first startup transistor and a control terminal coupled to the input voltage; a second startup transistor, a first terminal of the second startup transistor connected to the first terminal of the first startup transistor and the control terminal, and a second terminal of the second startup transistor coupled to the reference potential; a first bias transistor, a first terminal of the first bias transistor coupled to the input voltage; a second bias transistor, a first terminal of the second bias transistor coupled to the input voltage; a third bias transistor, a first terminal of the third bias transistor, a second terminal of the first bias transistor, a control terminal, and a control terminal of the second bias transistor connected to an initial upper bias node, the initial upper bias node having the initial upper bias; and a fourth bias transistor, a first terminal of the fourth bias transistor connected to the second terminal of the second bias transistor. A fifth bias transistor, wherein the first terminal of the fifth bias transistor, the second terminal and control terminal of the third bias transistor, and the control terminal of the fourth bias transistor are connected to a first upper bias node, the first upper bias node having the first upper bias voltage; a sixth bias transistor, wherein the first terminal and control terminal of the sixth bias transistor, the control terminal of the fifth bias transistor, and the second terminal of the first startup transistor are connected to a first lower bias node, the first lower bias node having the first lower bias voltage; a seventh bias transistor, wherein the first terminal of the seventh bias transistor is connected to the second terminal of the fifth bias transistor, the second terminal of the seventh bias transistor being coupled to the reference potential; and an eighth bias transistor, wherein the first terminal and control terminal of the eighth bias transistor, the second terminal of the sixth bias transistor, the control terminal of the seventh bias transistor, and the control terminal of the second startup transistor are connected to an initial lower bias node, the initial lower bias node having the initial lower bias voltage, the second terminal of the eighth bias transistor being coupled to the reference potential; The bandgap reference circuit outputs the reference voltage based on the initial upper bias, the first upper bias, the first lower bias, and the initial lower bias received from the connected initial upper bias node, the first upper bias node, the first lower bias node, and the initial lower bias node, respectively.

18. The overvoltage protection circuit as claimed in claim 17 further comprises: a resistor connected between a first terminal of the first start-up transistor and the input voltage.

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