Method for fabricating semiconductor device

Abstract

This disclosure provides a cell contact structure, a semiconductor device, and a method for fabricating the same. The cell contact structure includes: a bottom contact layer located on a substrate and surrounded by a plurality of bit line structures and a plurality of separator layers; a liner layer located between the bottom contact layer and the substrate, between the bottom contact layer and the bit line structures, and between the bottom contact layer and the separator layers; and a top contact layer located between the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer includes tungsten, titanium, or titanium nitride.

Description

Technical Field

[0001] This application is a division of U.S. Application No. 113114117, filed April 16, 2024, which claims priority and benefits from U.S. Official Application No. 18 / 433,904, filed February 6, 2024, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a unit contact structure, a semiconductor device, and a method for fabricating the same. In particular, it relates to a unit contact structure including a liner, a semiconductor device having the unit contact structure, and a method for fabricating the same. Prior Technology

[0003] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above description of "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a unit contact structure, comprising: a bottom contact layer located on a substrate and surrounded by a plurality of bit line structures and a plurality of separator layers; a liner layer located between the bottom contact layer and the substrate, between the bottom contact layer and the bit line structures, and between the bottom contact layer and the separator layers; and a top contact layer located between the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0006] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two separator layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other along the first direction, and simultaneously contacting the two bit line structures; and a unit contact structure. The unit contact structure includes: a bottom contact layer located on the substrate and surrounded by the two bit line structures and the two separator layers; a liner layer located between the substrate and the bottom contact layer, between the two bit line structures and the bottom contact layer, and between the two separator layers and the bottom contact layer; and a top contact layer located on the liner layer and the bottom contact layer. A top surface of the liner layer and a top surface of the bottom contact layer are substantially coplanar. The liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0007] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on the sides of the two bit line structures; forming two separator layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening that engages with the spacer structures; conformally forming a liner in and within the contact opening; forming a bottom contact layer on the liner and within the contact opening; and forming a top contact layer on the liner, on the bottom contact layer, and within the contact opening. The liner comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride. The liner, the bottom contact layer, and the top contact layer together constitute a unit contact structure.

[0008] Because of the semiconductor device design disclosed herein, junction leakage of the cell contact structure can be reduced by employing a substrate including doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. Furthermore, sheet resistance of the cell contact structure can be reduced by employing a bottom contact layer and a top contact layer including titanium nitride, tungsten, or titanium. As a result, the performance of the semiconductor device can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages that form the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] When considered in conjunction with the drawings, a more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims, wherein similar reference numerals represent similar elements in the overall drawings, and: Figure 1 shows a method for fabricating a semiconductor device in the form of a flowchart according to an embodiment of the present disclosure. Figure 2 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 2. Figure 4 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 4. Figure 6 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 6. Figure 8 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 8. Figure 10 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 10. Figure 12 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 13 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 12. Figure 14 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 15 and 16 are schematic cross-sectional views drawn along lines A-A' and B-B' in Figure 14, showing a portion of the process for fabricating semiconductor devices according to some embodiments. Figure 17 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 18 is a schematic cross-sectional view drawn along lines A-A' and B-B' in Figure 17. Figure 19 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 20 to 23 are schematic cross-sectional views drawn along lines A-A' and B-B' in Figure 19, showing a portion of the process for fabricating semiconductor devices according to some embodiments. Figure 24 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 25 and 26 are schematic cross-sectional views drawn along lines A-A' and B-B' in Figure 24, showing a portion of the process for fabricating semiconductor devices according to some embodiments. Figure 27 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 28 and 29 are schematic cross-sectional views drawn along lines A-A' and B-B' in Figure 27, showing a portion of the process for fabricating semiconductor devices according to some embodiments. Figures 30 to 32 show schematic cross-sectional views of semiconductor devices according to some embodiments of the present disclosure. Implementation

[0011] The following disclosure provides many different embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to define relationships between the different embodiments and / or structures discussed.

[0012] Furthermore, spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms are used to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of the element in use or operation, beyond the orientation depicted in the diagram. Element may be rotated to different orientations (90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted in the same way.

[0013] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0014] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0015] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical, for example, due to manufacturing processes, within acceptable variations. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar, for example, due to manufacturing processes, within acceptable variations.

[0016] In this disclosure, semiconductor devices generally refer to devices that can perform functions by utilizing the properties of semiconductors, and electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices.

[0017] It should be noted that in the description disclosed herein, "above" or "up" corresponds to the direction of the arrow in the Z direction, and "below" or "down" corresponds to the direction of the arrow opposite to the Z direction.

[0018] Figure 1 shows a flowchart of a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 2. Figure 4 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 4.

[0019] Referring to Figures 1 to 5, in step S11, a substrate 101 can be provided, an isolation layer 103 can be formed in the substrate 101 to define a plurality of active regions AA, and a plurality of character line structures 200 located in the substrate 101 and intersecting with the active regions AA can be formed.

[0020] Referring to Figures 2 and 3, substrate 101 may include a bulk semiconductor substrate. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0021] In some embodiments, the semiconductor substrate 101 may include a semiconductor-on-insulator (SBI) substrate comprising, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may comprise the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between approximately 10 nm and approximately 200 nm. The insulating layer can eliminate leakage current between adjacent elements in the substrate 101 and reduce source / drain-related parasitic capacitances.

[0022] It should be noted that in the description of this disclosure, the term "approximately" used to modify the amount of ingredients, components, or reactants used in this disclosure refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the preparation of the composition or the implementation of the method. On one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. Also, on another hand, the term "approximately" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0023] Referring to Figures 2 and 3, an isolation layer 103 can be formed in the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. Photolithography processes and subsequent etching processes, such as anisotropic etching, can be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer, and extend into the substrate 101. An insulating material can be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, can then be performed until the top surface of the substrate 101 is exposed to remove excess filler material, providing a substantially flat surface for subsequent processing steps, and simultaneously forming the isolation layer 103. The insulating material can be, for example, silicon oxide or other applicable insulating materials. The isolation layer 103 can define active regions AA in the substrate 101.

[0024] It should be noted that, in the description of this disclosure, the surface of an element (or component) located at the highest vertical level along the Z-axis is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along the Z-axis is referred to as the bottom surface of the element (or component).

[0025] It should be noted that each of the active regions AA may include a portion of the substrate 101 and the space above that portion of the substrate 101. Describing an element as disposed on the active region AA means that the element is disposed on the top surface of that portion of the substrate 101. Describing an element as disposed within the active region AA means that the element is disposed within that portion of the substrate 101. However, the top surface of the element may be flush with the top surface of that portion of the substrate 101. Describing an element as disposed above the active region AA means that the element is disposed above the top surface of that portion of the substrate 101.

[0026] Referring to Figures 2 and 3, a plurality of impurity regions 105 can be formed correspondingly within the active regions AA. In some embodiments, the fabrication technique of the impurity regions 105 may include an implantation process. That is, the impurity regions 105 may be derived from a portion of the active regions AA. The dopant in the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). P-type dopants may be added to intrinsic semiconductor materials to generate valence electron defects. In silicon-containing substrates, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, or indium. N-type dopants may be added to intrinsic semiconductor materials to contribute free electrons to the intrinsic semiconductor material. In silicon-containing substrates, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, or phosphorus. In some embodiments, the dopant concentration of the impurity regions 105 may be between approximately 1E19 atoms / cm^3 and approximately 1E21 atoms / cm^3. After the implantation process, these impurity regions 105 can have an electrical type such as n-type or p-type.

[0027] Referring to Figures 4 and 5, a plurality of character line trenches TR can be formed in the substrate 101 to define the positions of the character line structures 200. The fabrication techniques for these character line trenches TR may include photolithography and subsequent etching processes. In some embodiments, in a top perspective view, the character line trenches TR may have a linear cross-sectional profile and extend along the X direction, passing through (or intersecting with) the impurity regions 105. For example, each impurity region 105 may intersect with two character line trenches TR. The character line trenches TR can divide each of the impurity regions 105 into a plurality of common source regions 105-1 and a plurality of drain regions 105-3. For one impurity region 105, a common source region 105-1 can be formed between two character line trenches TR, and two drain regions 105-3 can be correspondingly formed between the isolation layer 103 and the two character line trenches TR.

[0028] Referring to Figures 4 and 5, the character line structures 200 (e.g., two character line structures 200) can be formed correspondingly in the character line trenches TR (e.g., two character line trenches TR). For the sake of brevity, clarity, and convenience, only one character line structure 200 is described. The character line structure 200 may include a character line dielectric layer 201, a character line barrier layer 203, a character line conductive layer 205, and a character line capping layer 207.

[0029] Referring to Figures 4 and 5, a character line dielectric layer 201 can be conformally formed on the inner surface of the character line trench TR. The character line dielectric layer 201 can have a U-shaped cross-sectional profile. In other words, the character line dielectric layer 201 can be formed inward in the active region AA. In some embodiments, the fabrication technique of the character line dielectric layer 201 can include a thermal oxidation process. For example, the character line dielectric layer 201 can be formed by oxidizing the inner surface of the character line trench TR. In some embodiments, the fabrication technique of the character line dielectric layer 201 can include deposition processes such as chemical vapor deposition or atomic layer deposition. The character line dielectric layer 201 can include a high-k material, oxide, nitride, oxynitride, or a combination thereof. In some embodiments, after depositing a pad polysilicon layer (not shown for clarity), the character line dielectric layer 201 can be formed by radical oxidation of the pad polysilicon layer. In some embodiments, after forming a pad silicon nitride layer (not shown for clarity), the word line dielectric layer 201 can be formed by free radical oxidation of the pad silicon nitride layer.

[0030] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0031] Referring to Figures 4 and 5, a character line barrier layer 203 can be conformally formed on the character line dielectric layer 201 and within the character line trench TR. In some embodiments, the character line barrier layer 203 may include, for example, titanium nitride, titanium, or a combination thereof. In some embodiments, the character line barrier layer 203 may include, for example, titanium nitride. In some embodiments, the fabrication techniques for the character line barrier layer 203 may include, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition, or other applicable deposition processes.

[0032] Referring to Figures 4 and 5, a character line conductive layer 205 can be formed on the character line barrier layer 203 and within the character line trench TR. In some embodiments, to form the character line conductive layer 205, a conductive layer (not shown for clarity) can be formed to fill the character line trench TR, and a recess process can then be performed. The recess process can be performed as an etch-back process or as a planarization process and an etch-back process sequentially. The character line conductive layer 205 can have a recessed shape that partially fills the character line trench TR. That is, the top surface of the character line conductive layer 205 can be lower than the top surface of the substrate 101.

[0033] In some embodiments, the character line conductive layer 205 may include a metal, a metal nitride, or a combination thereof. For example, the character line conductive layer 205 may include titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, titanium nitride / tungsten may have a structure in which tungsten partially fills the character line trench TR. Titanium nitride or tungsten may be used alone in the character line conductive layer 205. In some embodiments, the character line conductive layer 205 may include, for example, a conductive material, such as doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the character line conductive layer 205 may include, for example, tungsten, aluminum, titanium, copper, similar materials, or a combination thereof.

[0034] Referring to Figures 4 and 5, a dielectric material (not shown) can be deposited, for example, by chemical vapor deposition, to completely fill the word line trench TR and cover the top surface of the substrate 101. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent processing steps and form the word line capping layer 207. In some embodiments, the word line capping layer 207 may include silicon nitride, or other applicable dielectric materials.

[0035] Figure 6 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 6. Figure 8 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 9 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 8. Figure 10 shows a top view of an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 10. It should be noted that some elements are omitted in the top view for clarity.

[0036] Referring to Figures 1 and 6 to 11, in step S13, a plurality of bit line structures 300 can be formed on the substrate 101, and a plurality of spacer structures 400 can be formed on the side surfaces 300S of these bit line structures.

[0037] Referring to Figures 6 and 7, a bottom dielectric layer 107 can be formed on the substrate 101. In some embodiments, the bottom dielectric layer 107 may include a material that is etch-selective to the substrate 101 and the isolation layer 103. In some embodiments, the bottom dielectric layer 107 may include, for example, silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon boron carbon nitride, or a combination thereof. In some embodiments, the bottom dielectric layer 107 may include, for example, silicon nitride. In some embodiments, the fabrication techniques for the bottom dielectric layer 107 may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes.

[0038] Referring to Figures 6 and 7, a plurality of bit line contacts 309 can be formed, each correspondingly passing through the bottom dielectric layer 107 and extending to the common source regions 105-1. In some embodiments, the bit line contacts 309 may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the bit line contacts 309 may have a square cross-sectional profile in a top perspective view, but are not limited to this shape. In some embodiments, the bit line contacts 309 may have a rectangular, circular, or other applicable shape cross-sectional profile in a top perspective view.

[0039] Referring to Figures 8 and 9, the bit line structures 300 can be formed on the bottom dielectric layer 107 and electrically connected to the bit line contacts 309 respectively. In the top perspective view, the bit line structures 300 can extend along the Y direction and be separated from each other. In other words, in the top perspective view, the bit line structures 300 can intersect with the word line structures 200. For the sake of brevity, clarity and convenience, only one bit line structure 300 is described. In some embodiments, the bit line structure 300 may include a top conductive layer 301 and a bit line capping layer 307.

[0040] A top conductive layer 301 for the bit line can be formed on and electrically connected to the bit line contact 309. In some embodiments, the top conductive layer 301 may include, for example, titanium nitride, tungsten, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations thereof. A bit line capping layer 307 may be formed on the top conductive layer 301. In some embodiments, the bit line capping layer 307 may include, for example, silicon nitride or other applicable insulating materials.

[0041] Referring to Figures 10 and 11, the spacer structures 400 can be formed on the side surfaces 300S of the bitline structures 300. In other words, in the top perspective view, the spacer structures 400 can extend along the direction Y. For the sake of brevity, clarity, and convenience, only one spacer structure 400 is described. In some embodiments, the spacer structure 400 may include an in-bitline spacer 401, a mid-bitline spacer 403, and an out-of-bitline spacer 405.

[0042] In-bit spacers 401 may be formed on the side surface 300S of the bitline structure 300. In some embodiments, the in-bit spacers 401 may comprise the same material as the bitline capping layer 307. In some embodiments, the in-bit spacers 401 may comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the in-bit spacers 401 may be formed by conformally depositing an insulating material (not shown) over the bottom dielectric layer 107 and a subsequent anisotropic etching process.

[0043] Bit line spacers 403 may be conformally formed on bit line spacers 401. In some embodiments, bit line spacers 403 may include, for example, silicon oxide or other applicable insulating oxides. In some embodiments, bit line spacers 403 may be formed by conformally depositing an insulating oxide layer (not shown) on the bottom dielectric layer 107 and a subsequent anisotropic etching process.

[0044] The external spacer 405 may be conformally formed on the intermediate spacer 403 of the bit line. In some embodiments, the external spacer 405 may comprise the same material as the internal spacer 401 of the bit line or the bit line overlay 307. In some embodiments, the external spacer 405 may comprise, for example, silicon nitride or other applicable insulating materials. In some embodiments, the external spacer 405 may be formed by conformally depositing an insulating material (not shown) on the bottom dielectric layer 107 and a subsequent anisotropic etching process.

[0045] In some embodiments, the spacer 401 within the bit line may be optional. That is, the spacer 403 between the bit lines may be formed directly on the side surface 300S of the bit line structure 300.

[0046] Figure 12 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 13 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 12. Figure 14 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 15 and 16 are cross-sectional views drawn along lines A-A' and B-B' in Figure 14, showing a portion of the fabrication process of semiconductor device 1A according to some embodiments. Figure 17 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figure 18 is a cross-sectional view drawn along lines A-A' and B-B' in Figure 17.

[0047] Referring to Figures 1 and 12 to 18, in step S15, a sacrificial layer 801 can be formed to cover the bit line structures 300 and the spacer structures 400. A first mask layer 701 including a linear pattern P1 can be formed on the sacrificial layer 801 to partially expose the sacrificial layer 801, the bit line structures 300, and the spacer structures 400. The sacrificial layer 801 can be selectively removed to form a plurality of partition openings OP1, and a plurality of partition layers 601 can be formed in the partition openings OP1.

[0048] Referring to Figures 12 and 13, a sacrificial layer 801 can be formed over the bottom dielectric layer 107 to cover the bit line structures 300 and the spacer structures 400. In some embodiments, the sacrificial layer 801 may include a material, for example, having etch selectivity for the bit line spacers 405 or the bit line overlay layer 307. In some embodiments, the sacrificial layer 801 may include, for example, silicon oxynitride, silicon oxynitride, or other applicable materials. In some embodiments, the fabrication techniques for the sacrificial layer 801 may include, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other applicable deposition processes. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed until the top surface 307TS of the bit line structures 300 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0049] It should be noted that, in the description of this disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0050] Referring to Figures 12 and 13, a first masking layer 701 can be formed on the sacrificial layer 801. In some embodiments, the first masking layer 701 may be a photoresist layer. In a top perspective view, the linear pattern P1 of the first masking layer 701 may include a plurality of rectangular spaces extending along the X direction and alternately arranged along the Y direction. Through these spaces, the sacrificial layer 801, the bit line structures 300, and the spacer structures 400 can be partially exposed.

[0051] Referring to Figures 14 and 15, the sacrificial layer 801 exposed by the linear pattern P1 of the first masking layer 701 can be selectively removed. In some embodiments, the sacrificial layer 801 can be removed using an anisotropic etching process, such as anisotropic dry etching. After removing the sacrificial layer 801, the separating openings OP1 can be formed in the locations where the sacrificial layer 801 was exposed by the linear pattern P1 of the first masking layer 701. The first masking layer 701 can then be removed after forming these separating openings OP1.

[0052] Referring to FIG16, a layer of separator material 803 can be formed on the sacrificial layer 801 to completely fill the separator openings OP1. In some embodiments, the separator material 803 may be a material that is etch-selective on the sacrificial layer 801. In some embodiments, the separator material 803 may be the same material as the bit line overlay layer 307 or the bit line spacer 405. In some embodiments, the separator material 803 may be, for example, silicon nitride or other applicable insulating materials. In some embodiments, the fabrication technique of the separator material 803 may include, for example, chemical vapor deposition or other applicable deposition processes.

[0053] Referring to Figures 17 and 18, a planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps, transforming the layer of separating material 803 into a plurality of separating layers 601. In a top perspective view, each of these separating layers 601 may have a linear (or rectangular) cross-sectional profile extending along the X direction. These separating layers 601 may be alternately arranged along the X direction, with each corresponding bit line structure 300 located between two adjacent separating layers 601. Along the Y direction, these separating layers 601 may be alternately arranged, with a sacrificial layer 801 inserted therebetween. In a top perspective view, the arrangement of these separating layers 601 and the bit line structures 300 can divide the sacrificial layer 801 into multiple segments.

[0054] For the sake of brevity, clarity, and convenience, only one separator layer 601 is described. In some embodiments, after a planarization process, the intra-bit spacer 401, the intermediate bit-line spacer 403, and the outer bit-line spacer 405 may be exposed. The top surface 601TS of the separator layer 601, the top surface 401TS of the intra-bit spacer 401, the top surface 403TS of the intermediate bit-line spacer 403, the top surface 405TS of the outer bit-line spacer 405, and the top surface 307TS of the bit-line overlay layer 307 may be substantially coplanar.

[0055] In some embodiments, after the planarization process, the outer spacer 405 (not shown) may cover the inner spacer 401 and the intermediate spacer 403. In this case, the top surface 405TS of the outer spacer 405 and the top surface 307TS of the bit line cover layer 307 may be substantially coplanar.

[0056] Figure 19 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 20 to 23 are cross-sectional views drawn along lines A-A' and B-B' in Figure 19, showing partial processes of fabricating semiconductor device 1A according to some embodiments. Figure 24 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 25 and 26 are cross-sectional views drawn along lines A-A' and B-B' in Figure 24, showing partial processes of fabricating semiconductor device 1A according to some embodiments. Figure 27 shows a top view of an intermediate semiconductor device according to an embodiment of the present disclosure. Figures 28 and 29 are cross-sectional views drawn along lines A-A' and B-B' in Figure 27, showing partial processes of fabricating semiconductor device 1A according to some embodiments.

[0057] Referring to Figures 1 and 19 to 29, in step S17, the sacrificial layer 801 can be selectively removed to form a plurality of contact openings OP2, a plurality of unit contact structures 500 can be formed in the contact openings OP2, and a top insulating layer 109 can be formed to cover the bit line structures 300, the spacer structures 400, and the unit contact structures 500.

[0058] Referring to Figures 19 and 20, the sacrificial layer 801 can be selectively removed via an etching process. For example, the removal of the sacrificial layer 801 can be achieved via an anisotropic etching process. After the sacrificial layer 801 is removed, contact openings OP2 can be formed in the locations previously occupied by the sacrificial layer 801 (in the form of multiple fragments). For the sake of brevity, clarity, and convenience, only one contact opening OP2 is described. In the cross-sectional perspective view, the contact opening OP2 can be disposed on the bottom dielectric layer 107. In the top perspective view, the contact opening OP2 can be surrounded by two adjacent spacer layers 601 along the Y direction and can be surrounded by two adjacent bit line structures 300 (or spacer structures 400 disposed on the sides 300S of two adjacent bit line structures 300) along the X direction.

[0059] Referring to FIG21, a punch-through process can be performed to remove a portion of the bottom dielectric layer 107 exposed by the contact openings OP2. In some embodiments, the punch-through process can be an anisotropic dry etching process. During the punch-through process, the contact openings OP2 can be extended downward to the substrate 101. After the punch-through process, the drain regions 105-3 can be exposed through the contact openings OP2.

[0060] Referring to FIG22, a pad material 805 can be conformally formed to cover the substrate 101, the bit line structures 300, the spacer structures 400, and the separator layers 601. In some embodiments, the pad material 805 may include doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. In some embodiments, the pad material 805 may include a p-type dopant or an n-type dopant. In some embodiments, the fabrication technique of the pad material 805 may include atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. By using doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium as the pad material 805 of the unit contact structure 500, junction leakage can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0061] Referring to FIG23, a first conductive material 807 can be formed on the pad material 805 and completely fill the contact openings OP2. In some embodiments, the first conductive material 807 may be a material with good conductivity (or a material with better conductivity than doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium). In some embodiments, the first conductive material 807 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the first conductive material 807 may be, for example, titanium nitride, titanium, tungsten, or combinations thereof. By using a material with good conductivity, the sheet resistance of the unit contact structure 500 can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0062] Referring to Figures 24 and 25, an etch-back process can be performed to remove portions of the pad material 805 and the first conductive material 807. After the etch-back process, the remaining pad material 805 is correspondingly transformed into a plurality of substrate layers 501 within the contact openings OP2. The remaining first conductive material 807 is correspondingly transformed into a plurality of bottom contact layers 503 within the contact openings OP2.

[0063] For the sake of brevity, clarity, and convenience, only one liner 501 and one bottom contact layer 503 are described. In some embodiments, in a cross-sectional perspective view, the top surface 503TS of the bottom contact layer 503 and the top surface 501TS of the liner 501 may be substantially coplanar. The top surface 503TS of the bottom contact layer 503 and the top surface 501TS of the liner 501 may be lower than the top surface 307TS of the bitline overlay layer 307 (i.e., the top surface of the bitline structure 300). In some embodiments, in a top perspective view, the liner 501 may have a square-ring-shaped or rectangular-ring-shaped cross-sectional profile. The bottom contact layer 503 may have a square or rectangular cross-sectional profile.

[0064] Referring to FIG26, a second conductive material 809 can be formed on the substrate 101 to completely fill the contact openings OP2 and cover and contact the spacer layers 601, the bit line structures 300, and the spacer structures 400. In some embodiments, the second conductive material 809 may be a material with good conductivity (or a material with better conductivity than doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium). In some embodiments, the second conductive material 809 may be the same material as the bottom contact layer 503. In some embodiments, the second conductive material 809 may be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. In some embodiments, the second conductive material 809 may be, for example, titanium nitride, titanium, tungsten, or combinations thereof.

[0065] Referring to Figures 27 and 28, an etch-back process can be performed to remove a portion of the second conductive material 809. After the etch-back process, the remaining second conductive material 809 can be transformed into a plurality of top contact layers 505 within the contact openings OP2. For the sake of brevity, clarity, and convenience, only one top contact layer 505 is described. In some embodiments, in a cross-sectional perspective view, the top surface 505TS of the top contact layer 505 may be lower than the top surface 307TS of the bit line overlay layer 307. In some embodiments, the width W1 of the top contact layer 505 may be greater than the width W2 of the bottom contact layer 503. In some embodiments, in a top perspective view, the top contact layer 505 may have a square or rectangular cross-sectional profile. The liner 501, the bottom contact layer 503, and the top contact layer 505 together constitute a unit contact structure 500. The unit contact structure 500 can be electrically connected to the corresponding drain regions 105-3.

[0066] By employing a top contact layer 505 made of a material with good conductivity, the sheet resistance of the cell contact structure 500 can be reduced. As a result, the performance of the semiconductor device 1A can be further improved.

[0067] Referring to FIG29, a top insulating layer 109 may be formed on the substrate 101 to cover the separator layers 601, the cell contact structures 500, the spacer structures 400, and the bit line structures 300. In some embodiments, the top insulating layer 109 may include the same material as the bit line cover layer 307. In some embodiments, the top insulating layer 109 may include, for example, silicon nitride or other applicable insulating materials.

[0068] Using a substrate 501, including doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium, can reduce interface leakage in the cell contact structure 500. Furthermore, using a bottom contact layer 503 and a top contact layer 505, including materials such as titanium nitride, tungsten, or titanium, can effectively reduce the sheet resistance of the cell contact structure 500. These enhancements collectively improve the performance of the semiconductor device 1A.

[0069] Figures 30 to 32 show schematic cross-sectional views of semiconductor elements 1B, 1C, and 1D according to some embodiments of the present disclosure.

[0070] As shown in Figure 30, semiconductor element 1B can have a structure similar to that shown in Figure 29. Elements in Figure 30 that are the same as or similar to those in Figure 29 are represented by the same symbols, and repeated descriptions have been omitted.

[0071] In semiconductor device 1B, bit line structure 300 may include a bottom conductive layer 305, a middle conductive layer 303, a top conductive layer 301, and a capping layer 307.

[0072] The bottom conductive layer 305 of the bit line can be disposed on the bit line contact 309. In some embodiments, the bottom conductive layer 305 of the bit line may include, for example, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the dopant used for the bottom conductive layer 305 of the bit line may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus.

[0073] The intermediate conductive layer 303 of the bit line can be disposed on the bottom conductive layer 305 of the bit line. In some embodiments, the intermediate conductive layer 303 of the bit line may include, for example, titanium silicon, nickel silicon, nickel platinum silicon, tantalum silicon, or cobalt silicon. In some embodiments, the intermediate conductive layer 303 of the bit line may have a thickness between about 2 nm and about 20 nm.

[0074] The top conductive layer 301 of the bit line can be disposed on the middle conductive layer 303 of the bit line. In some embodiments, the top conductive layer 301 of the bit line may include, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other applicable conductive materials, or combinations thereof.

[0075] The bit line overlay 307 may be disposed on the top conductive layer 301 of the bit line. In some embodiments, the bit line overlay 307 may include, for example, silicon nitride or other applicable insulating materials.

[0076] Referring to Figure 31, semiconductor element 1C can have a structure similar to that shown in Figure 29. Elements in Figure 31 that are the same as or similar to those in Figure 29 are represented by the same symbols, and repeated descriptions have been omitted.

[0077] In a semiconductor device 1C, the spacer structures 400 may include a plurality of in-line spacers 401, a plurality of air gaps 407, and a plurality of out-of-line spacers 405. The in-line spacers 401 may be correspondingly disposed on the side surfaces 300S of the bit line structure 300. The out-of-line spacers 405 may be correspondingly disposed on the in-line spacers 401. The air gaps 407 may be disposed between the in-line spacers 401 and the out-of-line spacers 405. The use of air gaps 407 can reduce the dielectric constant of the spacer structure 400. As a result, the parasitic capacitance between adjacent conductive components (e.g., adjacent bit line structures 300) can be reduced.

[0078] Referring to Figure 32, semiconductor element 1D can have a structure similar to that shown in Figure 29. Elements in Figure 32 that are the same as or similar to those in Figure 29 are represented by the same symbols, and repeated descriptions have been omitted.

[0079] One aspect of this disclosure provides a unit contact structure, comprising: a bottom contact layer located on a substrate and surrounded by a plurality of bit line structures and a plurality of separator layers; a liner layer located between the bottom contact layer and the substrate, between the bottom contact layer and the bit line structures, and between the bottom contact layer and the separator layers; and a top contact layer located between the bottom contact layer and the liner layer. A top surface of the bottom contact layer and a top surface of the liner layer are substantially coplanar. The liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0080] Another aspect of this disclosure provides a semiconductor device comprising: a substrate; two bit line structures formed on the substrate, extending along a first direction and separated from each other; two separator layers located on the substrate, extending along a second direction perpendicular to the first direction and separated from each other along the first direction, and simultaneously contacting the two bit line structures; and a unit contact structure. The unit contact structure includes: a bottom contact layer located on the substrate and surrounded by the two bit line structures and the two separator layers; a liner layer located between the substrate and the bottom contact layer, between the two bit line structures and the bottom contact layer, and between the two separator layers and the bottom contact layer; and a top contact layer located on the liner layer and the bottom contact layer. A top surface of the liner layer and a top surface of the bottom contact layer are substantially coplanar. The liner layer comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride.

[0081] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming two bit line structures on the substrate, extending along a first direction and separated from each other; forming a plurality of spacer structures on the sides of the two bit line structures; forming two separator layers on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening that engages with the spacer structures; conformally forming a liner in and within the contact opening; forming a bottom contact layer on the liner and within the contact opening; and forming a top contact layer on the liner, on the bottom contact layer, and within the contact opening. The liner comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. The bottom contact layer comprises tungsten, titanium, or titanium nitride. The liner, the bottom contact layer, and the top contact layer together constitute a unit contact structure.

[0082] Due to the design of the semiconductor device disclosed herein, the interface leakage of the cell contact structure 500 can be reduced by employing a substrate 501 comprising doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. Furthermore, the sheet resistance of the cell contact structure 500 can be reduced by employing a bottom contact layer 503 and a top contact layer 505 comprising titanium nitride, tungsten, or titanium. As a result, the performance of the semiconductor device 1A can be improved.

[0083] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0084] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0085] 1A: Semiconductor components 1B: Semiconductor components 1C: Semiconductor components 1D: Semiconductor Components 10: Method 101:Substrate 103: Isolation layer 105: Impurity Region 105-1: Source Region 105-3: Duct region 107: Bottom Dielectric Layer 109: Top insulation layer 200: Character Line Structure 201: Character line dielectric layer 203: Character Line Barrier Layer 205: Character Line Conductive Layer 207: Character Line Overlay 300: Bitline Structure 300S: Side View 301: Top conductive layer of bit line 303: Intermediate conductive layer of bit line 305: Bottom conductive layer of bit line 307: Bitline overlay 307TS: Top Surface 309: Bit line contact 400: Spacer Structure 401: Spacers within the bit line 401TS: Top Surface 403: Bit line spacer 403TS: Top Surface 405: Spacers outside the bit line 405TS: Top Surface 407: Air gap 500: Unit contact structure 501: Lining 501TS: Top Surface 503: Bottom Contact Layer 503TS: Top Surface 505: Top Contact Layer 505TS: Top Surface 601: Separator Layer 601TS: Top Surface 701: First Cover Layer 801: Sacrificial Layer 803: Separating Material 805: Padding Material 807: First conductive material 809: Second conductive material AA: Active Region A-A': line B-B': line OP1: Separating opening OP2: Contact opening P1: Linear pattern S11: Steps S13: Steps S15: Steps S17: Steps TR: Character line groove W1: Width W2: Width X: Direction Y: direction Z: Direction

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a substrate; Two bit line structures are formed on the substrate, extending along a first direction and separated from each other; A plurality of spacer structures are formed on the sides of the two bit line structures; two separator layers are formed on the substrate, extending along a second direction perpendicular to the first direction and separated from each other, thereby creating a contact opening that engages with the spacer structures; a liner is conformally formed in and within the contact opening; a bottom contact layer is formed on the liner and within the contact opening; and a top contact layer is formed on the liner, the bottom contact layer, and within the contact opening, contacting the spacer structures and the two separator layers, wherein the liner comprises doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium, wherein the bottom contact layer comprises tungsten, titanium, or titanium nitride, wherein the liner, the bottom contact layer, and the top contact layer together constitute a unit contact structure.

2. A method for fabricating a semiconductor device as described in claim 1, wherein forming two separating layers comprises: A sacrificial layer is formed on the substrate to cover the two bit line structures and the spacer structures; Perform a first planarization process until the top surfaces of the two bit line structures are exposed; form a first mask layer on the sacrificial layer, wherein the first mask layer includes a linear pattern that partially exposes the sacrificial layer, the two bit line structures, and the spacer structures; selectively remove the sacrificial layer to form two separation openings; remove the first mask layer; form a layer of separator material to completely fill the two separation openings and cover the two bit line structures and the spacer structures; and perform a second planarization process until the top surfaces of the two bit line structures and the sacrificial layer are exposed to convert the layer of separator material into the two separator layers.

3. A method for fabricating a semiconductor device as described in claim 2, wherein the sacrificial layer comprises silicon oxynitride or silicon oxynitride.

4. A method for fabricating a semiconductor device as described in claim 2, wherein the separating material of the layer comprises silicon nitride.

5. The method for fabricating a semiconductor device as described in claim 2 further includes: The sacrificial layer is selectively removed to form the contact opening.

6. A method for fabricating a semiconductor device as described in claim 5, wherein forming the spacer structures comprises: A plurality of intra-bit spacers are formed on the sides of the two bit line structures; a plurality of intermediate bit spacers are formed on the intra-bit spacers; and a plurality of extra-bit spacers are formed on the intermediate bit spacers.

7. A method for fabricating a semiconductor element as described in claim 6, wherein the intra-bit spacers and the intermediate bit spacers comprise the same material.

8. A method for fabricating a semiconductor element as described in claim 6, wherein the top contact layer comprises tungsten, titanium, or titanium nitride.

9. A method for fabricating a semiconductor element as described in claim 6, wherein the top contact layer and the bottom contact layer comprise the same material.

10. A method for fabricating a semiconductor device as described in claim 6, wherein the substrate comprises an n-type dopant or a p-type dopant.

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