Method and apparatus for performing device type detection of memory device with aid of driving voltage path detection, and associated computer-readable medium

Abstract

This invention provides a method and related apparatus for detecting the device type of a memory device by means of drive voltage path detection, wherein the memory device is mounted on a printed circuit board of a host device. The method may include: determining a device type of the memory device in response to a detection signal obtained from one of two sets of drive voltage terminals in the printed circuit board, for determining whether a memory device version belongs to a first set of versions or a second set of versions; and selecting a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selection voltage level, for providing the selection voltage level to the memory device via at least a portion of the two sets of drive voltage terminals.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method for detecting the device type of a memory device by means of drive voltage path detection, the related devices being such as a host device, a printed circuit board (PCB) of the host device, an electronic device including the host device and the memory device, the memory device, a memory controller within the memory device, and related computer-readable media. Prior Technology

[0002] Memory devices can include flash memory for storing data, but managing and accessing flash memory is quite complex. For example, memory devices can be memory cards, solid-state drives, or embedded storage devices such as those conforming to the Universal Flash Storage (UFS) standard. Memory devices can be used to store files of various sizes in a host's file system, such as system files and user files. However, some problems may arise. When a host's hardware architecture is designed to meet the requirements of one version of a UFS product, this hardware architecture may be incompatible with another version of a UFS product. Related technologies attempt to correct these problems, but this has also led to further problems such as certain side effects. Therefore, a novel method and related architecture are needed to solve these problems without or with fewer side effects. Summary of the Invention

[0003] The purpose of this invention is to provide a method for detecting the device type of a memory device by means of drive voltage path detection, and related equipment such as a host device, a printed circuit board of the host device, an electronic device including the host device and the memory device, the memory device, a memory controller in the memory device, and related computer-readable media, to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for detecting the device type of a memory device by means of drive voltage path detection, wherein the memory device is mounted on a printed circuit board of a host device. For example, an electronic device may include the host device and the memory device. The memory device may include a memory controller and a non-volatile (NV) memory, and the NV memory may include at least one NV memory element (e.g., one or more NV memory elements). The method may include: determining a device type of the memory device in response to a detection signal obtained from a predetermined drive voltage terminal of one of two sets of drive voltage terminals in the printed circuit board, for determining whether a memory device version of the memory device belongs to a first set of versions or a second set of versions; and selecting a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selection voltage level, for providing the selection voltage level to the memory device by at least a portion of the drive voltage terminals of the two sets of drive voltage terminals. For example, the first set of versions may include the second version of the UFS specification (referred to as "v2"), while the second set of versions may include several newer versions of the UFS specification, such as the third version (referred to as "v3"), the fourth version (referred to as "v4"), etc.

[0005] In addition to the methods described above, the present invention also provides a host device operating according to the methods described above, and a computer-readable medium storing code, wherein the code causes the host device to operate according to the methods described above when executing the code. For example, the host device can determine the device type of the memory device and provide the selection voltage level to the memory device through at least a portion of the aforementioned drive voltage terminals to enhance overall performance.

[0006] In addition to the methods described above, the present invention also provides a printed circuit board for detecting the device type of a memory device by means of drive voltage path detection, wherein the memory device is mounted on the printed circuit board of a host device. The printed circuit board may include a control module and at least one power management integrated circuit (PMIC) (e.g., one or more PMICs) coupled to the control module. The control module can be used to control the operation of the printed circuit board, wherein the control module may include at least one circuit. Furthermore, the at least one PMIC can be used to perform power management under the control of the control module to selectively provide at least one drive voltage to the memory device as a power source for the memory device. For example, in response to a detection signal obtained from a predetermined drive voltage terminal of one of two sets of drive voltage terminals in the printed circuit board, the control module determines a device type of the memory device to determine whether a memory device version belongs to a first set of versions or a second set of versions; and the control module selects a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selection voltage level, so as to provide the selection voltage level to the memory device by at least a portion of the drive voltage terminals of the two sets of drive voltage terminals.

[0007] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the host device within the electronic device. In another example, the device may include the printed circuit board of the host device. In yet another example, the device may include the electronic device. In some examples, the device may include the memory device and / or the memory controller within the memory device. Additionally, the control module (or at least one of the aforementioned circuits) may be implemented using a system-on-a-chip (SoC), a microcontroller unit (MCU), a power management integrated circuit, and an automatic control circuit within the power management integrated circuit (e.g., a power management integrated circuit automatic control circuit for automatically controlling the at least one power management integrated circuit).

[0008] The method and apparatus of the present invention ensure that the memory device operates correctly under various conditions. In particular, the hardware architecture of the host device is compatible with any version of the UFS specification (e.g., v2, v3, and v4). For example, when the memory device version belongs to the first set of UFS specifications (e.g., v2), the hardware architecture of the host device can meet the requirements of the first set of versions. In another example, when the memory device version belongs to the second set of UFS specifications (e.g., v3 and v4), the hardware architecture of the host device can meet the requirements of the second set of versions. Furthermore, the method and apparatus of the present invention solve the problems of related technologies without introducing any side effects or in a manner unlikely to introduce side effects. Simple Explanation of the Diagram

[0009] Figure 1 is a schematic diagram of an electronic device according to one embodiment of the present invention. Figure 2 illustrates a control scheme for a first-plate system according to an embodiment of the present invention. Figure 3 illustrates a control scheme for a second-plate system according to an embodiment of the present invention. Figure 4 illustrates a general board system control scheme for a method of detecting the device type of a memory device (e.g., a UFS device) by means of drive voltage path detection, according to an embodiment of the present invention. Figure 5 illustrates a first detection operation and a first sample in a terminal reuse / redefinition control scheme according to an embodiment of the present invention. Figure 6 illustrates a second detection operation and a second sample in the detection process in the terminal reuse / redefinition control scheme of the method according to an embodiment of the present invention. Figure 7 illustrates a first drive operation in a drive voltage control scheme according to an embodiment of the present invention, and a first sample of a set of drive voltages using the first drive operation. Figure 8 illustrates a second drive operation in the drive voltage control scheme of the method according to an embodiment of the present invention, and a second sample of a set of drive voltages using the second drive operation. Figure 9 illustrates the workflow of the method according to an embodiment of the present invention. Implementation

[0010] Figure 1 is a schematic diagram of an electronic device 10 according to one embodiment of the present invention, wherein the electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors) collectively referred to as processor 52, a computer-readable medium 52M storing program code 52C, a power supply circuit 54, and a transmission interface circuit 58, and may include at least one printed circuit board (e.g., one or more printed circuit boards) collectively referred to as printed circuit board 50B, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus and may be coupled to the power supply circuit 54 to obtain power, and one or more components of the host device 50, such as the processor 52, the computer-readable medium 52M, the power supply circuit 54, and the transmission interface circuit 58, may be mounted on the printed circuit board 50B of the host device 50. The processor 52 can be used to control the operation of the host device 50, and the power supply circuit 54 can be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more drive voltages to the memory device 100. The memory device 100 can provide storage space to the host device 50 and can obtain the one or more drive voltages from the host device 50 as power for the memory device 100. Examples of the host device 50 may include (but are not limited to) multifunction mobile phones, tablet computers, wearable devices, and personal computers such as desktop computers and laptop computers. Examples of the memory device 100 may include (but are not limited to) portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS, or XD specifications), solid-state drives (SSDs), and various types of embedded memory devices (e.g., memory devices conforming to UFS or eMMC specifications). Additionally, the computer-readable media 52M can be implemented using one or more hard disk drives (HDDs), one or more solid-state drives, etc. According to this embodiment, the memory device 100 may include a controller, such as a memory controller 110, and may further include a non-volatile (NV) memory 120, wherein the controller is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, ..., and 122-N, wherein "N" may represent a positive integer greater than one. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.。

[0011] As shown in Figure 1, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read-only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (e.g., implemented using static random access memory (SRAM)), and a transmission interface circuit 118, wherein at least some (e.g., some or all) of the above components may be interconnected via buses. The random access memory 116 may be used to provide internal storage space (e.g., to temporarily store information) to the memory controller 110, but the invention is not limited thereto. Furthermore, in this embodiment, the read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the non-volatile memory 120. Note that program code 112C may also be stored in the random access memory 116 or any type of memory. Furthermore, control logic circuitry 114 can be used to control non-volatile memory 120. Control logic circuitry 114 may include an error correction code (ECC) circuit (not shown in Figure 1) that can encode and decode error correction codes to protect data and / or perform error correction. Transmission interface circuitry 118 may include multiple sub-circuits that can interact with each other for communication. The transmission interface circuit 118 may conform to one or more of the following communication standards: Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIe), embedded Multi Media Card (eMMC), and Universal Flash Storage (UFS). It may also enable the memory device 100 to communicate with the host device 50 (or its transmission interface circuit 58) according to these communication standards. Similarly, the transmission interface circuit 58 may conform to these communication standards and enable the host device 50 to communicate with the memory device 100 (or its transmission interface circuit 118) according to these communication standards.For example, the plurality of sub-circuits of the transmission interface circuit 118 may include a UFS controller 118C, a Unified Protocol (UniPro) circuit 118U, and a physical layer (PHY) circuit such as a Mobile Industry Processor Interface (MIPI) M-PHY circuit 118M (denoted as "M-PHY" circuit for simplicity). The transmission interface circuit 58 may be implemented using a similar or identical circuit architecture to the transmission interface circuit 118 (e.g., a plurality of corresponding sub-circuits), but the invention is not limited thereto.

[0012] In this embodiment, the host device 50 can transmit a plurality of host instructions and corresponding plurality of logical addresses to the memory controller 110 to indirectly access the non-volatile memory 120 in the memory device 100. The memory controller 110 receives the plurality of host instructions and the plurality of logical addresses, and translates the plurality of host instructions into a plurality of memory operation instructions (hereinafter referred to as operation instructions), and then uses the plurality of operation instructions to control the non-volatile memory 120 to read or write / program memory cells or data pages at specific physical addresses within the non-volatile memory 120, wherein the specific physical address can be associated with the plurality of logical addresses. For example, the memory controller 110 can generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between physical addresses and logical addresses. The non-volatile memory 120 may store a global logic-to-physical address mapping table 120T for the memory controller 110 to control the memory device 100 to access the data in the non-volatile memory 120, but the present invention is not limited thereto.

[0013] For ease of understanding, the global logic-to-physical address mapping table 120T may be located in a predetermined region, such as a system region, within the non-volatile memory element 122-1, but the invention is not limited thereto. For example, the global logic-to-physical address mapping table 120T may be divided into a plurality of region logic-to-physical address mapping tables, and the plurality of region logic-to-physical address mapping tables may be stored in one or more of the non-volatile memory elements 120-1, 120-2, ..., and 120-N, particularly in the form of separate storage in the non-volatile memory elements 120-1, 120-2, ..., and 120-N. When needed, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global logic-to-physical address mapping table 120T into the random access memory 116 or other memory. For example, the memory controller 110 may load one of the plurality of region logic-to-physical address mapping tables into random access memory 116 as a temporary logic-to-physical address mapping table 116T, so as to access data in non-volatile memory 120 according to the region logic-to-physical address mapping table stored as temporary logic-to-physical address mapping table 116T, but the present invention is not limited thereto.

[0014] Furthermore, the aforementioned at least one non-volatile memory element (e.g., the one or more non-volatile memory elements such as {122-1, 122-2, …, 122-N}) may comprise a plurality of blocks, wherein the smallest unit for the memory controller to perform data erasure operations on the non-volatile memory 120 may be a block, and the smallest unit for the memory controller 110 to perform data writing operations on the non-volatile memory 120 may be a page, but the present invention is not limited thereto. For example, any non-volatile memory element 120-n (where "n" may represent any integer in the interval [1, N]) among the non-volatile memories 120-1, 120-2, …, and 120-N may comprise a plurality of blocks, and one of the plurality of blocks may contain and record a specific number of pages, wherein the memory controller 110 may access a specific page of a specific block among the plurality of blocks according to a block address and a page address.

[0015] Figure 2 illustrates a first board system control scheme according to an embodiment of the present invention, wherein a board system corresponding to the first board system control scheme, such as a printed circuit board 200, can support any memory device 100 conforming to the second version of the UFS specification (hereinafter referred to as "v2"), such as a UFS v2 sample with its package (labeled "Board System: PCB for UFS v2" for simplicity), and can be an example of the printed circuit board 50B shown in Figure 1. The printed circuit board 200 may include at least one power management integrated circuit (e.g., one or more power management integrated circuits) such as power management integrated circuits 210 and 220 (labeled "PMIC" for simplicity) for generating multiple drive voltages VCCQ2 and VCC, and can output the multiple drive voltages VCCQ2 and VCC through multiple sets of terminals on the printed circuit board 200 for the multiple drive voltages VCCQ2 and VCC, respectively. Of the multiple sets of terminals used to output the multiple drive voltages VCCQ2 and VCC, the set of terminals used to output drive voltage VCCQ2 can be referred to as the VCCQ2 terminal, and the set of terminals used to output drive voltage VCC can be referred to as the VCC terminal. Additionally, power management integrated circuits 210 and 220 can be configured to provide drive voltages VCCQ2 and VCC to the UFS v2 sample mounted at a mounting area 201 on the printed circuit board 200 via VCCQ2 power plan 230 and VCC power plan 240 (e.g., VCCQ2 power plan 230 and VCC power plan 240 respectively equipped with power delivery sub-circuits for drive voltages VCCQ2 and VCC) and related terminals (e.g., the VCCQ2 terminal and VCC terminal of the ball out according to the UFS specification). The voltage levels of drive voltages VCCQ2 and VCC can be equal to 1.8 volts (V) and 3.3 V, respectively.

[0016] When the hardware architecture on the printed circuit board 50B (e.g., printed circuit board 200) of the host device 50 is designed to meet the requirements of a predetermined version of a UFS product, such as the UFS v2 sample, this hardware architecture may be incompatible with at least one other version of a UFS product, such as a UFS product that conforms to a later version of the UFS specification.

[0017] Figure 3 illustrates a second board system control scheme according to an embodiment of the present invention, wherein a board system corresponding to the second board system control scheme, such as a printed circuit board 300, can support any memory device 100 conforming to the third version (hereinafter referred to as "v3"), fourth version (hereinafter referred to as "v4"), or at least a newer and / or subsequent version (hereinafter referred to as "newer version") of the UFS specification. For example, a UFS sample (hereinafter referred to as "UFS v3, v4, or newer sample") of the v3, v4, or newer version has its package (labeled as "board system: PCB for UFS v3, v4, or newer version" for simplicity) and can be an example of the printed circuit board 50B shown in Figure 1. The printed circuit board 300 may include at least one power management integrated circuit (e.g., one or more power management integrated circuits), such as power management integrated circuits 310 and 320 (denoted as "PMIC" for simplicity) for generating multiple drive voltages VCCQ and VCC, and can output the multiple drive voltages VCCQ2 and VCCQ2 respectively through multiple sets of terminals on the printed circuit board 300 for the multiple drive voltages VCCQ and VCC. Among the multiple sets of terminals for outputting the multiple drive voltages VCCQ and VCC, the set of terminals for outputting drive voltage VCCQ may be referred to as the VCCQ terminal, and the set of terminals for outputting drive voltage VCC may be referred to as the VCC terminal. Additionally, power management circuits 310 and 320 can be configured to provide drive voltages VCCQ and VCC to the UFS v3, v4, or newer sample mounted on a mounting area 301 on the printed circuit board 300 via VCCQ power supply 330 and VCC power supply 340 (e.g., VCCQ power supply 330 and VCC power supply 340 respectively equipped with power delivery sub-circuits for drive voltages VCCQ and VCC) and associated terminals (e.g., VCCQ and VCC terminals of the ball output according to the v3, v4, or newer version of the UFS specification). The voltage levels of drive voltages VCCQ and VCC can be equal to voltage levels of 1.2 V and 2.5 V, respectively.

[0018] When the hardware architecture on the printed circuit board 50B (e.g., printed circuit board 300) of the host device 50 is designed to meet the needs of another predetermined version of the UFS product, such as the UFS v3, v4 or a newer sample, this hardware architecture may be incompatible with at least one other version of the UFS product, such as a UFS product that conforms to UFS specification v2.

[0019] Because the circuit board layout typically requires specific design for the UFS v2 sample and the UFS v3, v4, or newer samples, the printed circuit board design and bill of materials (BOM) of the printed circuit board 50B (e.g., printed circuit board 200 or printed circuit board 300) may vary in response to different requirements such as ball output, leading to increased costs such as material costs and labor costs. According to some embodiments, the electronic device 10 (or the host device 50 and / or memory device 100 within it) can be operated according to a method for detecting the device type of the memory device 100 (e.g., a UFS device) by means of drive voltage path detection, thereby improving overall performance. In response to a detection signal (e.g., a UFS version detection signal UFS_VERSION_DETECTION) obtained from one of two sets of drive voltage terminals (e.g., a set of VCCQ terminals and a set of VCCQ2 terminals), a control module on the printed circuit board 50B can determine a device type of the memory device 100, to determine whether the memory device version of the memory device 100 (e.g., the UFS device) belongs to a first set of versions or a second set of versions, and select a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selection voltage level, so that the selection voltage level is provided to the memory device 100 by at least a portion of the two sets of drive voltage terminals (e.g., a portion of the drive voltage terminals or all of the drive voltage terminals). For example, the first set of versions may include the second version (v2) of the UFS specification, and the second set of versions may include multiple newer versions of the UFS specification, such as the third version (v3), the fourth version (v4), etc. of the UFS specification.

[0020] Figure 4 illustrates a general board system control scheme according to an embodiment of the present invention, wherein a board system corresponding to the general board system control scheme, such as a printed circuit board 400, can support any version of any memory device 100 conforming to various versions of the UFS specification (e.g., v2, v3, v4, and the newer version), such as a UFS sample of v2, v3, v4, or the newer version with its package (labeled "Board System: PCB for UFS Sample" for simplicity), and can be an example of the printed circuit board 50B shown in Figure 1. The printed circuit board 400 may include at least one power management integrated circuit (e.g., one or more power management integrated circuits), such as power management integrated circuits 410 and 420. In a first predetermined configuration of a plurality of predetermined configurations of the host device 50 (or its printed circuit board 50B, such as printed circuit board 400), under the control of the aforementioned control module, such as control module 480, power management integrated circuits 410 and 420 can be configured to provide drive voltages PWR1 and PWR2 (e.g., drive voltages PWR1 and PWR2 acting as drive voltages VCCQ2 and VCC, respectively) to the UFS v2 sample mounted at a mounting area 401 on the printed circuit board 400 via PWR1 power plan 430 and PWR2 power plan 440 on the printed circuit board 400 and related terminals (e.g., VCCQ2 and VCC terminals of the ball output according to the UFS specification). The voltage levels of drive voltages VCCQ2 and VCC can be equal to 1.8 V and 3.3 V, respectively. The voltage level V. In a second predetermined configuration of the plurality of predetermined configurations of the host device 50 (or the printed circuit board 50B within it, such as printed circuit board 400), under the control of the aforementioned control module, such as control module 480, power management integrated circuits 410 and 420 can be configured to supply power to the UFS mounted on the mounting area 401 on the printed circuit board 400 via PWR1 power plan 430 and PWR2 power plan 440 (e.g., PWR1 power plan 430 and PWR2 power plan 440 acting as VCCQ power plan 330 and VCC power plan 340 respectively) and related terminals (e.g., VCCQ terminals and VCC terminals of the ball output according to the v3, v4 or the newer version of the UFS specification). The v3, v4, or newer samples provide drive voltages PWR1 and PWR2 (e.g., drive voltages PWR1 and PWR2 that act as drive voltages VCCQ and VCC), wherein the voltage levels of drive voltages VCCQ and VCC can be equal to voltage levels of 1.2 V and 2.5 V, respectively.

[0021] In the above embodiments, the aforementioned control module, such as control module 480, can be implemented in various ways. For example, control module 480 can be implemented using a SoC, MCU, or similar methods. In particular, it can be implemented using a program module running on a processor / microprocessor, such as a software module or a firmware module. As another example, control module 480 can be implemented using a power management integrated circuit (PMIC) automatic control circuit (referred to as "PMIC automatic circuit" for simplicity). In particular, it can be implemented using hardware circuits that include logic circuits for automatic control.

[0022] Figure 5 illustrates a first detection operation and a first sample in a terminal reuse / redefinition control scheme according to an embodiment of the present invention. The control module 480 can utilize any power management integrated circuit of the power circuit 58 shown in Figure 1, such as a predetermined power management integrated circuit among power management integrated circuits 410 and 420 within the power supply circuit 58, to generate a test voltage VTEST in a test phase of a plurality of stages of the host device 50 (or the control module 480 within it) to test the memory device 100, for example, the first sample. For example, the first sample can represent a UFS sample shown in the upper half of Figure 5, such as at least one die (e.g., one or more dies) and its package 500, which can be collectively referred to as die 501. The control module 480 can utilize power management integrated circuit 410 to generate a drive voltage VCCQ, for example, VCCQ = 1.2V, as the test voltage VTEST in the first detection operation, but the invention is not limited thereto. In some instances, as long as it does not impede the implementation of the invention and the electronic device 10 (or the host device 50 and / or memory device 100 therein) does not malfunction, the control module 480 may use any of the aforementioned power management integrated circuits to generate any voltage PWR at any voltage level as the test voltage V TEST in the first detection operation.

[0023] As shown in the lower half of Figure 5, all terminals in the VCCQ terminal group 451 and most terminals in the VCCQ2 terminal group 452, except for one predetermined terminal in the VCCQ2 terminal group 452, can be coupled to the test voltage V TEST. When the first sample, for example, a bare die 501 with its package 500, is mounted on the printed circuit board 400, the VCCQ terminal group 451 and the VCCQ2 terminal group 452 are coupled to the corresponding terminals on the package 500, such as the ball output terminals of any version conforming to the UFS specification (e.g., v2, v3, v4, or the newer version). Typically, for drive voltages VCCQ and VCCQ2, the wire bonding of the bare die 501 can involve only one of the drive voltages VCCQ and VCCQ2 to save associated costs such as material costs and time costs. Therefore, the drive voltage connection path corresponding to one of the drive voltages VCCQ and VCCQ2 will be valid, while the drive voltage connection path corresponding to the other drive voltage of VCCQ and VCCQ2 will be invalid, causing the voltage level of the UFS version detection signal UFS_VERSION_DETECTION to be equal to zero (0). Therefore, in this test phase, the control module 480 can classify the memory device 100, such as the first sample (or the chip 501 packaged in its package 500), according to the UFS version detection signal UFS_VERSION_DETECTION (e.g., UFS_VERSION_DETECTION = 0) to determine the memory device type of the memory device 100, and in particular, determine whether the first sample belongs to a UFS v2 sample or a UFS v3, v4 or newer version sample.

[0024] Figure 6 illustrates a second detection operation and a second sample in the terminal reuse / redefinition control scheme of the method according to an embodiment of the present invention. The control module 480 can utilize any of the aforementioned power management integrated circuits of the power circuit 58 shown in Figure 1, such as the predetermined power management integrated circuits in power management integrated circuits 410 and 420 within the power supply circuit 58, to generate a test voltage VTEST in the test phase of the plurality of phases of the host device 50 (or the control module 480 within it) for testing the memory device 100, such as the second sample. For example, the second sample can represent the UFS sample shown in the upper half of Figure 6, such as at least one die (e.g., one or more dies) and its package 600, which can be collectively referred to as die 601. The control module 480 can utilize the power management integrated circuit 410 to generate a drive voltage VCCQ, for example, VCCQ = 1.2V, as the test voltage VTEST in the second detection operation, but the invention is not limited thereto. In some instances, as long as it does not impede the implementation of the invention and the electronic device 10 (or the host device 50 and / or memory device 100 therein) does not malfunction, the control module 480 may use any of the aforementioned power management integrated circuits to generate any of the aforementioned voltage levels PWR as the test voltage V TEST in the second detection operation.

[0025] As shown in the lower half of Figure 6, all terminals in the VCCQ terminal group 451 and most terminals in the VCCQ2 terminal group 452, except for the predetermined terminals in the VCCQ2 terminal group 452, can be coupled to the test voltage V TEST. When the second sample, for example, a bare die 601 with its package 600, is mounted on the printed circuit board 400, the VCCQ terminal group 451 and the VCCQ2 terminal group 452 are coupled to the corresponding terminals on the package 600, such as the ball output terminals of any of the aforementioned versions conforming to the UFS specification (e.g., v2, v3, v4, or the newer version). Typically, for drive voltages VCCQ and VCCQ2, the wire bonding of the bare die 601 can involve only one of the drive voltages VCCQ and VCCQ2 to save associated costs such as material costs and time costs. Therefore, the drive voltage connection path corresponding to one of the drive voltages VCCQ and VCCQ2 will be valid, while the drive voltage connection path corresponding to the other drive voltage of VCCQ and VCCQ2 will be invalid, causing the voltage level of the UFS version detection signal UFS_VERSION_DETECTION to be equal to the test voltage V TEST. Thus, in this testing phase, the control module 480 can classify the memory device 100, such as the second sample (or the chip 601 packaged in its package 600), according to the UFS version detection signal UFS_VERSION_DETECTION (e.g., UFS_VERSION_DETECTION = V TEST) to determine the memory device type of the memory device 100, and in particular, to determine whether the second sample belongs to a UFS v2 sample or a UFS v3, v4, or a newer version sample.

[0026] Figure 7 illustrates a first drive operation in a drive voltage control scheme according to an embodiment of the present invention, and a first sample of a set of drive voltages using the first drive operation. In one of the driving stages of the host device 50, the control module 480 can set the respective states (or logic values) of the control signals CONTROL1 and CONTROL2 according to the classification result of the first sample, and control the power management circuits 410 and 420 with the control signals CONTROL1 and CONTROL2 respectively to set the driving voltages PWR1 and PWR2. The UFS version detection signal UFS_VERSION_DETECTION (e.g., UFS_VERSION_DETECTION = 0) can indicate the classification result of the first sample, such as whether the first sample belongs to the classification result of UFS v2 sample or UFS v3, v4 or a newer version sample. Therefore, the control module 480 can set the respective states (or logic values) of the control signals CONTROL1 and CONTROL2 according to the UFS version detection signal UFS_VERSION_DETECTION to provide the driving voltage corresponding to the classification result.

[0027] When UFS_VERSION_DETECTION = 0, it indicates that the first sample belongs to UFS v3, v4 or a newer version sample. The control module 480 can set the respective states of the control signals CONTROL1 and CONTROL2 according to the UFS version detection signal UFS_VERSION_DETECTION, so as to set the voltage level of the drive voltage PWR1 (hereinafter referred to as "PWR1 level") and the voltage level of the drive voltage PWR2 (hereinafter referred to as "PWR2 level"), so as to control the power management circuits 410 and 420 to provide drive voltages VCCQ and VCCQ corresponding to the classification result, where VCCQ = 1.2 V and VCC = 2.5 V.

[0028] Figure 8 illustrates a second drive operation in the drive voltage control scheme of the method according to an embodiment of the present invention, and a second sample of a set of drive voltages using the second drive operation. In the driving stage of the multiple stages of the host device 50, the control module 480 can set the respective states (or logic values) of the control signals CONTROL1 and CONTROL2 according to the classification result of the second sample, and control the power management circuits 410 and 420 with the control signals CONTROL1 and CONTROL2 respectively to set the driving voltages PWR1 and PWR2. The UFS version detection signal UFS_VERSION_DETECTION (e.g., UFS_VERSION_DETECTION = V TEST) can indicate the classification result of the second sample, such as whether the second sample belongs to the classification result of UFS v2 sample or UFS v3, v4 or a newer version sample. Therefore, the control module 480 can set the respective states (or logic values) of the control signals CONTROL1 and CONTROL2 according to the UFS version detection signal UFS_VERSION_DETECTION to provide the driving voltage corresponding to the classification result.

[0029] When UFS_VERSION_DETECTION = V TEST, it indicates that the second sample belongs to UFS v2 sample. The control module 480 can set the respective states of the control signals CONTROL1 and CONTROL2 according to the UFS version detection signal UFS_VERSION_DETECTION, so as to set the voltage level of drive voltage PWR1 (hereinafter referred to as "PWR1 level") and the voltage level of drive voltage PWR2 (hereinafter referred to as "PWR2 level"), so as to control the power management circuits 410 and 420 to provide drive voltages VCCQ2 and VCC corresponding to the classification result, where VCCQ2 = 1.8V and VCC = 3.3V.

[0030] According to some embodiments, program code 52C stored in computer-readable medium 52M can cause host device 50 (e.g., processor 52) to operate according to the method when executed by host device 50 (e.g., processor 52), and the related operations of the method may include: (1) During this testing phase, the host device 50 (or its control module 480, such as processor 52) may use any of the aforementioned power management integrated circuits, such as power management integrated circuit 410, to output any of the aforementioned voltages PWR, such as drive voltage PWR1, as the test voltage V TEST, where PWR = 1.2V; (2) During this testing phase, the host device 50 (or its control module 480, such as processor 52) can determine whether the voltage level of the UFS version detection signal UFS_VERSION_DETECTION is a preset voltage level (e.g., a connection level) indicating a preset logic value (e.g., logic value 0), or a first voltage level (e.g., a power level) indicating a first logic value (e.g., logic value 1); (3) When the voltage level of the UFS version detection signal UFS_VERSION_DETECTION is detected to be the first voltage level (e.g., the power level such as a high level) indicating the first logic value (e.g., logic value 1), the host device 50 (or its control module 480, such as the processor 52) may change any of the aforementioned voltages PWR, such as the drive voltage PWR1, to 1.8V for use in the drive phase; (4) When the voltage level of the UFS version detection signal UFS_VERSION_DETECTION is detected to be the preset voltage level (e.g., the connection level, e.g., a lower level) indicating the preset logic value (e.g., logic value 0), the host device 50 (or its control module 480, e.g., processor 52) may maintain any of the aforementioned voltages PWR, e.g., the drive voltage PWR1, at 1.2V for use in the drive phase; and (5) The host device 50 (or its control module 480, such as the processor 52) can unlock the host device 50, such as the SoC or peripheral circuit system, and then boot the system of the host device 50, such as a system implemented by a main program module running on the processor 52; However, the present invention is not limited thereto. As long as it does not impede the implementation of the present invention and the electronic device 10 (or the host device 50 and / or memory device 100 within it) does not malfunction, the relevant operations can be modified. For example, in a first control module setting control scheme of the method, the control module 480 can be implemented by a SoC or MCU and internal firmware or software (e.g., firmware or software running thereon), wherein the control module 480 can be configured to detect a detection signal (e.g., UFS version detection signal UFS_VERSION_DETECTION) from the printed circuit board 50B (e.g., printed circuit board 400) during the test phase, and then the firmware (FW) or software (SW) can determine to set the voltage level of the drive voltage PWR1 (e.g., the voltage output (Vout) of the power management integrated circuit 410) to 1.8V or 1.2V for use during the drive phase. The architecture of this first control module setting control scheme can be applied to any telephone system or any embedded system that requires UFS memory. As another example, in a second control module setting control scheme of this method, control module 480 can be implemented using a power management integrated circuit (PMIC) automatic control circuit (hereinafter referred to as "PMIC automatic circuit"). Since any embedded system in most embedded systems can boot from its UFS memory, this second control module setting control scheme (or the PMIC automatic circuit) can be used to identify the UFS version detection signal UFS_VERSION_DETECTION as a switch / toggle option. The system sets the desired voltage level as a boot result. In some examples, control module 480 can be implemented using one or a combination of power management integrated circuits, SoC architecture, PMIC automatic circuit, ROM code, etc.

[0031] Figure 9 illustrates the workflow of the method according to an embodiment of the present invention. The host device 50 (or its control module 480, such as processor 52) can be operated according to the method to perform the workflow shown in Figure 9, and in particular, can be operated according to at least one control scheme (e.g., one or more control schemes) of the method, such as the general board system control scheme, the terminal reuse / redefinition control scheme, the drive voltage control scheme, etc.

[0032] In step S11, during this testing phase, in response to the detection signal (e.g., UFS version detection signal UFS_VERSION_DETECTION) obtained from the predetermined drive voltage terminal of one of the two sets of drive voltage terminals in the printed circuit board 50B (e.g., printed circuit board 400), the host device 50 (or its control module 480, such as processor 52) can determine the device type (or memory device type) of the memory device 100, so as to determine whether the memory device version of the memory device 100 belongs to the first set of versions or the second set of versions.

[0033] In step S12, during the driving phase, the host device 50 (or its control module 480, such as processor 52) can select a voltage level corresponding to the device type from the plurality of predetermined voltage levels as the selected voltage level, so that the selected voltage level can be provided to the memory device 100 by at least a portion of the driving voltage terminals in the two sets of driving voltage terminals.

[0034] Memory device 100 may represent the UFS device. Taking the architecture shown in any of Figures 4 through 8 as an example, the two sets of drive voltage terminals may include a set of VCCQ drive voltage terminals such as the set of VCCQ terminals 451 and a set of VCCQ2 drive voltage terminals such as the set of VCCQ2 terminals 452. For example, one set of drive voltage terminals and the other set of drive voltage terminals may represent the set of VCCQ2 drive voltage terminals and the set of VCCQ drive voltage terminals, respectively. In addition, all terminals in the printed circuit board 50B (e.g., printed circuit board 400) used to mount memory device 100 may conform to ball outputs defined by multiple versions of the UFS specification, wherein the multiple versions may include at least v2, v3, and v4. In particular, in addition to v2, v3, and v4, the multiple versions may also include at least one subsequent version (or the newest version). For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0035] For ease of understanding, the method can be illustrated using the workflow shown in Figure 9, but the invention is not limited thereto. According to certain embodiments, one or more steps may be added, deleted, or modified in the workflow shown in Figure 9. For example, one set of drive voltage terminals and the other set of drive voltage terminals may respectively represent a second set of drive voltage terminals, such as the VCCQ2 drive voltage terminals, and a first set of drive voltage terminals, such as the VCCQ drive voltage terminals. During this testing phase, the host device 50 (or its control module 480, such as processor 52) can output a first voltage with a predetermined voltage level, such as a drive voltage VCCQ with a predetermined voltage level of 1.2V, using a first power management integrated circuit (e.g., power management integrated circuit 410) as the test voltage VTEST. The test voltage can be received using all the first drive voltage terminals in the group of second drive voltage terminals (excluding the predetermined drive voltage terminal) and all the first drive voltage terminals in the group of first drive voltage terminals, to obtain the detection signal, such as the UFS version detection signal UFS_VERSION_DETECTION, from the predetermined drive voltage terminal. Additionally, the memory device can be implemented using at least one die and its package (e.g., die 501 and its package 500 in the architecture shown in Figure 5, or die 601 and its package 600 in the architecture shown in Figure 6). For a first driving voltage and a second driving voltage corresponding to one of the first driving voltage terminals and the second driving voltage terminals of the group, such as driving voltages VCCQ and VCCQ2 corresponding to the VCCQ driving voltage terminals and the VCCQ2 driving voltage terminals of the group, the wire bonding of the aforementioned at least one bare die may involve only one of the first driving voltage and the second driving voltage (e.g., driving voltage VCCQ in the architecture shown in Figure 7, or driving voltage VCCQ2 in the architecture shown in Figure 8), to save costs. For the sake of simplicity, similar content in these embodiments will not be repeated here. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the scope of the claims of the present invention shall be covered by the present invention.

[0036] 10: Electronic devices 50: Main unit 50B, 200, 300, 400: Printed Circuit Board (PCB) 52: Processor 52M: Computer-readable media 52C: Code 54: Power Supply Circuit 58: Transmission Interface Circuit 100: Memory device 110: Memory controller 112: Microprocessor 112M: Read-only memory 112C: Code 114: Control Logic Circuit 116: Random Access Memory 116T: Temporary Logic to Entity Address Mapping Table 118: Transmission Interface Circuit 118C: UFS Controller 118U: UniPro Circuit 118M:M - Physical Layer Circuit 120: Non-volatile memory 122-1, 122-2, 122-N: Non-volatile memory elements 120T: Global Logical to Entity Address Mapping Table 201, 301, 401: Installation Area 210, 220, 310, 320, 410, 420: Power Management Integrated Circuit (PMIC) 230:VCCQ2 Power Supply Plan 240, 340: VCC power supply plan 330:VCCQ Power Supply Plan 430:PWR1 Power Supply Plan 440:PWR2 Power Supply Plan 480: Control Module 500, 600: Package 501, 601: Bare Crystal 450: VCC terminal 451:VCCQ terminal 452:VCCQ2 terminal S11, S12: Steps UFS_VERSION_DETECTION: UFS version detection signal VCC, VCCQ, VCCQ2: Drive voltage V TEST: Test voltage

Claims

1. A method for detecting the device type of a memory device by means of drive voltage path detection, the memory device being mounted on a printed circuit board of a host device, the memory device including a memory controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the method comprising: determining a device type of the memory device in response to a detection signal obtained from a predetermined drive voltage terminal of one of two sets of drive voltage terminals in the printed circuit board, for determining whether a memory device version of the memory device belongs to a first set of versions or a second set of versions; and selecting a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selection voltage level, for providing the selection voltage level to the memory device via at least a portion of the drive voltage terminals of the two sets of drive voltage terminals.

2. The method as described in claim 1, wherein the memory device represents a Universal Flash Storage (UFS) device.

3. The method as described in claim 2, wherein the two sets of drive voltage terminals include a set of VCCQ drive voltage terminals and a set of VCCQ2 drive voltage terminals.

4. The method as described in claim 3, wherein the two sets of drive voltage terminals represent the VCCQ2 drive voltage terminals and the VCCQ drive voltage terminals, respectively.

5. The method as described in claim 1, wherein all terminals in the printed circuit board for mounting the memory device conform to ball out as defined by multiple versions of the Universal Flash Storage (UFS) specification, wherein the multiple versions include at least a second version, a third version and a fourth version.

6. The method as described in claim 5, wherein in addition to the second version, the third version and the fourth version, the plurality of versions further include at least one subsequent version.

7. The method as described in claim 1, wherein the plurality of stages of the host device includes a test stage and a drive stage; and in response to the detection signal obtained from the predetermined drive voltage terminal of the set of two sets of drive voltage terminals in the printed circuit board, determining the device type of the memory device for determining whether the memory device version belongs to the first set of versions or the second set of versions further includes: in the test stage, in response to the detection signal obtained from the predetermined drive voltage terminal of the set of two sets of drive voltage terminals in the printed circuit board, determining the device type of the memory device for determining whether the memory device version belongs to the first set of versions or the second set of versions; and wherein selecting a voltage level corresponding to the device type from the plurality of predetermined voltage levels as the selected voltage level for providing the selected voltage level to the memory device via at least a portion of the drive voltage terminals of the two sets of drive voltage terminals further includes: During the driving phase, a voltage level corresponding to the device type is selected from the plurality of predetermined voltage levels as the selected voltage level, so that the selected voltage level can be provided to the memory device by at least a portion of the driving voltage terminals in the two sets of driving voltage terminals.

8. The method as described in claim 7, wherein one set of driving voltage terminals and the other set of driving voltage terminals respectively represent a second set of driving voltage terminals and a first set of driving voltage terminals; and the method further comprises: during the test phase, using a first power management integrated circuit to output a first voltage having a predetermined voltage level as a test voltage; and during the test phase, using the second driving voltage terminals in the second set of driving voltage terminals other than the predetermined driving voltage terminals and all the first driving voltage terminals in the first set of driving voltage terminals to receive the test voltage, so as to obtain the detection signal from the predetermined driving voltage terminals.

9. The method as described in claim 1, wherein the memory device is implemented by at least one bare die and its package; one of the two sets of drive voltage terminals and the other set of drive voltage terminals respectively represent a set of second drive voltage terminals and a set of first drive voltage terminals; and for a first drive voltage and a second drive voltage corresponding to one of the first drive voltage terminals and the second drive voltage terminals respectively, the wire bonding of the at least one bare die involves only one of the first drive voltage and the second drive voltage to save costs.

10. A host device operating according to the method described in claim 1.

11. A computer-readable medium storing code, wherein the code causes a host device to operate in accordance with the method described in claim 1 when executing the code.

12. A printed circuit board for detecting the device type of a memory device by means of drive voltage path detection, the memory device being mounted on the printed circuit board of a host device, the printed circuit board comprising: a control module for controlling the operation of the printed circuit board, wherein the control module includes at least one circuit; and at least one power management integrated circuit (PMIC) coupled to the control module for performing power management under the control of the control module to selectively provide at least one drive voltage to the memory device as a power source for the memory device; wherein: In response to a detection signal obtained from a predetermined drive voltage terminal of one of two sets of drive voltage terminals within the printed circuit board, the control module determines a device type of the memory device to determine whether a memory device version belongs to a first set of versions or a second set of versions; and the control module selects a voltage level corresponding to the device type from a plurality of predetermined voltage levels as a selective voltage level, so as to provide the selective voltage level to the memory device via at least a portion of the drive voltage terminals of the two sets of drive voltage terminals.

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