Semiconductor device including isolation element and manufacturing method of the same

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a first spacer, a second spacer, a third spacer, a fourth spacer, a capacitor contact, an isolation element, and a landing pad. The first and second spacers are located above the substrate and extend along a first direction. The third and fourth spacers are located above the substrate and extend along a second direction different from the first direction. The capacitor contact is surrounded by the first, second, third, and fourth spacers. The isolation element is disposed on the capacitor contact. The isolation element extends along the first direction. The landing pad is disposed on the isolation element and electrically connected to the capacitor contact.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 775,201 (i.e., priority date "July 17, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, it relates to a semiconductor device including an isolation element and a method for fabricating the same. Prior Technology

[0003] With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high efficiency and miniaturization. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous generation.

[0004] A Dynamic Random Access Memory (DRAM) device is a type of random access memory that stores each bit of data in a single capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F 2DRAM cells, where F represents the minimum feature width or critical dimension (CD) of the lithography. However, recently, with the continuous reduction of word line pitch, DRAM manufacturers face a significant challenge in reducing the area of ​​memory cells. For example, leakage between a landing pad and a bit line has become a critical issue, degrading the performance of the semiconductor device.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first spacer, a second spacer, a third spacer, a fourth spacer, a capacitor contact, an isolation element, and a landing pad. The first and second spacers are located above the substrate and extend along a first direction. The third and fourth spacers are located above the substrate and extend along a second direction different from the first direction. The capacitor contact is surrounded by the first, second, third, and fourth spacers. The isolation element is disposed on the capacitor contact. The isolation element extends along the first direction. The landing pad is disposed on the isolation element and electrically connected to the capacitor contact.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first spacer, a second spacer, a capacitor contact, an isolation element, and a landing pad. The first spacer and the second spacer are located above the substrate and extend along a first direction. The capacitor contact is disposed between the first spacer and the second spacer. The isolation element is disposed on the capacitor contact. The landing pad includes a neck defined by the isolation element.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a first spacer and a second spacer extending along a first direction over the substrate; forming a third spacer and a fourth spacer over the substrate, wherein the third spacer and the fourth spacer extend along a second direction different from the first direction, wherein the first spacer, the second spacer, the third spacer, and the fourth spacer define an opening; forming a capacitor contact within the opening; forming an isolation element within the opening, wherein the isolation element extends along the first direction; and forming a landing pad on the isolation element and the capacitor contact.

[0009] The embodiments disclosed herein illustrate a semiconductor device. The semiconductor device arrangement includes an isolation element above a capacitor contact. By incorporating the isolation element, the distance between the landing pad and the bit line can be increased, thereby reducing leakage. In some embodiments, a portion of the isolation element is removed to allow a larger surface area of ​​the landing pad to contact the capacitor contact, which reduces resistance and enhances the performance of the semiconductor device.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and the claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description. Figure 1A is a top view schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 1B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 1A along section line A-A', representing some embodiments of this disclosure. Figure 1C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 1A along section line B-B', representing some embodiments of this disclosure. Figure 1D is a cross-sectional schematic diagram illustrating semiconductor elements of some embodiments of this disclosure. Figure 2 is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure. Figure 3 is a three-dimensional schematic diagram illustrating the intermediate structure of a semiconductor element in some embodiments of this disclosure. Figure 3A is a cross-sectional schematic diagram illustrating one or more stages of an illustrative method for fabricating a semiconductor device according to some embodiments of the present disclosure. Figure 3B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 3A along section line A-A', representing some embodiments of this disclosure. Figure 3C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 3A along section line B-B', representing some embodiments of this disclosure. Figure 4A is a cross-sectional schematic diagram illustrating one or more stages of an illustrative method for fabricating a semiconductor device according to some embodiments of the present disclosure. Figure 4B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 4A along section line A-A', according to some embodiments of this disclosure. Figure 4C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 4A along section line B-B', representing some embodiments of this disclosure. Figure 5A is a cross-sectional schematic diagram illustrating one or more stages of an illustrative method for fabricating a semiconductor device according to some embodiments of the present disclosure. Figure 5B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 5A along section line A-A', representing some embodiments of this disclosure. Figure 5C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 5A along section line B-B', representing some embodiments of this disclosure. Figure 6A is a cross-sectional schematic diagram illustrating one or more stages of an illustrative method for fabricating a semiconductor device according to some embodiments of the present disclosure. Figure 6B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 6A along section line A-A', according to some embodiments of this disclosure. Figure 6C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 6A along section line B-B', representing some embodiments of this disclosure. Figure 7A is a cross-sectional schematic diagram illustrating one or more stages of an illustrative method for fabricating a semiconductor device according to some embodiments of this disclosure. Figure 7B is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 7A along section line A-A', according to some embodiments of this disclosure. Figure 7C is a cross-sectional schematic diagram illustrating a cross-section of a semiconductor element as shown in Figure 7A along section line B-B', representing some embodiments of this disclosure. Implementation

[0012] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplification and clarity, and unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0013] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0014] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0015] Figures 1A, 1B, 1C, and 1D are schematic cross-sectional views illustrating a semiconductor element 300 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 300 may include a cell region in which a memory element is formed. For example, the memory element may include a dynamic random access memory (DRAM) element, an one-time programmable (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, for example, DRAM may include transistors, capacitors, and other components. During a read operation, a word line may be asserted, thereby turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor through the bit line. During a write operation, when the word line is asserted, data to be written may be provided on the bit line.

[0016] Semiconductor element 300 may include a carrier 100 and an element 200 disposed above the carrier 100. The carrier 100 may include a switch (e.g., a transistor) configured to turn on or off a capacitor within the element 200.

[0017] As shown in Figure 1A, the semiconductor element 300 may include multiple word lines 110, multiple bit lines 120, multiple spacers 130, multiple spacers 138, multiple capacitor contacts 140, multiple pads 146, and multiple isolation elements 150.

[0018] As shown in Figures 1B and 1C, the carrier 100 may include a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 102 may include elemental semiconductors, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe characteristic to another ratio at another location. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 102 may have a multilayer structure, or the substrate 102 may include a multilayer compound semiconductor structure.

[0019] In some embodiments, the carrier 100 may include a plurality of active regions. For example, the active regions may be used as channels for electrical connections.

[0020] In some embodiments, the carrier 100 may include a plurality of isolation structures (not shown). In some embodiments, a plurality of active regions may be separated by such isolation structures. In some embodiments, the isolation structures may be embedded in the substrate 102. In some embodiments, for example, the isolation structures may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), or other suitable materials. In some embodiments, a portion of the substrate 102 may be removed to form a plurality of trenches, and a dielectric material may be filled into the trenches to form a plurality of isolation structures. In some embodiments, the isolation structures may include shallow trench isolation (STI).

[0021] The carrier 100 may include a dielectric layer 104. In some embodiments, the dielectric layer 104 may be disposed within the substrate 102. For example, the dielectric layer 104 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), high-k materials, or combinations thereof.

[0022] Each character line 110 may extend along the Y direction. The character line 110 may be disposed within the substrate 102. The character line 110 may be embedded within the substrate 102. The character line 110 may be disposed above or below the dielectric layer 104. The character line 110 may include a gate dielectric layer and a gate electrode (not shown). The gate dielectric layer may include silicon oxide or other suitable materials. The gate electrode may include a conductive material, such as titanium nitride, tungsten, polycrystalline silicon, or other suitable materials.

[0023] In some embodiments, the carrier 100 may include a plurality of insulating layers 106. The insulating layers 106 may be disposed on or above the substrate 102. The insulating layers 106 may separate the capacitor contacts 140 from the substrate 102. For example, the insulating layers 106 may include silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxynitride (N₂OSi₂), silicon nitride oxide (N₂OSi₂), or other suitable materials.

[0024] In some embodiments, the carrier 100 may include a plurality of dielectric layers 114. The dielectric layers 114 may be disposed on the substrate 102. The dielectric layers 114 may be configured to decouple a portion of the bit line 120 from the substrate 102. In some embodiments, for example, the dielectric layer 114 may include, for example, silicon oxide (SiO₂), silicon nitride (Si₃N₄), silicon oxynitride (N₂OSi₂), silicon nitride oxide (N₂OSi₂), a high-k material, or a combination thereof. Examples of high-k materials include a dielectric material having a dielectric constant greater than that of silicon dioxide (SiO₂), or a dielectric material with a dielectric constant greater than about 3.9. In some embodiments, the dielectric layer 114 may include at least one metal element, such as hafnium oxide (HfO 2), silicon-doped hafnium oxide (HSO), lanthanum oxide (La 2O 3), aluminum lanthanum oxide (LaAlO 3), zirconium orthosilicate (ZrSiO 4), aluminum oxide (Al 2O 3), or a combination thereof.

[0025] In some embodiments, the carrier 100 may include a plurality of bit line contacts 116. In some embodiments, the bit line contacts 116 may be disposed on the active region of the carrier 100. The bit line contacts 116 may include metals, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or any metallic material having suitable resistance and gap-filling capability.

[0026] In some embodiments, the carrier 100 may include a plurality of bit line stacks 118. In some embodiments, the bit line stacks 118 may include a multilayer structure. In some embodiments, a portion of the bit line stacks 118 may be disposed on bit line contacts 116. A portion of the bit line stacks 118 may be spaced apart from the substrate 102 by a dielectric layer 114. In some embodiments, a portion of the bit line stacks 118 may contact the bit line contacts 116. In some embodiments, a portion of the bit line stacks 118 may be electrically connected to the bit line contacts 116. In some embodiments, a portion of the bit line stacks 118 may be disposed on the dielectric layer 114. In some embodiments, a portion of the bit line stacks 118 may contact the dielectric layer 114. The bit line stacks 118 may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), copper (Cu), tantalum nitride (TaN), manganese nitride (MnN), or combinations thereof.

[0027] As shown in Figure 1A, each bit line 120 may extend along the X direction. As shown in Figure 1B, each bit line 120 may be disposed on the bit line stack 118. In some embodiments, a portion of the bit line 120 may be disposed on the bit line contact 116. In some embodiments, a portion of the bit line 120 may be electrically connected to the bit line contact 116. In some embodiments, a portion of the bit line 120 may be disposed on the dielectric layer 114. The bit line 120 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or combinations thereof.

[0028] In some embodiments, the carrier 100 may include a plurality of dielectric layers 122. In some embodiments, each dielectric layer 122 may be disposed on a bit line 120. In some embodiments, for example, the dielectric layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high-k materials, or combinations thereof.

[0029] As shown in Figure 1A, each spacer 130 can extend along the X direction. The spacer 130 can be disposed on the opposite side (or sidewall) of the bit line 120. The spacer 130 can include a multilayer structure. For example, the spacer 130 can have dielectric layers 132, 134, and 136.

[0030] In some embodiments, dielectric layer 132 may be formed on the bit line contact 116, bit line stack 118, bit line 120, and each sidewall of dielectric layer 122. In some embodiments, a portion of dielectric layer 132 may be embedded in substrate 102. In some embodiments, for example, dielectric layer 132 may include silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, high-k materials, or combinations thereof.

[0031] In some embodiments, dielectric layer 134 may be spaced apart from bit line 120 by dielectric layer 132. Dielectric layer 134 may be disposed between dielectric layers 132 and 136. In some embodiments, for example, dielectric layer 134 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high-k material, or a combination thereof. Dielectric layer 134 may include a material different from the material of dielectric layer 132.

[0032] In some embodiments, dielectric layer 136 may be spaced apart from dielectric layer 132 by dielectric layer 134. In some embodiments, for example, dielectric layer 136 may include silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, a high-k material, or a combination thereof. Dielectric layer 136 may include a material different from that of dielectric layer 132. For example, dielectric layers 132 and 136 may include silicon nitride, and dielectric layer 134 may include silicon oxide. In some embodiments, dielectric layer 134 may be replaced by an air gap.

[0033] In some embodiments, the dielectric layer 136 may have a rounded corner, such that the upper surface of the dielectric layer 136 may be tapered.

[0034] As shown in FIG1A, in some embodiments, each spacer 138 may extend along the Y direction. As shown in FIG1C, the spacer 138 may be disposed on or directly above the character line 110. The spacer 138 may cover a portion of the spacer 130. In some embodiments, for example, the spacer 138 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, high-k materials, or combinations thereof.

[0035] In some embodiments, from a top view, spacers 130 and 138 may define a plurality of openings O1. The openings O1 may have a rectangular profile, a circular profile, an elliptical profile, an oval profile, or other suitable profile.

[0036] In some embodiments, capacitor contacts 140 may be disposed within opening O1. In some embodiments, capacitor contacts 140 may be formed between two bit lines 120. In some embodiments, capacitor contacts 140 may be formed between spacers 130. Capacitor contacts 140 may comprise metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or any metallic material.

[0037] In some embodiments, the carrier 100 may include a plurality of conductive stacked structures 142. In some embodiments, the conductive stacked structures 142 may be disposed within the opening O1. In some embodiments, the conductive stacked structures 142 may be disposed above or above the capacitor contact 140. The conductive stacked structures 142 may include a multilayer structure. The conductive stacked structures 142 may be disposed between spacers 130 (or spacers 138). In some embodiments, the conductive stacked structures 142 may include a metal silicide, such as cobalt silicide (CoSi) or other suitable materials.

[0038] In some embodiments, a pad (or landing pad) 146 may be disposed within an opening O1. Each pad 146 may be configured to electrically connect to a capacitor assembly (as shown in FIG. 1D). In some embodiments, a pad 146 may be formed between spacers 130. In some embodiments, a pad 146 may be formed between spacers 138. In some embodiments, a pad 146 may cover an upper surface of a conductive stack structure 142. In some embodiments, a pad 146 may comprise a metal, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), silver (Ag), gold (Au), alloys thereof, or combinations thereof.

[0039] In some embodiments, the carrier 100 may include a plurality of isolation elements 150. In some embodiments, the isolation elements 150 may be disposed within an opening O1. In some embodiments, each opening O1 may be configured to receive two separate isolation elements 150-1 and 150-2. In some embodiments, each isolation element 150 (e.g., isolation elements 150-1 and 150-2) may extend along the X direction, as shown in FIG1A. In some embodiments, the isolation elements 150 may be disposed on a surface 130s1 (or side surface) of the spacer 130. For example, the isolation element 150 may be disposed on a sidewall of the dielectric layer 136. The isolation elements 150 may extend continuously between the spacers 138. In some embodiments, the isolation element 150 may include silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the material of the isolation element 150 may be the same as or similar to the material of the spacer 130.

[0040] As shown in FIG1A, the spacer 138 may have a surface (or side) 138s1 facing the pad 146. In some embodiments, from a top view, a portion 138p1 of the surface 138s1 of the spacer 138 may be exposed by the insulating element 150. In some embodiments, from a top view, a portion 138p2 of the surface 138s1 of the spacer 138 may be covered by the insulating element 150. The pad 146 may have a length T1 along the X direction. The insulating element 150 may have a length T2 along the X direction. In some embodiments, the length T1 may be substantially equal to the length T2.

[0041] As shown in FIG1B, the isolation element 150 may be disposed above or above the capacitor contact 140. In some embodiments, isolation elements 150-1 and 150-2 may be disposed on two sidewalls (or side surfaces) of a portion 146p2 of the pad 146. In some embodiments, isolation elements 150-1 and 150-2 may be disposed on two sidewalls (or side surfaces) of the conductive stack structure 142. In some embodiments, isolation element 150-1 may be spaced apart from isolation element 150-2 by means of the conductive stack structure 142. In some embodiments, isolation element 150-1 may be spaced apart from isolation element 150-2 by means of a portion 146p2 of the pad 146.

[0042] The insulating element 150 may have a surface 150s1 (or lower surface) adjacent to the capacitor contact 140, a surface 150s2 (or upper surface) opposite to the surface 150s1, and a surface 150s3 (or side surface) extending between the surfaces 150s1 and 150s2. In some embodiments, a pad 146 may cover or contact the surface 150s2 of the insulating element 150. In some embodiments, a portion 146p1 of the pad 146 may cover the surface 150s2 of the insulating element 150. In some embodiments, the pad 146 may cover or contact the surface 150s3. In some embodiments, a portion 146p2 of the pad 146 may cover or contact the surface 150s3. In some embodiments, a conductive stack structure 142 may cover or contact the surface 150s3. The portion 146p1 of the pad 146 may have a length T3 along the Y direction. The portion 146p2 of the pad 146 may have a length T4 along the Y direction. In some embodiments, the length T4 may be less than the length T3.

[0043] As shown in Figures 1A and 1B, a surface 146s1 (or side surface) of the pad 146 may contact the insulating element 150. As shown in Figures 1A and 1C, a surface 146s2 (or side surface) of the pad 146 may contact the spacer 138. The surface 146s1 extending along the X direction may be adjacent to the surface 146s2 extending along the Y direction. As shown in Figure 1B, the pad 146 may have a portion (e.g., an upper portion) 146p1 located above the insulating element 150 and a portion (e.g., a lower portion or a neck) 146p2 surrounded by the insulating elements 150 (e.g., insulating elements 150-1 and 150-2).

[0044] As shown in Figure 1B, a distance D1 between the surface 150s2 of the isolation element 150 and the substrate 102 may be different from a distance D2 between the surface 130s2 (or upper surface) of the spacer 130 and the lower surface (or back surface) of the substrate 102. For example, distance D1 may be less than the distance between the upper surface of the dielectric layer 136 and the lower surface (or back surface) of the substrate 102. In some embodiments, distance D2 may be greater than distance D1. In some embodiments, a distance D3 between the surface 150s1 of the isolation element 150 and the lower surface (or back surface) of the substrate 102 may be different from a distance D4 between the surface 130s3 (or lower surface) of the spacer 130 and the surface 130s3 (or lower surface) of the substrate 102. In some embodiments, distance D3 may be greater than distance D4. For example, distance D3 may be greater than the distance between the lower surface of the dielectric layer 136 and the lower surface (or back surface) of the substrate 102. In some embodiments, the surface 130s2 of the spacer 130 may be misaligned or non-coplanar with the surface 150s2 of the isolation element 150. For example, the upper surfaces of the dielectric layer 136 and the substrate 102 may be misaligned or non-coplanar with the surface 150s2 of the isolation element 150.

[0045] In this embodiment, the isolation element 150 can be configured to increase the distance between the pad 146 and the bit line 120 (e.g., the distance along the Y direction), thereby preventing leakage between the pad 146 and the bit line 120. Furthermore, the isolation element 150 exposes a portion of the spacer 138. For example, a portion 138p1 of the surface 138s1 of the space 138 can be exposed by the isolation element 150. As a result, the interface between the pad 146 and the capacitor contact 140 can be larger than a comparative example where the isolation element 150 is formed on the portion 138p1 of the surface 138s1 of the space 138, thereby reducing resistance.

[0046] Figure 1D illustrates in detail an element 200 according to some embodiments of the present disclosure. In some embodiments, a semiconductor element 300 may include an element 200. The element 200 may be disposed on or above a pad 146. The element 200 may include a capacitor assembly electrically connected to the pad 146. The transistor shown in Figure 1D may be configured to turn on or off the capacitor assembly within the element 200.

[0047] Component 200 may be disposed above carrier 100 to cover pad 146. In some embodiments, component 200 may include a support layer 202, a support layer 204 and a support layer 206, which are located at different heights and configured to support capacitor assembly 210.

[0048] In some embodiments, a support layer 202 (or a lower support layer) may be disposed on or above the passivation layer 148. In some embodiments, the support layer 202 may cover a portion of the pad 146. In some embodiments, the support layer 202 may contact the pad 146. In some embodiments, the support layer 202 may be configured to support the capacitor assembly 210. The support layer 202 may be used to define a pattern of the capacitor assembly 210. In some embodiments, the support layer 202 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0049] In some embodiments, a support layer 204 (or an intermediate support layer) may be disposed above or on top of the support layer 202. In some embodiments, the support layer 204 may be spaced apart from the support layer 202. In some embodiments, the support layer 204 may be configured to support the capacitor assembly 210. The support layer 204 may be used to define a pattern of the capacitor assembly 210. In some embodiments, the support layer 204 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0050] In some embodiments, a support layer 206 (or an upper support layer) may be disposed above or on top of a support layer 204. In some embodiments, the support layer 206 may be spaced apart from the support layer 204. In some embodiments, the support layer 206 may be configured to support a capacitor assembly 210. The support layer 206 may be used to define a pattern of the capacitor assembly 210. In some embodiments, the support layer 206 may include silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, or other suitable materials.

[0051] Capacitor assembly 210 may be disposed on or above carrier 100. In some embodiments, capacitor assembly 210 may be electrically connected to pad 146. In some embodiments, capacitor assembly 210 may be supported by and in contact with support layers 202, 204, and 206. In some embodiments, capacitor assembly 210 may include a lower electrode 212, a capacitor dielectric 214, and an upper electrode 216.

[0052] In some embodiments, the lower electrode 212 (or the first electrode) may be disposed on the carrier 100. In some embodiments, the lower electrode 212 may be disposed on and electrically connected to the pad 146. In some embodiments, the lower electrode 212 may be disposed within an opening defined by the support layer 202, support layer 204, and support layer 206. In some embodiments, the lower electrode 212 may be disposed on or in contact with the side surface of the support layer 202. In some embodiments, the lower electrode 212 may be disposed on or in contact with the side surface of the support layer 204. In some embodiments, the lower electrode 212 may be disposed on or in contact with the side surface of the support layer 206. The lower electrode 212 may include a conductive material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like), a metal (e.g., copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, or the like), and a conductive metal oxide (e.g., iridium oxide or the like).

[0053] The lower electrode 212 may have a surface 212s1 (or a lower surface) adjacent to the carrier 100 and a surface 212s2 (or an upper surface) opposite to the surface 210s1. In some embodiments, the thickness L1 (or length or depth) of the lower electrode 212-1 may be different from the thickness L2 (or length or depth) of the lower electrode 212-2.

[0054] The capacitor dielectric 214 may be conformally disposed on the lower electrode 212. In some embodiments, the capacitor dielectric 214 may be disposed on or in contact with the upper surface of the support layer 202. In some embodiments, the capacitor dielectric 214 may be disposed on or in contact with the upper surfaces of the support layers 204 and 206. In some embodiments, the capacitor dielectric 214 may be disposed on or in contact with the lower surfaces of the support layers 204 and 206. In some embodiments, the capacitor dielectric 214 may be disposed on or in contact with the side surfaces of the support layers 204 and 206. The capacitor dielectric 214 may include silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like.

[0055] In some embodiments, the upper electrode 216 (or the second electrode) may be disposed on the capacitor dielectric 214. The upper electrode 216 may be spaced apart from the lower electrode 212 by the capacitor dielectric 214. The upper electrode 216 may include a conductive material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, or the like), a metal (e.g., copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, or the like), and a conductive metal oxide (e.g., iridium oxide or the like). In some embodiments, from a top view, each of the support layer 202, support layer 204, and support layer 206 may define an annular profile to accommodate the capacitor assembly 210.

[0056] In some embodiments, element 200 further includes a ground electrode 220. In some embodiments, ground electrode 220 may be electrically connected to ground. In some embodiments, ground electrode 220 may be electrically connected to capacitor assembly 210. In some embodiments, ground electrode 220 may be electrically connected to and in contact with upper electrode 216. In some embodiments, ground electrode 220 may include doped polycrystalline silicon or other suitable materials.

[0057] Figure 2 is a flowchart illustrating a method 400 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0058] Fabrication method 400 may begin at step 402, wherein a substrate is provided. The substrate has a plurality of active regions defined by an isolation structure (STI structure). A plurality of word lines are formed within the substrate. A plurality of bit lines are formed above the substrate. A plurality of first spacers are formed on opposite sides of the bit lines. A plurality of second spacers are formed directly above the word lines. The bit lines extend along a first direction. The first spacers extend along the first direction. The word lines extend along a second direction substantially orthogonal to the first direction. The second spacers extend along the second direction. The first spacers and the second spacers define a plurality of openings. A plurality of capacitor contacts are formed within the openings.

[0059] The fabrication method 400 may proceed to step 404, wherein a dielectric layer is conformally formed on or above the capacitor contact, the first spacers, and the second spacers. The dielectric layer is conformally formed within the openings defined by the first spacers and the second spacers.

[0060] The fabrication method 400 may continue to perform step 406, wherein a first portion of the dielectric layer located above each of the upper surfaces of the first spacers and each of the upper surfaces of the second spacers is removed. The remaining portion of the dielectric layer is located within the opening. Each of the upper surfaces of the first spacers and the second spacers is exposed.

[0061] The fabrication method 400 may proceed to step 408, in which a second portion of the dielectric layer is removed to expose the upper surface of the capacitor contact and the side surfaces of the second spacers. The remaining dielectric layer is formed on the sidewalls of the first spacers and extends along the first direction. As a result, a plurality of isolation elements are produced.

[0062] The preparation method 400 may continue to perform step 410, wherein a plurality of landing pads are formed within the openings. The landing pads are formed on the isolation elements and the capacitor contacts. The landing pads are spaced apart from the bit lines by the first spacer and the isolation elements.

[0063] Preparation method 400 is merely an example and is not intended to limit this disclosure to the content expressly described in the claims. Additional steps may be provided before, during, or after each step of preparation method 400, and some described steps may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 400 may include other steps not depicted in FIG2. In some embodiments, preparation method 400 may include one or more steps depicted in FIG2.

[0064] Figure 3 is a three-dimensional schematic diagram of the intermediate structure of a semiconductor device. Figure 3A is a top view of Figure 3, and Figures 3B and 3C are cross-sectional views of Figure 3A. Figures 4A to 4C, 5A to 5C, 6A to 6C, and 7A to 7C respectively illustrate the structure after the stages shown in Figures 3A to 3C.

[0065] Referring to Figures 3, 3A, 3B, and 3C, a substrate 102 is provided. In some embodiments, the substrate 102 may include a plurality of active regions. A dielectric layer 114 may be formed on the substrate 102. In some embodiments, the fabrication techniques for the dielectric layer 114 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), and flowable chemical vapor deposition (FCVD).

[0066] Multiple word lines 110 may be formed within the substrate 102. In some embodiments, multiple trenches may be formed, and a gate dielectric material and a gate electrode material may be formed within the trenches to generate the word lines 110. For example, the fabrication techniques for each of the gate dielectric material and the gate electrode material may include CVD, ALD, FCVD, PVD, LPCVD, or other suitable processes.

[0067] In some embodiments, a portion of the substrate 102 may be removed to form an opening. In some embodiments, a conductive material may be filled into the trenches to create bit line contacts 116. In some embodiments, the fabrication techniques for the bit line contacts 116 may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes. Furthermore, a chemical polishing process may be performed to planarize the upper surfaces of the bit line contacts 116 and the dielectric layer 114.

[0068] In some embodiments, bit line stack 118, bit line 120, and dielectric layer 122 may be formed over substrate 102 and dielectric layer 114. Bit line stack 118, bit line 120, and dielectric layer 122 may be patterned to extend along the X direction. The fabrication techniques for each of bit line stack 118, bit line 120, and dielectric layer 122 may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0069] A portion of substrate 102 can be removed. A portion of dielectric layer 114 can be removed. Spacers 130 can be formed on the sidewalls (or side surfaces) of bit line stack 118, bit line 120, and dielectric layer 122, as well as over substrate 102 and dielectric layer 114. The fabrication techniques for each of dielectric layers 132, 134, and 136 can include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0070] A dielectric material can be formed on dielectric layers 122 and 104, and then patterned to form spacers 138 extending along the Y direction. Spacers 138 may cover spacers 130. For example, the fabrication techniques of spacers 138 may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0071] In some embodiments, spacers 138 and 130 may define a plurality of openings O1. Capacitor contacts 140 may be formed within the openings O1. For example, the fabrication techniques for capacitor contacts 140 may include CVD, ALD, PVD, FCVD, LPCVD, or other suitable processes.

[0072] Referring to Figures 4A, 4B, and 4C, a dielectric layer 150' can be conformally formed on surface 130s1 of spacer 130, surface 130s2 of spacer 130, upper surface of capacitor contact 140, surface 138s1 of spacer 138, and surface 138s2 (or an upper surface) of spacer 138. For example, the fabrication techniques for dielectric layer 150' may include ALD, CVD, PVD, FCVD, LPCVD, or other suitable processes.

[0073] Referring to Figures 5A, 5B, and 5C, a portion 150p1 as shown in Figures 4B and 4C can be removed. The portion 150p1 can be located above the surface 130s2 of the spacer 130. The portion 150p1 can partially cover the surface 130s1 of the spacer 130. The portion 150p1 can be located above the surface 138s2 of the spacer 138. The portion 150p1 can partially cover the surface 138s1 of the spacer 138. As a result, the surface 150s2 of the isolation element 150, located at a height (or plane) relative to the substrate 102, can be lower than the height (or plane) of the surface 130s2 of the spacer 130. The portion 150p1 of the isolation element 150 can be removed by an etching technique, such as dry etching or other suitable techniques.

[0074] Referring to Figures 6A, 6B, and 6C, as shown in Figures 5A, 5B, and 5C, a portion 150p2 of the isolation element 150 can be removed. The portion 150p2 can be disposed on the surface 138s1 of the spacer 138 and on the upper surface of the capacitor contact 140. A portion of the surface 138s1 of the spacer 138 can be exposed by the isolation element 150. The capacitor contact 140 can be exposed by the isolation element 150. The portion 150p2 of the isolation element 150 can be removed by an etching technique, such as dry etching or other suitable techniques.

[0075] Referring to Figures 7A, 7B, and 7C, a pad 146 can be formed on a plurality of openings O1. The pad 146 can cover the insulating element 150. The pad 146 can be electrically connected to the capacitor contact 140. As a result, a carrier 100 can be produced. For example, the fabrication techniques of the pad 146 can include ALD, CVD, PVD, FCVD, LPCVD, or other suitable processes. An element 200 can be formed on or over the carrier 100 to produce a semiconductor element 300.

[0076] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first spacer, a second spacer, a third spacer, a fourth spacer, a capacitor contact, an isolation element, and a landing pad. The first and second spacers are located above the substrate and extend along a first direction. The third and fourth spacers are located above the substrate and extend along a second direction different from the first direction. The capacitor contact is surrounded by the first, second, third, and fourth spacers. The isolation element is disposed on the capacitor contact. The isolation element extends along the first direction. The landing pad is disposed on the isolation element and electrically connected to the capacitor contact.

[0077] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first spacer, a second spacer, a capacitor contact, an isolation element, and a landing pad. The first spacer and the second spacer are located above the substrate and extend along a first direction. The capacitor contact is disposed between the first spacer and the second spacer. The isolation element is disposed on the capacitor contact. The landing pad includes a neck defined by the isolation element.

[0078] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a first spacer and a second spacer extending along a first direction over the substrate; forming a third spacer and a fourth spacer over the substrate, wherein the third spacer and the fourth spacer extend along a second direction different from the first direction, wherein the first spacer, the second spacer, the third spacer, and the fourth spacer define an opening; forming a capacitor contact within the opening; forming an isolation element within the opening, wherein the isolation element extends along the first direction; and forming a landing pad on the isolation element and the capacitor contact.

[0079] The embodiments disclosed herein illustrate a semiconductor device. The semiconductor device arrangement includes an isolation element above a capacitor contact. By incorporating the isolation element, the distance between the landing pad and the bit line can be increased, thereby reducing leakage. In some embodiments, a portion of the isolation element is removed to allow a larger surface area of ​​the landing pad to contact the capacitor contact, which reduces resistance and enhances the performance of the semiconductor device.

[0080] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0081] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0082] 100: Carrier 102: Base 104: Dielectric layer 106: Isolation layer 110: Character Line 114: Dielectric layer 116: Bit line contact 118: Bit line stacking 120: Bit line 122: Dielectric layer 130: Gap element 130s1: Surface 130s2: Surface 130s3: Surface 132: Dielectric layer 134: Dielectric layer 136: Dielectric layer 138: Gap element 138p1: Part 138p2: Part 138s1: Surface 138s2: Surface 140: Capacitor contacts 142: Conductive stacked structure 146: Cushion 146p1: Part 146p2: Part 146s1: Surface 146s2: Surface 148: Passivation layer 150: Isolation element 150': Dielectric layer 150-1: Isolation element 150-2: Isolation element 150p1: Partial 150p2: Partial 150s1: Surface 150s2: Surface 150s3: Surface 200: Components 202: Support layer 204: Support layer 206: Support layer 210: Capacitor Assembly 210s1: Surface 212: Lower electrode 212-1: Lower electrode 212-2: Lower electrode 212s1: Surface 212s2: Surface 214: Capacitor dielectric 216: Upper electrode 220: Grounding electrode 300: Semiconductor Components 400: Preparation method 402~410: Steps D1: Distance D2: Distance D3: Distance D4: Distance L1: Thickness L2: Thickness O1: Opening T1: Length T2: Length T3: Length T4: Length X: Direction Y: direction Z: Direction

Claims

1. A semiconductor device, comprising: One base; A first spacer and a second spacer are located above the substrate and extend along a first direction; A third spacer and a fourth spacer are located above the substrate and extend along a second direction different from the first direction; a capacitor contact is surrounded by the first spacer, the second spacer, the third spacer, and the fourth spacer; an isolation element is disposed on the capacitor contact, wherein the isolation element extends along the first direction; and a landing pad is disposed on the isolation element and electrically connected to the capacitor contact; wherein a first distance between an upper surface of the first spacer and the substrate is different from a second distance between an upper surface of the isolation element and the substrate; wherein, in the top view, a portion of a side of the third spacer is exposed by the isolation element, and the landing pad includes a neck surrounded by the isolation element and electrically connected to the capacitor contact.

2. The semiconductor element as claimed in claim 1 further includes a bit line extending along the first direction and disposed between the third spacer and the fourth spacer.

3. The semiconductor element as claimed in claim 2, wherein the bit line is spaced apart from the isolation element.

4. The semiconductor element as described in claim 1, wherein the first distance is greater than the second distance.

5. The semiconductor element as claimed in claim 1, wherein the landing pad covers the upper surface of the isolation element.

6. The semiconductor element as claimed in claim 1, wherein the landing pad has a first side facing the first spacer, and the first side of the landing pad is spaced apart from the first spacer by the insulating element.

7. The semiconductor element as claimed in claim 6, wherein the landing pad has a second side abutting the first side and facing the third spacer, and the second side is in contact with the third spacer.

8. The semiconductor device as claimed in claim 1, wherein the isolation element comprises silicon nitride, silicon oxynitride, or a combination thereof.

9. The semiconductor element as claimed in claim 1, wherein a third distance between a lower surface of the first spacer and the substrate is different from a fourth distance between a lower surface of the isolation element and the substrate.

10. The semiconductor element as claimed in claim 9, wherein the third distance is less than the fourth distance.

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