Semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device that is easily scalable. The semiconductor memory device of the embodiment includes: a plurality of conductive layers stacked along a stacking direction; a semiconductor pillar extending along the stacking direction and facing the plurality of conductive layers; a charge storage film disposed between the plurality of conductive layers and the semiconductor pillar; a bit line disposed on one side of the stacking direction relative to the plurality of conductive layers and connected to the semiconductor pillar; and a contact electrode extending along the stacking direction and connected to a bit line side surface of one of the plurality of conductive layers. The semiconductor pillar includes a plurality of first portions arranged along the stacking direction, the width of the bit line side end in the stacking direction being larger than the width of the end opposite to the bit line in the stacking direction of the plurality of first portions. The contact electrode includes a plurality of second portions arranged along the stacking direction, the width of the bit line side end in the stacking direction being larger than the width of the end opposite to the bit line in the stacking direction of the plurality of second portions. The number of the plurality of second portions included in the contact electrode is greater than the number of the plurality of first portions included in the semiconductor pillar.

Description

Technical Field

[0001] [References to related applications] This application enjoys priority to Japanese Patent Application No. 2024-160650 (filed on September 18, 2024). This application incorporates the entire contents of the basic application by reference to that basic application.

[0002] This embodiment relates to a semiconductor memory device. Prior Technology

[0003] A known semiconductor memory device includes: a plurality of conductive layers stacked along a stacking direction; semiconductor pillars facing the plurality of conductive layers; and a charge storage film disposed between the conductive layers and the semiconductor pillars. The charge storage film may be, for example, an insulating charge storage film such as silicon nitride (Si3N4), or a conductive charge storage film such as a floating gate. The charge storage film includes a memory portion capable of storing data. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device that is easy to achieve high integration.

[0005] The semiconductor memory device of the embodiment includes: a plurality of conductive layers stacked along a stacking direction; a semiconductor pillar extending along the stacking direction and facing the plurality of conductive layers; a charge storage film disposed between the plurality of conductive layers and the semiconductor pillar; a bit line disposed on one side of the stacking direction relative to the plurality of conductive layers and electrically connected to the semiconductor pillar; and a contact electrode extending along the stacking direction and connected to the bit line side surface of one of the plurality of conductive layers. The semiconductor pillar includes a plurality of first portions arranged along the stacking direction, the width of the bit line side end in the stacking direction being larger than the width of the end opposite to the bit line in the stacking direction of the plurality of first portions in the stacking direction intersecting the stacking direction. The contact electrode includes a plurality of second portions arranged along the stacking direction, the width of the bit line side end in the stacking direction being larger than the width of the end opposite to the bit line in the stacking direction of the plurality of second portions in the stacking direction in the stacking direction. The number of the plurality of second portions included in the contact electrode is greater than the number of the plurality of first portions included in the semiconductor pillar. Simple Explanation of the Diagram

[0006] Figure 1 is a schematic plan view of the memory die MD according to the embodiment. Figure 2 is a schematic enlarged view of parts A and B in Figure 1. Figure 3 is a schematic enlarged view of part C shown in Figure 2. Figure 4 is a schematic cross-sectional view of the structure shown in Figure 3 cut along line D-D' and viewed in the direction of the arrow. Figure 5 is a schematic enlarged view of the part shown in E of Figure 4. Figure 6 is a schematic cross-sectional view of the structure shown in Figure 2 cut along line F-F' and viewed in the direction of the arrow. Figure 7 is a schematic cross-sectional view of the structure shown in Figure 2 cut along line G-G' and viewed in the direction of the arrow. Figure 8 is a schematic cross-sectional view of a portion of Figure 6, enlarged from the original. Figure 9 is a schematic cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to an embodiment. Figure 10 is a schematic cross-sectional view illustrating the manufacturing method. Figure 11 is a schematic plan view illustrating the manufacturing method. Figure 12 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 13 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 14 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 15 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 16 is a schematic plan view illustrating the manufacturing method. Figure 17 is a schematic cross-sectional view illustrating the manufacturing method. Figure 18 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 19 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 20 is a schematic cross-sectional view illustrating the manufacturing method. Figure 21 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 22 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 23 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 24 is a schematic plan view illustrating the manufacturing method. Figure 25 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 26 is a schematic cross-sectional view illustrating the manufacturing method. Figure 27 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 28 is a schematic cross-sectional view illustrating the manufacturing method. Figure 29 is a schematic plan view illustrating the manufacturing method. Figure 30 is a schematic cross-sectional view illustrating the manufacturing method. Figure 31 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 32 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 33 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 34 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 35 is a schematic cross-sectional view illustrating the manufacturing method. Figure 36 is a schematic cross-sectional view illustrating the manufacturing method. Figure 37 is a schematic plan view illustrating the manufacturing method. Figure 38 is a schematic cross-sectional view illustrating the manufacturing method. Figure 39 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 40 is a schematic cross-sectional view illustrating the manufacturing method. Figure 41 is a schematic cross-sectional view for illustrating the manufacturing method. Figure 42 is a schematic plan view of a comparative example semiconductor memory device. Figure 43 is a schematic cross-sectional view of the structure shown in Figure 42 cut along line H-H' and viewed in the direction of the arrow. Figure 44 is a schematic cross-sectional view of the structure shown in Figure 42 cut along line I-I' and viewed in the direction of the arrow. Figure 45 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device of the comparative example. Figure 46 is a schematic cross-sectional view illustrating the manufacturing method of a semiconductor memory device for a comparative example. Figure 47 is a schematic cross-sectional view of a semiconductor memory device according to other embodiments. Implementation

[0007] Secondly, the semiconductor memory device of the embodiments will be described in detail with reference to the drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and sometimes parts of the structure are omitted for ease of explanation. Also, sometimes common parts in multiple embodiments are labeled with the same symbols and their descriptions are omitted.

[0008] Furthermore, in this specification, when referring to "semiconductor memory device," it sometimes refers to a memory die, and sometimes to a memory system including a controller die, such as a memory chip, memory card, or solid-state drive (SSD). Moreover, it sometimes refers to the structure of a smartphone, tablet, personal computer, or host computer.

[0009] Furthermore, in this specification, when it is mentioned that the first structure is "electrically connected" to the second structure, the first structure can be directly connected to the second structure, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] In addition, in this specification, when it is said that the first structure is "connected between the second structure and the third structure", it sometimes means that the first structure, the second structure and the third structure are connected in series, and the second structure is connected to the third structure through the first structure.

[0011] In addition, in this specification, the specified direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0012] In addition, in this specification, the direction intersecting the surface of the substrate is sometimes referred to as the lamination direction. Furthermore, the direction along a predetermined surface intersecting the lamination direction is sometimes referred to as the first direction, and the direction along the predetermined surface intersecting the first direction is sometimes referred to as the second direction. The lamination direction may or may not be the same as the Z-direction. Furthermore, the first and second directions may correspond to either the X-direction or the Y-direction, or they may not correspond.

[0013] Furthermore, in this specification, the terms "upper" or "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Also, regarding a certain structure, when referring to a lower surface or lower end, it refers to the surface or end of the structure on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of the structure on the side opposite to the substrate. Additionally, the surface intersecting the X or Y direction is called a side surface, etc.

[0014] In addition, in this specification, when referring to structures, components, etc., the terms "width", "length" or "thickness" in a specified direction are sometimes used to refer to the width, length or thickness of a cross-section observed by scanning electron microscopy (SEM) or transmission electron microscopy (TEM).

[0015] [Implementation Method] [structure] Figure 1 is a schematic plan view of a memory die (MD). Figure 2 is a schematic enlarged view of portions A and B in Figure 1. Figure 3 is a schematic enlarged view of portion C in Figure 2. Figure 4 is a schematic cross-sectional view of the structure shown in Figure 3 cut along line D-D' and viewed in the direction of the arrow. Figure 5 is a schematic enlarged view of portion E in Figure 4. Figure 6 is a schematic cross-sectional view of the structure shown in Figure 2 cut along line F-F' and viewed in the direction of the arrow. Figure 7 is a schematic cross-sectional view of the structure shown in Figure 2 cut along line G-G' and viewed in the direction of the arrow. Figure 8 is an enlarged schematic cross-sectional view of a portion of Figure 6.

[0016] For example, as shown in FIG1, the memory chip MD includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate including P-type silicon (Si) containing P-type impurities such as boron (B). An N-type well region containing N-type impurities such as phosphorus (P), a P-type well region containing P-type impurities such as boron (B), a semiconductor substrate region without N-type well regions and P-type well regions, and an insulating region are provided on the surface of the semiconductor substrate 100.

[0017] In addition, the memory die MD includes four memory cell array regions RMCA arranged along the X and Y directions. The memory cell array regions RMCA include two memory via regions RMH arranged along the X direction, and wiring regions RHU disposed between these memory via regions RMH.

[0018] In the memory cell array region RMCA, multiple memory blocks BLK are arranged along the Y direction. For example, as shown in Figure 2, the memory block BLK includes multiple string cells SU arranged along the Y direction. Between two adjacent memory blocks BLK in the Y direction, an inter-block insulating layer ST such as silicon oxide (SiO2) is provided. For example, as shown in Figure 3, an inter-string insulating layer SHE such as silicon oxide (SiO2) is provided between two adjacent string cells SU in the Y direction.

[0019] The memory block BLK includes multiple (two in the illustrated example) layer structures MT1 and MT2 arranged along the Z-direction. Layer structure MT1 includes multiple (two in the illustrated example) segment structures HT11 and HT12 arranged along the Z-direction. Similarly, layer structure MT2 includes multiple (two in the illustrated example) segment structures HT21 and HT22 arranged along the Z-direction. The multiple segment structures HT11, HT12, HT21, and HT22 in the memory block BLK each include multiple conductive layers 110 and multiple insulating layers 101 such as silicon oxide (SiO2) arranged alternately along the Z-direction. Furthermore, insulating layers 105 such as silicon oxide (SiO2) are respectively provided between the multiple segment structures HT11, HT12, HT21, and HT22 in the memory block BLK. Additionally, an insulating layer 107 such as silicon oxide (SiO2) is provided above the uppermost segment structure HT22. The thickness of insulating layer 105 in the Z direction is greater than the thickness of insulating layer 101 in the Z direction. In addition, the thickness of insulating layer 107 in the Z direction is greater than the thickness of insulating layer 105 in the Z direction.

[0020] In addition, the memory hole region RMH of the memory block BLK includes: a plurality of semiconductor pillars 120 extending along the Z direction across a plurality of partition structures HT11, HT12, HT21, HT22; and a plurality of gate insulating films 130 respectively disposed between a plurality of conductive layers 110 and a plurality of semiconductor pillars 120.

[0021] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction. The conductive layer 110 may also comprise a barrier conductive film such as titanium nitride (TiN) or a laminated film of a metal film such as tungsten (W). Additionally, the conductive layer 110 may also comprise, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 110 functions as the gate electrode and word line of a memory cell, or the gate electrode and select gate line of a select transistor.

[0022] A semiconductor layer 112 is disposed below the conductive layer 110. The semiconductor layer 112 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Furthermore, an insulating layer 101, such as silicon oxide (SiO2), is disposed between the semiconductor layer 112 and the conductive layer 110. The semiconductor layer 112 functions as part of the source line. An insulating layer 106, such as silicon oxide (SiO2), is disposed below the semiconductor layer 112.

[0023] For example, as shown in FIG3, the semiconductor pillars 120 are arranged in a predetermined pattern along the X and Y directions. The semiconductor pillars 120 function as channel regions for multiple memory cells and select transistors. The semiconductor pillars 120 are, for example, semiconductor layers such as polycrystalline silicon (Si). For example, as shown in FIG4, the semiconductor pillars 120 have a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion. In addition, the outer peripheral surfaces of the semiconductor pillars 120 are surrounded by conductive layers 110 and face each other.

[0024] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor pillar 120. In the example of FIG4, the lower end of the impurity region 121 is indicated by a dashed line. The impurity region 121 is connected to the bit line BL via contact electrode Ch and contact electrode Vy (FIG. 3).

[0025] An impurity region 122 containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor pillar 120. In the example of FIG4, the upper end of the impurity region 122 is indicated by a dashed line. The impurity region 122 is connected to the semiconductor layer 112.

[0026] Furthermore, in this embodiment, the semiconductor pillar 120 includes two portions 123 arranged along the Z direction corresponding to the hierarchical structures MT1 and MT2, respectively. The portion of the two portions 123 corresponding to the hierarchical structure MT1 is positioned from a height position corresponding to the lower surface of the lowest conductive layer 110 included in the hierarchical structure MT1 to a height position corresponding to the upper surface of the highest conductive layer 110 included in the hierarchical structure MT1. Similarly, the portion of the two portions 123 corresponding to the hierarchical structure MT2 is positioned from a height position corresponding to the lower surface of the lowest conductive layer 110 included in the hierarchical structure MT2 to a height position corresponding to the upper surface of the highest conductive layer 110 included in the hierarchical structure MT2. The width (diameter when viewed from the Z direction) of these portions 123 in the X and Y directions increases from the lower end to a predetermined height position and decreases from the height position to the upper end. The width (diameter) of the upper end of these portions 123 is greater than the width (diameter) of the lower end of these portions 123.

[0027] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. For example, as shown in FIG5, the gate insulating film 130 includes a tunneling insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor pillar 120 and the conductive layer 110. The tunneling insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunneling insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the semiconductor pillar 120 and the semiconductor layer 112.

[0028] Furthermore, Figure 5 shows an example of a charge storage film 132 comprising silicon nitride or the like as the gate insulating film 130. However, the gate insulating film 130 may also include, for example, a floating gate comprising polycrystalline silicon or the like containing N-type or P-type impurities.

[0029] For example, as shown in Figure 2, the wiring area RHU of the memory block BLK includes a portion of the conductive layer 110 and two contact electrode rows (CCGs) arranged along the Y direction. In Figure 2, the two contact electrode rows CCGs are represented as CCG(0) and CCG(1).

[0030] Additionally, for example, as shown in Figure 6, the wiring area RHU includes multiple supporting insulating members HR. The supporting insulating members HR may contain, for example, silicon oxide (SiO2). As shown in Figures 6-8, the supporting insulating members HR extend along the Z-direction across multiple segmented structures HT11, HT12, HT21, and HT22, and penetrate multiple conductive layers 110 and insulating layers 101. The outer peripheral surfaces of the supporting insulating members HR are each surrounded by at least a portion of the conductive layers 110.

[0031] In this embodiment, for example, as shown in FIG8, the supporting insulating member HR includes two HRP portions arranged along the Z direction corresponding to the hierarchical structures MT1 and MT2, respectively. The portion of the two HRPs corresponding to the hierarchical structure MT1 is positioned from a height position corresponding to the lower surface of the lowest conductive layer 110 included in the hierarchical structure MT1 to a height position corresponding to the upper surface of the uppermost conductive layer 110 included in the hierarchical structure MT1. Similarly, the portion of the two HRPs corresponding to the hierarchical structure MT2 is positioned from a height position corresponding to the lower surface of the lowest conductive layer 110 included in the hierarchical structure MT2 to a height position corresponding to the uppermost conductive layer 110 included in the hierarchical structure MT2. The width (diameter when viewed from the Z direction) of these HRP portions in the X and Y directions increases from the lower end to a predetermined height position and decreases from the height position to the upper end. The width (diameter) of the upper end of these HRP portions is greater than the width (diameter) of the lower end of these HRP portions. The positions where the width in the X and Y directions of some HRPs reaches their maximum height are approximately the same as those where the width in the X and Y directions of parts 123 reaches their maximum height. In these HRP parts, the width (diameter) of the upper end is greater than the width (diameter) of the lower end.

[0032] In the layered structures MT1 and MT2, the height position of the portion HRP of the support insulating member HR with the maximum width (diameter) in the Z direction is approximately the same as the height position of the portion 123 of the semiconductor pillar 120 with the maximum width (diameter) in the Z direction.

[0033] As shown in Figures 6 and 7, the contact electrode row CCG includes multiple contact electrodes CC arranged along the X direction. These multiple contact electrodes CC extend along the Z direction, covering multiple segmented structures HT11, HT12, HT21, and HT22, penetrating multiple conductive layers 110 and insulating layers 101, and are connected to the conductive layers 110 at their lower ends. The contact electrodes CC may also include, for example, a barrier conductive film such as titanium nitride (TiN) or a laminated film of metal films such as tungsten (W). Furthermore, an insulating layer 103 is provided on the outer peripheral surface of the contact electrodes CC.

[0034] Furthermore, in the following description, the nth conductive layer 110 (where n is an integer greater than or equal to 1) counting from the top is sometimes referred to as conductive layer 110(n-1). Additionally, the contact electrode among the plurality of contact electrodes CC that is connected to conductive layer 110(n) is sometimes referred to as contact electrode CC(n).

[0035] As shown in Figure 6, the contact electrode row CCG(0) starting from the one closest to the memory hole region RMH includes contact electrode CC(0), contact electrode CC(2), contact electrode CC(4), contact electrode CC(6), contact electrode CC(8), and contact electrode CC(10).

[0036] As shown in Figure 7, the contact electrode row CCG(1) starts from the one closest to the memory hole region RMH and includes contact electrode CC(1), contact electrode CC(3), contact electrode CC(5), contact electrode CC(7), contact electrode CC(9), and contact electrode CC(11).

[0037] Furthermore, as shown in Figure 2, multiple contact electrodes CC(0), CC(2), CC(4), CC(6), CC(8), and CC(10) in the contact electrode row CCG(0) are arranged in the Y direction with multiple contact electrodes CC(1), CC(3), CC(5), CC(7), and CC(11) in the contact electrode row CCG(1).

[0038] Furthermore, in this embodiment, for example, as shown in FIG8, the contact electrode CC (10) includes four portions CCP arranged along the Z direction corresponding to each of the segmented structures HT11, HT12, HT21, and HT22. The portion of the four portions CCP corresponding to the segmented structure HT11 is positioned from the lower end of the contact electrode CC (10) to a predetermined height position Z1, which is lower than the lower surface of the lowest conductive layer 110 included in the segmented structure HT12. The portion of the four portions CCP corresponding to the segmented structure HT12 is positioned from height position Z1 to a predetermined height position Z2, which is lower than the lower surface of the lowest conductive layer 110 included in the segmented structure HT21. The portion of the four portions CCP corresponding to the segmented structure HT21 is positioned from height position Z2 to a predetermined height position Z3, which is lower than the lower surface of the lowest conductive layer 110 included in the segmented structure HT22. The portions of the four CCPs corresponding to the segmented structure HT22 are positioned from height position Z3 to a predetermined height position Z4, which is located above the upper surface of the uppermost conductive layer 110 included in the segmented structure HT22. The width (diameter when viewed from the Z direction) of these portions of the CCP in the X and Y directions increases from the lower end to the upper end. The width (diameter) of the upper end of these portions of the CCP is greater than the width (diameter) of the lower end of these portions of the CCP. The height position where the width in the X and Y directions of the portions of the CCP is the largest (in the first embodiment, the height position of the upper end of the portions of the CCP) is different from the height positions where the width in the X and Y directions of portions 123 and HRP is the largest.

[0039] In this embodiment, the other contact electrodes CC (9) and CC (11) corresponding to the conductive layers 110 (9), 110 (10), and 110 (11) in the segmented structure HT11 also have the same structure as the contact electrode CC (10).

[0040] In this embodiment, the contact electrodes CC(6), CC(7), and CC(8) corresponding to the conductive layers 110(6), 110(7), and 110(8) in the segmented structure HT12 have a structure that is substantially the same as that of the contact electrodes CC(9), CC(10), and CC(11). However, the contact electrodes CC(6), CC(7), and CC(8) do not include the portion CCP corresponding to the segmented structure HT11. In addition, the portion of the three portions CCP included in the contact electrodes CC(6), CC(7), and CC(8) that corresponds to the segmented structure HT12 is provided from the lower end of the contact electrodes CC(6), CC(7), and CC(8) to a height position Z2.

[0041] In this embodiment, the contact electrodes CC(3), CC(4), and CC(5) corresponding to the conductive layers 110(3), 110(4), and 110(5) in the segmented structure HT21 have a structure that is substantially the same as that of the contact electrodes CC(6), CC(7), and CC(8). However, the contact electrodes CC(3), CC(4), and CC(5) do not include the portion CCP corresponding to the segmented structure HT12. In addition, the portion of the two portions CCP included in the contact electrodes CC(3), CC(4), and CC(5) corresponding to the segmented structure HT21 is provided from the lower end of the contact electrodes CC(3), CC(4), and CC(5) to a height position Z3.

[0042] In this embodiment, the contact electrodes CC(0), CC(1), and CC(2) corresponding to the conductive layers 110(0), 110(1), and 110(2) in the segmented structure HT22 have a structure that is substantially the same as that of the contact electrodes CC(3), CC(4), and CC(5). However, the contact electrodes CC(0), CC(1), and CC(2) do not include the portion of CCP corresponding to the segmented structure HT21. In addition, the portion of CCP included in the contact electrodes CC(0), CC(1), and CC(2) is provided from the lower end of the contact electrodes CC(0), CC(1), and CC(2) to a height position Z4.

[0043] Viewed from the Z direction, the insulating layer 103 has a generally cylindrical shape covering the outer peripheral surface of the contact electrode CC. For example, as shown in FIG8, the insulating layer 103 includes a spacer oxide film 1031 and a barrier oxide film 1032 deposited between the contact electrode CC and the conductive layer 110. The spacer oxide film 1031 and the barrier oxide film 1032 contain, for example, silicon oxide (SiO2). The spacer oxide film 1031 is a film used to maintain the voltage resistance of the contact electrode CC and the conductive layer 110 (word line). The barrier oxide film 1032 is a film used to protect the structure in the contact hole CH in the manufacturing step described later (FIG. 37), for example, having phosphoric acid resistance. The spacer oxide film 1031 and the barrier oxide film 1032 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120, except for the contact portion between the contact electrode CC and the semiconductor layer 112.

[0044] The thickness of the spacer oxide film 1031 is greater than the thickness of the barrier oxide film 1032. Furthermore, the hydrogen content of the spacer oxide film 1031 and the barrier oxide film 1032 differs from each other, for example. Additionally, the etching rates of the spacer oxide film 1031 and the barrier oxide film 1032 differ from each other, for example. Furthermore, the nitrogen (N) content in the barrier oxide film 1032 is higher than the nitrogen (N) content in the spacer oxide film 1031.

[0045] [Manufacturing Method] Next, the manufacturing method of memory die (MD) will be described with reference to Figures 9 to 41. Figures 11, 16, 24, and 29 are schematic plan views illustrating the manufacturing method, showing the plane corresponding to Figure 2. Figures 9, 10, 12-15, 17-23, 25-28, and 30-41 are schematic cross-sectional views illustrating the manufacturing method, showing the cross-section corresponding to Figure 6.

[0046] During the fabrication of the memory die MD in this embodiment, for example, as shown in FIG9, a semiconductor layer 112 is formed. Furthermore, a plurality of insulating layers 101 and a plurality of sacrificial layers 111 corresponding to the partition structure HT11 are alternately formed above the semiconductor layer 112. The sacrificial layer 111 includes, for example, silicon nitride (Si3N4). Additionally, an insulating layer 105 is formed above the uppermost sacrificial layer 111. This process is performed, for example, by a method such as chemical vapor deposition (CVD). In the following description, the sacrificial layer 111 corresponding to the nth (n is an integer greater than or equal to 1) conductive layer 110(n-1) from the top is sometimes referred to as sacrificial layer 111(n-1).

[0047] Secondly, for example, as shown in FIG10, an amorphous silicon (aSi) capping layer 104 as a sacrificial layer is formed on the upper surface of the structure described with reference to FIG9. This step is performed, for example, by a method such as CVD.

[0048] Secondly, for example, as shown in Figures 11 and 12, a contact hole CH is formed at a position corresponding to a portion of the contact electrode CC. In the following description, the contact hole CH that exposes the upper surface of the sacrificial layer 111(n) and is disposed above all the sacrificial layers 111(n) is sometimes referred to as the contact hole CH(n).

[0049] In the aforementioned steps, for example, a resist layer is formed on the upper surface of the cover layer 104. The resist layer exposes the upper surface of the cover layer 104 at the positions corresponding to the contact electrodes of the segmented structure HT11 among the plurality of contact electrodes CC (contact electrodes CC(9), CC(10), and CC(11) in this embodiment). Next, the cover layer 104 and the insulating layer 105 are removed by a method such as reactive ion etching (RIE) to expose the upper surface of the uppermost sacrificial layer 111 (sacrificial layer 111(9) in this embodiment). Through the aforementioned steps, a contact hole CH(9) is formed at a height position corresponding to the segmented structure HT11.

[0050] Next, the resist layer is removed to form the resist layer 115 illustrated in FIG12. The upper surface of the uppermost sacrificial layer 111 (9) is exposed at the position corresponding to the contact electrode (contact electrode CC (10)) of the 2a+2th (a is an integer greater than or equal to 0) sacrificial layer 111 (sacrificial layer 111 (10) in this embodiment) among the plurality of contact electrodes CC corresponding to the segmented structure HT11. Next, one sacrificial layer 111 and the insulating layer 101 provided on its lower surface are removed by means of RIE, etc., so that the upper surface of the 2a+2th sacrificial layer 111 is exposed. By the above steps, a contact hole CH (10) is formed at the height position corresponding to the segmented structure HT11.

[0051] Next, the resist layer 115 is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the 2a+2th sacrificial layer 111 at the position corresponding to the contact electrode (in this embodiment, contact electrode CC(11)) of the 4a+3rd and 4a+4th (a is an integer greater than or equal to 0) sacrificial layers 111 (in this embodiment, sacrificial layer 111(11)) at the position corresponding to the contact electrode (in this embodiment, contact electrode CC(11)) among the plurality of contact electrodes CC corresponding to the segmented structure HT11. Next, the two sacrificial layers 111 and the two insulating layers 101 respectively disposed on their lower surfaces are removed by methods such as RIE, thereby exposing the upper surface of the sacrificial layer 111. Through the above steps, a contact hole CH(11) is formed at a height position corresponding to the segmented structure HT11.

[0052] Secondly, for example, as shown in FIG13, the resist layer is removed, and an amorphous silicon (aSi) capping layer 104 is further formed on the upper surface of the capping layer 104, and the contact holes CH are filled. This step is performed, for example, by a method such as CVD.

[0053] Secondly, for example, as shown in FIG14, a portion of the cover layer 104 is removed, exposing the upper surface of the insulating layer 105. This step is performed, for example, by a planarization process such as Chemical Mechanical Polishing (CMP).

[0054] Secondly, for example, as shown in FIG15, a plurality of insulating layers 101 and a plurality of sacrificial layers 111 corresponding to the segmentation structure HT12 are alternately formed on the upper surface of the insulating layer 105. In addition, an insulating layer 105 and a cover layer 104 are formed above the uppermost sacrificial layer 111. The steps are performed, for example, by a method such as CVD.

[0055] Secondly, for example, as shown in Figures 16 and 17, a contact hole CH is formed at a position corresponding to a portion of the contact electrode CC.

[0056] In the aforementioned steps, for example, firstly, a resist layer is formed on the upper surface of the cover layer 104. This resist layer exposes the upper surface of the cover layer 104 at the positions corresponding to the contact electrodes CC of the plurality of contact electrodes and the sacrificial layer 111 in the segmented structures HT11 and HT12. Next, the cover layer 104 and the insulating layer 105 are removed by methods such as RIE, exposing the upper surface of the uppermost sacrificial layer 111 (6). Through this step, a contact hole CH (6) is formed at a height position corresponding to the segmented structure HT12.

[0057] Next, the resist layer is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the uppermost sacrificial layer 111 (6) at the position corresponding to the plurality of contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structure HT11. In addition, the resist layer exposes the upper surface of the uppermost sacrificial layer 111 (6) at the position corresponding to the contact electrode of the 2a+2 (a is an integer greater than or equal to 0) sacrificial layer 111 among the plurality of contact electrodes CC corresponding to the segmented structure HT12. Next, one sacrificial layer 111 and the insulating layer 101 disposed on its lower surface are removed by means of RIE, etc., so that the upper surface of the 2a+2 sacrificial layer 111 is exposed. By means of the above steps, a contact hole CH (7) is formed at the height position corresponding to the segmented structure HT12.

[0058] Next, the resist layer is removed to form a resist layer 116. The upper surface of the uppermost sacrificial layer 111 (6) is exposed at the positions corresponding to the plurality of contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structure HT11. In addition, the upper surface of the sacrificial layer 111 is exposed at the positions corresponding to the contact electrodes CC corresponding to the 4a+3 and 4a+4th (a is an integer greater than or equal to 0) sacrificial layers 111 from the top. Next, the two sacrificial layers 111 and the two insulating layers 101 respectively disposed on their lower surfaces are removed by methods such as RIE to expose the upper surface of the sacrificial layer 111. By the above steps, a contact hole CH (8) is formed at the height position corresponding to the segmented structure HT12.

[0059] Next, for example, as shown in FIG18, the resist layer 116 is removed to form a resist layer 117. The resist layer 117 exposes the upper surface of the lowermost sacrificial layer 111(7) in the segmented structure HT12 at the position corresponding to the plurality of contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structure HT11. Next, one sacrificial layer 111 is removed by means of RIE or the like, exposing the upper surface of the cover layer 104 in the segmented structure HT11. By the above steps, a plurality of contact holes CH corresponding to the sacrificial layer 111 in the segmented structure HT11 are formed at the height position corresponding to the segmented structure HT12.

[0060] Secondly, for example, as shown in FIG19, the resist layer 117 is removed, and a further cover layer 104 is formed on the upper surface of the cover layer 104, and the contact hole CH is filled. This step is performed, for example, by a method such as CVD.

[0061] Secondly, for example, as shown in FIG20, a portion of the cover layer 104 is removed, exposing the upper surface of the insulating layer 105. This step is performed, for example, by a planarization process such as CMP.

[0062] Secondly, for example, as shown in FIG21, a plurality of through holes 120a are formed at positions corresponding to the plurality of semiconductor pillars 120. Additionally, a plurality of through holes HRa are formed at positions corresponding to the plurality of supporting insulating members HR. The through holes 120a and HRa respectively penetrate the plurality of insulating layers 101 and the plurality of sacrificial layers 111 included in the hierarchical structure MT1 and extend along the Z direction, exposing the upper surface of the semiconductor layer 112. These steps are performed, for example, by a method such as RIE.

[0063] Secondly, for example, as shown in FIG22, a sacrificial layer 120b and a sacrificial layer HRb, such as carbon, are formed inside the through-hole 120a and the through-hole HRa. This step is performed, for example, by a method such as plasma CVD.

[0064] Secondly, for example, as shown in FIG23, an insulating layer 105 is further formed on the upper surface of the insulating layer 105 described with reference to FIG22. Furthermore, a plurality of insulating layers 101 and a plurality of sacrificial layers 111 corresponding to the segmentation structure HT21 are alternately formed on the upper surface of the insulating layer 105. Additionally, an insulating layer 105 and a cover layer 104 are formed above the uppermost sacrificial layer 111. These steps are performed, for example, by a method such as CVD.

[0065] Secondly, for example, as shown in Figures 24 and 25, a contact hole CH is formed at a position corresponding to a portion of the contact electrode CC.

[0066] In the aforementioned steps, for example, firstly, a resist layer is formed on the upper surface of the cover layer 104. This resist layer exposes the upper surface of the cover layer 104 at the positions corresponding to the contact electrodes of the plurality of contact electrodes CC and the sacrificial layer 111 in the segmented structures HT11, HT12, and HT21. Secondly, the cover layer 104 and the insulating layer 105 are removed by methods such as RIE, exposing the upper surface of the uppermost sacrificial layer 111 (3). Through this step, a contact hole CH (3) is formed at a height position corresponding to the segmented structure HT21.

[0067] Next, the resist layer is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the uppermost sacrificial layer 111(3) at the position corresponding to the multiple contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structures HT11 and HT12. In addition, the resist layer exposes the upper surface of the uppermost sacrificial layer 111(3) at the position corresponding to the contact electrode of the 2a+2 (a is an integer greater than or equal to 0) sacrificial layer 111 among the multiple contact electrodes CC corresponding to the segmented structure HT21. Next, one sacrificial layer 111 and the insulating layer 101 provided on its lower surface are removed by means of RIE, etc., so that the upper surface of the 2a+2 sacrificial layer 111 is exposed. By the above steps, a contact hole CH(4) is formed at the height position corresponding to the segmented structure HT21.

[0068] Next, the resist layer is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the sacrificial layer 111 at the positions corresponding to the multiple contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structures HT11 and HT12. In addition, the resist layer exposes the upper surface of the sacrificial layer 111 at the positions corresponding to the contact electrodes CC corresponding to the multiple contact electrodes CC corresponding to the segmented structure HT21, specifically the 4a+3rd and 4a+4th (where a is an integer greater than or equal to 0) sacrificial layers 111. Next, the two sacrificial layers 111 and the two insulating layers 101 respectively disposed on their lower surfaces are removed by methods such as RIE, exposing the upper surface of the sacrificial layer 111. Through the above steps, contact holes CH (5) are formed at the height position corresponding to the segmented structure HT21. In addition, multiple contact holes CH corresponding to the sacrificial layers 111 in the segmented structures HT11 and HT12 are formed at the height position corresponding to the segmented structure HT21.

[0069] Next, the resist layer is removed to form a resist layer 118. The resist layer 118 exposes the upper surface of the lowest sacrificial layer 111(5) in the segmented structure HT21 at positions corresponding to the multiple contact electrodes CC of the sacrificial layer 111 in the segmented structures HT11 and HT12. Next, one sacrificial layer 111 and the insulating layer 105 are removed by a method such as RIE, exposing the upper surface of the cover layer 104 in the segmented structure HT12. Through these steps, multiple contact holes CH corresponding to the sacrificial layer 111 in the segmented structures HT11 and HT12 are formed at height positions corresponding to the segmented structure HT21.

[0070] Secondly, for example, as shown in FIG26, the resist layer 118 is removed, a further cover layer 104 is formed on the upper surface of the cover layer 104, and the contact hole CH is filled. This step is performed, for example, by a method such as CVD.

[0071] Secondly, for example, as shown in FIG27, a portion of the cover layer 104 is removed to expose the insulating layer 105. This step is performed, for example, by planarization processing such as CMP.

[0072] Secondly, for example, as shown in FIG28, a plurality of insulating layers 101 and a plurality of sacrificial layers 111 corresponding to the segmentation structure HT22 are alternately formed on the upper surface of the insulating layer 105. In addition, a portion of the insulating layer 107 and a cover layer 104 are formed above the uppermost sacrificial layer 111. The steps are performed, for example, by a method such as CVD.

[0073] Secondly, for example, as shown in Figures 29 and 30, a contact hole CH is formed at a position corresponding to the contact electrode CC.

[0074] In the aforementioned steps, for example, firstly, a resist layer is formed on the upper surface of the cover layer 104. This resist layer exposes the upper surface of the cover layer 104 at positions corresponding to the plurality of contact electrodes CC. Secondly, the cover layer 104 and the insulating layer 107 are removed by methods such as RIE, exposing the upper surface of the uppermost sacrificial layer 111(0). Through this step, contact holes CH(0) are formed at height positions corresponding to the segmentation structure HT22.

[0075] Next, the resist layer is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the uppermost sacrificial layer 111(0) at the position corresponding to the plurality of contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structures HT11, HT12, and HT21. Additionally, the resist layer exposes the upper surface of the uppermost sacrificial layer 111(0) at the position corresponding to the contact electrode CC of the plurality of contact electrodes CC corresponding to the segmented structure HT22, which is the 2a+2th (a is an integer greater than or equal to 0) sacrificial layer 111 counted from the top. Next, one sacrificial layer 111 and the insulating layer 101 disposed on its lower surface are removed by a method such as RIE, exposing the upper surface of the 2a+2th sacrificial layer 111. Through these steps, a contact hole CH(1) is formed at a height position corresponding to the segmented structure HT22.

[0076] Next, the resist layer is removed, and a further resist layer is formed. The resist layer exposes the upper surface of the sacrificial layer 111 at the positions corresponding to the multiple contact electrodes CC corresponding to the sacrificial layer 111 in the segmented structures HT11, HT12, and HT21. Additionally, the resist layer exposes the upper surface of the sacrificial layer 111 at the positions corresponding to the contact electrodes CC corresponding to the 4a+3 and 4a+4th (where a is an integer greater than or equal to 0) sacrificial layers 111 from the top. Next, the two sacrificial layers 111 and the two insulating layers 101 respectively disposed on their lower surfaces are removed by methods such as RIE, exposing the upper surface of the sacrificial layer 111. Through these steps, a contact hole CH(2) is formed at a height position corresponding to the segmented structure HT22.

[0077] Next, the resist layer is removed to form a resist layer 119. The resist layer 119 exposes the upper surface of the lowest sacrificial layer 111(2) in the segmented structure HT22 at positions corresponding to the multiple contact electrodes CC of the sacrificial layer 111 in the segmented structures HT11, HT12, and HT21. Next, one sacrificial layer 111 is removed by a method such as RIE, exposing the upper surface of the cover layer 104 in the segmented structure HT21. Through these steps, multiple contact holes CH corresponding to the sacrificial layer 111 in the segmented structures HT11, HT12, and HT21 are formed at height positions corresponding to the segmented structure HT22.

[0078] Next, for example, as shown in FIG31, the resist layer 119 and the cover layer 104 are removed. This step is performed, for example, by a method such as wet etching.

[0079] Next, a barrier oxide film 1032 is formed by forming a silicon nitride (Si3N4) film inside the contact hole CH and oxidizing the film. This step is performed, for example, by a method such as CVD.

[0080] Secondly, for example, as shown in FIG32, a cover layer 104 is formed on the upper surface of the insulating layer 107, and the contact hole CH is filled. This step is performed, for example, by a method such as CVD.

[0081] Secondly, for example, as shown in FIG33, a portion of the cover layer 104 is removed, exposing the upper surface of the insulating layer 107. This step is performed, for example, by planarization processing such as CMP.

[0082] Secondly, for example, as shown in FIG34, a plurality of through holes 120c are formed at positions corresponding to the plurality of semiconductor pillars 120. Additionally, a plurality of through holes HRc are formed at positions corresponding to the plurality of supporting insulating members HR. The through holes 120c and HRc respectively penetrate the plurality of insulating layers 101 and the plurality of sacrificial layers 111 included in the hierarchical structure MT2 and extend along the Z direction, exposing the upper surfaces of the sacrificial layers 120b and HRb. These steps are performed, for example, by a method such as RIE.

[0083] Secondly, for example, as shown in FIG35, a sacrificial layer 120d and a sacrificial layer HRd, such as carbon, are formed inside the through-hole 120c and the through-hole HRc. This step is performed, for example, by a method such as plasma CVD.

[0084] Next, for example, as shown in FIG36, a plurality of semiconductor pillars 120 and a plurality of supporting insulating members HR are formed. In the above steps, for example, sacrificial layers 120b and 120d are removed by means of wet etching. Next, by means of CVD or the like, gate insulating film 130 (FIG. 5), semiconductor pillars 120 and insulating layer 125 are formed on the inner peripheral surfaces of vias 120a and 120c. Next, for example, sacrificial layers HRb and HRd are removed by means of wet etching or the like. Next, by means of CVD or the like, supporting insulating members HR are formed inside vias HRa and HRc.

[0085] Next, a portion of the insulating layer 107 is further formed on the upper surface of the insulating layer 107. This step is performed, for example, by a method such as CVD.

[0086] Next, for example, as shown in FIG37, multiple conductive layers 110 are formed. In the above step, for example, by means of RIE or the like, trenches are formed at positions corresponding to the inter-block insulating layer ST, penetrating the multiple insulating layers 101 and multiple sacrificial layers 111 included in the hierarchical structure MT1 and hierarchical structure MT2. Next, by means of wet etching or the like through the trenches, the multiple sacrificial layers 111 included in the hierarchical structure MT1 and hierarchical structure MT2 are removed, forming multiple voids. Thereby, a hollow structure is formed, the hollow structure including multiple insulating layers 101 arranged along the Z direction with gaps, multiple semiconductor pillars 120 supporting the multiple insulating layers 101 in the memory via region RMH, and multiple supporting insulating members HR supporting the multiple insulating layers 101 in the wiring region RHU. Next, the multiple conductive layers 110 included in the hierarchical structure MT1 and hierarchical structure MT2 are formed by means of CVD or the like.

[0087] Secondly, for example, as shown in FIG38, a plurality of through holes are formed in the insulating layer 107 at positions corresponding to the plurality of contact holes CH. These through holes penetrate a portion of the insulating layer 107 and extend along the Z direction, exposing the upper surface of the cover layer 104. This step is performed, for example, by a method such as RIE.

[0088] Next, for example, as shown in FIG39, the cover layer 104 is removed. This step is performed, for example, by a method such as wet etching.

[0089] Next, for example, as shown in FIG40, an insulating layer 103 is formed inside the contact hole CH. In the above step, for example, a spacer oxide film 1031 is formed on the inner peripheral surface of the contact hole CH by a method such as CVD. In addition, the portion of the spacer oxide film 1031 and the blocking oxide film 1032 formed on the bottom surface of the contact hole CH is removed, exposing the upper surface of the conductive layer 110.

[0090] Secondly, for example, as shown in Figure 41, a contact electrode CC is formed inside the contact hole CH. This step is performed, for example, by a method such as CVD.

[0091] Subsequently, by using methods such as CVD, contact electrodes Ch, Vy, and bit lines BL as illustrated in Figures 6 to 8 are formed, thereby forming a semiconductor memory device as illustrated in Figures 1 to 7.

[0092] [Comparative Example] [structure] Next, referring to Figures 42 to 44, the structure of the comparative example semiconductor memory device will be described. Figure 42 is a schematic plan view of the comparative example semiconductor memory device. Figure 43 is a schematic cross-sectional view of the structure shown in Figure 42 cut along line H-H' and viewed in the direction of the arrow. Figure 44 is a schematic cross-sectional view of the structure shown in Figure 42 cut along line I-I' and viewed in the direction of the arrow.

[0093] The comparative example memory block BLK includes hierarchical structures MT91 and MT92 instead of hierarchical structures MT1 and MT2. Unlike hierarchical structures MT1 and MT2, hierarchical structures MT91 and MT92 do not include partition structures HT11, HT12, HT21, and HT22.

[0094] The comparative example semiconductor memory device includes contact electrode rows CCG' instead of contact electrode rows CCG. In FIG42, the two contact electrode rows CCG' are represented as CCG'(0) and CCG'(1).

[0095] The contact electrode row CCG'(0) starts from the one closest to the memory hole region RMH and includes contact electrode CC'(0), contact electrode CC'(2), contact electrode CC'(4), contact electrode CC'(6), contact electrode CC'(8), and contact electrode CC'(10).

[0096] The contact electrode row CCG'(1) starts from the one closest to the memory hole region RMH and includes contact electrode CC'(1), contact electrode CC'(3), contact electrode CC'(5), contact electrode CC'(7), contact electrode CC'(9), and contact electrode CC'(11).

[0097] In the comparative example, among the multiple contact electrodes CC', the contact electrode corresponding to the conductive layer 110 in the layered structure MT91 includes two portions CCP' arranged along the Z direction corresponding to the layered structures MT91 and MT92. The portion of the two portions CCP' corresponding to the layered structure MT91 is positioned from the lower end of the contact electrode CC' to a predetermined height position below the lower surface of the lowest conductive layer 110 included in the layered structure MT92. The portion of the two portions CCP' corresponding to the layered structure MT92 is positioned from the predetermined height position to the upper end of the contact electrode CC'. The width (diameter when viewed from the Z direction) of one portion of the portion CCP' in the X and Y directions increases from the lower end to the predetermined height position and decreases from the height position to the upper end. The height position where the width of these portions of the portion CCP' in the X and Y directions reaches its maximum is approximately the same as the height position where the width of portion 123 and portion HRP in the X and Y directions reaches its maximum.

[0098] Here, as described above, during the fabrication of the semiconductor memory device of the first embodiment, the sacrificial layer 111 in the layered structure MT1 is formed in two steps: the steps described with reference to FIG9 and the steps described with reference to FIG15. Additionally, the contact holes CH in the layered structure MT1 are formed in two steps. Subsequently, through-holes HRa are formed. Furthermore, the sacrificial layer 111 in the layered structure MT2 is formed in two steps: the steps described with reference to FIG23 and the steps described with reference to FIG28. Additionally, the contact holes CH in the layered structure MT2 are formed in two steps. Subsequently, through-holes HRc are formed.

[0099] On the other hand, during the manufacturing of the comparative example semiconductor memory device, all sacrificial layers 111 in the hierarchical structure MT91 are formed in the step corresponding to FIG. 9, without performing the step corresponding to FIG. 15. In addition, after performing the step corresponding to FIG. 9, contact holes CH corresponding to all sacrificial layers 111 in the hierarchical structure MT91 are formed, thereby forming through holes HRa.

[0100] Figure 45 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device of the comparative example, showing the situation after performing the steps corresponding to Figure 21. As shown, in the manufacturing steps of the semiconductor memory device of the comparative example, the height position where the width in the X and Y directions of a portion of the contact hole CH (contact hole CH (10) in the illustrated example) is the largest coincides with the height position where the width in the X and Y directions of the through hole HRa is the largest. The reason for this is that the formation of the contact hole CH corresponding to the layer structure MT91 and the formation of the through hole HRa corresponding to the layer structure MT91 are both performed when the sacrificial layer 111 corresponding to the layer structure MT91 is fully formed.

[0101] Similarly, in the manufacturing of the comparative example semiconductor memory device, all sacrificial layers 111 in the hierarchical structure MT92 are formed in the step corresponding to FIG. 23, without performing the step corresponding to FIG. 28. In addition, after performing the step corresponding to FIG. 23, contact holes CH corresponding to all sacrificial layers 111 in the hierarchical structure MT92 are formed, and through holes HRc are formed.

[0102] Figure 46 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device of the comparative example, showing the situation after performing the steps corresponding to Figure 34. As shown, in the manufacturing steps of the semiconductor memory device of the comparative example, the height positions where the width in the X and Y directions of a portion of the contact holes CH (contact holes CH (6), CH (8), and CH (10) in the illustrated example) is the largest are approximately the same as the height positions where the width in the X and Y directions of the through hole HRc is the largest. This is because the formation of the contact holes CH corresponding to the layer structure MT92 and the formation of the through hole HRc corresponding to the layer structure MT92 are both performed when the sacrificial layer 111 corresponding to the layer structure MT92 is fully formed.

[0103] [Effect] With the increasing integration of semiconductor memory devices, the aspect ratio (the ratio of length in the Z direction to width in the X and Y directions) of the semiconductor pillar 120, the supporting insulating member HR, and the contact electrode CC is gradually increasing. When a through-hole with a large aspect ratio is formed by methods such as RIE, the width (diameter when viewed from the Z direction) of the through-hole in the X and Y directions sometimes increases from the bottom to a predetermined height position and decreases from the height position to the top.

[0104] Here, for the high integration of the semiconductor memory device, it is ideal that the distance between the contact electrodes CC is close. Furthermore, in order to properly support the multiple insulating layers 101 in the steps described with reference to FIG37, it is ideal that the supporting insulating members HR are arranged at predetermined intervals. However, as described with reference to FIGS. 45 and 46, during the manufacturing of the comparative example semiconductor memory device, in a portion of the contact hole CH, the height position where the width in the X and Y directions is greatest coincides approximately with the height position where the width in the X and Y directions of the through holes HRa and HRc is greatest. Therefore, when the contact hole CH and the through holes HRa and HRc are close to or greater than a predetermined amount, there is a risk that the cover layer 104 in the contact hole CH may be exposed on the inner peripheral surface of the through holes HRa and HRc. If, in this state, the sacrificial layers HRb and HRd in the through holes HRa and HRc are removed in the steps corresponding to FIG35, the cover layer 104 in the contact hole CH is also removed. Furthermore, if a supporting insulating member HR is formed in the through hole HRa and through hole HRc under this condition, an insulating layer of silicon oxide or the like will be formed on the bottom surface, top surface and inner circumferential surface of the contact hole CH, and the contact electrode CC cannot be formed.

[0105] Therefore, in the manufacturing of the semiconductor memory device of this embodiment, the sacrificial layer 111 in the layered structure MT1 is formed in two steps, namely the steps described with reference to FIG9 and the steps described with reference to FIG15. Additionally, the contact holes CH in the layered structure MT1 are formed in two steps. Then, the through-hole HRa is formed. Furthermore, the sacrificial layer 111 in the layered structure MT2 is formed in two steps, namely the steps described with reference to FIG23 and the steps described with reference to FIG28. Additionally, the contact holes CH in the layered structure MT2 are formed in two steps. Then, the through-hole HRc is formed.

[0106] Therefore, in the semiconductor memory device of the embodiment, the height position of the portion with the maximum width (diameter) in the contact hole CH in the Z direction is different from the height position of the portion with the maximum width (diameter) in the Z direction in the through hole HRa and through hole HRc. As a result, the cover layer 104 in the contact hole CH is not easily exposed to the inner peripheral surface of the through hole HRa and through hole HRc.

[0107] Furthermore, by forming the contact hole CH in two separate steps in the layered structure MT1 and layered structure MT2, the aspect ratio of the portion of the contact hole CH formed in a single step (the portion corresponding to the portion of CCP) can be reduced. This prevents the shape of the contact hole CH from becoming such that its width (diameter when viewed from the Z direction) increases from the lower end to a predetermined height position and decreases from the height position to the upper end, thereby easily ensuring the distance to the through holes HRa and HRc.

[0108] Furthermore, in the manufacturing of the semiconductor memory device according to the embodiment, the contact holes CH in the layered structure MT1 are formed in two stages, and the contact holes CH in the layered structure MT2 are formed in two stages. Therefore, the aspect ratio of the contact holes CH formed each time is reduced, and the selectivity during etching of the contact holes CH formed each time is reduced. Thus, even if the contact holes CH are formed in multiple stages (four times in this embodiment), the offset of the contact holes CH (through holes) in the Z-axis direction can be suppressed. In addition, since the contact holes CH are formed in multiple stages (four times in this embodiment), the thickness of the resist layer applied when forming a single contact hole CH can be relatively increased.

[0109] [Other Implementation Methods] The semiconductor memory device according to the embodiments has been described above. However, the structure and manufacturing method of the semiconductor memory device according to the embodiments are merely exemplary, and the specific structure and manufacturing method can be adapted accordingly.

[0110] For example, the memory block BLK in the first embodiment includes multiple (two in the illustrated example) hierarchical structures MT1 and MT2 arranged along the Z direction. However, the memory block BLK may also include three or more hierarchical structures. Furthermore, the semiconductor pillar 120 and the supporting insulating member HR may also include three or more structures corresponding to portions 123 and HRP, respectively, corresponding to the three or more hierarchical structures.

[0111] Figure 47 is a schematic cross-sectional view of a semiconductor memory device according to other embodiments.

[0112] As shown in Figure 47, another embodiment of the semiconductor memory device includes three layered structures MT1, MT2, and MT3 arranged along the Z-direction. Furthermore, each of the three layered structures MT1, MT2, and MT3 includes two segmented structures arranged along the Z-direction. Moreover, since the other structures are as described in the embodiment, further explanation is omitted.

[0113] Additionally, for example, the hierarchical structure in the memory block BLK may also include three or more segmented structures arranged along the Z direction. Furthermore, the contact electrode CC may also include three or more structures corresponding to a portion of the CCP, corresponding to the three or more segmented structures.

[0114] Additionally, for example, in the described embodiment, one end of the semiconductor pillar 120 in the Z direction is connected to the semiconductor layer 112. However, one end of the semiconductor pillar 120 in the Z direction may also be connected to the semiconductor substrate 100. Furthermore, the structure in the embodiment may also be formed upside down.

[0115] [other] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0116] 100: Semiconductor substrate 101, 103, 105, 106, 107, 125: Insulation layer 104: Overlay 110, 110(0), 110(1), 110(2), 110(3), 110(4), 110(5), 110(6), 110(7), 110(8), 110(9), 110(10), 110(11): Conductive layer 111(0), 111(2), 111(3), 111(5), 111(6), 111(7), 111(9), 111(10), 111(11), 120b, 120d, HRb, HRd: Sacrificial layer 112: Semiconductor layer 115, 116, 117, 118, 119: Anti-corrosion layer 120: Semiconductor column 120a, 120c, HRa, HRc: Through holes 121, 122: Impurity regions 123, A, B, C, E, CCP, CCP', HRP: Partial 130: Gate insulating film 131: Tunneling Insulation Film 132: Charge storage membrane 133: Barrier insulating film 1031: Spacer oxide film 1032: Barrier oxide film BL: Bitline BLK: Memory Block CC, CC(0), CC(1), CC(2), CC(3), CC(4), CC(5), CC(6), CC(7), CC(8), CC(9), CC(10), CC(11), CC', CC'(0), CC'(1), CC'(2), CC'(3), CC'(4), CC'(5), CC'(6), CC'(7), CC'(8), CC'(9), CC'(10), CC'(11), Ch, Vy: Contact electrode CCG(0), CCG(1), CCG'(0), CCG'(1): Contact electrode row CH, CH(0), CH(1), CH(2), CH(3), CH(4), CH(5), CH(6), CH(7), CH(8), CH(9), CH(10), CH(11): Contact holes D-D', F-F', G-G', H-H', I-I': lines HR: Supporting insulation component HT, HT11, HT12, HT21, HT22: Segmentation Structure MD: Memory chip MT, MT1, MT2, MT3, MT91, MT92: Hierarchical Structure RMCA: Memory Cell Array Region RMH: Memory Hole Area RHU: Wiring Area SHE: Inter-cell insulation layer ST: Inter-block insulation layer SU: Serial unit X, Y, Z: Direction Z1, Z2, Z3, Z4: Height position

Claims

1. A semiconductor memory device, comprising: Multiple conductive layers are stacked along the stacking direction; Semiconductor pillars extend along the stacking direction and face the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor pillar; a bit line is disposed on one side of the stacking direction relative to the plurality of conductive layers and electrically connected to the semiconductor pillar; and a plurality of contact electrodes extend along the stacking direction and are connected to the bit line side surface of one of the plurality of conductive layers. The semiconductor pillar includes a plurality of first portions arranged along the stacking direction, the width of the bit line side end of the plurality of first portions in the stacking direction being larger than the width of the bit line side end of the plurality of first portions in the stacking direction in the first direction intersecting the stacking direction. The plurality of contact electrodes include a plurality of second portions arranged along the stacking direction, the width of the bit line side end of the plurality of second portions in the stacking direction being larger than the width of the bit line side end of the plurality of second portions in the stacking direction in the first direction. The number of the plurality of second portions included in at least one of the plurality of contact electrodes is greater than the number of the plurality of first portions included in the semiconductor pillar.

2. The semiconductor memory device as claimed in claim 1, wherein, The plurality of conductive layers include: a first conductive layer, which is connected to the contact electrode; and a plurality of second conductive layers disposed on the bit line side in the stacking direction relative to the first conductive layer, wherein the outer peripheral surface of the contact electrode is surrounded by the plurality of second conductive layers.

3. The semiconductor memory device as claimed in claim 1, wherein, Between a first position in the stacking direction corresponding to the end of one of the plurality of first portions on the side opposite to the bit line and a second position in the stacking direction corresponding to the end of one of the plurality of first portions on the bit line side, a plurality of second portions are provided.

4. The semiconductor memory device as claimed in claim 3, wherein, Between a third position in the stacking direction corresponding to the end of one of the plurality of first portions disposed on the bit line side of the stacking direction relative to one of the plurality of first portions, and a fourth position in the stacking direction corresponding to the end of the bit line side of the other of the plurality of first portions, a plurality of second portions are disposed.

5. The semiconductor memory device as claimed in claim 1, wherein, The positions in the stacking direction where the width of the plurality of second parts in the first direction is the largest are all different from the positions in the stacking direction where the width of each of the plurality of first parts in the first direction is the largest.

6. The semiconductor memory device as claimed in claim 1, wherein, The width of the plurality of first portions in the first direction increases from the end opposite to the bit line to a predetermined height position in the stacking direction, and decreases from the predetermined height position to the end on the bit line side. The width of the plurality of second portions in the first direction increases from the end opposite to the bit line to the end on the bit line side.

7. The semiconductor memory device of claim 1, further comprising a supporting insulating member extending along the stacking direction and including an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers, the supporting insulating member including a plurality of third portions arranged along the stacking direction, the width of the portion of the plurality of third portions in the first direction of the bit-line side of the stacking direction being greater than the width of the portion of the plurality of third portions in the first direction of the bit-line side of the stacking direction, and the number of the plurality of second portions included in the contact electrode being greater than the number of the plurality of third portions included in the supporting insulating member.

8. The semiconductor memory device as claimed in claim 7, wherein, The number of the plurality of third portions included in the supporting insulating member is equal to the number of the plurality of first portions included in the semiconductor pillar.

9. The semiconductor memory device as claimed in claim 7, wherein, Between a fifth position in the stacking direction corresponding to the end of one of the plurality of third portions on the side opposite to the bit line and a sixth position in the stacking direction corresponding to the end of one of the plurality of third portions on the bit line side, a plurality of the plurality of second portions are provided.

10. The semiconductor memory device as claimed in claim 9, wherein, Between a seventh position in the stacking direction corresponding to the end of one of the plurality of third portions disposed on the bit line side of the stacking direction relative to one of the plurality of third portions, and an eighth position in the stacking direction corresponding to the end of the bit line side of the other of the plurality of third portions, a plurality of the plurality of second portions are disposed.

11. The semiconductor memory device as claimed in claim 7, wherein, The positions in the stacking directions where the width of the plurality of second parts in the first direction is maximized are all different from the positions in the stacking directions where the width of the plurality of third parts in the first direction is maximized.

12. The semiconductor memory device as claimed in claim 11, wherein, The positions in the stacking directions where the width of the plurality of third portions in the first direction is the largest are respectively substantially the same as any one of the positions in the stacking directions where the width of the plurality of first portions in the first direction is the largest.

13. The semiconductor memory device as claimed in claim 7, wherein, The widths of the plurality of third portions in the first direction increase from the end opposite to the bit line to a predetermined height position in the stacking direction, and decrease from the predetermined height position to the end on the bit line side. The widths of the plurality of second portions in the first direction increase from the end opposite to the bit line to the end on the bit line side.

14. The semiconductor memory device as claimed in claim 13, wherein, The width of each of the plurality of first portions in the first direction increases from the end opposite to the bit line to the predetermined height position in the stacking direction, and decreases from the predetermined height position to the end on the bit line side.

15. A semiconductor memory device, comprising: Multiple conductive layers are stacked along the stacking direction; Semiconductor pillars extend along the stacking direction and face the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor pillar; a bit line is disposed on one side of the stacking direction relative to the plurality of conductive layers and electrically connected to the semiconductor pillar; a plurality of contact electrodes extend along the stacking direction and are connected to the bit line side surface of one of the plurality of conductive layers; and a supporting insulating member extends along the stacking direction and includes an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The semiconductor pillar includes a plurality of first portions arranged along the stacking direction, the width of the bit line side end of the stacking direction being larger than the width of the bit line side end of the plurality of first portions in the stacking direction intersecting the stacking direction in a first direction. The plurality of contact electrodes include a plurality of second portions arranged along the stacking direction, the width of the bit line side end of the stacking direction being larger than the width of the bit line side end of the plurality of second portions in the stacking direction in the first direction. The supporting insulating member includes a plurality of third portions arranged along the stacking direction. The width of the end of the plurality of third portions on the bit line side in the stacking direction is greater than the width of the first direction of the end of the plurality of third portions on the stacking direction opposite to the bit line. The number of the plurality of second portions included in at least one of the plurality of contact electrodes is greater than the number of the plurality of third portions included in the supporting insulating member.

16. The semiconductor memory device as claimed in claim 15, wherein, The plurality of conductive layers include: a first conductive layer, which is connected to the contact electrode; and a plurality of second conductive layers disposed on the bit line side in the stacking direction relative to the first conductive layer, wherein the outer peripheral surface of the contact electrode is surrounded by the plurality of second conductive layers.

17. The semiconductor memory device as claimed in claim 15, wherein, The positions in the stacking directions where the width of the plurality of second parts in the first direction is maximized are all different from the positions in the stacking directions where the width of the plurality of third parts in the first direction is maximized.

18. The semiconductor memory device as claimed in claim 15, wherein, The widths of the plurality of third portions in the first direction increase from the end opposite to the bit line to a predetermined height position in the stacking direction, and decrease from the predetermined height position to the end on the bit line side. The widths of the plurality of second portions in the first direction increase from the end opposite to the bit line to the end on the bit line side.

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