Semiconductor device with recessed gate

Abstract

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate comprising a first peripheral region and a second peripheral region; a plurality of recessed gates, each comprising a recessed gate dielectric layer located within the first peripheral region and having a U-shaped cross-sectional profile, a recessed gate bottom conductive layer located on the recessed gate dielectric layer and having a valley-shaped cross-sectional profile forming a first valley, a recessed gate top conductive layer conforming to the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer located on the recessed gate top conductive layer; and a peripheral gate structure located on the second peripheral region. An insulating portion is disposed within each of the plurality of recessed gates, and a gap surrounds the insulating portion. The device density in the first peripheral region is greater than the device density in the second peripheral region.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 829,710 (i.e., priority date "September 10, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device having a recessed gate and a method for manufacturing a semiconductor device having a recessed gate. Prior Technology

[0003] Semiconductor devices are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demand for computing power, the size of semiconductor devices continues to shrink. However, various problems arise during the shrinking process, and these problems continue to increase. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case. Summary of the Invention

[0005] This disclosure provides a semiconductor device comprising a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates, each including a recessed gate dielectric layer located within the first peripheral region and having a U-shaped cross-sectional profile; a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a U-shaped or V-shaped cross-sectional profile to form a first valley; a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer; and a recessed gate cap layer located on the recessed gate top conductive layer; and a peripheral gate structure located on the second peripheral region; wherein an insulating portion is disposed within each of the plurality of recessed gates, a gap surrounds the insulating portion, and the component density of the first peripheral region is greater than the component density of the second peripheral region.

[0006] Another aspect of this disclosure provides a semiconductor device comprising a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates, each including a recessed gate dielectric layer located within the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile to form a first valley, a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer, and a recessed gate cap layer located on the recessed gate top conductive layer; and a peripheral gate structure located on the second peripheral region; wherein a plurality of sidewall spacers cover the sidewalls of the recessed gates and an air gap is provided between the sidewall spacers, and the device density of the first peripheral region is greater than the device density of the second peripheral region.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, wherein the method includes providing a substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer covering the mandrel layer on the bottom hard mask layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on the side of the mandrel layer; and forming a cover on the bottom hard mask layer. A lower layer covering the mandrel layer and the plurality of sacrificial spacers is formed; the lower layer is recessed to expose the mandrel layer and the plurality of sacrificial spacers; the plurality of sacrificial spacers are selectively removed to form a plurality of openings exposing the bottom hard mask layer; the plurality of openings are deepened to expose the first peripheral region of the substrate; a plurality of gate recesses are formed in the first peripheral region; a plurality of gate recesses are formed on the plurality of gate recesses; an insulating portion is formed in each of the plurality of gate recesses; and a void is formed around the insulating portion.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, wherein the method includes providing a substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer covering the mandrel layer on the bottom hard mask layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on the side of the mandrel layer; and forming a mandrel layer covering the bottom hard mask layer. The lower layer of the plurality of sacrificial spacers; the lower layer is recessed to expose the mandrel layer and the plurality of sacrificial spacers; the plurality of sacrificial spacers are selectively removed to form a plurality of openings exposing the bottom hard mask layer; the plurality of openings are deepened to expose the first peripheral region of the substrate; a plurality of gate recesses are formed in the first peripheral region; a plurality of gate recesses are formed on the plurality of gate recesses; a plurality of sidewall spacers are formed covering the sidewalls of each of the gate recesses; and an air gap is formed between each pair of the sidewall spacers.

[0009] Due to the design of the semiconductor device disclosed herein, leakage current issues associated with smaller gate sizes can be effectively controlled by utilizing a recessed gate dielectric layer. Furthermore, the ability to fabricate both recessed and planar gates (i.e., peripheral gate structures) simultaneously helps reduce manufacturing costs.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments with the scope of the patent application. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity, the dimensions of various features may be arbitrarily enlarged or reduced. According to an embodiment of the present disclosure, FIG1 shows a method for manufacturing a semiconductor device in the form of a flowchart. According to one embodiment of the present disclosure, Figures 2 to 24 show a portion of the process for manufacturing a semiconductor device 1A in the form of cross-sectional schematic diagrams. According to one embodiment of the present disclosure, Figures 25 to 33 are close-up cross-sectional schematic diagrams showing a portion of the process of manufacturing a semiconductor device. According to another embodiment of this disclosure, FIG34 shows a method for manufacturing a semiconductor device in the form of a flowchart. According to another embodiment of this disclosure, Figures 35 to 42 show the process of manufacturing a semiconductor device in the form of cross-sectional schematic diagrams. Implementation

[0012] The following disclosure provides many different embodiments or examples to achieve different features of the provided technical content. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this disclosure. For example, when the description refers to a first feature being formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or designations may be repeated in various examples in this disclosure. This repetition is for simplification and clarity and is not intended to limit the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, spatially related terms such as "below," "under," "down," "above," and "above," and similar terms are used here to facilitate the description of the relationship between one element or feature shown in the diagram and one or more other elements or features. These spatially related terms are used to cover different orientations of the device in use or operation, in addition to the orientation depicted in the diagram. The instrument may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used therein can be interpreted accordingly.

[0014] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be directly connected to or coupled to another component or layer, or there may be a component or layer in between.

[0015] It should be understood that although terms such as "first," "second," etc., are used herein to describe various elements, these elements are not limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from other elements. Thus, for example, the first element, first component, or first segment discussed below may be referred to as the second element, second component, or second segment, without departing from the teachings of this disclosure.

[0016] Unless the context otherwise specifies, the terms used here, such as “same,” “equal,” “plane,” or “coplanar,” when referring to orientation, layout, location, shape, size, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure. Rather, they mean that these orientations, layouts, locations, shapes, sizes, quantities, or other measures are substantially the same within acceptable variations, for example, variations that may arise from the manufacturing process. The term “generally” may be used here to express this meaning. For example, items described as “generally the same,” “generally equal,” or “generally plane” may be exactly the same, equal, or plane, or the same, equal, or plane within acceptable variations that may arise from the manufacturing process.

[0017] In this disclosure, semiconductor devices generally refer to devices that can operate using the characteristics of semiconductors, and optoelectronic devices, light-emitting display devices, semiconductor circuits and electronic devices all fall under the category of semiconductor devices.

[0018] It should be noted that in the description disclosed herein, "above" corresponds to the direction of the Z-direction arrow, and "below" corresponds to the opposite direction of the Z-direction arrow.

[0019] It should be noted that, in the description of this disclosure, the terms "forming" and "formed" may mean and include any method of creating, constructing, patterning, implanting, or depositing elements, dopants, or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, lithography, dry etching, and wet etching.

[0020] It should be noted that the functions or steps mentioned herein may occur in a manner different from that shown in the diagrams. For example, two consecutively displayed diagrams may actually be executed substantially simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

[0021] According to one embodiment of the present disclosure, FIG1 shows a method 10 for manufacturing a semiconductor device 1A in the form of a flowchart. According to method 10, FIGS. 2 to 24 show a portion of the process for manufacturing the semiconductor device 1A in the form of cross-sectional schematic diagrams. According to some embodiments of the present disclosure, FIGS. 25 to 30 are close-up cross-sectional schematic diagrams showing a portion of the process for manufacturing the semiconductor device 1A. According to some embodiments of the present disclosure, FIG. 31 shows a portion of the process for manufacturing the semiconductor device 1A in the form of a cross-sectional schematic diagram.

[0022] Referring to Figures 1 to 11, in step S11, a substrate 101 comprising an array region AR, a first peripheral region PR1, and a second peripheral region PR2 can be provided. A plurality of character line trenches 103-1 and 103-3 can be formed in the array region AR, and a plurality of character line structures 200 can be formed in the plurality of character line trenches 103-1 and 103-3.

[0023] Referring to Figure 2, in some embodiments, the array region AR and the first peripheral region PR1 may be adjacent to each other. For example, in a top-down view, the array region AR may be surrounded by the first peripheral region PR1 (not shown). In some embodiments, the first peripheral region PR1 and the second peripheral region PR2 may be adjacent to each other. For example, in a top-down view, the first peripheral region PR1 may be surrounded by the second peripheral region PR2 (not shown). In some embodiments, the first peripheral region PR1 and the second peripheral region PR2 may be separate from each other.

[0024] It should be noted that the array region AR may include a portion of the substrate 101, and the space above that portion of the substrate 101. Describing an element as disposed on the array region AR means that the element is disposed on the top surface of that portion of the substrate 101; describing an element as disposed within the array region AR means that the element is disposed within that portion of the substrate 101; however, the top surface of the element may be flush with the top surface of that portion of the substrate 101. Describing an element as disposed above the array region AR means that the element is disposed above the top surface of that portion of the substrate 101. Therefore, the first peripheral region PR1 and the second peripheral region PR2 may include other portions of the substrate 101, and the space above those other portions of the substrate 101.

[0025] Referring to Figure 2, the substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor substrate may be formed of an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors.

[0026] Referring to Figure 2, an isolation layer 107 can be formed within the substrate 101. For example, the isolation layer 107 can be formed within the array region AR of the substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. Optical lithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide layer and the pad nitride layer and extend into the substrate 101. An insulating material can be deposited within the trenches, followed by a planarization process, such as chemical mechanical polishing, until the top surface 101TS of the substrate 101 is exposed to remove excess filler material, providing a generally flat surface for subsequent process steps, and simultaneously forming the isolation layer 107. For example, the insulating material can be silicon oxide or other suitable insulating materials.

[0027] Referring to Figure 3, a first hard mask layer 511 may be formed on the substrate 101. In some embodiments, the first hard mask layer 511 may be formed of a material that is etch-selective to the substrate 101. In some embodiments, the first hard mask layer 511 may be formed of a material that is etch-selective to both the substrate 101 and the isolation layer 107. In some embodiments, the first hard mask layer 511 may be formed, for example, of silicon nitride, boron nitride, boron phosphide, or boron carbide. In some embodiments, the first hard mask layer 511 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0028] Referring to Figure 3, a first masking layer 721 may be formed on the first hard masking layer 511. In some embodiments, the first masking layer 721 may be a photoresist layer and may contain a pattern of a plurality of character line structures 200.

[0029] Referring to Figure 4, an etching process can be performed to remove a portion of the first hard mask layer 511. In some embodiments, during the etching process, the ratio of the etching rate of the first hard mask layer 511 to the etching rate of the substrate 101 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the etching process, the ratio of the etching rate of the first hard mask layer 511 to the etching rate of the isolation layer 107 can be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. A pattern of the first mask layer 721 can be transferred to the first hard mask layer 511 and may be referred to as the first pattern 513. A portion of the isolation layer 107 and a portion of the substrate 101 can be exposed via the first pattern 513. After the etching process, the first mask layer 721 can be removed by ashing or other suitable semiconductor processes.

[0030] Referring to Figure 5, a first hard mask layer 511 can be used as a mask to perform a trench etching process to remove a portion of the isolation layer 107 and a portion of the substrate 101, while simultaneously forming a plurality of character line trenches 103-1 and 103-3. In some embodiments, the plurality of character line trenches 103-1 formed in the substrate 101 are shallower than the plurality of character line trenches 103-3 formed in the isolation layer 107. In some embodiments, during the trench etching process, the ratio of the etching rate of the isolation layer 107 to the etching rate of the first hard mask layer 511 can be between approximately 100:1 and approximately 5:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 5:1. In some embodiments, during the trench etching process, the ratio of the etching rate of the substrate 101 to the etching rate of the first hard mask layer 511 may be between about 80:1 and about 5:1, between about 10:1 and about 5:1, or between about 8:1 and about 5:1.

[0031] Referring to Figure 6, a first insulating material layer 711 is compliantly formed on the first hard mask layer 511 and within the plurality of character line trenches 103-1, 103-3. The first insulating material layer 711 may have a U-shaped cross-sectional profile within the plurality of character line trenches 103-1, 103-3. In some embodiments, the first insulating material layer 711 may have a thickness in the range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0032] In some embodiments, the first insulating layer 711 may be formed by a thermal oxidation process. For example, the first insulating layer 711 may be formed by oxidizing the surfaces of a plurality of character line trenches 103-1, 103-3. In some embodiments, the first insulating layer 711 may be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating layer 711 may comprise a dielectric material with a high dielectric constant, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing an inner polycrystalline silicon liner (not shown for clarity), the first insulating layer 711 may be formed by radical oxidation of the inner polycrystalline silicon liner. In some embodiments, after forming an inner silicon nitride liner (not shown for clarity), the first insulating layer 711 may be formed by radical oxidation of the inner silicon nitride liner.

[0033] In some embodiments, the high dielectric constant dielectric material may comprise a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, or a combination thereof. In some embodiments, the high dielectric constant dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, aluminum oxide, or a combination thereof.

[0034] Referring to Figure 7, a plurality of character-line bottom conductive layers 203 may be formed respectively and correspondingly within a plurality of character-line trenches 103-1, 103-3. For example, conductive material (not shown) may be formed to fill the plurality of character-line trenches 103-1, 103-3. Subsequently, an etch-back process may be performed to partially remove the conductive material formed within the plurality of character-line trenches 103-1, 103-3, while simultaneously forming the plurality of character-line bottom conductive layers 203. In some embodiments, the conductive material may be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the bulk chemical potential of a material (e.g., a metal) relative to a vacuum level.

[0035] For example, in this embodiment, the conductive material is titanium nitride, which can be formed by chemical vapor deposition. In some embodiments, the deposition of the conductive material may include a source gas introduction step, a first cleaning step, a reactant flow step, and a second cleaning step. The source gas introduction step, the first cleaning step, the reactant flow step, and the second cleaning step can be referred to as a cycle. Multiple cycles can be implemented to fill a plurality of character line trenches 103-1, 103-3.

[0036] In detail, the intermediate semiconductor device shown in Figure 6 can be loaded into the reaction chamber. In the source gas introduction step, a source gas containing precursors and reactants can be introduced into the reaction chamber containing the intermediate semiconductor device. The precursors and reactants can diffuse through the boundary layer and reach the surface of the intermediate semiconductor device. The precursors and reactants can adsorb onto and subsequently migrate to the surface. The adsorbed precursors and reactants can react on the surface and form solid byproducts. The solid byproducts can nucleate on the surface. These nuclei can grow into islands, and these islands can merge to form a continuous thin film on the surface. In the first cleaning step, a cleaning gas, such as argon, can be injected into the reaction chamber to clean away gaseous byproducts, unreacted precursors, and unreacted reactants.

[0037] In the reactant flow step, reactants can be introduced into the reaction chamber to transform the continuous film into a titanium nitride layer. In the second cleaning step, a cleaning gas, such as argon, can be injected into the reaction chamber to remove gaseous byproducts and unreacted reactants.

[0038] In some embodiments, conductive material deposition can be performed using chemical vapor deposition with the aid of plasma. The plasma source can be, for example, argon, hydrogen, or a combination thereof.

[0039] For example, the precursor can be titanium tetrachloride. The reactant can be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, they can react on the surface to form a titanium nitride layer containing high levels of chlorine contaminants. The ammonia in the reactant flow step can reduce the chlorine content of the titanium nitride layer.

[0040] In some embodiments, during the etch-back process, the ratio of the etch rate of the bottom conductive layer 203 to the etch rate of the first insulating material layer 711 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0041] Referring to Figure 8, a plurality of character-line top conductive layers 205 can be formed within a plurality of character-line trenches 103-1 and 103-3. In some embodiments, the plurality of character-line top conductive layers 205 can be formed, for example, from polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the plurality of character-line top conductive layers 205 can be doped with P-type or N-type dopants. In some embodiments, conductive materials, such as polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium, can be deposited within the plurality of character-line trenches 103-1 and 103-3. Subsequently, an etch-back process can be performed to remove portions of the conductive material to form the plurality of character-line top conductive layers 205. In some embodiments, dopants can be added during the deposition process of the conductive material. In some embodiments, dopant can be incorporated using a fabrication process after the etch-back process.

[0042] The term "P-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, create valence electron vacancies. Examples of P-type dopants in silicon-containing semiconductors include, but are not limited to, boron, aluminum, gallium, and indium. The term "N-type dopant" refers to impurities that, when added to an intrinsic semiconductor material, contribute free electrons to the intrinsic semiconductor material. Examples of N-type dopants in silicon-containing materials include, but are not limited to, antimony, arsenic, and phosphorus.

[0043] Referring to Figure 9, a character line capping layer 207 can be formed on the first hard mask layer 511 to completely fill the plurality of character line trenches 103-1, 103-3. In some embodiments, the character line capping layer 207 can be formed, for example, from silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the character line capping layer 207 can be formed, for example, from chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. Planarization processes such as chemical mechanical polishing can be implemented to remove excess material and provide a generally flat surface for subsequent process steps.

[0044] It should be noted that, in this disclosure, silicon nitride refers to a substance containing silicon, nitrogen, and oxygen, with oxygen comprising a greater proportion than nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, with nitrogen comprising a greater proportion than oxygen.

[0045] Referring to Figure 9, a second masking layer 725 may be formed on the character line capping layer 207 and above the array region AR of the substrate 101. In some embodiments, the second masking layer 725 may be a photoresist layer. The second masking layer 725 may mask the array region AR of the substrate 101.

[0046] Referring to Figure 10, the second masking layer 725 can be used as a mask to perform an etching process to remove the portions of the character line capping layer 207, the first insulating material layer 711, and the first hard masking layer 511 that are not covered by the second masking layer 725 (i.e., the portions within the first peripheral region PR1 and the second peripheral region PR2). After the etching process, the remaining portion of the first insulating material layer 711 can be referred to as the character line dielectric layer 201. The character line dielectric layer 201, the plurality of character line bottom conductive layers 203, the plurality of character line top conductive layers 205, and the character line capping layer 207 together constitute the plurality of character line structures 200.

[0047] Referring to Figure 11, after the etching process, the second masking layer 725 can be removed by an ashing process or other suitable semiconductor process.

[0048] Referring to Figures 1 and 12 to 17, in step S13, a bottom hard mask layer 517 may be formed on the substrate 101, a first auxiliary layer 535 may be formed on the bottom hard mask layer 517, a mandrel layer 723 may be formed on the first auxiliary layer 535 and above the first peripheral region PR1, a plurality of sacrificial spacers 515 may be formed on the side 723S of the mandrel layer 723, and a lower layer 531 may be formed on the first auxiliary layer 535.

[0049] Referring to Figure 12, a bottom hard mask layer 517 can be formed over the substrate 101 to cover the first peripheral region PR1, the second peripheral region PR2, and the character line capping layer 207. A planarization process, such as chemical mechanical polishing, can be implemented to provide a generally flat surface for subsequent process steps. In some embodiments, the bottom hard mask layer 517 may be formed of a material that is etch-selective for the character line capping layer 207.

[0050] In some embodiments, the bottom hard mask layer 517 may be formed, for example, from boron nitride, borosilicate silicon nitride, borosilicate phosphorus nitride, or borosilicate carbide. In some embodiments, the bottom hard mask layer 517 may be formed, for example, by atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, the bottom hard mask layer 517 may be formed by a film deposition process and a processing process. Specifically, in the film deposition process, a first precursor (which may be a boron-based precursor) may be introduced over the substrate 101 to form a boron-based layer. Subsequently, in the processing process, a second precursor (which may be a nitrogen-based precursor) may be introduced to react with the boron-based layer and transform the boron-based layer into the bottom hard mask layer 517.

[0051] In some embodiments, the first precursor may be, for example, diborane, cycloborane, or an alkyl-substituted cycloborane derivative. In some embodiments, the flow rate of introducing the first precursor may be between about 5 sccm and about 50 slm (standard liters per minute), or between about 10 sccm and about 1 slm. In some embodiments, the first precursor may be introduced by a diluent gas such as nitrogen, hydrogen, argon, or a combination thereof. The flow rate of the diluent gas may be between about 5 sccm and about 50 slm, or between about 1 slm or about 10 slm.

[0052] In some embodiments, the film-forming process can be performed without plasma assistance. In such embodiments, the substrate temperature of the film-forming process can be between about 100°C and about 1000°C. For example, the substrate temperature of the film-forming process can be between about 300°C and about 500°C. The process pressure of the film-forming process can be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film-forming process can be between about 2 Torr and about 10 Torr.

[0053] In some embodiments, the film deposition process can be performed in the presence of plasma. In such embodiments, the substrate temperature of the film deposition process can be between about 100°C and about 1000°C. For example, the substrate temperature of the film deposition process can be between about 300°C and about 500°C. The process pressure of the film deposition process can be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film deposition process can be between about 2 Torr and about 10 Torr. The plasma can be generated by an RF power between 2 W and 5000 W. For example, the RF power can be between 30 W and 1000 W.

[0054] In some embodiments, the second precursor may be, for example, ammonia or hydrazine. In some embodiments, the flow rate of introducing the second precursor may be between about 5 sccm and about 50 slm, or between about 10 sccm and about 1 slm.

[0055] In some embodiments, an oxygen-based precursor may be introduced together with a second precursor during the processing. The oxygen-based precursor may be, for example, oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0056] In some embodiments, the silicon-based precursor may be introduced together with the second precursor during the processing. The silicon-based precursor may be, for example, a silane, a trisilaneamine, a trimethylsilane, or a silazane (e.g., hexamethylcyclotrisilazane).

[0057] In some embodiments, a phosphorus-based precursor may be introduced together with a second precursor during the processing. The phosphorus-based precursor may be, for example, phosphine.

[0058] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor may be introduced together with a second precursor during the processing.

[0059] In some embodiments, the processing may be carried out with the assistance of plasma processing, UV curing processing, thermal annealing processing, or a combination thereof.

[0060] When a processing step is performed with the aid of a plasma process, plasma for the plasma process can be generated using RF power. In some embodiments, the RF power can be between about 2 W and about 5000 W, and at a single low frequency between about 100 kHz and about 1 MHz. In some embodiments, the RF power can be between about 30 W and about 1000 W, and at a single high frequency greater than about 13.6 MHz. In such embodiments, the substrate temperature of the processing step can be between about 20°C and about 1000°C. The process pressure of the processing step can be between about 10 mTorr and about 760 Torr.

[0061] When the processing is performed with the assistance of a UV curing process, the substrate temperature of the processing can be between approximately 20°C and approximately 1000°C. The process pressure of the processing can be between approximately 10 mTorr and approximately 760 Torr. The UV radiation for UV curing can be provided by any UV source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or a high-efficiency UV light-emitting diode array. The UV source can provide UV radiation with wavelengths between approximately 170 nm and approximately 400 nm. The photon energy provided by the UV source is between approximately 0.5 eV and approximately 10 eV, or between approximately 1 eV and approximately 6 eV. The UV curing process can remove hydrogen from the first hard mask layer 511. Since hydrogen can diffuse into other areas of the semiconductor device 1A and may reduce the reliability of the semiconductor device 1A, removing hydrogen by the UV curing process can improve the reliability of the semiconductor device 1A. In addition, the UV curing process can increase the density of the bottom hard mask layer 517.

[0062] When the processing is performed with the assistance of a thermal annealing process, the substrate temperature of the processing can be between approximately 20°C and approximately 1000°C. The process pressure of the processing can be between approximately 10 mTorr and approximately 760 Torr.

[0063] In some embodiments, the bottom hard masking layer 517 may be a carbon film. The term "carbon film" is used herein to describe a material whose mass is primarily composed of carbon, whose structure is primarily defined by carbon atoms, or whose physical and chemical properties are primarily dominated by carbon content. The term "carbon film" excludes materials containing only mixtures or compounds of carbon, such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polycrystalline silicon dielectric materials. In some embodiments, the bottom hard masking layer 517 may be composed of carbon and hydrogen. In some embodiments, the bottom hard masking layer 517 may be composed of carbon, hydrogen, and oxygen. In some embodiments, the bottom hard masking layer 517 may be composed of carbon, hydrogen, and fluorine.

[0064] In some embodiments, carbon films can be deposited via a process that includes introducing a mixture of process gases (composed of one or more hydrocarbons) into a process chamber. The hydrocarbons have the chemical formula CxHy, where x is between 2 and 4, and y is between 2 and 10. The hydrocarbons may be, for example, propylene, propyne, propane, butane, butene, butadiene, or acetylene, or combinations thereof.

[0065] Referring to Figure 13, a first auxiliary layer 535 may be formed on the bottom hard mask layer 517. In some embodiments, the first auxiliary layer 535 may be an anti-reflective coating, such as a bottom anti-reflective coating. In some embodiments, the first auxiliary layer 535 may, for example, comprise a high-square-based material and may contain chromophores to further absorb UV or deep UV light. In some embodiments, the first auxiliary layer 535 may, for example, comprise silicon oxynitride and silicon nitride. In some embodiments, the first auxiliary layer 535 may be formed, for example, by spin coating, chemical vapor deposition, or other suitable deposition processes.

[0066] Referring to Figure 14, a mandrel layer 723 may be formed on the first auxiliary layer 535 and above the first peripheral region PR1. In some embodiments, the mandrel layer 723 may be a photoresist layer. The mandrel layer 723 is characterized by a plurality of gate recesses GR (described in more detail below). This layer may consist of multiple segments with different widths or having substantially the same width, depending on the specific embodiment. Similarly, the distance between two adjacent segments of the mandrel layer 723 may be consistent or may vary.

[0067] Referring to Figure 15, an interstitial material layer 713 covering the mandrel layer 723 can be compliantly formed above the first auxiliary layer 535. In some embodiments, the interstitial material layer 713 may be, for example, silicon oxide. In some embodiments, the interstitial material layer 713 may be formed, for example, by a deposition process such as atomic layer deposition (ALD). Generally, an ALD process alternately supplies two (or more) different gas sources to the process target (i.e., the first auxiliary layer 535) under predetermined process conditions, causing chemicals to be adsorbed onto the process target at a single atomic layer level and deposited onto the process target via surface reaction. For example, first and second gas sources are alternately supplied to the process target, flowing along its surface, thereby adsorbing molecules contained in the first gas source onto the surface, while molecules contained in the second gas source react with the molecules adsorbed from the first gas source to form a film with a thickness of a single molecule. Such process steps are repeated to form a high-quality film on the process target.

[0068] In some embodiments, the interstitial material layer 713 can be formed by atomic layer deposition of a first auxiliary layer 535 in a silicon-containing precursor gas (e.g., silicon tetrachloride) and an oxygen-containing precursor (e.g., water) at temperatures between approximately 320 °C and approximately 530 °C. In some embodiments, the formation of the interstitial material layer 713 may include exposing the intermediate semiconductor device shown in FIG. 14, located in a reaction chamber, to the silicon-containing precursor to achieve chemisorption of silicon on the intermediate semiconductor device. Theoretically, chemisorption would form a silicon-containing monolayer of uniform thickness, consisting of a single atom or a single molecule, over the entire exposed substrate. Excess silicon-containing precursor is washed away from the reaction chamber, and the intermediate semiconductor device is exposed to the oxygen-containing precursor. The oxygen-containing precursor undergoes chemisorption on the silicon-containing monolayer, forming an oxygen-containing monolayer. Excess oxygen-containing precursor is then washed away from the reaction chamber. These steps are repeated to form silicon dioxide of the desired thickness. Silicon- and oxygen-containing precursors can be mixed with catalysts such as pyridine to accelerate deposition at reaction temperatures between approximately 50°C and approximately 100°C. In some cases, deposition of the interstitial material layer 713 at low temperatures may be advantageous due to the thermal sensitivity of the substrate or the material deposited thereon.

[0069] In detail, in the first reaction of the atomic layer deposition process, a silicon-containing precursor can be introduced into the reaction chamber along with pyridine and chemisorbed onto the substrate surface. In some embodiments, the silicon-containing precursor may comprise hydrogenated silicon or silanes, such as hexachlorosilane, dichlorosilane, silane, disilane, trichlorosilane, or any other silicon-containing compound suitable as a precursor. The silicon-containing precursor supplied at this stage can be selected such that the amount of silicon-containing precursor that can bind to the substrate surface can be determined by the number of available binding sites and the physical size of the chemisorbed species (including ligands). The chemisorbed silicon-containing monolayer formed from the silicon-containing precursor can self-terminate when its surface becomes unreactive to the remaining chemicals used to form the silicon-containing monolayer.

[0070] Subsequent cleaning with an inert gas removes excess silicon-containing precursors from the reaction chamber, particularly those not chemisorbed onto the substrate surface. The inert gas can be nitrogen, argon, helium, neon, krypton, or xenon. Cleaning the reaction chamber also removes volatile byproducts generated during the atomic layer deposition process. In some embodiments, nitrogen may be used as the inert gas. The inert gas may, for example, be introduced into the reaction chamber for approximately 10 seconds. After cleaning, the reaction chamber can be emptied to remove gases, such as excess silicon-containing precursors or volatile byproducts. For example, cleaning away silicon-containing precursors from the reaction chamber can be achieved by techniques including contacting the substrate and / or the silicon-containing monolayer with an inert gas, and / or reducing the pressure within the reaction chamber below the deposition pressure of the silicon-containing precursors, thereby reducing the concentration of silicon-containing precursors in contact with the substrate and / or chemisorbed species, but is not limited to these methods. Additionally, cleaning may involve contacting the silicon-containing monolayer with any substance that allows for the desorption of chemisorption byproducts, and reducing the concentration of the silicon-containing precursor before introducing the oxygen-containing precursor. The appropriate cleaning amount to remove the silicon-containing precursor and volatile byproducts can be determined experimentally. The aeration and cleaning sequence can be repeated multiple times. The aeration and cleaning sequence can begin or end with either the aeration step or the cleaning step. During the sequential aeration and cleaning, the duration and other parameters, such as gas flow rate, pressure, and temperature, can be varied. Reducing the cleaning and / or aeration time can increase the amount of silicon oxide deposited per minute (Å / min) and can improve the growth rate of the interstitial material layer 713.

[0071] The second reaction in the atomic layer deposition process introduces an oxygen-containing precursor and pyridine into the reaction chamber, forming an oxygen-containing monolayer on the silicon-containing monolayer. The oxygen-containing monolayer reacts with the silicon-containing monolayer to form a silicon oxide film (i.e., the interstitial material layer 713). The aforementioned aeration and cleaning sequence can be used to remove reaction byproducts and excess oxygen-containing precursors from the reaction chamber. For example, cleaning can be performed by introducing an inert gas into the reaction chamber. Generally, the precursor pulse time is in the range of about 0.5 seconds to about 30 seconds. The interstitial material layer 713 can be deposited on the first auxiliary layer 535 through continuous or repeated cycles, wherein a monolayer of silicon oxide is deposited in each cycle. The required thickness of the interstitial material layer 713 can be achieved by exposing the intermediate semiconductor device to multiple repeated cycles.

[0072] Referring to Figure 16, a spacer etching process can be performed to remove a portion of the spacer material layer 713. After the spacer etching process, the remaining spacer material layer 713 may be referred to as a plurality of sacrificial spacers 515. In some embodiments, the spacer etching process may be an anisotropic etching process, such as an anisotropic dry etching process. In some embodiments, during the spacer etching process, the ratio of the etching rate of the spacer material layer 713 to the etching rate of the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the spacer etching process, the ratio of the etching rate of the spacer material layer 713 to the etching rate of the first auxiliary layer 535 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0073] Referring to Figure 16, a plurality of sacrificial spacers 515 may be formed on the side (or sidewall) 723S of the mandrel layer 723. In some embodiments, the width W1 of the plurality of sacrificial spacers 515 may be substantially the same. In some embodiments, the distance D1 between adjacent sacrificial spacers 515 is consistent. In some embodiments, the distance D1 between adjacent sacrificial spacers 515 is different. Notably, some adjacent sacrificial spacers 515 are not located on both sides of the same segment of the mandrel layer 723.

[0074] Referring to Figure 17, a lower layer 531 covering the mandrel layer 723 and a plurality of sacrificial spacers 515 may be formed on the first auxiliary layer 535. The lower layer 531 may completely fill the gaps between successive sacrificial spacers 515. In some embodiments, a planarization process may be performed to remove excess material and provide a generally flat surface for subsequent process steps. In some embodiments, the lower layer 531 may contain a self-planarizing material, such as spin-coated glass or spin-coated low-dielectric-constant dielectric material. The use of a self-planarizing dielectric material eliminates the need for subsequent planarization steps. In some embodiments, the lower layer 531 may be used as an anti-reflection layer. In some embodiments, the lower layer 531 may consist of a thin film structure of alternating layers with contrasting refractive indices. The thickness T1 of the lower layer 531 may be selected to produce destructive interference in beams reflected from the interface and constructive interference in corresponding transmitted beams. For example, the lower layer 531 may be formed of, for instance, oxides, sulfides, fluorides, nitrides, selenides, or combinations thereof, but is not limited thereto. In some embodiments, the lower layer 531 may improve the resolution of the lithography process. In some embodiments, the lower layer 531 may be formed by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, spin coating, or other suitable deposition processes.

[0075] Referring to Figures 1 and 18 to 24, in step S15, the lower layer 531 is recessed to expose a plurality of sacrificial spacers 515, the plurality of sacrificial spacers 515 are selectively removed to expose a first peripheral region PR1 of the substrate 101, and a plurality of gate recesses GR are formed in the first peripheral region PR1 of the substrate 101.

[0076] Referring to Figure 18, a recess process can be implemented to lower the top surface of the lower layer 531. In some embodiments, the recess process can be an etching process with etch selectivity for the lower layer 531. In some embodiments, the recess process can be an isotropic etching process, such as a wet etching process. In some embodiments, during the recess process, the ratio of the etching rate of the lower layer 531 to the etching rate of the plurality of sacrificial spacers 515 can be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the recess process, the ratio of the etching rate of the lower layer 531 to the etching rate of the mandrel layer 723 can be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, the endpoint of the recess process can be determined by signals from a plurality of sacrificial spacers 515 and the mandrel layer 723. After the etching process, the top surfaces of the plurality of sacrificial spacers 515 and the mandrel layer 723 are exposed.

[0077] Referring to Figure 19, a selective removal process can be implemented to selectively remove a plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an etching process with etch selectivity for the plurality of sacrificial spacers 515. In some embodiments, the selective removal process may be an isotropic etching process, such as an isotropic wet etching process. In some embodiments, during the selective removal process, the ratio of the etching rate of the spacer material layer 713 to the etching rate of the underlying layer 531 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, the ratio of the etching rate of the spacer material layer 713 to the etching rate of the mandrel layer 723 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, during the selective removal process, the ratio of the etching rate of the spacer material layer 713 to the etching rate of the first auxiliary layer 535 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the selective removal process, a plurality of openings 533 may be formed in the lower layer 531 adjacent to the mandrel layer 723 and above the first peripheral region PR1 of the substrate 101. The plurality of openings 533 may replace the positions previously occupied by the sacrificial spacer 515. Parts of the first auxiliary layer 535 may be exposed through the plurality of openings 533.

[0078] Referring to Figures 20 and 21, the lower layer 531 and the mandrel layer 723 can be used as masks to perform the etching process to remove the unmasked portions of the first auxiliary layer 535 and the bottom hard mask layer 517. In some embodiments, the etching process can be a multi-stage etching process. For example, the etching process can be a two-stage anisotropic dry etching process. The etching chemicals in each stage can be different to provide different etching selectivity.

[0079] Referring to Figure 20, in some embodiments, during the first stage of the etching process, the ratio of the etching rate of the first auxiliary layer 535 to the etching rate of the lower layer 531 may be between approximately 100:1 and approximately 5:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 5:1. In some embodiments, during the first stage of the etching process, the ratio of the etching rate of the first auxiliary layer 535 to the etching rate of the mandrel layer 723 may be between approximately 100:1 and approximately 5:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 5:1.

[0080] Referring to Figure 21, in some embodiments, during the second stage of the etching process, the ratio of the etching rate of the bottom hard mask layer 517 to the etching rate of the lower layer 531 may be between approximately 100:1 and approximately 5:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 5:1. In some embodiments, during the second stage of the etching process, the ratio of the etching rate of the bottom hard mask layer 517 to the etching rate of the mandrel layer 723 may be between approximately 100:1 and approximately 5:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 5:1.

[0081] The etching process can extend multiple openings 533 through the first auxiliary layer 535 and the bottom hard mask layer 517, exposing the top surface 101TS of the first peripheral region PR1 of the substrate 101.

[0082] Referring to Figure 22, the lower layer 531, the mandrel layer 723, and the first auxiliary layer 535 can be removed by a removal process. In some embodiments, the removal process may be an etching process with etch selectivity for the lower layer 531 or the mandrel layer 723. For example, the removal process may be an isotropic wet etching process. In some embodiments, the removal process may be an ashing process.

[0083] Referring to Figure 23, a gate recess process can be performed to remove a portion of the first peripheral region PR1 of the substrate 101. In some embodiments, the gate recess process can be an anisotropic etching process with etch selectivity for the substrate 101. For example, the gate recess process can be an anisotropic dry etching process. In some embodiments, during the gate recess process, the ratio of the etching rate of the substrate 101 to the etching rate of the bottom hard mask layer 517 can be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. After the gate recess process, a plurality of gate recesses GR can be formed within the first peripheral region PR1 of the substrate 101. The advantage of using the bottom hard mask layer 517 is that the etch selectivity during the gate recess etching process is easily controlled.

[0084] Referring to Figure 24, the bottom hard mask layer 517 can be removed, exposing the first peripheral region PR1 of the substrate 101, the second peripheral region PR2 of the substrate 101, the plurality of gate recesses GR, and the character line capping layer 207.

[0085] Referring to Figures 1 and 25 to 33, in step S17, a plurality of gates 400 with recesses are formed on a plurality of gate recesses GR, a peripheral gate structure 300 is formed on the second peripheral region PR2 of the substrate 101, an insulating portion 152 is formed in each of the plurality of gates 400 with recesses, and a gap 170 is formed around the insulating portion 152.

[0086] Referring to Figure 25, a gate dielectric material layer 731 is compliantly formed on the top surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the substrate 101, and on a plurality of gate recesses GR. In some embodiments, the gate dielectric material layer 731 may, for example, comprise oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high dielectric constant dielectric materials, or combinations thereof. In some embodiments, the gate dielectric material layer 731 may be formed by a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, chemical solution deposition, or other suitable deposition processes. In some embodiments, the gate dielectric material layer 731 may be formed by the top surface 101TS of the first peripheral region PR1 and the second peripheral region PR2 of the oxide substrate 101 and a plurality of gate recesses GR. In some embodiments, the thickness of the gate dielectric layer 731 may be between about 10 angstroms and about 50 angstroms. In some embodiments, the gate dielectric layer 731 may comprise a multilayer structure. For example, the gate dielectric layer 731 may be an oxide-nitride-oxide (ONO) structure. In another example, the gate dielectric layer 731 may comprise a silicon oxide underlayer and a top layer of a high-dielectric-constant dielectric material.

[0087] Examples of high dielectric constant materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon nitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High dielectric constant materials may further include dopants such as lanthanum and aluminum.

[0088] Referring to Figure 25, the gate dielectric material layer 731 formed in a plurality of gate recesses GR may include a valley-shaped, U-shaped, or V-shaped profile.

[0089] Referring to Figure 26, a first conductive material layer 733 can be compliantly formed above the surface of the gate dielectric material layer 731. Since the first conductive material layer 733 partially fills the plurality of gate recesses GR, upward-facing valleys (referred to as first valleys VY1) are formed within the plurality of gate recesses GR. In some embodiments, the first conductive material layer 733 may, for example, comprise polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or other suitable conductive materials. In some embodiments, the first conductive material layer 733 may be doped with a P-type dopant or an N-type dopant. In some embodiments, the first conductive material layer 733 formed within the plurality of gate recesses GR may have a valley-shaped, U-shaped, or V-shaped cross-sectional profile.

[0090] Referring to Figure 27, a second conductive material layer 735 may be compliantly formed above the surface of the first conductive material layer 733. Since the second conductive material layer 735 partially fills the first valley VY1, upward-facing valleys (referred to as second valleys VY2) are formed within the plurality of gate recesses GR. In some embodiments, the second conductive material layer 735 may, for example, comprise tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the second conductive material layer 735 formed within the plurality of gate recesses GR may have a valley-shaped, U-shaped, or V-shaped cross-sectional profile. In some embodiments, the bottom surface 735BS of the second conductive material layer 735 (or the bottom portion of the second valley VY2) may be located at a vertical height VL1, and the vertical height VL1 is lower than the top surface 101TS of the substrate 101.

[0091] Referring to Figure 28, an isolation material layer 160 may be formed on or above the second conductive material layer 735, and a trench 112 may be formed through the isolation material layer 160, the second conductive material layer 735, and the bottom surface 735BS of the second conductive material layer 735 to contact the first conductive material layer 733.

[0092] Referring to Figure 29, an insulating material layer 150 may be formed on or above the insulating material layer 160, and the insulating material layer 150 may fill the trench 112.

[0093] Referring to Figure 30, a portion of the insulating material layer 150 and a portion of the insulating material layer 160 can be removed, allowing a top insulating material layer 737 to be formed on the second conductive material layer 735. The top insulating material layer 737 can completely fill the second valley VY2, while the remaining portion of the insulating material layer 150 can be retained to form a rod-shaped insulating portion 152 contacting the first conductive material layer 733. Furthermore, a void 170 can be formed around the insulating portion 152. That is, as shown in Figure 30, the rod-shaped insulating portion 152 is formed in the top insulating material layer 737 and extends through the second conductive material layer 735 to contact the first conductive material layer 733. Each void 170 is formed between the rod-shaped insulating portion 152, the second conductive material layer 735, and the top insulating material layer 737. In some embodiments, the top insulating material layer 737 may, for example, comprise silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the top insulating layer 737 may be formed, for example, by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. In some embodiments, the insulating layer 150 may contain nitrogen and is formed using a (plasma) CVD process. In some embodiments, the insulating layer 150 may contain silicon nitride. In some embodiments, the insulating layer 160 may be deposited using a CVD process or an ALD process, wherein the ALD process has good coverage and can form a void-free insulating layer 160. In some embodiments, voids 170 may be introduced into the insulating layer 160 by adjusting the deposition rate of the insulating layer 160. Specifically, when the insulating layer 160 is deposited at a faster rate, the insulating layer 160 may not completely fill the trench 112. In some embodiments, the insulating layer 160 may contain silicon oxide, silicon nitride, silicon oxynitride, hafnium dioxide, or zirconium dioxide. Planarization processes such as chemical mechanical polishing can be implemented to remove excess material and provide a generally flat surface for subsequent process steps. In some embodiments, the bottom surface (or bottom portion) of the top insulating layer 737 may be located at a vertical height below the top surface 101TS of the substrate 101.

[0094] Referring to Figure 31, a gate shielding layer 727 may be formed on the top insulating material layer 737. In some embodiments, the gate shielding layer 727 may be a photoresist layer and may include a pattern of peripheral gate structures 300 and a plurality of recessed gates 400.

[0095] Referring to Figure 32, a gate etching process can be performed to remove portions of the top insulating material layer 737, the second conductive material layer 735, the first conductive material layer 733, and the gate dielectric material layer 731 that are not covered by the gate masking layer 727. In some embodiments, the gate etching process can be a multi-stage etching process. For example, the gate etching process can be a four-stage anisotropic dry etching process. The etching chemicals in each stage can be different to provide different etching selectivity.

[0096] Referring to Figure 32, the remaining portion of the gate dielectric material layer 731 can be converted into a plurality of recessed gate dielectric layers 401 and gate dielectric layers 301. For simplicity, clarity, and ease of description, only one recessed gate dielectric layer 401 is described. The recessed gate dielectric layer 401 can be compliantly formed on the gate recess GR and can include a U-shaped or V-shaped cross-sectional profile. The two ends of the recessed gate dielectric layer 401 can be aligned with the top surface 101TS of the substrate 101 extending in opposite directions. The gate dielectric layer 301 can be formed on the second peripheral region PR2. In some embodiments, the width W2 of the recessed gate dielectric layer 401 can be smaller than the width W3 of the gate dielectric layer 301.

[0097] Referring to Figure 32, the remaining portion of the first conductive material layer 733 can be converted into a plurality of recessed gate bottom conductive layers 403 and gate bottom conductive layers 303. For simplicity, clarity, and ease of description, only one recessed gate bottom conductive layer 403 is described. The recessed gate bottom conductive layer 403 can be compliantly formed on the recessed gate dielectric layer 401. The recessed gate bottom conductive layer 403 may include a valley-shaped, V-shaped, or U-shaped cross-sectional profile. The bottom portion 403BP of the recessed gate bottom conductive layer 403 may be disposed within the gate recess GR, creating a first valley VY1. The two ends of the recessed gate bottom conductive layer 403 may protrude above the top surface 101TS of the substrate 101. The top portion of the top surface 403TS of the recessed gate bottom conductive layer 403 may be located at a vertical height VL3, and the vertical height VL3 is higher than the top surface 101TS of the substrate 101. The gate bottom conductive layer 303 may be formed on the gate dielectric layer 301 and above the second peripheral region PR2 of the substrate 101.

[0098] Referring to Figure 32, the remaining portion of the second conductive material layer 735 can be converted into a plurality of recessed gate top conductive layers 405 and gate top conductive layers 305. For simplicity, clarity, and ease of description, only one recessed gate top conductive layer 405 is described. The recessed gate top conductive layer 405 can be compliantly formed on the recessed gate bottom conductive layer 403. The recessed gate top conductive layer 405 may include a U-shaped or V-shaped cross-sectional profile. The bottom portion of the recessed gate top conductive layer 405 may be disposed within the gate recess GR, creating a second valley VY2. The two ends of the recessed gate top conductive layer 405 may protrude above the top surface 101TS of the substrate 101. The top portion of the top surface 405TS of the recessed gate top conductive layer 405 may be located at a vertical height VL4, and the vertical height VL4 is higher than the top surface 101TS of the substrate 101. Conversely, the bottom surface 405BS of the recessed gate top conductive layer 405 may be located at a vertical height VL1, and the vertical height VL1 is lower than the top surface 101TS of the substrate 101. The gate top conductive layer 305 may be formed on the gate bottom conductive layer 303 and above the second peripheral region PR2 of the substrate 101.

[0099] Referring to Figure 32, the remaining portion of the top insulating material layer 737 can be converted into a plurality of recessed gate cap layers 407 and gate cap layers 307. For simplicity, clarity, and ease of description, only one recessed gate cap layer 407 is described. The recessed gate cap layer 407 can be formed on the recessed gate top conductive layer 405. As shown in Figure 32, a rod-shaped insulating portion 152 is formed within the recessed gate cap layer 407 and passes through the recessed gate top conductive layer 405 to contact the recessed gate bottom conductive layer 403. Each gap 170 is formed between the rod-shaped insulating portion 152, the recessed gate top conductive layer 405, and the recessed gate cap layer 407. The bottom portion 407BS of the recessed gate cap layer 407 can have a downward-pointing triangular cross-sectional profile. The gate cap layer 307 can be formed on the gate top conductive layer 305. The recessed gate dielectric layer 401, the recessed gate bottom conductive layer 403, the recessed gate top conductive layer 405, and the recessed gate capping layer 407 together constitute the recessed gate 400. The gate dielectric layer 301, the gate bottom conductive layer 303, the gate top conductive layer 305, and the gate capping layer 307 together constitute the peripheral gate structure 300. In some embodiments, the width W2 of the recessed gate 400 is smaller than the width W3 of the peripheral gate structure 300.

[0100] Compared to a gate structure with the same width W2 as the recessed gate 400 but using a planar gate dielectric layer (similar to gate dielectric layer 301), the U-shaped profile of the recessed gate dielectric layer 401 provides a larger channel length. Therefore, leakage current problems in the semiconductor device 1A containing the recessed gate 400 can be alleviated. This improved leakage current control facilitates gate miniaturization.

[0101] Referring to Figure 32, the gate dielectric layer 301 may include a width W3, which is greater than the width of the recessed gate dielectric layer 401. This increased width allows the peripheral gate structure 300 to have a larger channel length, enabling it to support larger drive currents. This characteristic is particularly advantageous for power-related circuits. In some embodiments, the peripheral gate structure 300 and the recessed gate 400 can be used in the core circuitry.

[0102] Referring to Figure 33, the gate masking layer 727 can be removed using ashing or other suitable semiconductor processes. It should be noted that, for clarity, Figure 33 omits the gate dielectric layer 301 and the recessed gate dielectric layer 401. In some embodiments, the device density (or pattern density) of the first peripheral region PR1 may be greater than the device density of the second peripheral region PR2. Device density can be defined as the number of devices (e.g., recessed gate 400 or peripheral gate structure 300) formed on the first peripheral region PR1 (or the second peripheral region PR2) divided by the surface area of ​​the first peripheral region PR1 (or the second peripheral region PR2) in a top-view perspective. In some embodiments, from a cross-sectional perspective, a higher device density may refer to a smaller distance between two adjacent devices. In other words, the device density of a semiconductor device may be inversely proportional to the critical dimensions of its devices. As shown in Figure 33, more recessed gates 400 are shown to emphasize that the first peripheral region PR1 has a larger device density than the second peripheral region PR2. It should be noted that the number of recessed gate poles 400 or peripheral gate pole structures 300 shown in Figure 33 is for illustrative purposes only.

[0103] Using a recessed gate dielectric layer 401 can effectively alleviate leakage current problems associated with smaller gate sizes. Furthermore, recessed gates (e.g., recessed gate 400) and planar gates (e.g., peripheral gate structure 300) can be fabricated simultaneously, thus reducing manufacturing costs.

[0104] According to another embodiment of this disclosure, FIG34 shows a method 20 for manufacturing semiconductor device 1B in the form of a flowchart. According to method 20, FIGS. 35 to 42 show the process of manufacturing semiconductor device 1B in the form of cross-sectional schematic diagrams. Semiconductor device 1B is similar to semiconductor device 1A, except for the structure shown in FIG41. Method 20 is similar to method 10, the difference being that in method 10 step S17 and in method 20 step S27. Method 20 includes steps S11, S13, S15, and S27. Steps S11, S13, and S15 of method 20 are the same as in method 10, therefore their descriptions are omitted. Step S27 corresponds to FIG27 and FIGS. 35 to 42.

[0105] Referring to Figure 35, a top insulating material layer 737 that completely fills the second valley VY2 can be formed on the second conductive material layer 735. In some embodiments, the top insulating material layer 737 may, for example, comprise silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the top insulating material layer 737 may be formed, for example, by chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. Planarization processes such as chemical mechanical polishing may be performed to remove excess material and provide a generally flat surface for subsequent process steps. In some embodiments, the bottom surface 737BS (or bottom portion) of the top insulating material layer 737 may be located at a vertical height VL2, and the vertical height VL2 is lower than the top surface 101TS of the substrate 101.

[0106] Referring to Figure 36, a gate shielding layer 727 may be formed on the top insulating material layer 737. In some embodiments, the gate shielding layer 727 may be a photoresist layer and may include a pattern of peripheral gate structures 300 and a plurality of recessed gates 400.

[0107] Referring to Figure 37, a gate etching process can be performed to remove portions of the top insulating material layer 737, the second conductive material layer 735, the first conductive material layer 733, and the gate dielectric material layer 731 that are not covered by the gate masking layer 727. In some embodiments, the gate etching process can be a multi-stage etching process. For example, the gate etching process can be a four-stage anisotropic dry etching process. The etching chemicals in each stage can be different to provide different etching selectivity.

[0108] Referring to Figure 37, the remaining portion of the gate dielectric material layer 731 can be converted into a plurality of recessed gate dielectric layers 401 and gate dielectric layers 301. For simplicity, clarity, and ease of description, only one recessed gate dielectric layer 401 is described. The recessed gate dielectric layer 401 can be compliantly formed on the gate recess GR and can include a U-shaped, valley-shaped, or V-shaped cross-sectional profile. The two ends of the recessed gate dielectric layer 401 can be aligned with the top surface 101TS of the substrate 101 extending in opposite directions. The gate dielectric layer 301 can be formed on the second peripheral region PR2. In some embodiments, the width W2 of the recessed gate dielectric layer 401 can be smaller than the width W3 of the gate dielectric layer 301.

[0109] Referring to Figure 37, the remaining portion of the first conductive material layer 733 can be converted into a plurality of recessed gate bottom conductive layers 403 and gate bottom conductive layers 303. For simplicity, clarity, and ease of description, only one recessed gate bottom conductive layer 403 is described. The recessed gate bottom conductive layer 403 can be compliantly formed on the recessed gate dielectric layer 401. The recessed gate bottom conductive layer 403 may include a valley-shaped, V-shaped, or U-shaped cross-sectional profile. The bottom portion 403BP of the recessed gate bottom conductive layer 403 may be disposed within the gate recess GR, creating a first valley VY1. The two ends of the recessed gate bottom conductive layer 403 may protrude above the top surface 101TS of the substrate 101. The top portion of the top surface 403TS of the recessed gate bottom conductive layer 403 may be located at a vertical height VL3, and the vertical height VL3 is higher than the top surface 101TS of the substrate 101. The gate bottom conductive layer 303 may be formed on the gate dielectric layer 301 and above the second peripheral region PR2 of the substrate 101.

[0110] Referring to Figure 37, the remaining portion of the second conductive material layer 735 can be converted into a plurality of recessed gate top conductive layers 405 and gate top conductive layers 305. For simplicity, clarity, and ease of description, only one recessed gate top conductive layer 405 is described. The recessed gate top conductive layer 405 can be compliantly formed on the recessed gate bottom conductive layer 403. The recessed gate top conductive layer 405 may include a valley-shaped, V-shaped, or U-shaped cross-sectional profile. The bottom portion of the recessed gate top conductive layer 405 may be disposed within the gate recess GR, creating a second valley VY2. The two ends of the recessed gate top conductive layer 405 may protrude above the top surface 101TS of the substrate 101. The top portion of the top surface 405TS of the recessed gate top conductive layer 405 may be located at a vertical height VL4, and the vertical height VL4 is higher than the top surface 101TS of the substrate 101. Conversely, the bottom surface 405BS of the recessed gate top conductive layer 405 may be located at a vertical height VL1, and the vertical height VL1 is lower than the top surface 101TS of the substrate 101. The gate top conductive layer 305 may be formed on the gate bottom conductive layer 303 and above the second peripheral region PR2 of the substrate 101.

[0111] Referring to Figure 37, the remaining portion of the top insulating material layer 737 can be converted into a plurality of recessed gate cap layers 407 and gate cap layers 307. For simplicity, clarity, and ease of description, only one recessed gate cap layer 407 is described. The recessed gate cap layer 407 can be formed on the recessed gate top conductive layer 405. The bottom portion 407BS of the recessed gate cap layer 407 can have a downward-pointing triangular cross-sectional profile. The bottom portion 407BS (or bottom surface) of the recessed gate cap layer 407 can be located at a vertical height VL2, and the vertical height VL2 is lower than the top surface 101TS of the substrate 101. The gate cap layer 307 can be formed on the gate top conductive layer 305. The recessed gate dielectric layer 401, the recessed gate bottom conductive layer 403, the recessed gate top conductive layer 405, and the recessed gate capping layer 407 together constitute the recessed gate 400. The gate dielectric layer 301, the gate bottom conductive layer 303, the gate top conductive layer 305, and the gate capping layer 307 together constitute the peripheral gate structure 300. In some embodiments, the width W2 of the recessed gate 400 is smaller than the width W3 of the peripheral gate structure 300.

[0112] Compared to a gate structure with the same width W2 as the recessed gate 400 but using a planar gate dielectric layer (similar to gate dielectric layer 301), the U-shaped profile of the recessed gate dielectric layer 401 provides a larger channel length. This larger channel length alleviates leakage current problems in the semiconductor device 1A containing the recessed gate 400. This improved leakage current control facilitates gate miniaturization.

[0113] Referring to Figure 37, the gate dielectric layer 301 may include a width W3, which is greater than the width of the recessed gate dielectric layer 401. This increased width allows the peripheral gate structure 300 to have a larger channel length, enabling it to support larger drive currents. This characteristic is particularly advantageous for power-related circuits. In some embodiments, the peripheral gate structure 300 and the recessed gate 400 can be used in the core circuitry.

[0114] Referring to Figure 38, sidewall spacers 110a, 110b and sacrificial sidewall spacers 306 can be formed on the sidewalls of the stacked structure including the gate shielding layer 727 and the recessed gate 400. The sacrificial sidewall spacer 306 is disposed between sidewall spacers 110a and 110b and has a similar shape to sidewall spacers 110a and 110b. The sacrificial sidewall spacers 306 are then removed, and the space occupied by each sacrificial sidewall spacer 306 becomes an air gap AG, as described below in Figure 41. In order to remove the sacrificial sidewall spacers 306 without damaging the sidewall spacers 110a and 110b, the sacrificial sidewall spacers 306 must have sufficient etch selectivity to the sidewall spacers 110a and 110b. In some embodiments, the sacrificial sidewall spacer 306 is formed of doped silicon oxide, while the sidewall spacers 110a and 110b are formed of carbon-containing materials. Furthermore, the carbon-containing material may include high-density carbon (HDC), silicon carbide (SiC), or silicon carbonitride (SiCN). For example, sidewall spacer 110a may be formed from HDC, while sidewall spacer 110b may be formed from HDC, SiC, or SiCN. Compared to using silicon oxide to form sacrificial sidewall spacer 306 and using silicon nitride to form sidewall spacers 110a and 110b, forming sacrificial sidewall spacer 306 and sidewall spacers 110a and 110b by a combination of doped silicon oxide and carbon-containing material allows sacrificial sidewall spacer 306 to exhibit better etch selectivity towards sidewall spacers 110a and 110b. Therefore, after the sacrificial sidewall spacer 306 is removed, the sidewall spacers 110a and 110b can remain largely intact and can effectively prevent unintended electron paths from the source side of the recessed gate 400 to the recessed gate 400.

[0115] In some embodiments, the method of forming the sidewall spacer 110a includes comprehensively and compliantly covering the material layer on the substrate 101 and the stacked structure, and performing an anisotropic etching process on the material layer. During the anisotropic etching process, a portion of the material layer covering the top surface of the gate mask layer 727 and the substrate 101 is removed, and the shape of the portion of the material layer covering the sidewalls of the stacked structure is changed to form the sidewall spacer 110a. Subsequently, sacrificial sidewall spacers 306 and 110b are formed in a similar manner, respectively.

[0116] Referring to Figure 39, a dielectric material layer 308 can be formed on the current structure. Therefore, the dielectric material layer 308 covers the substrate 101, sidewall spacers 110a, 110b, sacrificial sidewall spacer 306, and the stacked structure including the gate masking layer 727 and the recessed gate 400. In some embodiments, the method of forming the dielectric material layer 308 includes a deposition process, such as a CVD process.

[0117] Referring to 40, the dielectric material layer 308 is removed, exposing and thinning the top surface of the gate shielding layer 727 and the top ends of the sidewall spacers 110a, 110b and the sacrificial sidewall spacer 306. In some embodiments, thinning the top ends of the sidewall spacers 110a, 110b and the sacrificial sidewall spacer 306 includes a planarization process. For example, the planarization process may include a polishing process, an etching process, or a combination thereof.

[0118] Referring to Figure 41, the sacrificial sidewall spacer 306 is removed. Therefore, the space previously occupied by the sacrificial sidewall spacer 306 becomes the air gap AG. It should be noted that at this stage, the air gap AG is not sealed, and the top of the air gap AG is exposed to the external environment. In some embodiments, the method for removing the sacrificial sidewall spacer 306 includes an etching process, such as an isotropic etching process. In embodiments where the sacrificial sidewall spacer 306 is formed from doped silicon oxide, and the sidewall spacers 110a and 110b are formed from carbon-containing materials, the etchant used in the etching process may include vapor hydrofluoric acid (VHF). The etchant used in the etching process can react with the sacrificial sidewall spacer 306 from its top. Because the sacrificial sidewall spacer 306 has sufficient etch selectivity for the sidewall spacers 110a and 110b, the sidewall spacers 110a and 110b can remain substantially intact during the removal of the sacrificial sidewall spacer 306.

[0119] Referring to Figure 42, semiconductor device 1B includes a plurality of recessed gates 400, each recessed gate 400 including sidewall spacers 110 covering the sidewalls of the recessed gate 400. The sidewall spacers 110 include sidewall spacers 110a and 110b, wherein sidewall spacer 110a contacts the recessed gate 400, while sidewall spacer 110b is separated from the recessed gate 400. An air gap AG is provided between the sidewall spacers 110a and 110b. In an embodiment where the recessed gate 400 is formed in a linear shape, each sidewall spacer 110 may include portions of opposite sides of the recessed gate 400. Furthermore, in an embodiment where a gate masking layer 727 covers the recessed gate 400, the sidewall spacers 110 may further cover the sidewalls of the gate masking layer 727.

[0120] Compared to a gate structure with the same width W2 as the recessed gate 400 but using a planar gate dielectric layer (similar to gate dielectric layer 301), the U-shaped profile of the recessed gate dielectric layer 401 provides a larger channel length. This larger channel length alleviates leakage current problems in the semiconductor device 1B containing the recessed gate 400. This improved leakage current control facilitates gate miniaturization.

[0121] This disclosure provides a semiconductor device comprising a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates, each including a recessed gate dielectric layer located within the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile to form a first valley, a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer, and a recessed gate cap layer located on the recessed gate top conductive layer; and a peripheral gate structure located on the second peripheral region; wherein an insulating portion is disposed within each of the plurality of recessed gates, a gap surrounds the insulating portion, and the component density of the first peripheral region is greater than the component density of the second peripheral region.

[0122] Another aspect of this disclosure provides a semiconductor device comprising a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates, each including a recessed gate dielectric layer located within the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile to form a first valley, a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer, and a recessed gate cap layer located on the recessed gate top conductive layer; and a peripheral gate structure located on the second peripheral region; wherein a plurality of sidewall spacers cover the sidewalls of the recessed gates and an air gap is provided between the sidewall spacers, and the device density of the first peripheral region is greater than the device density of the second peripheral region.

[0123] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, wherein the method includes providing a substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer covering the mandrel layer on the bottom hard mask layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on the side of the mandrel layer; and forming a cover on the bottom hard mask layer. A lower layer covering the mandrel layer and the plurality of sacrificial spacers is formed; the lower layer is recessed to expose the mandrel layer and the plurality of sacrificial spacers; the plurality of sacrificial spacers are selectively removed to form a plurality of openings exposing the bottom hard mask layer; the plurality of openings are deepened to expose the first peripheral region of the substrate; a plurality of gate recesses are formed in the first peripheral region; a plurality of gate recesses are formed on the plurality of gate recesses; an insulating portion is formed in each of the plurality of gate recesses; and a void is formed around the insulating portion.

[0124] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, wherein the method includes providing a substrate including a first peripheral region and a second peripheral region; forming a bottom hard mask layer on the substrate; forming a mandrel layer on the bottom hard mask layer and above the first peripheral region; conformally forming a spacer material layer covering the mandrel layer on the bottom hard mask layer; performing a spacer etching process to convert the spacer material layer into a plurality of sacrificial spacers on the side of the mandrel layer; and forming a mandrel layer covering the bottom hard mask layer. The lower layer of the plurality of sacrificial spacers; the lower layer is recessed to expose the mandrel layer and the plurality of sacrificial spacers; the plurality of sacrificial spacers are selectively removed to form a plurality of openings exposing the bottom hard mask layer; the plurality of openings are deepened to expose the first peripheral region of the substrate; a plurality of gate recesses are formed in the first peripheral region; a plurality of gate recesses are formed on the plurality of gate recesses; a plurality of sidewall spacers are formed covering the sidewalls of each of the gate recesses; and an air gap is formed between each pair of the sidewall spacers.

[0125] Due to the design of the semiconductor device disclosed herein, leakage current issues associated with smaller gate sizes can be effectively controlled by utilizing a recessed gate dielectric layer. Furthermore, both recessed and planar gates can be fabricated simultaneously, which helps reduce manufacturing costs.

[0126] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0127] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0128] 1A: Semiconductor Device 1B: Semiconductor Devices 10: Method 20: Method 101: Base 101TS: Top surface 103-1: Character line groove 103-3: Character line groove 107: Isolation Layer 110: Sidewall gap material 110a: Sidewall gap material 110b: Sidewall gap material 112: Trench 150: Insulation material layer 152: Insulation Part 160: Insulation material layer 170: Gap 200: Character Line Structure 201: Character line dielectric layer 203: Conductive layer at the bottom of the character line 205: Top conductive layer of character line 207: Character Line Cover Layer 300: Peripheral gate structure 301: Gate dielectric layer 303: Gate bottom conductive layer 305: Gate top conductive layer 306: Sacrificial sidewall spacer 307: Gate cap layer 308: Dielectric material layer 400: Concave Gate 401: Recessed Gate Dielectric Layer 403: Concave Gate Bottom Conductive Layer 403BP: Bottom section 403TS: Top surface 405: Conductive layer at the top of the recessed gate electrode 405BS: Bottom surface 405TS: Top surface 407: Depressed gate cap layer 407BS: Bottom section 511: First hard mask layer 513: First Pattern 515: Sacrificial spacer 517: Bottom hard mask layer 531: Lower level 533: Opening 535: First Auxiliary Layer 711: First insulating material layer 713: Interstitial Material Layer 721: First masking layer 723: Core layer 723S: Side 725: Second masking layer 727: Gate shielding layer 731: Gate dielectric material layer 733: First conductive material layer 735: Second conductive material layer 735BS: Bottom 737: Top Insulation Layer 737BS: Bottom AG: Air gap AR: Array Area D1: Distance GR: Gate Depression PR1: First Surrounding Area PR2: Second Surrounding Area S11: Steps S13: Steps S15: Steps S17: Steps S27: Steps T1: Thickness VL1: Vertical height VL2: Vertical height VL3: Vertical Height VL4: Vertical Height VY1: First Valley VY2: The Second Valley W1: Width W2: Width W3: Width Z: Direction

Claims

1. A semiconductor device, comprising: A base, comprising a first peripheral zone and a second peripheral zone; A plurality of recessed gates, each comprising: a recessed gate dielectric layer located within the first peripheral region and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, thereby forming a first valley; and a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer, wherein both ends of the recessed gate top conductive layer protrude above a top surface of the substrate; and a recessed gate cap layer located on the top conductive layer of the recessed gate; and a peripheral gate structure located on the second peripheral region, wherein an insulating portion is disposed in each of the plurality of recessed gates, and a gap surrounds the insulating portion, wherein the element density of the first peripheral region is greater than the element density of the second peripheral region.

2. The semiconductor device as claimed in claim 1, wherein the peripheral gate structure includes: A gate dielectric layer is located on the second peripheral region; a gate bottom conductive layer is located on the gate dielectric layer; a gate top conductive layer is located on the gate bottom conductive layer; and a gate cap layer is located on the gate top conductive layer.

3. The semiconductor device as claimed in claim 2, wherein the width of the gate dielectric layer is greater than the width of the recessed gate dielectric layer.

4. The semiconductor device as claimed in claim 3, wherein the gate dielectric layer and the recessed gate dielectric layer comprise the same material.

5. The semiconductor device as claimed in claim 3, wherein the gate bottom conductive layer and the recessed gate bottom conductive layer comprise the same material.

6. The semiconductor device as claimed in claim 3, wherein the gate top conductive layer and the recessed gate top conductive layer comprise the same material.

7. The semiconductor device as claimed in claim 3, wherein the gate cap layer and the recessed gate cap layer comprise the same material.

8. The semiconductor device as claimed in claim 1, wherein the insulating portion is rod-shaped.

9. The semiconductor device of claim 1, wherein the insulating portion is formed within the recessed gate cap layer and the insulating portion extends through the recessed gate top conductive layer to contact the recessed gate bottom conductive layer.

10. The semiconductor device as claimed in claim 9, wherein the gap is formed between the insulating portion, the recessed gate top conductive layer and the recessed gate cap layer.

11. A semiconductor device, comprising: A base, comprising a first peripheral zone and a second peripheral zone; A plurality of recessed gates, each comprising: a recessed gate dielectric layer located within the first peripheral region and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer located on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, thereby forming a first valley; and a recessed gate top conductive layer compliantly located on the first valley of the recessed gate bottom conductive layer, wherein both ends of the recessed gate top conductive layer protrude above a top surface of the substrate; and a recessed gate cap layer located on the top conductive layer of the recessed gate; and a peripheral gate structure located on the second peripheral region, wherein a plurality of sidewall spacers cover the sidewalls of the recessed gate, and an air gap is provided between the sidewall spacers.

12. The semiconductor device as claimed in claim 11, wherein the element density of the first peripheral region is greater than the element density of the second peripheral region.

13. The semiconductor device as claimed in claim 11, wherein the peripheral gate structure comprises: A gate dielectric layer is located on the second peripheral region; a gate bottom conductive layer is located on the gate dielectric layer; a gate top conductive layer is located on the gate bottom conductive layer; and a gate cap layer is located on the gate top conductive layer.

14. The semiconductor device as claimed in claim 12, wherein the width of the gate dielectric layer is greater than the width of the recessed gate dielectric layer.

15. The semiconductor device as claimed in claim 13, wherein the gate dielectric layer and the recessed gate dielectric layer comprise the same material.

16. The semiconductor device as claimed in claim 13, wherein the gate bottom conductive layer and the recessed gate bottom conductive layer comprise the same material.

17. The semiconductor device as claimed in claim 13, wherein the gate top conductive layer and the recessed gate top conductive layer comprise the same material.

18. The semiconductor device as claimed in claim 13, wherein the gate cap layer and the recessed gate cap layer comprise the same material.

19. The semiconductor device as claimed in claim 11, wherein the air gap is not sealed and the top of the air gap is exposed to the external environment.

20. The semiconductor device as claimed in claim 11, wherein the plurality of sidewall spacers are each formed of a carbon-containing material.

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