Memory device

Abstract

The memory device includes a first bit line group, a first row select circuit, a first data line, and a second data line. The first bit line group includes a first bit line and a second bit line. The first row select circuit is coupled to the first bit line and the second bit line. The first data line includes a first segment coupled to the first row select circuit. The second data line includes a second segment coupled to the first row select circuit. The first row select circuit electrically connects the first bit line to the first segment to transmit the first bit of normal data to the first segment, and electrically connects the second bit line to the second segment to transmit the first bit of error correction / detection code data to the second segment.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a memory device that can increase input / output bandwidth by providing additional bits. Prior Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used as the main memory of computers due to its cost-effectiveness. A DRAM device consists of multiple memory cells, each capable of storing one data bit, typically implemented using capacitors and transistors. Capacitors can be charged or discharged to represent the value of the data bit stored in the memory cell. For example, an empty capacitor represents a logic value of 0, while a fully charged capacitor represents a logic value of 1. As technology nodes shrink, memory cells become smaller, and capacitors will store a very limited amount of charge. To provide correctly interpretable data, DRAM devices utilize sense amplifiers to generate an output in a recognizable logic level format. Summary of the Invention

[0003] This application provides a memory device that can increase input / output bandwidth by providing additional bits.

[0004] The memory device includes a first bit line group, a first row select circuit, a first data line, and a second data line. The first bit line group includes a first bit line and a second bit line. The first row select circuit is coupled to the first bit line and the second bit line. The first data line includes a first segment coupled to the first row select circuit. The second data line includes a second segment coupled to the first row select circuit. The first row select circuit electrically connects the first bit line to the first segment to transmit the first bit of normal data to the first segment, and electrically connects the second bit line to the second segment to transmit the first bit of error correction / detection code data to the second segment.

[0005] Another memory device includes multiple memory cell arrays and multiple data sensing circuit regions. Each data sensing circuit region is arranged between two adjacent memory cell arrays, and each data sensing circuit region includes a main space and an extension space. The main space has multiple input / output pads to output normal stored data during normal data read operations. The extension space is arranged adjacent to the main space and has multiple extended input / output pads to output error correction / detection code data during error correction / detection code data read operations. At least the first bit of the normal stored data is generated from the extension space during normal data read operations.

[0006] In summary, the memory device of this embodiment provides a segmented data line structure and can transmit additional bits through at least one additional segment of the data lines. In this embodiment, the additional bits can be provided as error correction / detection codes to improve the data reliability of the memory device. Simple Explanation of the Diagram

[0007] Figure 1 illustrates a schematic diagram of a partial physical design of a memory device according to some embodiments. Figure 2 illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. Figures 3A and 3B illustrate schematic diagrams of a portion of a memory device according to another embodiment of the present invention. Figure 4 illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. Figure 5 illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. Figure 6 illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. Figure 7 illustrates a schematic diagram of a semiconductor device according to an embodiment of this application. Figure 8 illustrates a block diagram of a semiconductor device according to an embodiment of the present invention. Implementation

[0008] Reference will now be made to details of the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0009] The accompanying drawings provide a detailed description of embodiments of the present invention. It should be understood that the present invention is not intended to be limited to the specifically disclosed structural embodiments and methods, but rather that other features, elements, methods, and embodiments may be used to implement the present invention. Preferred embodiments are used to illustrate the present invention and not to limit its scope, which is defined by the claims. Various equivalent variations described below will be recognized by those skilled in the art.

[0010] As used in this article, the term "coupling" refers to operational coupling. In this sense, coupled projects are not necessarily directly connected, and there may be intervening projects between coupled projects.

[0011] Please refer to Figure 1, which illustrates a schematic diagram of a partial physical design of a memory device according to some embodiments. In Figure 1, the memory device 100 may be implemented as a dynamic random access memory (DRAM) library comprising multiple modules 102 arranged in an array. Each module 102, also referred to as a memory array tile (MAT), may include a cell array (CA) 110, a column decoder (RDEC) 120, and a sense amplifier (SA) block 130. The cell array 110 includes multiple memory cells arranged in columns and rows. Memory cells in a given column share a common word line extending in the column direction (not shown); memory cells in a given row are coupled to the same bit line extending in the row direction (not shown). The column decoder 120 is set and configured to activate the word line. Multiple sense amplifiers are arranged in the sense amplifier block 130. The sense amplifier block 130 is configured to sense and amplify data signals on the bit lines and provide sense signals to the corresponding data lines.

[0012] The memory device 100 may be implemented using, but is not limited to, an open bit-line architecture. For example, in a given column of the cell array 110, a portion of the storage cells in that column are coupled to a sense amplifier block at the top of the cell array 110 via a portion of bit lines, while another portion of the storage cells are coupled to another sense amplifier block at the bottom of the cell array 110 via another portion of bit lines.

[0013] The memory device 100 may further include a row selection circuit 140 configured to select a sense amplifier from a sense amplifier block and couple the selected sense amplifier to a data line group. For example, each bit line in the cell array 110 is coupled to a corresponding sense amplifier in the sense amplifier block 130. The row selection circuit 140 can be used to activate the row selection lines in the row selection line group {CSL} to select a bit line group arranged in the cell array 110, and then couple the selected bit line group to the data line group {LDL}. Each data line in the data line group {LDL} can be shared among multiple rows of memory cells in the cell array 110. It should be noted that the memory device 100 may be implemented with a hierarchical structure, wherein the data line group {LDL} may be referred to as a local data line group, which is coupled to a global data line group (not shown) arranged along the row direction.

[0014] Please refer to FIG2, which illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. The portion of the memory device 200 in FIG2 corresponds to the sense amplifier block 130 in FIG1. ​​The memory device 200 includes multiple bit line groups BLSe, BLS1 to BLS8, a data line group LDLS, a row selection circuit 210, and an additional row selection circuit 220. In this embodiment, the bit line group BLSe includes bit lines B0e and B1e, and the bit line groups BLS1 to BLS8 include bit lines B01, B11 to B08, and B18, respectively. Compared to the corresponding portion of a conventional memory device, the bit line group BLSe is an additional bit line group. More specifically, at least two technical effects can be obtained from the bit line group BLSe: one is to solve the problem caused by the segmentation of the data line group {LDL}, and the other is to provide error correction / detection code (ECC) data for the memory device 200. A detailed description of the bit line group BLSe will be provided in the following paragraphs.

[0015] Bit line group BLSe corresponds to multiple sense amplifiers SA0e and SA1e, and bit line groups BLS1 to BLS8 correspond to multiple sense amplifiers SA01, SA11 to SA08, and SA18, respectively. Sensing amplifiers SA0e and SA1e are further coupled to complementary bit lines B0eB and B1eB, respectively, and sensing amplifiers SA01, SA11 to SA08, and SA18 are further coupled to complementary bit lines B01B, B11B to B08B, and B18B, respectively. For simplicity, bit lines B0eB, B1eB, B01B, B11B to B08B, B18B, and the bit lines in another embodiment can also be considered as data bits of a memory device, since these bit lines are electrically connected to the storage cells of the memory device. In this embodiment, the signals on bit lines B0e, B1e, and B01 to B18 can be inverted to the signals on complementary bit lines B0eB, B1eB, and B01B to B18B, respectively. In this embodiment, the structures of each sense amplifier SA0e, SA1e, SA01, SA11 to SA08 to SA18 can be identical, and can be implemented by any sense amplifier circuit well known to those skilled in the art.

[0016] The row selection circuit 210 includes a plurality of switches formed of transistors. Each switch corresponds to each bit line B01 to B18 and is used to couple the corresponding bit line to a data line. Two adjacent switches of the row selection circuit 210 form a switch pair. The control terminals of the switch pair are respectively coupled to the row selection lines CSL0-1 to CSL3-2.

[0017] For example, in the row selection circuit 210, transistors T01 and T11 form two switches. Transistor T01 is coupled between segment SEG11 of bit line B01 and data line LDL-1. Transistor T11 is coupled between segment SEG21 of bit line B11 and data line LDL-2. The control terminals of transistors T01 and T11 are coupled to the same row selection line CSL0-1 and have the same on or off state according to the row selection signal on the row selection line CSL0-1. In detail, when the switch formed by transistor T01 is on, bit line B01 is coupled to segment SEG11 of data line LDL-1, and when the switch formed by transistor T11 is on, bit line B11 is coupled to segment SEG21 of data line LDL-2.

[0018] In this embodiment, bit line groups BLS1 to BLS4 can form a first bit line group, and bit line groups BLS5 to BLS8 can form a second bit line group. Row selection lines CSL0-1 to CSL3-1 can correspond to the first bit line group, and row selection lines CSL0-2 to CSL3-2 can correspond to the second bit line group. During operation, in the first bit line group, one of the row selection lines CSL0-1 to CSL3-1 can be activated to turn on the corresponding switch, while the others in CSL0-1 to CSL3-1 are deactivated. Similarly, in the second bit line group, one of the row selection lines CSL0-2 to CSL3-2 can be activated simultaneously to turn on the corresponding switch, while the others in CSL0-2 to CSL3-2 are deactivated. In this embodiment, the row selection line CSL0-1 corresponding to the first bit line group and the row selection line CSL0-2 corresponding to the second bit line group are activated by the same row selection signal CSL0, wherein the row selection signal CSL0 may include CSL0-1 and CSL0-2. The row selection line CSL1-1 corresponding to the first bit line group and the row selection line CSL1-2 corresponding to the second bit line group are activated by the same row selection signal CSL1, wherein the row selection signal CSL1 may include CSL1-1 and CSL1-2. The row selection line CSL2-1 corresponding to the first bit line group and the row selection line CSL2-2 corresponding to the second bit line group are activated by the same row selection signal CSL2, wherein the row selection signal CSL2 may include CSL2-1 and CSL2-2. Row selection line CSL3-1 corresponds to the first bit line group and the second bit line group, and row selection line CSL3-2 corresponds to the second bit line group and the third bit line group (not shown in the figure). The row selection lines CSL3-1 and CSL3-2 can be activated by the same row selection signal CSL3, wherein the row selection signal CSL3 may include CSL3-1, CSL3-e and CSL3-2.

[0019] In this embodiment, compared to the corresponding portion of a conventional memory device, data line LDL-1 can be divided into multiple segments SEG11 to SEG13. Data line LDL-2 can be divided into multiple segments SEG21 to SEG22 and an additional segment SEG2e. Each segment SEG11 to SEG13 can be used to transmit first data, and each segment SEG21 to SEG22 can be used to transmit second data. In addition, besides the first and second data, the additional segment SEG2e can also be used to transmit additional bits. In this embodiment, in data line LDL-1, adjacent segments SEG11 and SEG12 are separated by a gap X, and adjacent segments SEG12 and SEG13 are separated by another gap X. Similarly, in data line LDL-2, adjacent segments SEG2e and SEG21 are separated by a gap X, and adjacent segments SEG21 and SEG22 are also separated by another gap. In some embodiments, the width GW of the segments is within 1 μm. This size is suitable for implementation in Local Data Line (LDL) designs, enabling higher density LDL segments. In some embodiments, because the spacing 230 between two adjacent vias on an LDL segment is approximately 1.1 μm, and gaps X with a width GW within 1 μm can be introduced into the LDL mask design, the size of gap X and the density of LDL segments can be well controlled. In some embodiments, implementing gap X on the data line does not result in wasted space in the sense amplifier block, and it eliminates the need to place virtual patterns in the sense amplifier block or unit array.

[0020] The additional row selection circuit 220 includes switches formed by transistors Te0 and Te1, respectively. Transistor Te0 is coupled between bit line B0e and the additional segment SEG2e of data line LDL-2. Transistor Te1 is coupled between bit line B1e and the segment SEG11 of data line LDL-1. Transistors Te0 and Te1 are jointly controlled by the row selection signal CSL3 on the row selection line CSL3-e. When the row selection signal CSL3 on the row selection line CSL3-e is activated, the switches formed by transistors Te0 and Te1 are turned on, allowing bit line B0e to be coupled to the additional segment SEG2e of data line LDL-2, and bit line B1e to be coupled to the segment SEG11 of data line LDL-1. It can be seen that the additional segment SEG2e of data line LDL-2 can be used to provide or receive additional bits generated by the sense amplifier SA0e.

[0021] In this embodiment, in detail, the line segment used to receive four bits corresponding to the row selection signals CSL0-1 to CSL3-1 or CSL0-2 to CSL3-2 is a complete bit segment. For example, line segment SEG11 includes four addressable bits, which respectively read bit line B01 selected by row selection signal CLS0-1; bit line B12 selected by row selection signal CSL1-1; bit line B03 selected by row selection signal CSL2-1; and bit line B1e selected by row selection signal CSL3-e. Similarly, line segment SEG21 includes four addressable bits, which respectively read bit line B11 selected by row selection signal CLS0-1; bit line B02 selected by row selection signal CSL1-1; bit line B13 selected by row selection signal CSL2-1; and bit line B04 selected by row selection signal CSL3-1. Similarly, segments SEG12 and SEG22 are also complete bit segments.

[0022] In this embodiment, in detail, the additional segment SEG2e is an incomplete bit segment. For simplicity, segment SEG13 can also be considered an incomplete bit segment. During operation, when one of the row selection signals CSL0, CSL1, and CSL2 is activated, the corresponding data is output on segments SEG11 and SEG21, and there are no bits on the additional segment SEG2e. When the row selection signal CSL3 is activated, not only are the corresponding data output on segments SEG11 (i.e., the bits read from bit line B1e) and SEG21 (i.e., the bits read from bit line B04), but the additional segment SEG2e also includes an addressable bit read from bit line B0e selected by the row selection signal CSL3-e. On the other hand, when one of the row selection signals CSL0, CSL1, and CSL2 is activated, the corresponding data is output on segments SEG12 and SEG22, and there are no bits on segment SEG13. When the row selection signal CSL3 is activated, not only are the corresponding data outputs on segments SEG12 (i.e., bits read from bit line B14) and SEG22 (i.e., bits read from bit line B08), but segment SEG13 also includes an addressable bit read from bit line B18 selected by the row selection signal CSL3-2. Therefore, during the read operation of memory device 200, the addressable bits on the additional segments SEG2e and SEG13 can be considered as additional bits.

[0023] Therefore, in this embodiment, the bits on segments SEG11, SEG12, SEG21, and SEG22 represent major bits stored in the memory device 200. The bits on segments SEG2e and SEG13 are additional bits besides the normally stored data. According to this application, the additional bits can be provided as ECC, such as ECC or any other error correction / detection information. The number of additional bits for ECC correction can be adjusted by adding additional segments, additional row select lines, and additional sense amplifiers. More additional bits can perform a higher level of error correction / detection.

[0024] Please refer to FIG3A, which illustrates a schematic diagram of a portion of a memory device according to another embodiment of the present invention. The portion of the memory device 300 in FIG3A may also correspond to the sense amplifier block 130 in FIG1. ​​Furthermore, in this embodiment, unlike the embodiment of FIG2, the number of additional bits can be increased by setting more additional bit lines. For brevity, the detailed description of the additional bits on line segment SEG13 in FIG2 is omitted in the following paragraphs.

[0025] In Figure 3A, the memory device 300 includes additional bit line groups BLse0 to BLse7. Each additional bit line group BLse0 to BLse7 includes two bit lines. For example, additional bit line group BLse0 includes bit lines B1e0 and B0e0, additional bit line group BLse1 includes bit lines B1e1 and B0e1, and so on. The additional bit line groups BLse0 to BLse7 correspond to sense amplifiers SA10e, SA00e to SA17e, and SA07e, respectively. The sense amplifiers SA10e, SA00e to SA17e, and SA07e are further coupled to complementary bit lines B1e0B, B0e0B to B1e7B, and B0e7B, respectively. Additional row selection circuits 321 and 322 include multiple switches formed by transistors Te10, Te00 to Te17, and Te07, respectively. Furthermore, in this embodiment, data line LDL-1 further includes additional segments SEG1e1 and SEG1e2, and data line LDL-2 further includes additional segments SEG2e1 and SEG2e2. Compared to the embodiment shown in FIG. 2, the length of the additional segment SEG2e1 of the second data line LDL-2 is extended to become a complete segment. The additional segments SEG1e1 and SEG1e2 are separated by a gap X, and the additional segments SEG2e1 and SEG2e2 are also separated by a gap X. The width GW of each gap X between two adjacent segments can be within 1 μm. However, this is not a limitation of the invention. The width GW can be adjusted according to the spacing between two adjacent through-holes on the segment.

[0026] In this embodiment, the bit line group BLS1 includes bit lines B01 and B11. Transistors T01 and T11 are arranged in the row selection circuit 320. Transistor T01 is coupled between bit line B01 and segment SEG11, and transistor T11 is coupled between bit line B11 and segment SEG21. Transistor T01 is used to electrically connect bit line B01 to segment SEG11 to transmit bits of general data from bit line B01 to segment SEG11. Transistor T11 is used to electrically connect bit line B11 to segment SEG21 to transmit bits of general data from bit line B11 to segment SEG21. In some embodiments, line segment SEG21 and line segment SEG2e1 are separated by gap X, wherein the gap X between line segment SEG11 and line segment SEG1e1 and the gap X between line segment SEG21 and line segment SEG2e1 can form a straight line, and this straight line is perpendicular to data line LDL-1 and data line LDL-2.

[0027] In detail, in the row selection circuit 321, a switch formed by transistor Te10 is coupled between the sensing amplifier SA10e and the data line LDL-1 segment SEG11; a switch formed by transistor Te00 is coupled between the sensing amplifier SA00e and the additional segment SEG2e1 of the data line LDL-2; a switch formed by transistor Te11 is coupled between the sensing amplifier SA11e and the additional segment SEG2e1 of the data line LDL-2; and a switch formed by transistor Te01 is coupled between the sensing amplifier SA01e and the additional segment SEG1e1 of the data line LDL-1. Furthermore, a switch formed by transistor Te12 is coupled between the sense amplifier SA12e and the additional segment SEG1e1 of the data line LDL-1; a switch formed by transistor Te02 is coupled between the sense amplifier SA02e and the additional segment SEG2e1 of the data line LDL-2; a switch formed by transistor Te13 is coupled between the sense amplifier SA13e and the additional segment SEG2e1 of the data line LDL-2; and a switch formed by transistor Te03 is coupled between the sense amplifier SA03e and the additional segment SEG1e1 of the data line LDL-1.

[0028] Furthermore, in the row selection circuit 322, a switch formed by transistor Te14 is coupled between the sensing amplifier SA14e and the additional segment SEG1e1 of the data line LDL-1; a switch formed by transistor Te04 is coupled between the sensing amplifier SA04e and the additional segment SEG2e2 of the data line LDL-2; a switch formed by transistor Te15 is coupled between the sensing amplifier SA15e and the additional segment SEG2e2 of the data line LDL-2; and a switch formed by transistor Te05 is coupled between the sensing amplifier SA05e and the additional segment SEG1e2 of the data line LDL-1. Furthermore, a switch formed by transistor Te16 is coupled between sense amplifier SA16e and additional segment SEG1e2 of data line LDL-1; a switch formed by transistor Te06 is coupled between sense amplifier SA06e and additional segment SEG2e2 of data line LDL-2; a switch formed by transistor Te17 is coupled between sense amplifier SA17e and additional segment SEG2e2 of data line LDL-2; and a switch formed by transistor Te07 is coupled between sense amplifier SA07e and additional segment SEG1e2 of data line LDL-1.

[0029] According to the present invention, in addition to normal data storage, the extra segments SEG1e1, SEG1e2, SEG2e1 and SEG2e2 are used to transmit extra bits, and the extra bits may be ECC.

[0030] In this embodiment, by arranging eight additional bit line groups BLSe0 to BLSe7, additional line segments SEG1e1 and SEG1e2 can provide seven additional bits, and additional line segments SEG2e1 and SEG2e2 can provide eight additional bits, providing a total of 15 additional bits in the memory device 300. In other embodiments, if four additional bit line groups are arranged, seven additional bits can be provided in the memory device.

[0031] It should be noted that in other embodiments, the number of data lines and additional bit groups can be adjusted according to user needs. For example, the number of data lines can be adjusted to 4, the number of additional bit groups can be adjusted to 4, and the memory device's bit group can provide 14 additional bits. By providing 14 additional bits for single error correction double error detection (SECDED), a codeword containing 2^13 bits can be checked and corrected. In some embodiments, the memory device includes n data lines and m groups of additional bit lines. The number of additional bits can be simplified to (n*m) - (n / 2). However, this is not a limitation. The number of additional bits can be adjusted by increasing or decreasing the number of data lines or additional bit groups.

[0032] Referring to Figure 3B, Figure 3B illustrates a schematic diagram of a portion of a memory device according to another embodiment of the present invention. The portion of memory device 300' in Figure 3B is similar to the portion of memory device 300 in Figure 3A. Unlike memory device 300, in memory device 300', the gaps X on data lines LDL-1 are aligned with the corresponding gaps X on data lines LDL-2 on the same straight line perpendicular to data lines LDL-1 and LDL-2. Thus, line segments SEG1e2 and SEG1e1 are aligned with the corresponding line segments SEG2e2 and SEG2e, respectively. Therefore, the layout complexity of memory device 300' is lower than that of memory device 300. In this embodiment, the width GW of each gap X can be within 1 μm. However, this is not a limitation of the present invention. The width GW can be adjusted according to the spacing between two adjacent vias on the line segment.

[0033] Referring to FIG4, FIG4 illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. In this embodiment, the memory device 400 may include four data lines LDL0 to LDL3, and a plurality of bit line groups. Each bit line group is controlled by signals on a plurality of row select lines CSL0-1 to CSL7-1 to CSL0-5 to CSL7-5. The memory device 400 further includes an additional bit line group controlled by control signals on additional row select lines CSL0-e to CSL7-e.

[0034] In this embodiment, each data line LDL0 to LDL3 is divided into multiple segments by multiple physical gaps GP. Specifically, data line LDL0 is divided into segments LDL0... <0> To LDL0 <5> Data line LDL1 is divided into line segments LDL1 <0> To LDL1 <5> The data line LDL2 is divided into line segments LDL2. <0> To LDL2 <5> ;and the data line LDL3 is divided into line segments LDL3 <0> Up to LDL3 <5> .

[0035] The row selection circuit of memory device 400 performs a selection operation among bit line groups in memory device 400 according to row selection lines CSL0-1~CLS7-1 to CSL0-5~CLS7-5, and couples each bit line in each selected bit line group to a corresponding segment of one of data lines LDL0~LDL3. The additional row selection circuit of memory device 400 selects one of additional bit line groups according to additional row selection lines CSL0-e to CSL7-e, and couples each bit line in the selected additional bit line group to a corresponding additional segment of one of data lines LDL0~LDL3.

[0036] It should be noted that the number of data lines and the number of bit groups can be adjusted by the designer according to the actual needs of the memory device. The illustration in Figure 4 is only an example and does not limit the scope of the invention.

[0037] In some embodiments, the gaps between the additional line segments may be aligned on the same straight line. In some embodiments, aligning gaps on the same straight line simplifies the design. In some embodiments, gaps aligned on the same straight line have the same width.

[0038] Please refer to Figure 5, which illustrates a schematic diagram of a portion of a memory device according to an embodiment of the present invention. The memory device has a main space MSPC and an extended space ECSL. The main space MSPC is the normal data input / output (I / O) space of the memory device, while the extended space ECSL is an additional storage I / O space in addition to the main space MSPC. In this embodiment, the main space MSPC is configured to have a plurality of I / O pads D0x8 to D3x8 to output normal stored data during normal data read operations. The extended space ECSL is arranged adjacent to the main space and is configured to have a plurality of extended I / O pads to output ECC data during ECC read operations, wherein at least one bit of the normal stored data is generated from the extended space during normal data read operations. More specifically, the main space MSPC is divided into 8 groups of memory spaces, each group controlled by 16 row select lines, i.e., CSL <15:0>. When one row select line is activated, each group can have four I / O pads to output four data bits on the four data lines, namely D0, D1, D2, and D3. In other words, in each group, the four I / O pads are electrically connected to the four data lines respectively. Therefore, when one row select line is activated, the eight memory spaces can output 32 bits of data (i.e., 4 bits * 8 groups) from the main space MSPC through 32 I / O pads (i.e., D3*8 + D2*8 + D0*8 + D1*8). Thus, the main space MSPC can have a memory capacity of 512 bits (i.e., 4 bits * 8 groups * 16 CSL).

[0039] On the other hand, the extended space ECSL is configured with four (or more) additional rows of memory space, thus outputting a total memory capacity of 16 bits. These four rows are controlled by four row select lines, namely CSL <3:0>. Similarly, when one row select line is activated, each row may output four data bits on four data lines via four I / O pads, namely D0, D1, D2, and D3. According to the present invention, the data bits D1 and D3 (i.e., the two data bits marked "X" in FIG5) controlled by row select line CSL 0 are allocated to the normal storage space. The reason has been described in the paragraphs related to FIG2-4 above, and for the sake of brevity, a detailed description is omitted here. Thus, 14 bits of additional data in the extended space ECSL can be output and used by the memory controller to perform ECC operations on data output from the main space MSPC. For example, performing a SECDED ECC operation on 512 bits of data output from the main space MSPC may require 10 bits of ECC. In this embodiment, the 14 extra bits output from the extended space ECSL are sufficient to perform a SECDED ECC operation on the data from the main space MSPC.

[0040] Furthermore, in Figure 5, in the extended space ECSL, data D3 controlled by the additional row select lines CSL1~CSL3, data D2 controlled by the additional row select lines CSL0~CSL3, data D1 controlled by the additional row select lines CSL1~CSL3, and data D0 controlled by the additional row select lines CSL0~CSL3 may be output to the controller through four different input / output (I / O) pads or vias that are electrically connected to the four data lines of the extended space ECSL.

[0041] Please refer to Figure 6, which is a schematic diagram illustrating the configuration of a memory device 600 according to an embodiment of the present invention. For simplicity, the capacity of the memory device 600 is similar to that of the memory device shown in Figure 5. The main space MSPC and the extended space ECSL are controlled by a row selection circuit 601. The main space MSPC is controlled by 16 row selection lines CSL <15:0>, and the extended space ECSL is controlled by 4 row selection lines CSL <3:0>. When one of the row selection lines in CSL <15:0> is activated, 32 bits of data (i.e., DQ<31:0>) are output from the main space MSPC. In addition, when one of the row selection lines in CSL <3:0> is activated, 4 bits of data (i.e., DQ<35:32>) are output from the extended space ECSL. It should be noted that when row select line CSL0 is activated, because the other 2 bits of data (i.e., D3 and D1) are allocated to the main space MSPC, only 2 bits of data (i.e., D2 and D0) are output from the extended space ECSL. For simplicity, a detailed description is omitted here. It can be seen that the size of the extended space ECSL, or circuit region A62, used to store ECC data, is smaller than the circuit region (i.e., A61 + A62) of the existing corresponding portion of the ECC data storage memory. More specifically, for performing ECC operations to access data, in the case of existing ECC data storage memory, the memory data length may extend to 36 bits (DQ<35:0>) to correspond to all row select lines CSL<15:0>, meaning that when one of the row select lines in CSL<15:0> is activated, 36 bits of data (i.e., DQ<35:0>) can be output from the memory space. In other words, circuit regions A61 and A62 are necessary for existing memory devices. Conversely, in this invention, only some (e.g., four line selection lines CSL<15:0>, CSL<3:0>) are connected to the extended space ECSL to output extended data DQ<35:32>. Therefore, only circuit region A62 is needed, and circuit region A61 can be saved. Thus, the circuit size of the memory device 600 can be reduced. It is worth noting that, according to this invention, the size of the extended space ECSL or the circuit region A62 is smaller than the size of the main space MSPC.

[0042] Furthermore, the memory controller can perform ECC operations after data in the main space MSPC has been read. In other words, the controller is configured to read ECC data in the extended space ECSL after the data in the main space MSPC has been read. Then, the memory controller can use the ECC data in the extended space ECSL to perform ECC operations on the data in the main space MSPC. For example, the memory controller can control the row select line CSL0 to read the corresponding ECC data in the extended space ECSL after the main data bits corresponding to row select line CSL0 in the main space MSPC have been read.

[0043] In some embodiments, the memory capacity of the main space MSPC can be expanded to 1024 bits by copying the original 512-bit main space. The original main space and the copied main space MSPC share the same region, which is also known as an open bit-line architecture. The original main space and the copied main space constitute the main space MSPC. Similarly, the extended space ECSL can also be expanded to 28 bits by copying the original 14-bit extended space. The original extended space and the copied extended space constitute the extended space ECSL. The 28 bits of data in the extended space ECSL can be used to perform a SECDED ECC operation on the 1024 bits of data in the main space MSPC. Note that the SECDED ECC operation is only an example, and those skilled in the art can modify the extended space ECSL to have an appropriate memory capacity according to different types of ECC operations.

[0044] Please refer to Figure 7, which illustrates a schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device 500 may be formed from two wafers 510 and 520, wherein wafers 510 and 520 are electrically stacked on top of each other. The semiconductor device 500 may be implemented using wafer-on-wafer (WoW) bonding technology. For example, one type of wafer-on-wafer bonding technology is hybrid bonding technology. For simplicity, the bonding between the two wafers 510 and 520 is shown as a dashed line in Figure 7.

[0045] Chip 510 includes multiple memory cell arrays (MCs) forming a memory device 511. Note that local data lines (LDLs) may be implemented in chip 510 along with their respective memory cell arrays (MCs). Chip 520 includes a controller comprising multiple logic circuits 521. The logic circuits 521 may be integrated with the memory cell arrays (MCs) in chip 510 via bonding processes or other integration methods well known to those skilled in the art. Each logic circuit 521 performs an ECC operation on its respective memory cell array (MC). Each logic circuit 521 may perform an ECC encoding operation or an ECC decoding operation. During a data write operation, each logic circuit 521 may perform an ECC encoding operation on the written data to generate an error correction code. Each logic circuit 521 further writes the written data and the corresponding error correction code into its respective memory cell array (MC). During a data read operation, stored data and corresponding ECC data can be read out, and each logic circuit 521 may perform an ECC decoding operation on the read stored data and corresponding ECC data to generate a symptom value. The logic circuit 521 checks the symptom value to determine whether the read stored data is correct, and can further correct erroneous bits in the read stored data through ECC operation. In some embodiments, the control logic may include a memory controller, an embedded memory controller, a processor, a central processing unit (CPU), or a graphics processing unit (GPU).

[0046] In this embodiment, ECC data can be transferred via additional bits through the LDL structure mentioned in the above embodiments. More specifically, ECC data can be transferred from the memory cell array MC in the two chips 510 to the logic circuit 521 through the junction between the two chips 510 and 520. The logic circuit 521 can first read the stored data from the corresponding memory cell array MC, then read the corresponding ECC data from the corresponding memory cell, and then perform the ECC operation. In some embodiments, each logic circuit 521 and each memory cell array MC can be placed horizontally rather than stacked vertically on a packaging substrate such as a package board or interposer.

[0047] Please note that each memory cell array (MC) may have its own additional bits, which are used to receive ECC data as detection or correction for that particular MC. In some embodiments, the additional bits of a particular MC are used to receive ECC data as detection or correction for another MC. In some embodiments, additional bits from multiple MCs are grouped and received as ECC data as detection or correction for the major bits in the multiple MCs.

[0048] In some embodiments, the memory device implemented by the semiconductor device 500 may include a memory controller. The memory controller may be disposed in the chip 520. The memory controller may be electrically coupled to the main space MSPC and the extended space ECSL shown in FIG. 6 via I / O pads 701 and extended I / O pads 702. The memory controller may receive normal storage data and ECC data via I / O pads 701 and extended I / O pads 702, respectively. Furthermore, in some embodiments, the memory controller may be further configured to perform ECC operations on the received normal storage data.

[0049] Please note that in some embodiments, the ECC decoder and ECC encoder may be arranged together with the corresponding memory cell array MC in the first chip 510. However, this is not a limitation. In some embodiments, the ECC decoder and ECC encoder may be arranged in the logic circuit 521 of the second chip 520 corresponding to the memory cell MC in the first chip 510.

[0050] Please refer to FIG8, which illustrates a block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 800 includes a controller 610 and a memory device 620. The controller 610 is electrically coupled to the memory device 620. The controller 610 includes an ECC circuit 611, which can be implemented by digital circuitry. The ECC circuit 611 is used to perform ECC operations based on additional bits transferred from the memory device 620. The memory device 620 includes a memory cell array 621, a word line (WL) decoder 622, a sense amplifier 623, and a row decoder 624. In this embodiment, a first portion of the memory cell array 621 can be used to store main bits, while another portion of the memory cell array 621 can be used to store additional bits. The additional bits may be error correction / detection information, such as ECC data. In some embodiments, the memory device 620 may be disposed in a first wafer 510, and the controller 610 may be disposed in a second wafer 520. In this embodiment, the memory cell array 621 may be a DRAM array.

[0051] The controller 610 is coupled to the WL decoder 622 and the line decoder 624, and transmits address information ADD to the WL decoder 622 and the line decoder 624. The WL decoder 622 and the line decoder 624 decode the address information ADD to access the memory cell array 621, and during the data readout operation, the memory cell array 621 can transmit the readout data to the controller 610 through the sense amplifier 623, wherein the readout data can be the major bits (MBIT, or normal stored data) or the extra bits (EBIT) described above.

[0052] The ECC circuit 611 may include multiple ECC decoders and ECC encoders. The memory cell array 621 may be divided into multiple parts, and the ECC decoders and ECC encoders may correspond to different parts of the memory cell array 621.

[0053] In this invention, a large number of I / O operations can be achieved through the segmentation of the Local Data Line (LDL) and Extra Bit Lines (EB-L) as shown in FIG1. ​​In some embodiments, the number of I / O operations can exceed 10,000. In some embodiments, the number of I / O operations can exceed 500,000. Therefore, high-bandwidth operation can be achieved on memory devices through a large number of I / O operations.

[0054] To those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

[0055] 100: Memory Device 102: Module 110: Cell Array 120: Column Decoder 130: Sensing Amplifier Block 140: Row selection circuit 200: Memory device 210, 220: Row selection circuit 230: Spacing 300, 300': Memory device 320, 321, 322: Row selection circuit 400: Memory Device 500: Semiconductor Devices 510: Chip 511: Memory Device 520: Chip 521: Logic Circuits 600: Memory Device 610: Controller 611: ECC circuit 620: Memory Device 621: Memory Cell Array 622: Word Line Decoder 623: Sensing Amplifier 624: Line Decoder 701: Input / Output Pads 702: Extended Input / Output Pads 800: Semiconductor Device A61, A62: Circuit Areas ADD: Address Information B01, B02, B03, B04, B05, B06, B07, B08, B11, B12, B13, B14, B15, B16, B17, B18, B0e, B1e, B0e0, B0e 1. B0e2, B0e3, B0e4, B0e5, B1e0, B1e1, B1e2, B1e3, B1e4, B1e5, B01B, B02B, B03B, B04B, B05B, B06 B, B07B, B08B, B11B, B12B, B13B, B14B, B15B, B16B, B17B, B18B, B0eB, B1eB, B0e0B, B0e1B, B0e2B, B0e3B, B0e4B, B0e5B, B0e6B, B0e7B, B1e0B, B1e1B, B1e2B, B1e3B, B1e4B, B1e5B, B1e6B, B1e7B: Bit lines BLS1, BLS2, BLS3, BLS4, BLS5, BLS6, BLS7, BLS8, BLSe, BLSe0, BLSe1, BLSe2, BLSe3, BLSe4, BLSe5, BLSe6, BLSe7: Bit line group CSL0-1, CSL0-2, CSL0-3, CSL0-4, CSL0-5, CSL1-1, CSL1-2, CSL1-3, CSL1-4, CSL1-5, CSL2-1, CSL2-2, C SL2-3, CSL2-4, CSL2-5, CSL3-1, CSL3-2, CSL3-3, CSL3-4, CSL3-5, CSL4-1, CSL4-2, CSL4-3, CSL4-4, CS L4-5, CSL5-1, CSL5-2, CSL5-3, CSL5-4, CSL5-5, CSL6-1, CSL6-2, CSL6-3, CSL6-4, CSL6-5, CSL7-1, CSL 7-2, CSL7-3, CSL7-4, CSL7-5, CSL0-e, CSL1-e, CSL2-e, CSL3-e, CSL4-e, CSL5-e, CSL6-e, CSL7-e: row selection line D0, D1, D2, D3: Data bits EBIT: Extra bits ECSL: Expanding Space GP: Solid gap GW: Width LDL0 <0> LDL0 <1> LDL0 <2> LDL0 <3> LDL0 <4> LDL0 <5> LDL1 <0> LDL1 <1> LDL1 <2> LDL1 <3> LDL1 <4> LDL1 <5> LDL2 <0> LDL2 <1> LDL2 <2> LDL2 <3> LDL2 <4> LDL2 <5> LDL3 <0> LDL3 <1> LDL3 <2> LDL3 <3> LDL3 <4> LDL3 <5> Line segment LDL0, LDL1, LDL2, LDL3: Data lines LDL-1, LDL-2: Data lines LDLS: Data Line Group MBIT: Principal Node MC: Memory Cell Array MSPC: Main Space SA01, SA02, SA03, SA04, SA05, SA06, SA07, SA08, SA11, SA12, SA13, SA14, SA15, SA16, SA17, SA18, SA0e, SA1e, SA00e, SA01e, SA02e, SA03e, SA04e, SA05e, SA06e, SA07e, SA10e, SA11e, SA12e, SA13e, SA14e, SA15e, SA16e, SA17e: Sensing Amplifier SEG11, SEG12, SEG13, SEG21, SEG22, SEG1e1, SEG1e2, SEG2e1, SEG2e, SEG2e1, SEG2e2: line segments T01, T11, Te0, Te1, Te00, Te01, Te02, Te03, Te04, Te05, Te06, Te07, Te1, Te10, Te11, Te12, Te13, Te14, Te15, Te16, Te17: Transistors X: Gap {CSL}: Row selection line group {LDL}: Data Line Group

Claims

1. A memory device, comprising: A first-bit line group includes a first-bit line and a second-bit line; A first row selection circuit is coupled to the first bit line and the second bit line; A first data line includes a first segment coupled to the first row selection circuit; A second data line, including a second segment coupled to the first row selection circuit; and a first through-hole, configured to be electrically coupled to the first segment; And a second via, configured to be electrically coupled to the second line segment; wherein, the first row selection circuit is configured to electrically connect the first bit line to the first line segment to transmit a first bit of normal data to the first line segment, and electrically connect the second bit line to the second line segment to transmit a first bit of error correction / detection code data to the second line segment, and the first via and the second via respectively transmit the first bit of the normal data and the first bit of the error correction / detection code data during a normal data read operation and an error correction / detection code data read operation.

2. The memory device as claimed in claim 1, further comprising: A memory controller is configured to be electrically coupled to the first via and the second via, to receive the first bit of the normal data and the first bit of the error correction / detection code data respectively during the normal data read operation and the error correction / detection code data read operation.

3. The memory device as claimed in claim 2, wherein the memory controller performs the error correction / detection code data read operation after the normal data read operation.

4. The memory device as claimed in claim 2, wherein the first data line further includes a third segment, and the memory device further includes: A second bit line group, including a third bit line and a fourth bit line; And a second row selection circuit coupled to the third bit line and the fourth bit line; wherein the second row selection circuit is used to electrically connect the third bit line to the third line segment to transmit a second bit of the error correction / detection code data to the third line segment, and electrically connect the fourth bit line to the second line segment to transmit a third bit of the error correction / detection code data to the second line segment.

5. The memory device as described in claim 4, further comprising: A third via is configured to be electrically coupled to the third line segment; wherein the memory controller is further configured to receive the second bit of the error correction / detection code data through the third via during the error correction / detection code data read operation, and to receive the third bit of the error correction / detection code data through the second via.

6. The memory device as claimed in claim 4, wherein the first line segment and the third line segment are separated by a first gap.

7. The memory device as claimed in claim 6, wherein the second data line further includes a fourth segment, and the memory device further includes: A third-bit line group, comprising a fifth-bit line and a sixth-bit line; A third row selection circuit is coupled to the fifth bit line and the sixth bit line; wherein the third row selection circuit is used to electrically connect the fifth bit line to the first line segment to transmit a second bit of the general data to the first line segment, and to electrically connect the sixth bit line to the fourth line segment to transmit a third bit of the general data to the fourth line segment, the second line segment and the fourth line segment are separated by a second gap, and the first gap and the second gap form a first straight line, the first straight line being perpendicular to the first data line and the second data line.

8. The memory device as claimed in claim 7, wherein the first data line further includes a fifth segment, and the second data line further includes a sixth segment, and the memory device further includes: A fourth bit line group, including a seventh bit line and an eighth bit line; A fourth row selection circuit is coupled to the seventh bit line and the eighth bit line; wherein the fourth row selection circuit is used to electrically connect the seventh bit line to the fifth line segment to transmit a fourth bit of the error correction / detection code data to the fifth line segment, and electrically connect the eighth bit line to the sixth line segment to transmit a fifth bit of the error correction / detection code data to the sixth line segment, the third line segment and the fifth line segment are separated by a third gap, the second line segment and the sixth line segment are separated by a fourth gap, and the third gap and the fourth gap form a second straight line, the second straight line being perpendicular to the first data line and the second data line.

9. The memory device as claimed in claim 8, further comprising: A fifth bit line group, including a ninth bit line and a tenth bit line; A fifth row selection circuit is coupled to the ninth bit line and the tenth bit line; wherein the fifth row selection circuit is used to electrically connect the ninth bit line to the third line segment to transmit a sixth bit of the error correction / detection code data to the third line segment, and to electrically connect the tenth bit line to the sixth line segment to transmit a seventh bit of the error correction / detection code data to the sixth line segment.

10. The memory device as claimed in claim 9, further comprising: A fourth through hole is provided for electrical coupling to the third line segment; And a fifth via, configured to be electrically coupled to the sixth line segment; wherein, the memory controller is further configured to be electrically coupled to the fourth via and the fifth via, to receive the sixth bit and the seventh bit of the error correction / detection code data during the error correction / detection code data read operation.

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