Dram device and method of manufacturing the same

Abstract

A DRAM device includes at least a substrate, a component isolation structure, multiple bit lines, multiple bit line contact windows, multiple spacer structures, and multiple capacitor landing contact windows. The component isolation structure is disposed in the substrate to define multiple active regions. The bit lines are disposed on the substrate. The bit line contact windows are located below the bit lines and connected to a first portion of the active regions, wherein each bit line contact window has a necking portion. The spacer structures extend vertically along the sidewalls of each bit line and the sidewalls of each bit line contact window. The capacitor landing contact windows are located between the bit lines and connected to a second portion of the active regions.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a dynamic random access memory (DRAM) device and a method of manufacturing the same. Prior Technology

[0002] As manufacturing processes shrink, bit line structures are becoming increasingly finer, and the distance between two bit lines is narrowing, leading to a significant increase in parasitic capacitance between bit lines. This parasitic capacitance directly affects the sensitivity of the DRAM device's sense margin (ΔV). Summary of the Invention

[0003] This invention provides a DRAM device and its manufacturing method, which are used to reduce parasitic capacitance.

[0004] A DRAM device according to one embodiment of the present invention includes at least a substrate, a component isolation structure, multiple bit lines, multiple bit line contact windows, multiple spacer structures, and multiple capacitor landing contact windows. The component isolation structure is disposed in the substrate to define multiple active regions. The bit lines are disposed on the substrate. The bit line contact windows are located below the bit lines and connected to a first portion of the multiple active regions, wherein each bit line contact window has a necking portion. The spacer structures extend vertically along the sidewalls of each bit line and the sidewalls of each bit line contact window. The capacitor landing contact windows are located between the multiple bit lines and connected to a second portion of the multiple active regions.

[0005] In one embodiment of the present invention, each bit line contact window has an upper portion located above the necked portion and a lower portion located below the necked portion, and the upper portion is in direct contact with the bit line.

[0006] In one embodiment of the present invention, the upper part is larger than the lower part, or the lower part is larger than the upper part.

[0007] In one embodiment of the present invention, the ratio of the minimum diameter of the necked portion to the maximum diameter of the bit line contact window is between 0.4 and 0.8.

[0008] In one embodiment of the present invention, the ratio of the height of the bit line contact window to the minimum diameter of the necking portion is between 4 and 10.

[0009] In one embodiment of the present invention, the bottom of the bit line contact window is located below the top of the element isolation structure.

[0010] In one embodiment of the present invention, each of the above-described spacer structures includes an inner spacer wall, an outer spacer wall, and a groove filler. The inner spacer wall is conformally disposed on the sidewall of each bit line and the sidewall of each bit line contact window. The outer spacer wall is located on one side of the inner spacer wall outside each bit line. The groove filler is disposed on this side of the inner spacer wall below the outer spacer wall.

[0011] In one embodiment of the present invention, the groove filler has a protrusion that corresponds to the necking portion of each bit line contact window.

[0012] In one embodiment of the present invention, the inner spacer is made of a low-k dielectric material, the outer spacer is made of an oxide, and the groove filler is a nitride filler.

[0013] In one embodiment of this disclosure, each capacitor landing contact window has a bottom located below the necked-out portion of each bit line contact window.

[0014] In one embodiment of the present invention, each bit line includes a barrier stack and a metal layer disposed on the barrier stack, wherein the barrier stack is disposed on the contact window of each bit line.

[0015] In one embodiment of the present invention, the metal layer is a tungsten layer, and the barrier stack includes a titanium film, a tungsten nitride film and a tungsten silicon film stacked in sequence.

[0016] A method for manufacturing a DRAM device according to another embodiment of the present invention includes providing a substrate; forming a device isolation structure in the substrate to define a plurality of active regions; forming a plurality of main contact windows in a portion of the substrate and a portion of the device isolation structure; forming a plurality of bit lines on the plurality of main contact windows above the substrate; side etching the plurality of main contact windows to form bit line contact windows having necking portions; having a plurality of vertically extending spacer structures on the sidewalls of each bit line and the sidewalls of each bit line contact window; and forming capacitor landing contact windows between the bit lines.

[0017] In another embodiment of the present invention, the step of forming the plurality of bit lines includes depositing a metal layer over a substrate; depositing a capping layer on the metal layer; patterning the capping layer to form a hard mask; and using the aforementioned hard mask as an etching mask to etch the metal layer.

[0018] In another embodiment of the present invention, after forming the above-mentioned bit lines, the main contact window is etched using the above-mentioned hard mask as an etching mask.

[0019] In another embodiment of the present invention, the step of forming the plurality of spacer structures includes conformally forming an inner spacer wall on the sidewall of each bit line and the sidewall of each bit line contact window; filling a groove with groove filler, wherein the groove is formed on the side of the plurality of bit line contact windows after the side etching; and forming an outer spacer wall on the inner spacer wall and the groove filler.

[0020] In another embodiment of the invention, the step of forming the plurality of capacitor landing contact windows includes forming a sidewall protection structure on the plurality of spacer structures to expose a portion of the active region; forming a polycrystalline silicon contact window to connect with the portion of the active region; and forming a plurality of landing metal pads above the polycrystalline silicon contact window.

[0021] Based on the above, the DRAM device according to the present invention can increase the distance between the bit line contact window and the capacitor landing contact window (including the cell contact window) to reduce the parasitic capacitance from BL (bit line) to CC (cell contact window).

[0022] To make the above features of the present invention more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0023] Figure 1 is a cross-sectional view of a DRAM device according to some embodiments of the present invention. Figure 2 is a perspective view of the bit line contact window of the DRAM device in Figure 1. Figures 3A to 3N are cross-sectional views of a manufacturing process of a DRAM device according to some embodiments of the present invention. Implementation

[0024] The invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for clarity and explicitness, the dimensions of each layer and region and their relative dimensions may not be shown to exact scale.

[0025] Figure 1 shows a cross-sectional view of a DRAM device according to some embodiments of the present invention.

[0026] Referring now to Figure 1, a DRAM device includes at least a substrate 100, a component isolation structure 102, multiple bit lines BL, multiple bit line contact windows BLC, multiple spacer structures 104, and multiple capacitor landing contacts 106. The component isolation structure 102 is disposed in the substrate 100 to define multiple active regions AA, wherein the component isolation structure 102 is, for example, an STI or other suitable structure. The bit lines BL are disposed on the substrate 100. In some embodiments, each bit line BL includes a barrier stack 114 and a metal layer 116 disposed on the barrier stack 114, wherein the barrier stack 114 is disposed on each bit line contact window BLC. In one example of this embodiment, the metal layer 116 is a tungsten layer, and the barrier stack 114 includes a titanium film 118, a tungsten nitride film 120, and a tungsten silicon film 122 stacked sequentially. However, this disclosure is not limited thereto; in some embodiments, the barrier stack 114 may be a double-layer stack or a multi-layer stack. In addition, an overlay layer CL can be optionally placed above each bit line BL as a mask or protective layer.

[0027] Referring again to Figure 1, multiple bit line contact windows (BLCs) are disposed below multiple bit lines (BLs) and connected to the first portion (a1) of multiple active regions (AAs), wherein each bit line contact window (BLC) has a necked portion (NP). In some embodiments, the bottom (BLCb) of the bit line contact window (BLC) is located below the top of the element isolation structure 102.

[0028] Figure 2 shows a perspective view of the bit line contact window (BLC) of the DRAM device of Figure 1. As shown in Figure 2, in some embodiments, a bit line contact window (BLC) has an upper portion (UP) located on the necking portion (NP) and a lower portion (LP) located below the necking portion (NP), and the upper portion (UP) is in direct contact with the bit line (BL) in Figure 1. The upper portion (UP) may be similar to the lower portion (LP) in size (e.g., volume, width, height, length, etc.), but is not limited thereto. In some embodiments, the upper portion (UP) is larger than the lower portion (LP). In some embodiments, the lower portion (LP) is larger than the upper portion (UP). In some embodiments, the ratio of the minimum diameter (d1) of the necking portion (NP) to the maximum diameter (d2) of the bit line contact window (BLC) is between 0.4 and 0.8; for example, between 0.5 and 0.75. In some embodiments, the ratio of the height (h1) of the bit line contact window (BLC) to the minimum diameter (d1) of the necking portion (NP) is between 4 and 10; for example, between 5 and 8.

[0029] Referring again to Figure 1, a plurality of spacer structures 104 extend vertically on the sidewall s1 of each bit line BL and the sidewall s2 of each bit line contact window BLC. The spacer structures 104 also extend vertically on the sidewall of the cover layer CL. In some embodiments, each spacer structure 104 includes an inner spacer wall 108, an outer spacer wall 110, and a recess filler 112. The inner spacer wall 108 is conformally disposed on the sidewall s1 of each bit line BL and the sidewall s2 of each bit line contact window BLC. The outer spacer wall 110 is located on one side of the inner spacer wall 108 outside each bit line BL. The recess filler 112 is disposed on this side of the inner spacer wall 108 below the outer spacer wall 110. In some embodiments, the inner spacer wall 108 may be disposed between the recess filler 112 and a first portion a1 of a plurality of active regions AA. In some embodiments, the recess filler 112 has a protrusion CP corresponding to a necking portion NP of each bit line contact window BLC. In some embodiments, the inner spacer 108 is made of a low-k dielectric material, the outer spacer 110 is made of an oxide, and the groove filler 112 is a nitride filler. However, this disclosure is not limited thereto; in some embodiments, the inner spacer 108 is not a low-k dielectric material but a silicon nitride layer.

[0030] The capacitor landing contact window 106 is disposed between multiple bit lines BL and connected to the second portion a2 of multiple active regions AA. In some embodiments, each capacitor landing contact window 106 has a bottom 106b located below the necking NP of the bit line contact window BLC. In some other embodiments, each capacitor landing contact window 106 has a bottom 106b located above the necking NP of the bit line contact window BLC. In some embodiments, each capacitor landing contact window 106 includes a polysilicon contact window 124, a buffer layer 126, a barrier layer 128, and a landing metal pad 130. The polysilicon contact window 124 is in direct contact with the second portion a2 of the multiple active regions AA. Due to the aforementioned necking NP, the distance between the bit line contact window BLC and the polysilicon contact window 124 can be increased to reduce parasitic capacitance. Therefore, the sensitivity of the sensing margin (ΔV) of the DRAM device can be improved. Meanwhile, the bottom BLCb of the bit line contact window BLC still maintains a large contact area with the active region AA, thereby avoiding an increase in contact resistance. The polysilicon contact window 124 is isolated from the bit line BL and the bit line contact window BLC through the spacer structure 104 and the sidewall protection structure 134 located between the spacer structure 104 and the capacitor landing contact window 106. In some other embodiments, the sidewall protection structure 134 may be omitted. In addition, a nitride layer 132 may be selectively provided on the substrate 100 as a hard mask for forming the bit line contact window BLC. In some embodiments, the buffer layer 126 may include a silicon layer. The barrier layer 128 may include a barrier metal, such as titanium nitride, on the buffer layer 126. The landing metal pad 130 may include a metal such as tungsten. A plurality of pad isolation insulators 136 may be formed to isolate the capacitor landing contact windows 106. In some embodiments, a capacitor structure (not shown) may be provided on each landing metal pad 130.

[0031] Figures 3A to 3N are cross-sectional views of the manufacturing process of a DRAM device according to some embodiments of the present invention, wherein the same or similar elements or regions are represented using the same element symbols as in Figure 1.

[0032] As shown in FIG. 3A, a substrate 100 is provided, and a device isolation structure 102 is formed in the substrate 100 to define a plurality of active regions AA. The plurality of active regions AA include at least a first portion a1 and a second portion a2. In some embodiments, the first portion a1 can be a source region and the second portion a2 can be a drain region. Primary contacts 300 are formed on a portion of the substrate 100 and a portion of the device isolation structure 102. The method of forming the primary contacts 300 may include forming a nitride layer 132 over the substrate 100, then patterning the nitride layer 132 to expose the first portion a1, then using the patterned nitride layer 132 as a hard mask to recess the upper part of the first portion a1, and then forming a conductive material as the primary contacts 300 in the recess, wherein the conductive material is, for example, polysilicon.

[0033] Referring to Figure 3B, in order to form multiple bit lines, the method may optionally include sequentially depositing a titanium film 118, a tungsten nitride film 120, and a tungsten silica film 122, then depositing a metal layer 116 on the tungsten silica film 122, and subsequently depositing a capping layer CL on the metal layer 116.

[0034] Referring to FIG3C, the cover layer CL can be patterned into a hard mask, and then the hard mask is used as an etching mask to etch the metal layer 116.

[0035] Referring to Figure 3D, a metal layer 116, a tungsten silicon film 122, a tungsten nitride film 120, and a titanium film 118 are sequentially etched to form a bit line BL, wherein a barrier stack 114 is formed. After forming the bit line BL, a hard mask (i.e., a capping layer CL) can be used as an etching mask to etch and form the main contact window. Since the nitride layer 132 has higher etch resistance than the device isolation structure 102 (e.g., silicon oxide), a plurality of grooves 302 are formed in the device isolation structure 102 and a portion of the first portion a1. Subsequently, the main contact window is etched laterally to form a bit line contact window BLC with a necking portion NP, wherein the etchant used for lateral etching is, for example, a silicon etchant.

[0036] Referring to Figure 3E, inner spacers 108 are conformally formed on the sidewalls s1 of each bit line BL and the sidewalls s2 of each bit line contact window BLC. The inner spacers 108 can be a low-k dielectric material such as SiCO or a silicon nitride layer.

[0037] Referring to Figure 3F, groove filler 304 can be used to fill the groove 302 located on the side of the bit line contact window (BLC), wherein the groove 302 can be filled by nitride refill deposition. Groove filler 304 can also be formed on the sidewall of the inner spacer 108.

[0038] Referring to Figure 3G, the groove filler 304 other than the groove 302 is removed to form the groove filler 112, and the inner spacer walls 108 on both sides of the bit line BL are exposed.

[0039] Referring to FIG3H, an outer spacer 110 is formed on the inner spacer 108 and the groove packing 112 to form a spacer structure 104.

[0040] Referring to Figure 3I, the outer spacer 110 is used as an etching mask to etch the inner spacer 108 and the structure below it until the second part a2 is exposed.

[0041] Referring to FIG3J, the sidewall protection structure 134 may be selectively formed to conformally cover the spacer structure 104. In some other embodiments, the formation of the sidewall protection structure 134 may be omitted.

[0042] Referring to Figure 3K, the sidewall protection structure 134 is anisotropically etched until the second portion a2 of the active region is exposed again. Then, using the sidewall protection structure 134 as an etching mask, the second portion a2 is etched to deepen the opening for forming the polysilicon contact window 124. The polysilicon contact window 124 and the buffer layer 126 are formed, and the polysilicon contact window 124 is connected to the second portion a2 of the active region. In Figure 3K, after the above etching steps, a round top can be formed on the top of the capping layer CL, the inner spacer 108, the outer spacer 110, and the sidewall protection structure 134. Compared with the case without the above side etching, the distance d3 between the bit line contact window BLC and the polysilicon contact window 124 after side etching can be increased, thereby reducing parasitic capacitance.

[0043] Referring to Figure 3L, a barrier layer 128 is conformally formed on the buffer layer 126, and a landing metal pad 130 is formed above the polycrystalline silicon contact window 124.

[0044] Referring to Figure 3M, an opening 306 is formed to separate the landing metal pad 130.

[0045] Referring to Figure 3N, a pad isolation insulator 136 is formed in the opening 306 to isolate the capacitor landing contact windows 106 between the metal layers 116.

[0046] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0047] 100:Substrate 102: Component isolation structure 104: Spacing structure 106: Capacitor landing contact window 106b, BLCb: Bottom 108: Inner partition wall 110: outer partition wall 112, 304: Groove packing 114: Barrier Stacking 116: Metal layer 118: Titanium film 120: Tungsten nitride film 122: Tungsten Silicide Film 124: Polycrystalline silicon contact window 126: Buffer layer 128: Barrier Layer 130: Landing Metal Pad 132: Nitride layer 134: Sidewall Protection Structure 136: Solder pad isolation insulator 300: Main Contact Window 302: Groove 306: Opening a1: Part 1 a2: Part Two AA: Active Zone BL: Bitline BLC: Bitline Contact Window CL: Overlay CP: Protrusion d1: minimum diameter d2: Maximum diameter d3: Distance h1: Height LP: Lower part NP: neck constriction s1, s2: sidewalls UP: upper part

Claims

1. A DRAM device, comprising: substrate; A component isolation structure is disposed in the substrate to define multiple active regions; Multiple bit lines are disposed on the substrate; Multiple bit line contact windows are disposed below the multiple bit lines and connected to a first portion of the multiple active areas, wherein each of the multiple bit line contact windows has a necked portion, an upper portion located on the necked portion and a lower portion located below the necked portion, and the minimum diameter of the necked portion is smaller than the width of the upper portion and the minimum diameter of the necked portion is smaller than the width of the lower portion. Multiple spacer structures extend vertically onto the sidewall of each of the multiple bit lines and onto the sidewall of each of the multiple bit line contact windows; And multiple capacitor landing contact windows, disposed between the multiple bit lines and connected to the second portion of the multiple active regions.

2. The DRAM device as claimed in claim 1, wherein the upper portion is in direct contact with the bit line.

3. The DRAM device as claimed in claim 2, wherein the upper portion is larger than the lower portion.

4. The DRAM device as claimed in claim 2, wherein the lower portion is larger than the upper portion.

5. The DRAM device of claim 1, wherein the ratio of the minimum diameter of the necking portion to the maximum diameter of the bit line contact window is between 0.4 and 0.

8.

6. The DRAM device of claim 1, wherein the ratio of the height of the bit line contact window to the minimum diameter of the necking portion is between 4 and 10.

7. The DRAM device as claimed in claim 1, wherein the bottom of the plurality of bit line contact windows is located below the top of the element isolation structure.

8. The DRAM device as claimed in claim 1, wherein each of the plurality of spacing structures comprises: The inner partition wall is conformally disposed on the sidewall of each of the plurality of bit lines and on the sidewall of each of the plurality of bit line contact windows; An outer partition wall is disposed on one side of the inner partition wall, outside each of the plurality of bit lines; And groove filler, disposed on the side of the inner partition wall below the outer partition wall.

9. The DRAM device of claim 8, wherein the groove filler has a protrusion corresponding to the necking portion of each of the plurality of bit line contact windows.

10. The DRAM device of claim 8, wherein the inner spacer is made of a low-k dielectric material, the outer spacer is made of an oxide, and the groove filler is a nitride filler.

11. The DRAM device of claim 1, wherein each of the plurality of capacitor landing contact windows has a bottom located below the necking portion of each of the plurality of bit line contact windows.

12. The DRAM apparatus of claim 1, wherein each of the plurality of bit lines comprises: A barrier stack is disposed on each of the plurality of bit line contact windows; And a metal layer, disposed on the barrier stack.

13. The DRAM device of claim 12, wherein the metal layer is a tungsten layer, and the barrier stack comprises a titanium film, a tungsten nitride film, and a tungsten silicon film stacked in sequence.

14. A method for manufacturing a DRAM device, comprising: Provide substrate; A component isolation structure is formed in the substrate to define multiple active regions; A plurality of main contact windows are formed in a portion of the substrate and a portion of the element isolation structure; Multiple bit lines are formed on the plurality of main contact windows above the substrate; the plurality of main contact windows are side-etched to form a plurality of bit line contact windows having a necked portion, an upper portion located on the necked portion and a lower portion located below the necked portion, wherein the minimum diameter of the necked portion is smaller than the width of the upper portion and the minimum diameter of the necked portion is smaller than the width of the lower portion. Multiple vertically extending spaced structures are formed on the sidewall of each of the plurality of bit lines and on the sidewall of each of the plurality of bit line contact windows. And multiple capacitor landing contact windows are formed between the multiple bit lines.

15. A method of manufacturing a DRAM device as claimed in claim 14, wherein the step of forming the plurality of bit lines includes: A metal layer is deposited on the substrate; Deposit a capping layer on the metal layer; The overlay layer is patterned to form a rigid mask; And using the hard mask as an etching mask to etch the metal layer.

16. A method of manufacturing a DRAM device as claimed in claim 15, wherein after the step of forming the plurality of bit lines, the method further comprises: The hard mask is used as an etching mask to etch the plurality of main contact windows.

17. A method of manufacturing a DRAM device as claimed in claim 14, wherein the step of forming a plurality of spacer structures includes: An inner spacer wall is conformally formed on the sidewall of each of the plurality of bit lines and on the sidewall of each of the plurality of bit line contact windows; a plurality of grooves are filled with groove filler, wherein the plurality of grooves are formed on the sidewalls of the plurality of bit line contact windows after the side etching; and an outer spacer wall is formed on the inner spacer wall and the groove filler.

18. A method of manufacturing a DRAM device as claimed in claim 14, wherein the step of forming the plurality of capacitor landing contact windows includes: Sidewall protection structures are formed on the plurality of spacer structures to expose a portion of the plurality of active regions; Multiple polycrystalline silicon contact windows are formed to connect with portions of the multiple active regions; And a plurality of landing metal pads are formed above the plurality of polycrystalline silicon contact windows.

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