Method of forming semiconductor device

Abstract

A method for forming a semiconductor device includes the following steps: forming trenches in a semiconductor layer; performing a surface treatment to reduce the surface roughness of the trenches; and forming an oxide layer in the trenches.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a method for forming a semiconductor device. Prior Technology

[0002] In the semiconductor industry, gate structures can be formed as buried gate structures within a semiconductor substrate. To form a buried gate structure, trenches are first formed in the semiconductor substrate. Generally, the surface of the trenches is not smooth, which affects the subsequent formation of the gate oxide layer. A poorly formed gate oxide layer can lead to a high risk of gate-induced drain leakage and degrade device performance. Furthermore, during trench formation, some charge may become trapped in the semiconductor layer, and this trapped charge can cause crosstalk between adjacent gate structures, further degrading device performance. Therefore, it is necessary to find solutions to eliminate these problems. Summary of the Invention

[0003] The present invention provides a method for forming a semiconductor device, which can improve the performance of the semiconductor device.

[0004] The method for forming a semiconductor device according to the present invention includes the following steps: forming trenches in a semiconductor layer; performing a surface treatment to reduce the surface roughness of the trenches; and forming an oxide layer in the trenches.

[0005] In an embodiment of the method of the present invention, the surface treatment is a hydrogenation treatment.

[0006] In embodiments of the method of the present invention, the surface treatment includes performing a rapid thermal annealing process containing hydrogen.

[0007] In embodiments of the method of the present invention, the surface treatment process temperature is in the range of 500 degrees Celsius to 900 degrees Celsius.

[0008] In embodiments of the method of the present invention, the surface treatment process time is in the range of 5 to 90 seconds.

[0009] In an embodiment of the method of the present invention, the surface roughness of the trench is reduced by 40% to 60% after surface treatment.

[0010] In an embodiment of the method of the present invention, Si-H bonds are formed on the surface of the trench after surface treatment is performed.

[0011] In an embodiment of the method of the present invention, the oxide layer is formed by a thermal oxidation process.

[0012] In an embodiment of the method of the present invention, forming a trench in a semiconductor layer includes the following steps: forming a hard mask layer on the semiconductor layer; patterning the hard mask layer to expose a portion of the top surface of the semiconductor layer; and using the patterned hard mask layer as an etching mask to remove a portion of the semiconductor layer to form a trench.

[0013] In embodiments of the method of the present invention, the method further includes the following steps: forming a word line structure in a trench; forming source / drain regions in a semiconductor layer.

[0014] Based on the above, the semiconductor device includes a buried word line structure in a semiconductor layer and an oxide layer between the word line structure and the semiconductor layer. Because surface treatment is performed on the trenches of the semiconductor layer before forming the oxide layer, the oxide layer can be formed uniformly and has a smooth surface, and trapped charges in the semiconductor layer are reduced, thereby improving the performance of the semiconductor device.

[0015] To make the foregoing easier to understand, several embodiments are described in detail below with reference to the accompanying drawings. Simple Explanation of the Diagram

[0016] Figures 1 to 6 are schematic cross-sectional views of a method for forming a semiconductor device according to an embodiment of the present invention. Implementation

[0017] The embodiments are described in detail below with reference to the accompanying drawings, but these embodiments are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same elements will be indicated by the same reference numerals in the following description.

[0018] In this document, terms such as “comprising,” “including,” “containing,” and “having” are open-ended terms, meaning “including but not limited to.”

[0019] When terms such as "first" and "second" are used to describe elements, they are only used to distinguish the elements from each other and do not limit the order or importance of the devices. Therefore, in some cases, a first element may also be referred to as a second element, and a second element may also be referred to as a first element, which does not exceed the scope of this invention.

[0020] Furthermore, directional terms mentioned in the text, such as "above," "on top of," "below," and "under," are used only to refer to the directions illustrated and are not intended to limit the invention.

[0021] Furthermore, the use of "from one value to another" to indicate a range is a general expression to avoid listing all values ​​within a range in the specification. Therefore, a description of a specific value range includes any value within that range, as well as the smaller range of values ​​defined by any value within that range.

[0022] Figures 1 to 6 are schematic cross-sectional views of a method for forming a semiconductor device 10 according to an embodiment of the present invention.

[0023] Referring to FIG. 1, a trench T is formed in the semiconductor layer 100. For example, firstly, a hard mask layer 102 is formed on the semiconductor layer 100 by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or other suitable methods. The hard mask layer 102 is patterned by a photolithography and etching process to expose a portion of the top surface of the semiconductor layer 100. In some embodiments, the semiconductor layer 100 comprises silicon, germanium, silicon-germanium, silicon carbide, or other suitable semiconductor materials. In some embodiments, the semiconductor layer 100 may be an epitaxial layer formed on a semiconductor substrate. In some embodiments, the hard mask layer 102 comprises silicon nitride or other suitable materials.

[0024] Then, using a hard mask layer 102 as an etching mask, a portion of the semiconductor layer 100 is removed by an etching process to form a trench T. In some embodiments, the etching process is a dry etching process, such as plasma etching, reactive ion etching, or a similar process. In some embodiments, the etching gas for the trench etching process includes CF4, SF6, XeF2, CCl4, their radicals or ions, or the like. Although only one trench T is shown in Figure 1, it should be understood that the number of trenches T is not limited and can be adjusted as needed.

[0025] In some embodiments, during trench T formation, the etching process damages the semiconductor layer 100 and forms defects (e.g., dangling bonds, trapped charges, or the like) in the semiconductor layer 100. The formation of dangling bonds DB can weaken the lattice of the semiconductor layer 100 near the trench T, and roughen the surface S of the trench T. The surface roughness of the trench T can affect the formation of the subsequently formed oxide layer. When the surface roughness of the trench T is high, the subsequently formed oxide layer may have a rough surface and may not form uniformly on the surface S of the trench T, thus potentially increasing the risk of leakage current in the semiconductor device 10. Furthermore, trapped charges may be free radicals or ions trapped or remaining in the semiconductor layer 100 during or after trench T formation, or may be inherently present in the semiconductor layer 100. Trapped charges in the semiconductor layer 100 can cause crosstalk and interfere with the signal transmission of the semiconductor device 10.

[0026] Referring to Figure 2, a surface treatment P is performed to reduce the surface roughness of the trench T. Surface treatment P is a hydrogenation process. In some embodiments, surface treatment P is a rapid thermal hydrogenation process. In some embodiments, a rapid thermal annealing process containing hydrogen is performed on the trench T. For example, a gas stream comprising hydrogen is introduced into the system simultaneously with the rapid thermal annealing process. In some embodiments, the gas stream is a pure hydrogen gas stream. That is, the gas stream contains approximately 100% hydrogen by volume. In some embodiments, the flow rate of the gas stream is in the range of 4 standard liters per minute (slm) to 16 slm.

[0027] In some embodiments, prior to surface treatment, an inert gas stream may be introduced into the trench T to remove impurities from the surface S of the trench T. In some embodiments, the inert gas stream includes nitrogen, argon, or other suitable inert gas. In some embodiments, after surface treatment, an additional inert gas stream may be introduced into the trench T to assist in cooling.

[0028] During the rapid thermal annealing process, hydrogen decomposes into hydrogen radicals (H*). These hydrogen radicals can contact the surface S of the trench T and repair the dangling bonds DB to form Si-H bonds. In addition, silicon migration may occur under thermal conditions. This stabilizes the lattice arrangement of the semiconductor layer 100 and also makes the surface S of the trench T smooth.

[0029] In some embodiments, the surface roughness of the trench T is reduced by 40% to 60% after surface treatment P is performed. For example, before surface treatment P, the surface roughness of the trench is approximately 0.15 nm to 0.25 nm or higher, while after surface treatment P, the surface roughness of the trench becomes approximately 0.09 nm to 0.11 nm. This reduction in the surface roughness of the trench T benefits the uniformity and roughness of the subsequently formed oxide layer.

[0030] In some embodiments, some hydrogen radicals may diffuse into the semiconductor layer 100 to neutralize trapped charges. As the trapped charges in the semiconductor layer 100 are neutralized, the number of trapped charges in the semiconductor layer 100 is reduced, which can mitigate crosstalk caused by trapped charges. In some embodiments, the neutralized trapped charges may contribute to the stability of the subsequently formed oxide layer.

[0031] In some embodiments, the process temperature of surface treatment P is in the range of 500 to 900 degrees Celsius to promote silicon migration and hydrogen decomposition.

[0032] In some embodiments, the process time of surface treatment P is in the range of 5 to 90 seconds to maintain a low thermal budget while smoothing the surface S of the trench T.

[0033] Referring to Figure 3, an oxide layer 110 is formed in the trench T. For example, the oxide layer 110 is formed by a thermal oxidation process. That is, the surface S of the trench T is oxidized to form the oxide layer 110. In embodiments where the semiconductor layer 100 includes silicon, the silicon is oxidized to form silicon oxide. That is, the oxide layer 110 is a silicon oxide layer. Since the surface of the trench T is smoothed by the surface treatment P, the oxide layer 110 can be uniformly formed in the trench T and has a smooth surface, thereby reducing the risk of leakage current in the semiconductor device 10.

[0034] In some embodiments, Si-H bonds may break during the thermal oxidation process, and hydrogen atoms may be released into the environment. In other embodiments, a small number of Si-H bonds may remain in the semiconductor layer 100 after the oxide layer 110 is formed.

[0035] In some embodiments, the process temperature of the thermal oxidation process is between 800 degrees Celsius and 1100 degrees Celsius, but is not limited thereto.

[0036] Referring to Figures 4 and 5, a word line structure 120 (also referred to as gate structure 120) is formed in a trench T. For example, in Figure 4, a barrier layer 122 is formed on an oxide layer 110 in the trench T. Then, in Figure 5, a conductive layer 124 is formed in the trench T, and a capping layer 126 is formed on the conductive layer 124 in the trench T. The barrier layer 122, the conductive layer 124, and the capping layer 126 together form the word line structure 120.

[0037] In some embodiments, the barrier layer 122 is conformally formed by physical vapor deposition (e.g., sputtering or similar methods) or other suitable methods. In some embodiments, the material of the barrier layer 122 includes titanium nitride, tantalum nitride, tantalum, or other suitable materials to prevent metal diffusion into the semiconductor layer 100.

[0038] In some embodiments, the formation of the conductive layer 124 includes the following steps: a conductive material is formed in a trench T using a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or other suitable methods; an etching process is then performed to remove a portion of the conductive material, leaving the remaining conductive material as the conductive layer 124. In some embodiments, the conductive layer 124 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the conductive layer 124 includes polycrystalline silicon, a metal (e.g., copper, tungsten, aluminum, titanium, or the like), a metal nitride, or other suitable conductive materials.

[0039] In some embodiments, the formation of the capping layer 126 includes the following steps: an insulating material is formed in the trench T and on the hard mask layer 102 by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or other suitable methods, and a planarization process (e.g., a chemical mechanical polishing process or a similar method) is performed to remove excess insulating material to expose the top surface of the hard mask layer 102, thereby forming the capping layer 126. In some embodiments, the material of the capping layer 126 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials.

[0040] Referring to Figure 6, source / drain regions 130 are formed in semiconductor layer 100. Source / drain regions 130 are formed via an ion implantation process. Source / drain regions 130 are located on opposite sides of the trench and adjacent to the top surface of semiconductor layer 100. Word line structure 120 and source / drain regions 130 together form a transistor in semiconductor layer 100.

[0041] In some embodiments, the semiconductor device 10 may be a memory device, but is not limited thereto. In some embodiments, a capacitor structure (not shown) may be formed on the semiconductor layer 100 and electrically connected to the source / drain regions 130 of the transistor to form a memory cell on the semiconductor layer 100.

[0042] Based on the above, the formation of the semiconductor device 10 can be largely completed. The semiconductor device 10 includes a buried word line structure 120 in the semiconductor layer 100 and an oxide layer 110 between the word line structure 120 and the semiconductor layer 100. Since a surface treatment P is performed on the trenches T of the semiconductor layer 100 before forming the oxide layer 110, the oxide layer 110 can be formed uniformly and has a smooth surface, and the trapped charge in the semiconductor layer 100 is reduced, thereby improving the performance of the semiconductor device 10.

[0043] Various modifications and variations can be made to the disclosed embodiments by those skilled in the art without departing from the scope or spirit of the disclosure. In view of the foregoing, it is contemplated that the disclosure covers modifications and variations as long as they fall within the scope of the following claims and their equivalents.

[0044] 10: Semiconductor devices 100: Semiconductor layer 102: Rigid Coverage Layer 110: Oxide layer 120: Word line structure / gate structure 122: Barrier Layer 124: Conductive layer 126: Covering layer 130: Source / Drain Region DB: Floating Key P: Surface treatment S: Surface T: Trench

Claims

1. A method of forming a semiconductor device, comprising: Trenches are formed in the semiconductor layer; Perform a surface treatment to reduce the surface roughness of the trench, wherein the surface treatment includes performing a rapid thermal annealing process containing hydrogen on the trench to repair the suspended bonds on the surface of the trench and to form Si-H bonds on the surface of the trench, wherein the surface treatment does not include forming a sacrificial oxide layer in the trench; forming an oxide layer in the surface-treated trench; and forming word line structures on the oxide layer in the trench.

2. The method of claim 1, wherein the surface treatment process temperature is in the range of 500 degrees Celsius to 900 degrees Celsius.

3. The method as described in claim 1, wherein the process time for the surface treatment is in the range of 5 seconds to 90 seconds.

4. The method as described in claim 1, wherein after performing the surface treatment, the surface roughness of the trench is reduced by 40% to 60%.

5. The method of claim 1, wherein the oxide layer is formed by a thermal oxidation process.

6. The method of claim 1, wherein forming the trench in the semiconductor layer comprises: A hard mask layer is formed on the semiconductor layer; Pattern the hard mask layer to expose a portion of the top surface of the semiconductor layer; And using the patterned hard mask layer as an etching mask, a portion of the semiconductor layer is removed to form the trench.

7. The method as described in claim 1, further comprising: Source / drain regions are formed in the semiconductor layer.

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