Semiconductor manufacturing apparatus and method

Abstract

The wafer processing apparatus disclosed herein includes an inner cup, a middle cup, an outer cup, and a separator. The inner cup includes a first cup wall and a first bottom surface. The middle cup surrounds the inner cup and includes a second cup wall and a second bottom surface between the first cup wall and the second cup wall. The outer cup surrounds the middle cup and includes a third cup wall and a third bottom surface between the second cup wall and the third cup wall. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator rises above the second bottom surface.

Description

Technical Field

[0001] This disclosure relates to semiconductor manufacturing equipment and semiconductor manufacturing methods. Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. Such scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Optical lithography is a critical process in IC manufacturing. During lithography, one or more developers or developer solutions are applied to the wafer to develop the lithographic image. Multiple pick-up cups can be installed to prevent the developer or solvent from detaching from the wafer as it rotates during the development process. When different developer solutions are allowed to mix, crystals may form in the discharge terminals, reducing discharge efficiency and causing environmental pollution. Summary of the Invention

[0004] In one example, this disclosure provides an apparatus for semiconductor manufacturing. The apparatus includes an inner cup, a middle cup, an outer cup, and a separator. The inner cup includes a first cup wall and a first bottom surface. The middle cup surrounds the inner cup and includes a second cup wall and a second bottom surface between the first cup wall and the second cup wall. The outer cup surrounds the middle cup and includes a third cup wall and a third bottom surface between the second cup wall and the third cup wall. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator rises above the second bottom surface.

[0005] Another aspect of this disclosure relates to a semiconductor manufacturing apparatus. The apparatus includes an inner cup, a middle cup, an outer cup, a separator, a first discharge port, a second discharge port, and a third discharge port. The inner cup includes a first cup wall and a first bottom surface. The middle cup surrounds the inner cup and includes a second cup wall and a second bottom surface between the first cup wall and the second cup wall. The outer cup surrounds the middle cup and includes a third cup wall and a third bottom surface between the second cup wall and the third cup wall. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator is raised above the second bottom surface. When the separator is in the second position, the second bottom surface is divided by the separator into an inner bottom surface wall adjacent to the first cup and an outer bottom surface away from the first cup wall. The first discharge port is in the inner bottom surface, the second discharge port is in the outer bottom surface, and the third discharge port is in the third bottom surface.

[0006] Another aspect of this disclosure relates to a method of semiconductor manufacturing. The method includes placing a first wafer on a wafer holder mechanically fixed to a rotatable shaft surrounded by an inner cup, which is surrounded by a middle cup, which in turn is surrounded by an outer cup; moving the first wafer to a first position above the first cup wall of the inner cup but below the second cup wall of the middle cup; dispersing a first developer over the first wafer; rotating the first wafer while collecting excess first developer in a first channel between the first and second cup walls; removing the first wafer; placing a second wafer on the wafer holder; moving the second wafer to a second position above the second cup wall of the middle cup but below the third cup wall of the outer cup; raising a separator wall in the first channel to divide the first channel into an inner channel near the first cup wall and an outer channel near the second cup wall; dispersing a second developer over the second wafer; rotating the second wafer while collecting excess second developer in a second channel between the second and third cup walls and in the inner channel; and removing the second wafer. Simple Explanation of the Diagram

[0007] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 shows a cross-sectional view of a wafer processing apparatus with the wafer holder in the first position. Figure 2 shows a top view of the wafer processing equipment in Figure 1. Figure 3 shows a cross-sectional view of a wafer processing device with the wafer holder in the second position. Figure 4 shows a top view of the wafer processing equipment in Figure 3. Figure 5 illustrates a cross-sectional view of a wafer processing apparatus in which one or more types of separator walls are mechanically coupled to a rotatable shaft according to the present disclosure. Figure 6 illustrates a method 1000 for developing a latent image on a photoresist layer on a wafer using a wafer processing apparatus according to various embodiments disclosed herein. Figures 7 through 14 illustrate cross-sectional views of the wafer processing apparatus in Figure 1 at different manufacturing stages of method 1000 according to some embodiments of the present disclosure. Figure 15 shows a cross-sectional view of a wafer processing apparatus with the wafer holder in the first position. Figure 16 shows a side view of the upper and lower middle cups of the wafer processing equipment when the spring door in the lower middle cup in Figure 15 is not activated. Figure 17 shows a side view of the upper and lower middle cups of the wafer processing equipment when the spring door in the lower middle cup is activated, as shown in Figure 15. Figure 18 shows a top view of the inner cup wall, separator, and lower middle cup of the wafer processing equipment in Figure 15. Figure 19 shows a cross-sectional view of a wafer processing apparatus with the wafer holder in the second position. Figure 20 illustrates a cross-sectional view of a wafer processing apparatus in which one or more types of separator walls are mechanically coupled to a rotatable shaft according to the present disclosure. Figures 21 through 28 illustrate cross-sectional views of the wafer processing apparatus in Figure 15 of some embodiments of the present disclosure at various manufacturing stages of method 1000. Implementation

[0008] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0010] Furthermore, when using "about," "approximately," and the like to describe a number or range of numbers, the term is intended to encompass a reasonable range of numbers that takes into account the inherent variations during manufacturing as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with the number, the number or range encompasses a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer with a thickness of "about 5 nm" may include a dimensional range of 4.25 nm to 5.75 nm, where a manufacturing tolerance associated with the deposited material layer is known to one of ordinary skill in the art to be + / - 15%. When describing the state of a transistor, depending on the context, (multiple) source / drain regions may refer individually or collectively to a source or drain.

[0011] In integrated circuit manufacturing processes, for example, optical lithography is frequently used to form features of semiconductor devices on semiconductor wafers. Optical lithography generally involves applying a layer of photoresist to the surface of the semiconductor wafer, followed by exposure via a mask defining the device feature pattern or by a trigger light source reflected from that mask. Exposure forms a latent image in the photoresist layer. Generally, the photoresist layer can be positive or negative. With positive photoresist, a portion exposed to the trigger light source may become soluble in a positive-tone developer, while the unexposed portion remains insoluble. With negative photoresist, a portion exposed to the trigger light source may become insoluble, while the unexposed portion remains soluble in a negative-tone developer. The semiconductor wafer is then subjected to a development process to develop the latent image. During the development process, as the semiconductor wafer rotates, negative and positive developers are dispersed over the photoresist layer on the semiconductor wafer. Negative or positive developer is evenly distributed above the wafer surface due to centrifugal force. Excess developer can detach from the edges of the semiconductor wafer. A retrieval cup surrounding a wafer holder can be used to collect the detached developer.

[0012] Modern lithography tools, such as coating machines or developers, require multiple developing chambers for different developing processes. When a single developing chamber can only be used with either positive or negative developers, more developing chambers are needed to increase the tool's capacity and throughput. One proposed solution is a multi-developer developing chamber that can handle both positive and negative development. Because different developers reside in different solvent systems, they may condense or form solids when mixed. These condensates and solids can clog drains, and solid waste may require incineration, which consumes energy and can cause pollution.

[0013] This disclosure describes a semiconductor processing apparatus including an inner cup surrounding a rotatable axis, a middle cup surrounding the inner cup, and an outer cup surrounding the middle cup. The inner cup includes a first cup wall and a first bottom surface. The middle cup includes a second cup wall and a second bottom surface. The outer cup includes a third cup wall and a third bottom surface. The semiconductor processing apparatus further includes a separator. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator is raised above the second bottom surface. This disclosure also describes a method of using the semiconductor processing apparatus. When a first developer is used, a first semiconductor wafer is in a first position such that waste first developer can be collected between the inner cup and the middle cup. When a second developer is used, a second semiconductor wafer is in a second position, and the separator is raised to form an internal channel between the inner cup and the middle cup. When the second semiconductor wafer rotates at a lower speed, a portion of the waste second developer can be collected in the internal channel. When the second semiconductor wafer rotates at a higher speed, substantially all of the waste second developer can be collected between the outer cup and the middle cup.

[0014] Figure 1 illustrates a cross-sectional view of a wafer processing apparatus 100 according to some embodiments of the present disclosure. The wafer processing apparatus 100 includes a rotatable shaft 104 and a wafer chuck 102 mechanically fixed to the rotatable shaft 104. The rotatable shaft 104 can be driven directly or indirectly by a direct-current (DC) motor, thereby rotating at different speeds. When the rotatable shaft 104 rotates, the wafer chuck 102 also rotates accordingly. The wafer chuck 102 can be an electrostatic chuck (or E-chuck) and is used to releasably hold semiconductor wafers by electrostatic force. In some embodiments shown in Figure 1, the wafer chuck 102 and the rotatable shaft 104 are surrounded by an inner cup 106. The inner cup 106 is surrounded by a middle cup 108, and the middle cup 108 is surrounded by an outer cup 110. The inner cup 106 includes a first bottom surface 106B, a first cup wall 106W extending from the first bottom surface 106B, and a first angled top portion 106A extending from the first cup wall 106W. The middle cup 108 includes a second bottom surface 108B, a second cup wall 108W extending from the second bottom surface 108B, and a second angled top portion 108A extending from the second cup wall 108W. The outer cup 110 has a third bottom surface 110B, a third cup wall 110W extending from the third bottom surface 110B, and a third angled top portion 110A extending from the third cup wall 110W. As shown in Figures 1 and 3, each of the first angled top portion 106A, the second angled top portion 108A, and the third angled top portion 110A is bent inward toward the wafer chuck 102 or the rotatable axis 104. Referring to Figure 2, which is a top view of the wafer processing apparatus 100 in Figure 1. As shown in Figure 2, the first cup wall 106W, the second cup wall 108W, and the third cup wall 110W are circular and concentric. The second cup wall 108W extends continuously around the first cup wall 106W to define the first discharge channel 107. The third cup wall 110W extends continuously around the second cup wall 108W to define the second discharge channel 109.

[0015] In some embodiments shown in Figure 1, the first bottom surface 106B, the second bottom surface 108B, and the third bottom surface 110B may be coplanar (i.e., extending along the same plane). As shown in Figure 1, the second bottom surface 108B and the third bottom surface 110B respectively include a first discharge opening 112 and a second discharge opening 114 to discharge waste developer from the first discharge channel 107 and the second discharge channel 109. For illustrative purposes, Figure 2 includes arrows indicating the flow of liquid waste toward the discharge openings. In some embodiments shown in Figures 1 and 2, the second bottom surface 108B further includes a third discharge opening 116. Unlike the first discharge opening 112 and the second discharge opening 114, the third discharge opening 116 is controlled by a valve 130. When the valve 130 is open, the third discharge opening 116 is open and can be used to discharge liquid waste. When the valve 130 is closed, the third discharge opening 116 is closed and cannot be used to discharge any liquid waste. In some embodiments, valve 130 may be a butterfly valve, ball valve, spherical valve, or check valve.

[0016] Referring to Figures 1 and 3, the rotatable shaft 104 and the wafer chuck 102 can move vertically between a lower position L and a higher position H. When the wafer chuck 102 is in the lower position L as shown in Figure 1, the top surface of the wafer chuck 102 is higher than the top surface of the first angled top portion 106A but lower than the top surface of the second angled top portion 108A. When the wafer chuck 102 is in the higher position H as shown in Figure 3, the top surface of the wafer chuck 102 is higher than the top surface of the second angled top portion 108A but lower than the top surface of the third angled top portion 110A. As shown in Figures 1 and 3, the first angled top portion 106A and the second angled top portion 108A define the lower pick-up opening OL. The second angled top portion 108A and the third angled top portion 110A define the upper pick-up opening OH.

[0017] As shown in Figures 1 and 3, the wafer processing apparatus 100 includes a separator 120. The separator 120 is vertically movable between a lower position shown in Figure 1 and an upper position shown in Figure 3. When the separator 120 is in the lower position as shown in Figure 1, the top surface of the separator 120 is flush with the second bottom surface 108B to allow unrestricted flow of liquid in the first discharge channel 107 toward the first discharge opening 112. When the separator 120 is in the upper position as shown in Figure 3, the top surface of the separator 120 rises above the second bottom surface 108B, dividing the first discharge channel 107 into an inner channel 107I adjacent to the first cup wall 106W and an outer channel 107O adjacent to the second cup wall 108W. In some embodiments shown in Figure 3, when the separator 120 is in the upper position, a valve 130 is activated to open a third discharge opening 116. That is, due to the operation of the separator 120 and the valve 130, the internal channel 107I discharges through the third discharge opening 116, while the external channel 107O discharges through the first discharge opening 112, as shown by the arrow in Figure 4.

[0018] Referring to Figure 3. Along the radial direction, concentric first cup wall 106W and second cup wall 108W define a first width W1 of the first discharge channel 107. A second width W2 of the internal channel 107I is radially defined between the separator 120 and the first cup wall 106W. A first beveled top portion 106A and a second beveled top portion 108A are separated by a third width W3. The top surface of the separator 120 is lower by a height 106H than the top surface of the first cup wall 106W. In some embodiments, the ratio of the second width W2 to the first width W1 is between about 0.1 and about 0.9. The ratio of the thickness T of the separator 120 to the first width W1 is between about 0.05 and about 0.3. The ratio of the third width W3 to the first width W1 is between about 0.3 and about 0.6. The ratio of the height 106H to the first width W1 is between about 0.2 and about 2.

[0019] In some embodiments shown in Figure 5, the separator 120 is mechanically coupled to a base member 122, which rises and falls together with the rotatable shaft 104. This base member 122 allows the separator 120 to rise and fall together with the wafer chuck 102. In these embodiments, when the wafer chuck 102 is in a lower position L, the separator 120 is in a lower position where its top surface is flush with the second bottom surface 108B. When the wafer chuck 102 is in a higher position H, the separator 120 is in an upper position where its top surface rises above the second bottom surface 108B to divide the first discharge channel 107 into an inner channel 107I and an outer channel 107O.

[0020] In some embodiments, the inner cup 106, middle cup 108, outer cup 110, base member 122, and separator 120 may comprise chemically resistant polymers such as polypropylene (PP), polyvinyl chloride (PVC), high-density polyethylene (HDPE), polyetherketone (PEEK), polytetrafluoroethylene (PTFE), polyvinylidene fluoride, or polyaniline. The rotatable shaft 104 may be made of stainless steel.

[0021] Figure 6 illustrates a method 1000 for developing a latent image on a photoresist layer on a semiconductor wafer using a wafer processing apparatus 100. Method 1000 is merely an example and is not intended to limit this disclosure to the content explicitly described in method 1000. Additional steps may be provided before, during, and after method 1000, and some described steps may be replaced, eliminated, or moved around for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Method 1000 is described below in conjunction with Figures 7 through 14, which are cross-sectional and top views of the wafer processing apparatus 100 at different manufacturing stages according to various embodiments of method 1000. For the avoidance of ambiguity, the X, Y, and Z directions in Figures 7 through 14 are perpendicular to each other. Throughout this disclosure, unless explicitly stated otherwise, the same reference numerals denote the same features.

[0022] Referring to Figures 6 and 7, method 1000 includes block 1002, in which a first wafer 10 is placed on a wafer chuck 102. As described above, the wafer chuck 102 may be an E-chuck. At block 1002, the first wafer 10 is loaded onto the wafer chuck 102, and the wafer chuck 102 is activated to secure the first wafer 10 on the wafer chuck. In some embodiments, the first wafer 10 is a semiconductor substrate comprising silicon (Si) in a crystal structure. In alternative embodiments, the first wafer 10 comprises other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The first wafer 10 may include a silicon-on-insulator (SOI) substrate subjected to strain / stress to improve performance, including epitaxial regions, including isolation regions, including doped regions, including one or more semiconductor devices or portions thereof, including conductive and / or non-conductive layers, and / or including other suitable features and layers. Although not explicitly shown in the figures, the first wafer 10 may include various device elements. Examples of device elements formed in the first wafer 10 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc.), diodes, and / or other suitable components. The first wafer 10 also includes a target layer, which is to be patterned using optical lithography and etching processes. The target layer may be a metal layer, a metal nitride layer, a metal oxide layer, a dielectric layer, a bottom antireflective coating (BARC) layer, or an epitaxial layer. As shown in Figure 7, the target layer of the first wafer 10 is coated with a first photoresist layer 12. In some embodiments, the first photoresist layer 12 may include a single layer or multiple layers, such as three layers.The first photoresist layer 12 may include photoresist materials suitable for use in deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam lithography, X-ray lithography, and other appropriate lithography processes.

[0023] Before loading the first wafer 10 onto the wafer chuck 102, the first photoresist layer 12 is exposed to radiation in an optical lithography system. In some embodiments, the radiation may be I-line (365 nm), DUV radiation (such as KrF excimer laser (248 nm) or ArF excimer laser (193 nm)), EUV radiation (e.g., 13.8 nm), e-beam, X-rays, ion beams, or other suitable radiation. Exposure may be performed in air, in a liquid (immersion lithography), or in a vacuum (e.g., for EUV lithography and e-beam lithography). The radiation is patterned with a photomask or master photomask (not shown), such as a transmission mask or a reflection mask, which may include resolution enhancement techniques such as phase transfer and / or optical proximity correction (OPC). In the depicted embodiment, the first photoresist layer 12 is a positive photoresist. The portion of the first photoresist layer 12 exposed to radiation may depolymerize and become soluble in a positive developer. Exposure of the first photoresist layer 12 forms a latent image within it. Following the exposure process, the first photoresist layer 12 undergoes a post-baking process. This post-baking process aids in the generation, dispersion, and reaction of acids / bases / free radicals generated during the exposure process by energy impacts on the photoactive compounds in the first photoresist layer 12. The post-baking process helps generate or enhance chemical reactions that create chemical differences and different polarities between the irradiated and unexposed portions of the first photoresist layer 12. These chemical differences result in differences in solubility between the irradiated and unexposed portions.

[0024] Referring to Figures 6 and 7, method 1000 includes block 1004, in which a first wafer 10 is moved to a first position. As described above, the wafer chuck 102 of the wafer processing apparatus 100 can move vertically between a lower position L and a higher position H. At block 1004, the first position corresponds to the lower position L. At the lower position L, the bottom surface of the first wafer 10 is higher than the top surface of the inner cup 106 but lower than the top surface of the middle cup 108, such that the lower pick-up opening OL opens toward the edge of the first wafer 10. Depending on the initial position of the wafer chuck 102, the wafer chuck 102 can be lowered to the lower position L.

[0025] Referring to Figures 6 and 8 through 10, method 1000 includes block 1006, wherein a first developer 210 is dispersed onto the first wafer 10 while the first wafer 10 is rotating at a first low rotational speed L1 and a first high rotational speed H1. As shown in Figure 8, at block 1006, the dispersing nozzle 202 is lowered or rotated until it is at a suitable distance from the top surface of the first photoresist layer 12. At block 1006, the first developer 210 is dispersed from the dispersing nozzle 202 onto the first photoresist layer 12. As the first developer 210 is dispersed onto the first photoresist layer 12, the first wafer 10 rotates together with the wafer chuck 102. In some embodiments shown in Figure 8, the first wafer 10 (together with the wafer chuck 102) can rotate at the first low rotational speed L1 when the first developer 210 is first dispersed onto the first wafer 10. In some embodiments, the first developer 210 is a positive developer and may be an aqueous solution comprising tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide, sodium hydroxide, potassium hydroxide, sodium carbonate, sodium bicarbonate, sodium silicate, sodium metasilicate, ammonia, monomethylamine, dimethylamine, trimethylamine, monoethylamine, diethylamine, monoisopropylamine, diisopropylamine, triisopropylamine, monobutylamine, dibutylamine, monoethanolamine, diethanolamine, triethanolamine, dimethylaminoethanol, diethylaminoethanol, ammonia, caustic soda, potassium caustic soda, potassium metasilicate, tetraethylammonium hydroxide, or combinations thereof. Thereafter, the first wafer 10 (together with the wafer chuck 102) can be rotated at a higher first high rotational speed H1. In some cases, the first low rotational speed L1 is equal to or less than 200 revolutions per minute (RPM), while the first high rotational speed H1 is greater than 200 RPM. As shown in Figure 9, when the wafer chuck 102 rotates at a first low rotational speed L1, excess first developer 210 can detach from the edge of the first wafer 10 and enter the first discharge channel 107. As shown in Figure 10, when the wafer chuck 102 rotates at a first high rotational speed H1, excess first developer 210 can detach from the edge of the first wafer 10 at a steeper angle. That is, as shown in Figure 10, even at the first high rotational speed H1, excess first developer 210 can be collected in the first discharge channel 107.

[0026] Referring to Figures 6, 9, and 10, method 1000 includes block 1008, in which excess first developer 210 is collected in a first discharge channel 107 between inner cup 106 and middle cup 108. As shown in Figures 9 and 10, excess first developer 210 can detach from the edge of the first wafer 10 and collect in the first discharge channel 107 between inner cup 106 and middle cup 108. More precisely, the first discharge channel 107 is defined between the first cup wall 106W and the second cup wall 108W. As shown in Figures 9 and 10, excess first developer 210 can flow downward toward the first discharge opening 112. Note that the third discharge opening 116 remains closed by valve 130. Excess first developer 210 is guided to a first developer waste reservoir 210W.

[0027] Referring to Figure 6, method 1000 includes block 1010, in which a first wafer 10 is removed from wafer chuck 102. After the latent image in the first photoresist layer 12 is developed by a first developer 210, the first wafer 10 may be rinsed with deionized (DI) water to remove excess chemicals, and then removed from wafer chuck 102. In some embodiments, the first wafer 10 may undergo a post-bake process to remove excess solvent.

[0028] Referring to Figures 6 and 11, method 1000 includes block 1012, in which a second wafer 20 is placed on a wafer chuck 102. At block 1012, the second wafer 20 is loaded onto the wafer chuck 102, and the wafer chuck 102 is activated to secure the second wafer 20 on the wafer chuck 102. Like the first wafer 10, the second wafer 20 is also a semiconductor substrate comprising silicon (Si). In alternative embodiments, the second wafer 20 comprises other elemental semiconductors, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP); alloy semiconductors, such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The second wafer 20 may include a silicon-on-insulator (SOI) substrate, subjected to strain / stress to improve performance, including epitaxial regions, including isolation regions, including doped regions, including one or more semiconductor devices or portions thereof, including conductive and / or non-conductive layers, and / or including other suitable features and layers. Although not explicitly shown in the figures, the second wafer 20 may include various device elements. Examples of device elements formed in the second wafer 20 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), etc.), diodes, and / or other suitable components. The second wafer 20 also includes a target layer, which may be a metal layer, a metal nitride layer, a metal oxide layer, a dielectric layer, a bottom antireflective coating (BARC) layer, or an epitaxial layer. As shown in Figure 11, a second photoresist layer 22 is coated on the second wafer 20. The second photoresist layer 22 is deposited on the target layer, which is to be etched after the second photoresist layer 22 has been patterned. In some embodiments, the second photoresist layer 22 may include a single layer or multiple layers, such as three layers.The second photoresist layer 22 may include photoresist materials suitable for use in deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam lithography, X-ray lithography, and other appropriate lithography processes.

[0029] Before the second wafer 20 is mounted on the wafer chuck 102, the second photoresist layer 22 is exposed to radiation in a lithography system. In some embodiments, the radiation may be I-line (365 nm), DUV radiation (such as KrF excimer laser (248 nm) or ArF excimer laser (193 nm)), EUV radiation (e.g., 13.8 nm), e-beam, X-rays, ion beams, or other suitable radiation. Exposure may be performed in air, in a liquid (immersion lithography), or in a vacuum (e.g., for EUV lithography and e-beam lithography). The radiation is patterned using a photomask or master photomask (not shown), such as a transmission mask or a reflection mask, which may include resolution enhancement techniques such as phase transfer and / or optical proximity correction (OPC). In the depicted embodiment, the second photoresist layer 22 is a negative resist. The portion of the second photoresist layer 22 exposed to radiation may become insoluble in a negative developer. Exposure of the second photoresist layer 22 forms a latent image within it. Following the exposure process, the second photoresist layer 22 undergoes a post-baking process. This post-baking process aids in the generation, dispersion, and reaction of acids / bases / free radicals generated during the exposure process by energy impacts on the photoactive compounds in the second photoresist layer 22. The post-baking process helps generate or enhance chemical reactions that create chemical differences and different polarities between the irradiated and unexposed portions of the second photoresist layer 22. These chemical differences result in differences in solubility between the irradiated and unexposed portions.

[0030] Referring to Figures 6 and 11, method 1000 includes block 1014, in which a second wafer 20 is moved to a second position and a separator 120 is raised in a first discharge channel 107 to divide the first discharge channel 107 into an inner channel 107I and an outer channel 107O. As described above, the wafer chuck 102 of the wafer processing apparatus 100 can move vertically between a lower position L and a higher position H. At block 1014, the second position corresponds to the higher position H. At the higher position H, the bottom surface of the second wafer 20 is higher than the top surface of the middle cup 108 but lower than the top surface of the outer cup 110, such that the upper pick-up opening OH opens toward the edge of the second wafer 20. Depending on the initial position of the wafer chuck 102, the wafer chuck 102 can be raised to the higher position H. At block 1014, the separator 120 is raised so that its top surface rises above the second bottom surface 108B, dividing the first discharge channel 107 into an inner channel 107I and an outer channel 107O. The inner channel 107I is closer to the first cup wall 106W, while the outer channel 107O is closer to the second cup wall 108W. Additionally, at block 1014, the valve 130 controlling the third discharge opening 116 is opened. When the separator 120 is raised and the valve 130 is open, the inner channel 107I discharges through the third discharge opening 116, while the outer channel 107O discharges through the first discharge opening 112.

[0031] Referring to Figures 6, 12, 13, and 14, method 1000 includes block 1016, wherein a second developer 220 is dispersed onto the second wafer 20 while the second wafer 20 rotates at a second low rotational speed L2 and a second high rotational speed H2. As shown in Figure 12, at block 1016, the dispersing nozzle 202 is lowered or rotated until it is at a suitable distance from the top surface of the second photoresist layer 22. At block 1016, the second developer 220 is dispersed from the dispersing nozzle 202 onto the second photoresist layer 22. In some embodiments, the second developer 220 is a negative developer and may be an organic solution or solvent, such as hexane, heptane, octane, toluene, xylene, dichloromethane, chloroform, carbon tetrachloride, trichloroethylene, methanol, ethanol, propanol, butanol, diethyl ether, dipropyl ether, dibutyl ether, ethyl vinyl ether, dioxane, propylene oxide, tetrahydrofuran, ceroxysulfone, methylceroxysulfone, butylceroxysulfone, methyl carbitol, diethylene glycol monoethyl ether, acetone, methyl ethyl ketone, methyl isobutyl ketone, isophorone, cyclohexanone, methyl acetate, ethyl acetate, propyl acetate, butyl acetate, pyridine, methylamine, N,N-dimethylformamide, or combinations thereof. As the second developer 220 is dispersed above the second photoresist layer 22, the second wafer 20 rotates together with the wafer chuck 102. In some embodiments shown in Figure 13, when the second developer 220 is first dispersed onto the second wafer 20, the second wafer 20 (together with the wafer chuck 102) can be rotated at a second low rotational speed L2. Subsequently, the second wafer 20 (together with the wafer chuck 102) can be rotated at a higher second high rotational speed H2, as shown in Figure 14. As shown in Figure 13, when the wafer chuck 102 rotates at the second low rotational speed L2, excess second developer 220 can detach from the edge of the second wafer 20 and enter the internal channel 107I. It has been observed that when the wafer chuck 102 is in a higher position H and rotating at a speed of less than 200 revolutions per minute (RPM), excess second developer 220 may not reach the upper pick-up opening OH. Instead, excess second developer 220 can fall onto the first beveled top portion 106A and enter the lower pick-up opening OL. This is where the separator 120 and the third discharge opening 116 function. Without the separator 120 and the third discharge opening 116, excess second developer 220 can be discharged through the first discharge opening 112 and enter the first developer waste reservoir 210W. Because the first developer 210 and the second developer 220 have different solvent types, mixing of the first developer 210 and the second developer 220 in the first developer waste reservoir 210W or the first discharge channel 107 can lead to coagulation or precipitation. Such coagulation or precipitation can reduce waste discharge efficiency and increase the energy and cost of treating mixed developer waste.As shown in Figure 14, when the wafer chuck 102 rotates at the second high rotational speed H2, excess second developer 220 can detach from the edge of the second wafer 20 at a steeper angle. As shown in Figure 14, at the second high rotational speed H2, excess second developer 220 can be collected in the second discharge channel 109.

[0032] Referring to Figures 6, 13, and 14, method 1000 includes block 1018, in which excess second developer 220 is collected in an inner channel 107I and a second discharge channel 109 between the middle cup 108 and the outer cup 110. As shown in Figures 13 and 14, excess second developer 220 can detach from the edge of the second wafer 20 and collect in the inner channel 107I and the second discharge channel 109 between the middle cup 108 and the outer cup 110. The inner channel 107I is defined between the first cup wall 106W and the separator 120. The second discharge channel 109 is defined between the second cup wall 108W and the third cup wall 110W. As shown in Figures 13 and 14, excess second developer 220 can flow downward toward the second discharge opening 114 and the third discharge opening 116. Unlike the first discharge opening 112, the second discharge opening 114 and the third discharge opening 116 lead to the second developer waste storage 220W, which is separate from the first developer waste storage 210W.

[0033] Referring to Figure 6, method 1000 includes block 1020, in which a second wafer 20 is removed from wafer chuck 102. After the latent image in the second photoresist layer 22 is developed by the second developer 220, the second wafer 20 may be rinsed to remove excess chemicals and then removed from wafer chuck 102. In some embodiments, the second wafer 20 may undergo a post-bake process to remove excess solvent.

[0034] Figure 15 illustrates a cross-sectional view of wafer processing apparatus 1100. Wafer processing apparatus 1100 shares some similar components with wafer processing apparatus 100 described above. For the purpose of describing wafer processing apparatus 100 and wafer processing apparatus 1100, unless otherwise explicitly stated, the same reference numerals denote the same features. Like wafer processing apparatus 100 described above, wafer processing apparatus 1100 includes a rotatable shaft 104 and a wafer chuck 102 mechanically fixed to the rotatable shaft 104. The wafer chuck 102 and rotatable shaft 104 are surrounded by an inner cup 106. The inner cup 106 is surrounded by a middle cup 108, and the middle cup 108 is surrounded by an outer cup 110. In some embodiments shown in Figure 15, the middle cup 108 includes a lower middle cup 108L and an upper middle cup 108U, and the outer cup 110 includes a lower outer cup 110L and an upper outer cup 110U. The inner cup 106 includes a first bottom surface 106B, a first cup wall 106W extending from the first bottom surface 106B, and a first angled top portion 106A extending from the first cup wall 106W. The middle cup 108 includes a second angled top portion 108A, which is part of the upper middle cup 108U. The outer cup 110 has a third angled top portion 110A, which is part of the upper outer cup 110U. As shown in Figure 15, each of the first angled top portion 106A, the second angled top portion 108A, and the third angled top portion 110A is bent inward toward the wafer chuck 102 or the rotatable axis 104.

[0035] Referring again to Figure 15. In the depicted embodiment, the support 1300 is mechanically attached to the upper middle cup 108U such that when the support 1300 is raised or lowered by a mechanical mechanism, the upper middle cup 108U also rises and falls accordingly. The upper outer cup 110U is disposed on the top surface of the support 1300 and also rises and falls with the support 1300. Because the support 1300 includes a support opening 1310, the opening between the upper middle cup 108U and the upper outer cup 110U is not blocked. That is, both the upper outer cup 110U and the upper middle cup 108U can move together with the support 1300 in the vertical direction (i.e., the Z direction). As shown in Figure 15, the upper middle cup 108U and the lower middle cup 108L are discontinuous. In fact, the upper middle cup 108U can move vertically relative to the lower middle cup 108L. Similarly, the upper outer cup 110U can move relative to the lower outer cup 110L. Referring now to Figures 15 and 16. The lower cup 108L includes a spring-loaded door 1080 that is vertically movable between an upper closed position and a lower open position. The upper cup 108U includes a passage extension 1082 that extends below the remainder of the upper cup 108U. Figures 16 and 17 illustrate partial side views of the lower cup 108L, the spring door 1080, the passage extension 1082, and the upper cup 108U along the Y direction. Referring to Figure 16, when the upper cup 108U is not lowered, the passage extension 1082 may contact or approach the top surface of the spring door 1080. Referring to Figure 17, when the upper cup 108U is lowered, the passage extension 1082 pushes the top surface of the spring door 1080 to activate the spring door 1080. The passage extension 1082 includes a passage opening 1084. When the spring door 1080 is pushed downward or activated by the passage extension 1082, the passage opening 1084 provides fluid communication across the lower middle cup 108L. As shown in Figures 16 and 17, the upper middle cup 108U also includes a second beveled top portion 108A curved toward the wafer chuck 102. The lower middle cup 108L extends continuously around the first cup wall 106W to define a first discharge channel 107. The lower outer cup 110L extends continuously around the lower middle cup 108L to define a second discharge channel 109. The first discharge channel 107 discharges via a first discharge opening 112, and the second discharge channel 109 discharges via a second discharge opening 114.

[0036] As shown in Figures 15 and 18, the wafer processing apparatus 1100 includes a separator 1200, which includes a passageway compartment 1202. The separator 1200 is vertically movable between a lower position shown in Figure 15 and an upper position shown in Figure 19. When the separator 1200 is in the lower position as shown in Figure 15, the top surface of the separator 1200 does not extend into the first discharge channel 107. When the separator 1200 is in the upper position as shown in Figure 19, the top surface of the separator 1200 rises together with the passageway compartment 1202 and extends into the first discharge channel 107 to divide the inner channel 107I. Unlike the wafer processing apparatus 100 described above, the inner channel 107I does not have its own discharge opening. When the separator 1200 is raised and the upper cup 108U is lowered, the passage extension 1082 attached to the upper cup 108U presses down on the spring door 1080, aligning the passage opening 1084 with the passage compartment 1202. As indicated by the arrow in Figure 19, the alignment of the passage compartment 1202 with the passage opening 1084 provides fluid communication between the internal passage 107I and the second discharge passage 109. When liquid waste or fluid accumulates in the internal passage 107I, it can flow to the second discharge passage 109 through the passage opening 1084 and the passage compartment 1202. Then, the liquid waste or fluid in the second discharge passage 109 can be discharged through the second discharge opening 114.

[0037] Referring to Figures 15 and 19, the rotatable axis 104 and wafer chuck 102 of the wafer processing apparatus 1100 can move vertically between a lower position L and a higher position H. When the wafer chuck 102 is in the lower position L as shown in Figure 15, the top surface of the wafer chuck 102 is higher than the top surface of the first angled top portion 106A but lower than the top surface of the second angled top portion 108A. When the wafer chuck 102 is in the higher position H as shown in Figure 19, the top surface of the wafer chuck 102 is higher than the top surface of the second angled top portion 108A but lower than the top surface of the third angled top portion 110A. As shown in Figures 15 and 19, the first angled top portion 106A and the second angled top portion 108A define the lower pick-up opening OL. The second angled top portion 108A and the third angled top portion 110A define the upper pick-up opening OH.

[0038] In some embodiments shown in Figure 20, the separator 1200 is mechanically coupled to a base member 122, which rises and falls together with the rotatable shaft 104. This base member 122 allows the separator 1200 to rise and fall together with the wafer chuck 102. In these embodiments, when the wafer chuck 102 is in a lower position L, the separator 1200 is in a lower position, and its top surface does not extend into the first discharge channel 107. When the wafer chuck 102 is in a higher position H, the separator 1200 is in an upper position, and its top surface extends into the first discharge channel 107 to define an inner channel 107I.

[0039] In some embodiments, the inner cup 106, middle cup 108, outer cup 110, base member 122, and separator 1200 may comprise chemically resistant polymers such as polypropylene (PP), polyvinyl chloride (PVC), high-density polyethylene (HDPE), polyetherketone (PEEK), polytetrafluoroethylene (PTFE), polyvinylidene fluoride, or polyaniline. The support 1300 and rotatable shaft 104 may be made of stainless steel.

[0040] The method 1000 in Figure 6 can be performed using wafer processing equipment 1100. The method 1000 is further described below with reference to Figures 21 to 28, which are cross-sectional views of the wafer processing equipment 1100 at different manufacturing stages according to various embodiments of the method 1000.

[0041] Referring to Figures 6 and 21, method 1000 includes block 1002, in which a first wafer 10 is placed on a wafer chuck 102. At block 1002, the first wafer 10 is loaded onto the wafer chuck 102, and the wafer chuck 102 is activated to secure the first wafer 10 on the wafer chuck. The first wafer 10 also includes a target layer, which is to be patterned using optical lithography and etching processes. The target layer may be a metal layer, a metal nitride layer, a metal oxide layer, a dielectric layer, a bottom antireflective coating (BARC) layer, or an epitaxial layer. As shown in Figure 21, a first photoresist layer 12 is coated on the target layer of the first wafer 10. In some embodiments, the first photoresist layer 12 may include a single layer or multiple layers, such as three layers. The first photoresist layer 12 may include photoresist materials suitable for use in deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam (e-beam) lithography, X-ray lithography, and other appropriate lithography processes.

[0042] Before loading the first wafer 10 onto the wafer chuck 102, a first photoresist layer 12 is exposed to radiation in a lithography system. The radiation is patterned using a photomask or master photomask (not shown), such as a transmission mask or a reflection mask, which may include resolution enhancement techniques such as phase transfer and / or optical proximity correction (OPC). In the depicted embodiment, the first photoresist layer 12 is a positive photoresist. The portion of the first photoresist layer 12 exposed to radiation is depolymerized and becomes soluble in a positive developer. The exposure of the first photoresist layer 12 forms a latent image in the first photoresist layer 12. After the exposure process, the first photoresist layer 12 is subjected to a post-bake process. The post-bake process is performed to aid in the generation, dispersion, and reaction of acids / bases / free radicals generated during the exposure process by energy impacts on the photoactive compounds in the first photoresist layer 12. The post-baking process helps to generate or enhance chemical reactions that create chemical differences and different polarities between the irradiated and unexposed portions within the first photoresist layer 12. These chemical differences result in differences in solubility between the irradiated and unexposed portions.

[0043] Referring to Figures 6 and 21, method 1000 includes block 1004, in which a first wafer 10 is moved to a first position. At block 1004, the first position corresponds to a lower position L. At the lower position L, the bottom surface of the first wafer 10 is higher than the top surface of the inner cup 106 but lower than the top surface of the middle cup 108, such that the lower pick-up opening OL opens toward the first wafer 10. Depending on the initial position of the wafer chuck 102, the wafer chuck 102 can be lowered to the lower position L.

[0044] Referring to Figures 6 and 22 through 24, method 1000 includes block 1006, wherein a first developer 210 is dispersed onto the first wafer 10 while the first wafer 10 is rotating at a first low rotational speed L1 and a first high rotational speed H1. As shown in Figure 22, at block 1006, the dispersing nozzle 202 is lowered or rotated until it is at a suitable distance from the top surface of the first photoresist layer 12. At block 1006, the first developer 210 is dispersed from the dispersing nozzle 202 onto the first photoresist layer 12. As the first developer 210 is dispersed onto the first photoresist layer 12, the first wafer 10 rotates together with the wafer chuck 102. In some embodiments shown in Figure 23, the first wafer 10 (together with the wafer chuck 102) can rotate at the first low rotational speed L1 while the first developer 210 is dispersed onto the first wafer 10. In some embodiments, the first developer 210 is a positive developer and may be an aqueous solution comprising tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide, sodium hydroxide, potassium hydroxide, sodium carbonate, sodium bicarbonate, sodium silicate, sodium metasilicate, ammonia, monomethylamine, dimethylamine, trimethylamine, monoethylamine, diethylamine, monoisopropylamine, diisopropylamine, triisopropylamine, monobutylamine, dibutylamine, monoethanolamine, diethanolamine, triethanolamine, dimethylaminoethanol, diethylaminoethanol, ammonia, caustic soda, potassium caustic soda, potassium metasilicate, tetraethylammonium hydroxide, or combinations thereof. Thereafter, the first wafer 10 (together with the wafer chuck 102) can be rotated at a higher first high rotational speed H1. In some cases, the first low rotational speed L1 is equal to or less than 200 revolutions per minute (RPM), while the first high rotational speed H1 is greater than 200 RPM. As shown in Figure 23, when the wafer chuck 102 rotates at a first low rotational speed L1, excess first developer 210 can detach from the edge of the first wafer 10 and enter the first discharge channel 107. As shown in Figure 24, when the wafer chuck 102 rotates at a first high rotational speed H1, excess first developer 210 can detach from the edge of the first wafer 10 at a steeper angle. That is, as shown in Figure 24, even at the first high rotational speed H1, excess first developer 210 can be collected in the first discharge channel 107.

[0045] Referring to Figures 6, 23, and 24, method 1000 includes block 1008, wherein excess first developer 210 is collected in a first discharge channel 107 between inner cup 106 and middle cup 108. As shown in Figures 23 and 24, excess first developer 210 can detach from the edge of the first wafer 10 and collect in the first discharge channel 107 between inner cup 106 and middle cup 108. More precisely, the first discharge channel 107 is defined between the lower middle cup 108L and the inner cup 106. As shown in Figures 23 and 24, excess first developer 210 can be collected in the first discharge channel 107 and discharged via a first discharge opening 112. Excess first developer 210 is guided to a first developer waste reservoir 210W.

[0046] Referring to Figure 6, method 1000 includes block 1010, in which a first wafer 10 is removed from wafer chuck 102. After the latent image in the first photoresist layer 12 is developed by a first developer 210, the first wafer 10 may be rinsed with deionized (DI) water to remove excess chemicals, and then removed from wafer chuck 102 of wafer processing apparatus 1100. In some embodiments, the first wafer 10 may undergo a post-bake process to remove excess solvent.

[0047] Referring to Figures 6 and 25, method 1000 includes block 1012, in which a second wafer 20 is placed on a wafer chuck 102. At block 1012, the second wafer 20 is loaded onto the wafer chuck 102, and the wafer chuck 102 is activated to secure the second wafer 20 on the wafer chuck 102. The second wafer 20 also includes a target layer, which may be a metal layer, a metal nitride layer, a metal oxide layer, a dielectric layer, a bottom antireflective coating (BARC) layer, or an epitaxial layer. As shown in Figure 25, a second photoresist layer 22 is coated on the second wafer 20. The second photoresist layer 22 is deposited on the target layer, which is to be etched after the second photoresist layer 22 is patterned. In some embodiments, the second photoresist layer 22 may include a single layer or multiple layers, such as three layers. The second photoresist layer 22 may include photoresist materials suitable for use in deep ultraviolet (DUV) lithography, extreme ultraviolet (EUV) lithography, electron beam (e-beam) lithography, X-ray lithography, and other appropriate lithography processes.

[0048] Before the second wafer 20 is loaded onto the wafer chuck 102, the second photoresist layer 22 is exposed to radiation in a lithography system. The radiation is patterned using a photomask or master photomask (not shown), such as a transmission mask or a reflection mask, which may include resolution enhancement techniques such as phase transfer and / or optical proximity correction (OPC). In the depicted embodiment, the second photoresist layer 22 is a negative photoresist. The exposed portions of the second photoresist layer 22 may become insoluble in a negative developer. The exposure of the second photoresist layer 22 forms a latent image in the second photoresist layer 22. After the exposure process, the second photoresist layer 22 is subjected to a post-baking process. The post-baking process helps to generate or enhance chemical reactions that create chemical differences and different polarities between the irradiated and unexposed portions within the second photoresist layer 22. These chemical differences result in differences in solubility between the irradiated and unexposed portions.

[0049] Referring to Figures 6 and 25, method 1000 includes block 1014, in which a second wafer 20 is moved to a second position and a separator 1200 is raised in a first discharge channel 107 to define an inner channel 107I and an outer channel 107O. As described above, the wafer chuck 102 of the wafer processing apparatus 1100 can move vertically between a lower position L and a higher position H. At block 1014, the second position corresponds to the higher position H. At the higher position H, the bottom surface of the second wafer 20 is higher than the top surface of the middle cup 108 but lower than the top surface of the outer cup 110, such that the upper pick-up opening OH opens toward the edge of the second wafer 20. Depending on the initial position of the wafer chuck 102, the wafer chuck 102 can be raised to the higher position H. At block 1014, the separator 1200 is raised such that its top surface extends into the first discharge channel 107 to separate it into the inner channel 107I and the outer channel 107O. The internal channel 107I is closer to the first cup wall 106W, while the external channel 107O is closer to the lower middle cup 108L. When the separator 1200 is raised and the upper middle cup 108U is lowered to activate the spring door 1080, the internal channel 107I is in fluid communication with the second discharge channel 109. The second discharge channel 109 discharges through the second discharge opening 114.

[0050] Referring to Figures 6, 26, 27, and 28, method 1000 includes block 1016, wherein a second developer 220 is dispersed onto the second wafer 20 while the second wafer 20 rotates at a second low rotational speed L2 and a second high rotational speed H2. As shown in Figure 26, at block 1016, the dispersing nozzle 202 is lowered or rotated until it is at a suitable distance from the top surface of the second photoresist layer 22. At block 1016, the second developer 220 is dispersed from the dispersing nozzle 202 onto the second photoresist layer 22. In some embodiments, the second developer 220 is a negative developer and may be an organic solution or solvent, such as hexane, heptane, octane, toluene, xylene, dichloromethane, chloroform, carbon tetrachloride, trichloroethylene, methanol, ethanol, propanol, butanol, diethyl ether, dipropyl ether, dibutyl ether, ethyl vinyl ether, dioxane, propylene oxide, tetrahydrofuran, ceroxysulfone, methylceroxysulfone, butylceroxysulfone, methyl carbitol, diethylene glycol monoethyl ether, acetone, methyl ethyl ketone, methyl isobutyl ketone, isophorone, cyclohexanone, methyl acetate, ethyl acetate, propyl acetate, butyl acetate, pyridine, methylamine, N,N-dimethylformamide, or combinations thereof. As the second developer 220 is dispersed above the second photoresist layer 22, the second wafer 20 rotates together with the wafer chuck 102. In some embodiments shown in Figure 27, when the second developer 220 is first dispersed onto the second wafer 20, the second wafer 20 (together with the wafer chuck 102) can be rotated at a second low rotational speed L2. Thereafter, the second wafer 20 (together with the wafer chuck 102) can be rotated at a higher second high rotational speed H2, as shown in Figure 28. In some cases, the second low rotational speed L2 is equal to or less than 200 RPM, while the second high rotational speed H2 is greater than 200 RPM. As shown in Figure 27, when the wafer chuck 102 rotates at the second low rotational speed L2, excess second developer 220 can detach from the edge of the second wafer 20 and enter the internal channel 107I. It has been observed that when the wafer chuck 102 is in a higher position H and rotating at a speed less than 200 revolutions per minute (RPM), excess second developer 220 may not reach the upper pick-up opening OH. Conversely, excess second developer 220 can fall onto the top portion 106A of the first angled section and enter the lower capture opening OL. This is the position where the separator 1200, passage extension 1082, spring door 1080, and passage compartment 1202 function to separate the different developer fluids. Without the separator 1200, passage extension 1082, spring door 1080, and passage compartment 1202, excess second developer 220 can be discharged through the first discharge opening 112 and enter the first developer waste reservoir 210W.Because the first developer 210 and the second developer 220 have different solvent types (i.e., aqueous and organic), mixing of the first developer 210 and the second developer 220 in the first developer waste reservoir 210W or the first discharge channel 107 can lead to coagulation or precipitation. Such coagulation or precipitation can reduce waste discharge efficiency and increase the energy and cost of treating mixed developer waste. As shown in Figure 28, when the wafer chuck 102 rotates at a second high rotational speed H2, excess second developer 220 can fall off the edge of the second wafer 20 at a steeper angle. As shown in Figure 28, at the second high rotational speed H2, excess second developer 220 can be collected in the second discharge channel 109.

[0051] Referring to Figures 6, 27, and 28, method 1000 includes block 1018, wherein excess second developer 220 is collected in an inner channel 107I and a second discharge channel 109 between the middle cup 108 and the outer cup 110. As shown in Figures 27 and 28, excess second developer 220 can detach from the edge of the second wafer 20 and collect in the inner channel 107I and the second discharge channel 109. The inner channel 107I is defined between the first cup wall 106W and the separator 1200. The second discharge channel 109 is defined between the lower middle cup 108L and the lower outer cup 110L. As shown in Figures 27 and 28, excess second developer 220 can flow from the inner channel 107I to the second discharge channel 109 via a passage opening 1084. Next, excess second developer 220 in the second discharge channel 109 can be discharged through the second discharge opening 114, which leads to the second developer waste storage 220W, which is separate from the first developer waste storage 210W.

[0052] Referring to Figure 6, method 1000 includes block 1020, in which a second wafer 20 is removed from wafer chuck 102. After the latent image in the second photoresist layer 22 is developed by the second developer 220, the second wafer 20 may be rinsed to remove excess chemicals and then removed from wafer chuck 102. In some embodiments, the second wafer 20 may undergo a post-bake process to remove excess solvent.

[0053] In one example, this disclosure provides a device. The device includes an inner cup, a middle cup, an outer cup, and a separator. The inner cup includes a first cup wall and a first bottom surface. The middle cup surrounds the inner cup and includes a second cup wall and a second bottom surface between the first cup wall and the second cup wall. The outer cup surrounds the middle cup and includes a third cup wall and a third bottom surface between the second cup wall and the third cup wall. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator rises above the second bottom surface.

[0054] In some embodiments, the separator is in a second position, and the second bottom surface is divided by the separator into an inner bottom surface adjacent to the first cup wall and an outer bottom surface away from the first cup wall. In some embodiments, the device may further include a first discharge port in the inner bottom surface, a second discharge port in the outer bottom surface, and a third discharge port in the third bottom surface. In some cases, the first and third discharge ports discharge into a first waste container, and the second discharge port discharges into a second waste container different from the first waste container. In some embodiments, the device further includes a rotatable shaft extending through the first bottom surface and a wafer holder mechanically coupled to the rotatable shaft. In some cases, the first cup wall completely surrounds the rotatable shaft, the second cup wall completely surrounds the first cup wall, and the third cup wall completely surrounds the second cup wall. In some embodiments, the first cup wall includes a first beveled top portion curved toward the rotatable shaft, the second cup wall includes a second beveled top portion curved toward the first beveled top portion, and the third cup wall includes a third beveled top portion curved toward the second beveled top portion. In some embodiments, the first and second beveled apex portions define a lower pick-up opening, and the second and third beveled apex portions define an upper pick-up opening. In some embodiments, the wafer holder is movable between a high position and a low position. When the wafer holder is in the low position, the wafer holder is substantially flush with the lower pick-up opening. When the wafer holder is in the high position, the wafer holder is substantially flush with the upper pick-up opening.

[0055] Another aspect of this disclosure relates to a device. The device includes an inner cup, a middle cup, an outer cup, a separator, a first discharge port, a second discharge port, and a third discharge port. The inner cup includes a first cup wall and a first bottom surface. The middle cup surrounds the inner cup and includes a second cup wall and a second bottom surface between the first cup wall and the second cup wall. The outer cup surrounds the middle cup and includes a third cup wall and a third bottom surface between the second cup wall and the third cup wall. The separator is movable between a first position where the top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator rises above the second bottom surface. When the separator is in the second position, the second bottom surface is divided by the separator into an inner bottom surface wall adjacent to the first cup and an outer bottom surface away from the first cup wall. The first discharge port is in the inner bottom surface, the second discharge port is in the outer bottom surface, and the third discharge port is in the third bottom surface.

[0056] In some embodiments, a first discharge port and a third discharge port discharge to a first waste container, and a second discharge port discharges to a second waste container different from the first waste container. In some embodiments, the device further includes a rotatable shaft extending through a first bottom surface and a wafer holder mechanically coupled to the rotatable shaft. In some embodiments, a first cup wall completely surrounds the rotatable shaft, a second cup wall completely surrounds the first cup wall, and a third cup wall completely surrounds the second cup wall. In some embodiments, the first cup wall includes a first angled top portion curved toward the rotatable shaft, the second cup wall includes a second angled top portion curved toward the first angled top portion, and the third cup wall includes a third angled top portion curved toward the second angled top portion. In some cases, the first angled top portion and the second angled top portion define a lower pick-up opening, and the second angled top portion and the third angled top portion define an upper pick-up opening.

[0057] Another aspect of this disclosure relates to a method. The method includes placing a first wafer on a wafer holder mechanically fixed to a rotatable shaft surrounded by an inner cup, which is surrounded by a middle cup, which in turn is surrounded by an outer cup; moving the first wafer to a first position above the first cup wall of the inner cup but below the second cup wall of the middle cup; dispersing a first developer over the first wafer; rotating the first wafer while collecting excess first developer in a first channel between the first and second cup walls; removing the first wafer; placing a second wafer on the wafer holder; moving the second wafer to a second position above the second cup wall of the middle cup but below the third cup wall of the outer cup; raising a separator wall in the first channel to divide the first channel into an inner channel near the first cup wall and an outer channel near the second cup wall; dispersing a second developer over the second wafer; rotating the second wafer while collecting excess second developer in a second channel between the second and third cup walls and in the inner channel; and removing the second wafer.

[0058] In some embodiments, the first developer is a positive developer and the second developer is a negative developer. In some embodiments, the internal channel includes a first drain hole, the external channel includes a second drain hole, and the second channel includes a third drain hole. In some embodiments, the first drain hole is closed before raising the separator wall. In some embodiments, raising the separator wall includes opening the first drain hole. In some embodiments, moving the second wafer to the second position is performed simultaneously with raising the separator wall.

[0059] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0060] 10: First Wafer 12: First photoresist layer 20: Second wafer 22: Second photoresist layer 100: Wafer Processing Equipment 102: Wafer Chuck 104: Rotatable shaft 106: Inner Cup 106A: Top portion of the first oblique angle 106B: First bottom surface 106H: Height 106W: First Cup Wall 107: First Emission Lane 107I: Internal Channel 107O: External Channel 108: Medium Cup 108A: Top portion of the second oblique angle 108B: Second bottom surface 108L: Lower middle cup 108U: Upper middle cup 108W: Second cup wall 109: Second Emission Lane 110:Outer cup 110A: Top portion of the third oblique angle 110B: Third bottom surface 110L: Lower outer cup 110U: Upper outer cup 110W: Third cup wall 112: First row opening 114: Second exhaust opening 116: Third row opening 120: Divider 122: Base components 130: Valve 202: Dispersion Nozzle 210: First developer 210W: First developer waste storage container 220: Second developer 220W: Second developer waste storage container 1000: Method 1002~1020: Square 1080: Spring Door 1082: Access Extension Section 1084: Passage opening 1100: Wafer Processing Equipment 1200: Divider 1202: Passageway Compartment 1300: Bracket 1310: Bracket opening H: Higher position H1: First highest rotational speed H2: Second highest rotational speed L: Lower position L1: First low rotational speed L2: Second lowest rotational speed OH: Upper collection opening OL: Lower part of the opening for picking T: Thickness W1: First width W2: Second width W3: Third width

[0061] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor manufacturing apparatus, comprising: an inner cup including a first cup wall and a first bottom surface; a middle cup surrounding the inner cup, the middle cup including a second cup wall and a second bottom surface between the first cup wall and the second cup wall; an outer cup surrounding the middle cup, the outer cup including a third cup wall and a third bottom surface between the second cup wall and the third cup wall; and a separator for moving between a first position where a top surface of the separator is coplanar with the second bottom surface and a second position where the top surface of the separator is raised above the second bottom surface.

2. The device as claimed in claim 1, wherein when the separator is in the second position, the second bottom surface is divided by the separator into an inner bottom surface adjacent to the first cup wall and an outer bottom surface away from the first cup wall.

3. The device as claimed in claim 1, further comprising: a rotatable shaft extending through the first bottom surface; and a wafer holder mechanically coupled to the rotatable shaft.

4. A semiconductor manufacturing apparatus, comprising: an inner cup including a first cup wall and a first bottom surface; a middle cup surrounding the inner cup, the middle cup including a second cup wall and a second bottom surface between the first cup wall and the second cup wall; an outer cup surrounding the middle cup, the outer cup including a third cup wall and a third bottom surface between the second cup wall and the third cup wall; a separator for moving between the first position where a top surface of the separator is coplanar with the second bottom surface and the second bottom surface and the second position where the top surface of the separator is raised above the second bottom surface, wherein when the separator is in the second position, the second bottom surface is divided by the separator into an inner bottom surface adjacent to the first cup wall and an outer bottom surface away from the first cup wall; a first discharge hole in the inner bottom surface; a second discharge hole in the outer bottom surface; and a third discharge hole in the third bottom surface.

5. The device as claimed in claim 4, wherein the first discharge port and the third discharge port discharge into a first waste container, and wherein the second discharge port discharges into a second waste container different from the first waste container.

6. The device as claimed in claim 4, further comprising: a rotatable shaft extending through the first bottom surface; and a wafer holder mechanically coupled to the rotatable shaft.

7. A method of semiconductor manufacturing, comprising: placing a first wafer on a wafer holder, the wafer holder being mechanically fixed to a rotatable shaft surrounded by an inner cup, the inner cup being surrounded by a middle cup, and the middle cup being surrounded by an outer cup; moving the first wafer to a first position above a first cup wall of the inner cup but below a second cup wall of the middle cup; dispersing a first developer above the first wafer; and rotating the first wafer while collecting excess first developer in a first channel between the first cup wall and the second cup wall. Remove the first wafer; place a second wafer on the wafer holder; move the second wafer to a second position above the second cup wall of the middle cup but below the third cup wall of the outer cup; raise a separator wall in the first channel to divide the first channel into an inner channel closer to the first cup wall and an outer channel closer to the second cup wall; A second developer is dispersed above the second wafer; the second wafer is rotated while excess second developer is collected in a second channel and the internal channel between the second cup wall and the third cup wall; And remove the second wafer.

8. The method as described in claim 7, wherein the first developer is a positive developer and the second developer is a negative developer.

9. The method as described in claim 7, wherein the internal channel includes a first discharge port, wherein the external channel includes a second discharge port, and wherein the second channel includes a third discharge port.

10. The method as described in claim 7, wherein moving the second wafer to the second position and raising the separator wall are performed simultaneously.

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