Physical layer circuit with improved read gating

Abstract

A physical layer circuit with improved read gate control includes a delay circuit and a control circuit. In a first mode, corresponding to a first instruction, the control circuit forms a first reference edge in response to a first gating edge formed by a memory, and the delay circuit forms a first internal edge; corresponding to a second instruction, the control circuit forms a second reference edge in response to a second gating edge formed by the memory, and the delay circuit forms a second internal edge based on a first time difference between the first internal edge and the first reference edge, such that a second time difference between the second internal edge and the second reference edge is less than the first time difference, for example, such that a plurality of times the second time difference is less than the first time difference.

Description

Technical Field

[0001] This invention relates to a physical layer circuit with improved read gate control, and more particularly to a physical layer circuit for accessing memory and capable of quickly locking the correct read gate control timing in training mode. Prior Technology

[0002] Memory is an indispensable component of modern electronic devices, and the physical layer circuitry used to access memory has become a key focus of modern electronic technology research and development. Summary of the Invention

[0003] One objective of this invention is to provide a physical layer circuit (e.g., 10, FIG. 1) with improved read gating, which can be coupled to a memory (e.g., 20, FIG. 1). This physical layer circuit may include a delay circuit (e.g., 110, FIG. 1), a gating circuit (e.g., 120, FIG. 1), and a detection circuit (e.g., 130, FIG. 1). The gating circuit can be coupled to the delay circuit and a select signal (e.g., DQS, FIG. 1), and the detection circuit can be coupled to the delay circuit and the gating circuit. In a first mode (e.g., a training mode), the physical layer circuit can transmit a first instruction (e.g., cmd1, FIG. 4a) to the memory, causing the memory to respond to the first instruction by sequentially forming a plurality of first gating edges in the select signal (e.g., the edge where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tc1 and tcc1, FIG. 4a). In response to the earliest of the plurality of first gating edges (e.g., the gating edge at time tc1, FIG. 4a), the control circuit can form a first reference edge (e.g., hr1, FIG. 4a) in a reference signal (e.g., rdgt_ref, FIG. 1 and FIG. 4a). Corresponding to the first instruction, the delay circuit can form a first internal edge (e.g., hn1, FIG. 4a) in an internal signal (e.g., rdgt_fbck, FIG. 1 and FIG. 4a), and the detection circuit can detect a first time difference (e.g., dt1, FIG. 4a) between the first internal edge and the first reference edge, and reflect the corresponding detection result in a control signal (e.g., s_c, FIG. 1). In this first mode, the physical layer circuitry can further transmit a second instruction (e.g., cmd2, Figure 4b) to the memory, enabling the memory to sequentially form a plurality of second gating edges in the gating signal in response to the second instruction (e.g., the edge where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tc2 and tcc2, Figure 4b). Responding to the earliest of the plurality of second gating edges (e.g., the gating edge at time point tc2, Figure 4b), the control circuitry can further form a second reference edge (e.g., hr2, Figure 4b) in the reference signal. Corresponding to the second instruction, the delay circuitry can further form a second internal edge (e.g., hn2, Figure 4b) in the internal signal according to the control signal, such that a second time difference (e.g., dt2, Figure 4b) between the second internal edge and the second reference edge is less than the first time difference.

[0004] In one embodiment (e.g., Figures 4a and 4b), when the delay circuit makes the second time difference less than the first time difference, the delay circuit may make a complex multiple (integer multiple) of the second time difference less than the first time difference.

[0005] In one embodiment (e.g., Figures 4a and 4b), the first time difference is greater than a complex multiple (integer multiple) of an interface clock cycle (e.g., T0, Figure 1); and when the delay circuit makes the second time difference less than the first time difference, the delay circuit may be such that the second time difference is less than the interface clock cycle.

[0006] In one embodiment (e.g., Figure 5), in a second mode (e.g., a normal mode), the physical layer circuit can further transmit a third instruction (e.g., cmd[i], Figure 5) to the memory, enabling the memory to respond to the third instruction by sequentially forming a plurality of third gating edges in the gating signal (e.g., the edge where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i], Figure 5), and enabling the memory to respond to the third instruction by providing a third data string (e.g., u[i], Figure 5) in a data signal (e.g., DQ, Figures 1 and 5). Corresponding to the third instruction, the delay circuit can further form a gate leading edge (e.g., hp[i], Figure 5) and a gate trailing edge (e.g., hpp[i], Figure 5) in a gate signal (e.g., rd_gt, Figures 1 and 5) according to the control signal. Based on the gate control signal, the effect control circuit can further filter out those located between the gate control leading edge and the gate control trailing edge from the plurality of third gating edges, and reflect the filtering result in a gate control selection signal (e.g., vDQS, Figures 1 and 5). That is, the effect control circuit can filter out a subset from the plurality of third gating edges, and each third gating edge in the subset occurs between the gate control leading edge and the gate control trailing edge. Furthermore, the physical layer circuit may also include a data circuit (e.g., 50, Figure 1); the data circuit may be coupled to the effect control circuit and the data signal, and can sample the data signal according to the timing of the gate control selection signal to retrieve the third data string.

[0007] In one embodiment (e.g., FIG. 5), corresponding to the third instruction, the delay circuit can further form a third internal edge (e.g., hn[i], FIG. 5) in the internal signal based on the control signal. Based on the filtering result, the control circuit can further form a third reference edge (e.g., hr[i], FIG. 5) in the reference signal, and the detection circuit can further detect a third time difference (e.g., dt[i], FIG. 5) between the third internal edge and the third reference edge, and make the corresponding detection result reflected in the control signal. The gate leading edge can be before the third internal edge, and the gate trailing edge can be after the third internal edge.

[0008] In one embodiment (e.g., FIG. 5), when the effect control circuit forms the third reference edge in the reference signal based on the screening result, the effect control circuit may form the third reference edge in the reference signal in response to the earliest one of the plurality of third gating edges that occurs after the gate leading edge (e.g., the gating edge at time point tc[i], FIG. 5).

[0009] In one embodiment (e.g., FIG. 1), the physical layer circuit may further include a filter circuit (e.g., 140, FIG. 1) coupled between the detection circuit and the delay circuit. When the detection circuit detects the third time difference and reflects the corresponding detection result in the control signal, the detection circuit may reflect the corresponding detection result in a detection signal (e.g., s_d, FIG. 1), and the filter circuit may perform signal processing (e.g., filtering) on ​​the detection signal and reflect the result of the signal processing (filtering) in the control signal.

[0010] In one embodiment (e.g., FIG. 5), when the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit may form the third internal edge at a third internal edge time point (e.g., tn[i], FIG. 5). The third internal edge time point may be after a third reference time point (e.g., to[i], FIG. 5), and the interval between the third reference time point and the third internal edge time point (e.g., dn[i], FIG. 5) may include a coarse adjustment period (e.g., Tn1, FIG. 5) and a fine adjustment period (e.g., Tn[i], FIG. 5). The coarse adjustment period may be a multiple of the interface clock cycle (e.g., T0, FIG. 5), and the fine adjustment period may be less than the interface clock cycle.

[0011] In one embodiment (e.g., Figure 5), the coarse adjustment period can be substantially equal to the first time difference minus the second time difference.

[0012] In one embodiment (e.g., Figures 1 and 5), the control signal may include a coarse adjustment signal (e.g., s_cr, Figure 1) and a fine adjustment signal (e.g., s_cf, Figure 1); when the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit may wait for the coarse adjustment period and the fine adjustment period according to the coarse adjustment signal and the fine adjustment signal respectively, and form the third internal edge at the time point of the third internal edge after the waiting ends.

[0013] In one embodiment (e.g., Figures 1 and 5), the delay circuit may include a counter (e.g., 1101, Figure 1), and the coarse adjustment signal may reflect a coarse adjustment number (e.g., Nk1, Figures 4a and 4b); when the delay circuit waits for the coarse adjustment period, the counter may count the number of interface clock cycles that have elapsed for the coarse adjustment period.

[0014] In one embodiment (e.g., Figures 4a, 4b, and 5), the number of coarse adjustments may be related to the first time difference.

[0015] In one embodiment (e.g., FIG. 1), the delay circuit may include a controlled delay line (e.g., 1102, FIG. 1). When the delay circuit waits for the fine-tuning period, the controlled delay line may wait for the fine-tuning period to pass; and the length of the fine-tuning period may be controlled by the fine-tuning signal.

[0016] In one embodiment (e.g., FIG. 5), when the detection circuit detects the third time difference between the third inner edge and the third reference edge, the operation of the detection circuit may include: comparing whether the third inner edge is earlier or later than the third reference edge.

[0017] In one embodiment (e.g., FIG4a), when the detection circuit detects the first time difference between the first internal edge and the first reference edge and makes the corresponding detection result reflectable in the control signal, the operation of the detection circuit may include: counting how many interface clock cycles the first time difference covers and making the counting result reflectable in the control signal.

[0018] In one embodiment (e.g., Figures 1 and 6a), in a second mode (e.g., a normal mode), the physical layer circuitry further sequentially transmits a third instruction (e.g., cmd[i], Figure 6a) and a fourth instruction (e.g., cmd[i+1], Figure 6a) to the memory, causing the memory to respond to the third and fourth instructions by sequentially forming a plurality of response gating edges in the gating signal (e.g., the edge where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i+1], Figure 6a), and causing the memory to also respond to the third and fourth instructions by providing a third data string (e.g., u[i], Figure 6a) and a fourth data string (e.g., u[i+1], Figure 6a) in a data signal (e.g., DQ, Figures 6a and 6b). If the interval between the third instruction and the fourth instruction (e.g., Tcc[i], Fig. 6a) is greater than a minimum interval period (e.g., T_min, Fig. 6a), the delay circuit can further form a third gate leading edge, a third gate trailing edge, a fourth gate leading edge and a fourth gate trailing edge (e.g., hp[i], hpp[i], hp[i+1] and hpp[i+1], Fig. 6a) in a gate signal (e.g., rd_gt, Fig. 1 and Fig. 6a) according to the control signal (e.g., s_c, Fig. 1), and the control circuit can further filter out one or more third gate gating edges (e.g., the gating edge between time points tp[i] and tpp[i]) and one or more fourth gate gating edges (e.g., the gating edge between time points tp[i+1] and tpp[i+1]) from the plurality of response gating edges according to the gate signal. Each of the third gate selection edges can be one of the plurality of response selection edges, and can be located between the leading edge and the trailing edge of the third gate; each of the fourth gate selection edges can be one of the plurality of response selection edges, and can be located between the leading edge and the trailing edge of the fourth gate. The physical layer circuit may further include a data circuit (e.g., 50, FIG. 1) coupled to the control circuit. The data circuit can sample the data signal according to one or more third gate selection edges to retrieve the third data string, and can sample the data signal according to one or more fourth gate selection edges to retrieve the fourth data string.

[0019] In one embodiment (e.g., Figures 1 and 6b), in a second mode (e.g., a normal mode), the physical layer circuitry further transmits a third instruction (e.g., cmd[i], Figure 6b) and a fourth instruction (cmd[i+1], Figure 6b) sequentially to the memory, enabling the memory to respond to the third and fourth instructions by sequentially forming a plurality of response gating edges in the gating signal (e.g., the edge where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i+1], Figure 6b), and enabling the memory to also respond to the third and fourth instructions by providing a third data string (e.g., u[i], Figure 6b) and a fourth data string (e.g., u[i+1], Figure 6b) in a data signal (e.g., DQ, Figure 6b). If the interval between the third instruction and the fourth instruction (e.g., Tcc[i], Figure 6b) is not greater than a minimum interval time period (e.g., T_min, Figure 6b), the delay circuit can further form an integrated gate leading edge and an integrated gate trailing edge (e.g., hp[i] and hpp[i+1], Figure 6b) in a gate signal (e.g., rd_gt, Figures 1 and 6b) according to the control signal. The control circuit can further filter out one or more gate selection edges (e.g., the selection edge between time points tp[i] and tpp[i+1]) from the plurality of response selection edges according to the gate signal; wherein each gate selection edge is one of the plurality of response selection edges and is located between the integrated gate leading edge and the integrated gate trailing edge. The physical layer circuit may further include a data circuit (e.g., 50, FIG. 1) coupled to the control circuit; the data circuit may sample the data signal according to one or more gate selection edges to retrieve the third data string and the fourth data string.

[0020] One objective of this invention is to provide an improved physical layer circuit (e.g., 10, FIG. 1) for read gate control, coupled to a memory (e.g., 20, FIG. 1). The physical layer circuit may include a delay circuit (e.g., 110, FIG. 1), a control circuit (e.g., 120, FIG. 1), and a detection circuit (e.g., 130, FIG. 1). The control circuit may be coupled to the delay circuit and a select signal (e.g., DQS_t, FIG. 1); the detection circuit may be coupled to the delay circuit and the control circuit. The physical layer circuit may transmit an instruction (e.g., cmd1, cmd2, or cmd[i], FIG. 4a, FIG. 4b, or FIG. 5) to the memory, causing the memory to sequentially form a plurality of select edges in the select signal in response to the instruction. Corresponding to the instruction, the delay circuit forms an internal edge (e.g., hn1, hn2, or hn[i], FIG. 4a, FIG. 4b, or FIG. 5) in an internal signal (e.g., rdgt_fbck, FIG. 1). In a first mode (e.g., a training mode, Figure 4a or Figure 4b), the control circuit can form a reference edge (e.g., hr1 or hr2, Figure 4a or Figure 4b) in a reference signal (e.g., rdgt_ref, Figure 1) in response to the earliest of the plurality of gating edges. In a second mode (e.g., a normal mode, Figure 5), the delay circuit can further form a gate leading edge (e.g., hp[i], Figure 5) in a gate signal (e.g., rd_gt, Figures 1 and 5), and the control circuit can further form the reference edge in the reference signal in response to the nearest one after the gate leading edge (e.g., the gating edge at time point tc[i], Figure 5). The gate leading edge is earlier than the inner edge. The detection circuit can detect the time difference between the internal edge and the reference edge (e.g., dt1, dt2 or dt[i], Figure 4a, Figure 4b or Figure 5) and reflect the corresponding detection result in a detection signal (e.g., s_d, Figure 1).

[0021] In one embodiment (e.g., FIG. 1), the physical layer circuitry further includes a filtering circuit (e.g., 140, FIG. 1) coupled between the detection circuit and the delay circuit. The filtering circuit can filter the detection signal to provide a control signal (e.g., s_c, FIG. 1). When the delay circuit forms the internal edge in the internal signal, the delay circuit can determine when to form the internal edge in the internal signal based on the control signal.

[0022] In one embodiment (e.g., FIG. 5), when the delay circuit forms the internal edge in the internal signal, the delay circuit may wait for a coarse adjustment period (e.g., Tn1, FIG. 5) and a fine adjustment period (e.g., Tn[i], FIG. 5) to pass, and form the internal edge at an internal edge time point (e.g., tn[i], FIG. 5) after the waiting period ends; wherein, the coarse adjustment period may be an integer multiple of an interface clock cycle (e.g., T0, FIG. 1 and FIG. 5), and the fine adjustment period may not be greater than the interface clock cycle.

[0023] One object of the present invention is to provide an improved read gate control method, wherein the method can be implemented by a read gate control circuit (e.g., 100, FIG. 1) in a physical layer circuit (e.g., 10, FIG. 1); the physical layer circuit can be coupled to a memory (e.g., 20, FIG. 1). The method may include a plurality of steps. One of these steps may be: when the memory responds to a first instruction (e.g., cmd1, FIG. 4a) to form a plurality of first gating edges in a select signal (e.g., DQS, FIG. 4a), a first reference edge (e.g., hr1, FIG. 4a) is formed in a reference signal (e.g., rdgt_ref, FIG. 4a) based on one of these first gating edges (e.g., the earliest one). One of these steps may be: corresponding to the first instruction, a first internal edge (e.g., hn1, FIG. 4a) is formed in an internal signal (e.g., rdgt_fbck, FIG. 1 and FIG. 4a). One of these steps could be: detecting a first time difference (e.g., dt1, FIG. 4a) between the first internal edge and the first reference edge, and reflecting the corresponding detection result in a control signal. Another step could be: when the memory responds to a second instruction (e.g., cmd2, FIG. 4b) to form a plurality of second gating edges in the gating signal, forming a second reference edge (e.g., hr2, FIG. 4b) in the reference signal based on one of these second gating edges (e.g., the earliest one). Yet another step could be: corresponding to the second instruction, forming a second internal edge (e.g., hn2, FIG. 4b) in the internal signal based on the control signal, such that a second time difference (e.g., dt2, FIG. 4b) between the second internal edge and the second reference edge is less than the first time difference, for example, making a plurality of multiples (integer multiples) of the second time difference less than the first time difference.

[0024] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Simple Explanation of the Diagram

[0025] Figure 1 illustrates an electronic device according to an embodiment of the present invention, wherein the electronic device may include a physical layer circuit and a memory, and the physical layer circuit may include a read gate circuit, etc. Figures 2a to 2d and 3a to 3c illustrate the waveform and timing examples of relevant signals when the physical layer circuit reads memory in a normal mode. Figures 4a to 4c illustrate examples of waveform timing implementations of relevant signals when the gate control circuit operates in a training mode. Figures 5, 6a, and 6b illustrate examples of waveform timing implementations for reading relevant signals when the gate control circuit operates in this normal mode. Implementation

[0026] Figure 1 illustrates an electronic device 1000 according to an embodiment of the present invention, which may be a smartphone, tablet computer, laptop computer, desktop computer, smart home appliance, or smart office appliance, etc. The electronic device 1000 may include one or more processing units PU[1] to PU[M], a memory controller 22, a physical layer circuit 10, and a memory 20. In the electronic device 1000, the processing units PU[1] to PU[M] may be coupled to the memory controller 22 via a bus 26, and the physical layer circuit 10 may be coupled between the memory controller 22 and the memory 20.

[0027] In the electronic device 1000, each processing unit PU[m] (one of PU[1] to PU[M]) can be a central processing unit (or core unit), application processing unit, logic processing unit, arithmetic processing unit, signal processing unit, graphics processing unit, neural network processing unit, or peripheral unit, etc. When the memory 20 operates in a normal mode, the memory 20 can provide memory space for the processing units PU[1] to PU[M]. In one embodiment, the memory 20 can be a synchronous dynamic random-access memory (SDRAM), such as a double data rate (DDR) synchronous dynamic random-access memory. In one embodiment, memory 20 may be a memory conforming to an industry standard; for example, this industry standard may be a standard developed by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association, such as standards related to fourth-generation dual data rate (DDR4), fifth-generation dual data rate (DDR5), fourth-generation low-power dual data rate (LPDDR4, where LP stands for low power) and / or fifth-generation low-power dual data rate (LPDDR5).

[0028] The physical layer circuit 10 may include a clock circuit 30, an instruction circuit 40, a data circuit 50, and an input / output circuit 60; to implement the present invention, the physical layer circuit 10 may further include a read gate circuit 100. In the physical layer circuit 10, the clock circuit 30 may include two output terminals, respectively coupled to two nodes n7 and n8. The instruction circuit 40 may include one output terminal, coupled to a node n9. The data circuit 50 may include one input terminal and two connection terminals, respectively coupled to three nodes n6, n10, and n11. The input / output circuit 60 may be coupled to the memory 20 via lines 12a to 12d; the input / output circuit 60 may include two input terminals, two output terminals, and four connection terminals, respectively coupled to nodes n7 and n9, lines 12a and 12b, line 12c, line 12d, and nodes n10 and n11. The gate control circuit 100 may include an input terminal and an output terminal, which are coupled to nodes n11 and n6 respectively.

[0029] In the physical layer circuit 10, the clock circuit 30 can provide a pair of differential clocks CK_t and CK_c at node n7, and another clock ck0 at node n8. As shown in Figure 1, clocks CK_t and CK_c can oscillate between two quasi-vc1 and vc0, with equal oscillation periods and a 180-degree phase difference. In one embodiment, quasi-vc0 and vc1 can represent logic 0 and logic 1, respectively. The edge where clock CK_t changes from quasi-vc0 to quasi-vc1 can be considered a main edge of clock CK_t, and the interval between two adjacent main edges of clock CK_t can be a period T0 of clock CK_t; for example, period T0 can represent the industry standard time measurement unit nCK. Clock ck0 can oscillate between two quasi-vk0 and vk1; in one embodiment, the oscillation period of clock ck0 can be half of clock CK_t. In one embodiment, quasi-vk0 and vk1 can represent logic 0 and logic 1, respectively. The edge where clock ck0 changes from level vk0 to level vk1 can be considered a main edge of clock ck0, and each main edge of clock CK_t can be synchronized (e.g., aligned) with a corresponding main edge of clock ck0. In one embodiment, physical layer circuit 10 can operate under the triggering of clock ck0, and input / output circuit 60 can drive line 12a according to the timing of clocks CK_t and CK_c, so that memory 20 can operate according to the timing of clocks CK_t and CK_c. In physical layer circuit 10, clocks CK_t and CK_c can be considered as interface clocks, period T0 can be considered as an interface clock period, and clock ck0 can be considered as an internal clock.

[0030] In the physical layer circuit 10, the instruction circuit 40 can provide a signal cmd at node n9, and the input / output circuit 60 can drive line 12b according to the signal cmd. When the processing unit PU[m] requests to store a piece of write data into memory 20, the memory controller 22 can control the physical layer circuit 10 according to this request; under the control of the memory controller 22, the instruction circuit 40 in the physical layer circuit 10 can keep memory 20 in a normal mode and can form a corresponding write instruction (not shown) in the signal cmd; the data circuit 50 can drive a signal DQ on node n10 according to the content of the write data, and can drive a signal DQS on node n11 according to the timing of the write data. According to the signal cmd, the input / output circuit 60 can drive line 12b to transmit the write instruction to memory 20. The data circuit 50 drives node n10, causing the input / output circuit 60 to drive line 12c accordingly, and consequently, the memory 20 receives a write data signal (not shown). The data circuit 50 drives node n11, causing the input / output circuit 60 to drive line 12d accordingly, and consequently, the memory 20 learns the timing of the write data in the write data signal. Based on the timing of the write data, the memory 20 can sample the write data signal to retrieve the write data, and can store the write data according to the write instruction.

[0031] On the other hand, when the processing unit PU[m] requests to read memory 20, the memory controller 22 can control the physical layer circuit 10 according to this request. Under the control of the memory controller 22, the instruction circuit 40 in the physical layer circuit 10 can keep memory 20 in normal mode and can generate a corresponding read instruction (not shown) in the signal cmd. According to the signal cmd, the input / output circuit 60 can drive line 12b to transmit the read instruction to memory 20. In response to this read instruction, memory 20 can read a corresponding piece of stored data (not shown), can drive line 12c according to the content of the stored data, and can drive line 12d according to the timing of the stored data. The driving of line 12c by memory 20 enables input / output circuit 60 to drive the signal DQ of node n10 accordingly, and also enables data circuit 50 to receive a stored data signal (not shown); the driving of line 12d by memory 20 enables input / output circuit 60 to drive the signal DQS of node n11 accordingly, and also enables read gate circuit 100 to know the timing of the stored data in the stored data signal. Read gate circuit 100 can reflect the timing of the stored data in a signal vDQS of node n6; based on signal vDQS, data circuit 50 can sample the stored data signal to retrieve the stored data, and memory controller 22 can send the retrieved stored data back to processing unit PU[m].

[0032] In the physical layer circuit 10, signal cmd can be considered a command signal, signal DQ can be considered a data signal, signal DQS can be considered a selection signal, and signal vDQS can be considered a gate control selection signal. In one embodiment, signal DQS may include a pair of differential signals DQS_t and DQS_c. In one embodiment, signal vDQS may include a pair of differential signals vDQS_t and vDQS_c.

[0033] Continuing from Figure 1, Figures 2a to 2d illustrate the waveform timing examples of relevant signals when the physical layer circuit 10 reads memory 20 in normal mode. As shown in Figure 2a, when reading memory 20 in normal mode, the instruction circuit 40 can form an instruction cmd[i], such as a read instruction, in the signal cmd between two time points ta[i] and taa[i]. In one embodiment, the interval between time points ta[i] and taa[i] can be equal to four cycles T0. Time points ta[i] and taa[i] can be located at two opposite edges of clock CK_c (the edge where clock CK_c changes from level vc0 to level vc1). The input / output circuit 60 in the physical layer circuit 10 can transmit the instruction cmd[i] to memory 20 via line 12b. In response to this instruction cmd[i], memory 20 can read the corresponding stored data (not shown), drive circuit 12c according to the content of the stored data, and drive circuit 12d according to the timing of the stored data.

[0034] The driving of the memory 20 on line 12d enables signals DQS_t and DQS_c to exhibit a definite waveform between two time points tz[i] and tzz[i], thereby sequentially forming multiple gating edges in signals DQS_t and DQS_c. Each gating edge in signal DQS_t can be an edge where signal DQS_t changes from one quasi-vq0 to another quasi-vq1, and each gating edge in signal DQS_c can be an edge where signal DQS_c changes from quasi-vq0 to quasi-vq1. In one embodiment, quasi-vq0 and vq1 can represent logic 0 and logic 1, respectively. Before and after memory 20 responds to instruction cmd[i] and drives line 12d, memory 20 does not drive line 12d. Therefore, the waveforms of signals DQS_t and DQS_c before time point tz[i] and after time point tzz[i] are unclear, which are represented by shading lines in Figure 2a.

[0035] The drive of memory 20 to line 12c enables signal DQ to present a distinct waveform between two time points td[i] and tdd[i], thereby providing a data string u[i] in signal DQ, which is the stored data read from memory 20. The data string u[i] can have a plurality of string columns of bits, and the number of these bits can be represented by a parameter BL (burst length, not shown) in the industry standard; for example, the parameter BL can be an even number. The data string u[i] can last for a time period Tdq0, that is, the interval between time points td[i] and tdd[i] can be equal to the time period Tdq0; in one embodiment, the length of the time period Tdq0 can be equal to half of the parameter BL multiplied by the period T0 (i.e., Tdq0 = (BL / 2)*T0). Before and after memory 20 responds to instruction cmd[i] and drives line 12c, memory 20 does not drive line 12c. Therefore, the waveform of signal DQ before time point td[i] and after time point tdd[i] is unclear, which is represented by a shaded line in Figure 2a.

[0036] Between two time points tc[i] and tcc[i], the gating edges in signals DQS_t and DQS_c can correspond to the timing of each bit in the data string u[i]. For example, the gating edge of signal DQS_t between time points tc[i] and tcc[i] can correspond to the odd-order bits (first, third, fifth, etc.) of data string u[i], while the gating edge of signal DQS_c between time points tc[i] and tcc[i] can correspond to the even-order bits (second, fourth, sixth, etc.) of data string u[i]. Time point tc[i] can be located at a gating edge of signal DQS_t, and time point tcc[i] can be located at a gating edge of signal DQS_c. The interval between time points tc[i] and tcc[i] can be equal to a time period Tdqs0, for example, period T0 multiplied by a value (BL / 2-0.5). Between time points tc[i] and tcc[i], the number of gating edges in signal DQS_t can be equal to half of parameter BL, and the number of gating edges in signal DQS_c can be equal to half of parameter BL. Because the routing distributions of lines 12c and 12d may be different, time point tc[i] can be earlier than time point td[i], and the interval between the two can be equal to a time period dd[i]; where the length of time period dd[i] can represent a parameter tDQSQ (gating-to-data time difference (DQS-DQ skew), not shown) in the industry standard.

[0037] Since the transmission of instruction cmd[i] and the response of memory 20 require time, time point tc[i] can lag behind a time point tb[i] in instruction cmd[i]. Here, time point tb[i] can be the last major edge of clock CK_t before the end of instruction cmd[i] (at time point taa[i]). There can be another time point tbb[i] between time point tb[i] and time point tc[i]. The interval between time points tb[i] and tbb[i] can be equal to a time period RL0, and the interval between time points tbb[i] and tc[i] can be equal to a time period d[i]. Here, time period RL0 can be equal to the period T0 multiplied by a parameter RL (read latency, not shown) in the industry standard. Time period d[i] can represent another parameter tDQSCK (DQS output access time from CK_t / CK_c), not shown.

[0038] As shown in Figure 2a, time point tz[i] can be earlier than time point tc[i], and can be separated from time point tc[i] by a time interval Tpre[i]. The time interval Tpre[i] is the preamble added to the signals DQS_t and DQS_c by memory 20; the length of the time interval Tpre[i] can represent a parameter tRPRE (read preamble, not shown) in the industry standard. Furthermore, as shown in Figure 2a, time point tcc[i] can be earlier than time point tzz[i], and can be separated from time point tzz[i] by a time interval Tpst[i]. The time interval Tpst[i] is the postamble added to the signals DQS_t and DQS_c by memory 20; the length of the time interval Tpst[i] can represent a parameter tRPST (read postamble, not shown) in the industry standard.

[0039] In the example of Figure 2a, the prefix of signals DQS_t and DQS_c in the prefix period Tpre[i] is the industry standard toggle form, and the suffix in the suffix period Tpst[i] is the industry standard 0.5nCK form; that is, the period Tpst[i] can be equal to half a cycle T0. The prefix and suffix of signals DQS_t and DQS_c can also be in other forms, as shown in Figures 2b to 2d. In the example of Figure 2b, the prefix of signals DQS_t and DQS_c in the prefix period Tpre[i] is the toggle form, and the suffix in the suffix period Tpst[i] is the industry standard 1.5nCK form; that is, the period Tpst[i] can be equal to one and a half cycles T0, and the suffix period Tpst[i] of signals DQS_t and DQS_c will be extended by one cycle T0 more than half a cycle T0. In the example of Figure 2c, the prefixes of signals DQS_t and DQS_c in the prefix period Tpre[i] are in the industry standard static form, while the suffixes in the suffix period Tpst[i] are in the 0.5nCK form. In the example of Figure 2d, the prefixes of signals DQS_t and DQS_c in the prefix period Tpre[i] are in the static form, while the suffixes in the suffix period Tpst[i] are in the 1.5nCK form.

[0040] As mentioned earlier, the gating edge between time points tc[i] and tcc[i] of signals DQS_t and DQS_c corresponds to the timing of each bit in the data string u[i]. Therefore, the gating edge between time points tc[i] and tcc[i] of signals DQS_t and DQS_c can be considered as a valid gating edge. When the data circuit 50 in the physical layer circuit 10 (Figure 1) needs to sample the signal DQ to retrieve the stored data returned from the memory 20 to the physical layer circuit 10, these valid gating edges can be used as the basis for sampling. Among the multiple valid gating edges between time points tc[i] and tcc[i] of signals DQS_t and DQS_c, the gating edge occurring at time point tc[i] is the earliest valid gating edge. On the other hand, as shown in Figures 2a to 2d, signals DQS_t and / or DQS_c can also have gating edges in the prefix period Tpre[i] and / or suffix period Tpst[i]. However, if the data circuit 50 in the physical layer circuit 10 incorrectly samples the signal DQ based on the gating edges in the prefix period Tpre[i] and / or suffix period Tpst[i], it will sample areas in the signal DQ where the waveform is unclear (shaded areas), and will be unable to correctly retrieve the stored data in memory 20. Therefore, the gating edges of signals DQS_t and DQS_c in the prefix and suffix can be considered invalid gating edges. The read gate circuit 100 in the physical layer circuit 10 can remove the prefix and suffix in the signals DQS_t and DQS_c, and reflect the removal result in the signals vDQS_t and vDQS_c, so that the data circuit 50 can correctly sample the signal DQ according to the signals vDQS_t and vDQS_c.

[0041] When processing units PU[1] to PU[M] frequently access memory 20, the physical layer circuit 10 will also frequently transmit the corresponding instructions to memory 20, thus shortening the interval between two adjacent instructions. Continuing from Figures 1 and 2a to 2d, Figures 3a to 3c illustrate the waveform timing of related signals when the physical layer circuit 10 accesses memory 20 with two adjacent instructions cmd[i] and cmd[i+1] in normal mode. As shown in Figure 3a, in response to a certain access request (e.g., a read request) from processing units PU[1] to PU[M], the instruction circuit 40 can form an instruction cmd[i] (e.g., a read instruction) in the signal cmd between time points ta[i] and taa[i]. In response to the next access request (e.g., the next read request) from processing units PU[1] to PU[M], the instruction circuit 40 can form a next instruction cmd[i+1] (e.g., the next read instruction) in the signal cmd between time points ta[i+1] and taa[i+1] after time point taa[i].

[0042] As described in Figures 2a to 2d, in response to the instruction cmd[i], memory 20 can drive lines 12c and 12d. The driving of line 12d by memory 20 can cause signals DQS_t and DQS_c to form multiple gating edges with defined waveforms between time points tz[i] and tzz[i]. The driving of line 12c by memory 20 can provide the data string u[i] in signal DQ between time points td[i] and tdd[i]. Here, time point tz[i] can be before time point tc[i], and separated from time point tc[i] by a prefix time period Tpre[i]; time point tzz[i] can be after time point tcc[i], and separated from time point tcc[i] by a suffix time period Tpst[i]; time point tcc[i] can be after time point tc[i], and separated from time point tc[i] by a time period Tdqs0. Regarding signal DQS, time point tc[i] can be after another time point tbb[i], with an interval of time d[i] between them; time point tbb[i] can be after time point tb[i], with an interval of time RL0 between them; time point tb[i] can be the last main edge of clock CK_t before the end of instruction cmd[i] (time point taa[i]). Regarding signal DQ, time point td[i] can be after time point tc[i], with an interval of time dd[i] between them; time point tdd[i] can be after time point td[i], with an interval of time Tdq0 between them.

[0043] Similarly, in response to the instruction cmd[i+1], memory 20 can drive lines 12c and 12d; the driving of line 12d by memory 20 can make signals DQS_t and DQS_c form a plurality of gating edges with a defined waveform between two time points tz[i+1] and tzz[i+1], and the driving of line 12c by memory 20 can provide a data string u[i+1] in signal DQ between two other time points td[i+1] and tdd[i+1]. Regarding the signal DQS, time point tz[i+1] can be before time point tc[i+1], and separated from time point tc[i+1] by a prefix period Tpre[i+1]; time point tzz[i+1] can be after another time point tcc[i+1], and separated from time point tcc[i+1] by a suffix period Tpst[i+1]; time point tcc[i+1] can be after time point tc[i+1], and separated from time point tc[i+1] by a period Tdqs0; Time point tc[i+1] can be after time point tbb[i+1], separated from time point tbb[i+1] by a time interval d[i+1]; Time point tbb[i+1] can be after another time point tb[i+1], separated from time point tb[i+1] by a time interval RL0; Time point tb[i+1] can be the last main edge of clock CK_t before the end of instruction cmd[i+1] (time point taa[i+1]). Regarding signal DQ, time point td[i+1] can be after time point tc[i+1], separated from time point tc[i+1] by a time interval dd[i+1]; Time point tdd[i+1] can be after time point td[i+1], separated from time point td[i+1] by a time interval Tdq0.

[0044] The time point tb[i+1] of the subsequent instruction cmd[i+1] and the time point tb[i] of the preceding instruction cmd[i] can be separated by a time interval Tcc[i]. This time interval Tcc[i] can represent a parameter tCCD (CAS-to-CAS delay, not shown) in the industry standard. The more frequent the read demand, the closer the time points tb[i] and tb[i+1] of adjacent instructions cmd[i] and cmd[i+1] will be, and the shorter the time interval Tcc[i] between the time points tb[i] and tb[i+1] will be. Consequently, the time points tzz[i] (the end point of the suffix time interval Tpst[i]) and tz[i+1] (the start point of the prefix time interval Tpre[i+1]) of the signals DQS_t and DQS_c will also be closer. As shown in Figure 3a, since time point tzz[i] can be equal to (tb[i] + RL0 + d[i] + Tdqs0 + Tpst[i]), and time point tz[i+1] can be equal to (tb[i+1] + RL0 + d[i+1] - Tpre[i+1]), the difference between time points tzz[i] and tz[i+1] (tz[i+1] – tzz[i]) can be equal to (tb[i+1] - tb[i] + d[i+1] - d[i] - Tpre[i+1] - Tdqs0 - Tpst[i]). Furthermore, since (tb[i+1] – tb[i]) can be equal to Tcc[i], and the difference between time periods d[i+1] and d[i] is relatively small and can be considered zero, the difference between time points tz[i+1] and tzz[i] (tz[i+1] – tzz[i]) can be equal to (tz[i+1] – tzz[i]). – tzz[i]) can be further simplified to (Tcc[i] – Tdqs0 – Tpre[i+1] – Tpst[i]). Therefore, when time interval Tcc[i] equals the sum of time intervals Tpre[i+1], Tdqs0, and Tpst[i], time point tz[i+1] will coincide with tzz[i]. For ease of discussion, the sum of time intervals Tpre[i+1], Tdqs0, and Tpst[i] is defined as a time interval T_mrg[i], as shown in Figure 3a.

[0045] In the example of Figure 3a, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_mrg[i], which is sufficient to make time point tzz[i] lead time point tz[i+1]. However, when instructions cmd[i] and cmd[i+1] are closer and the time interval Tcc[i] is less than the time interval T_mrg[i], memory 20 can combine (merge) the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1], as shown in Figure 3b. In Figure 3b, memory 20 can continuously drive line 12d in response to instructions cmd[i] and cmd[i+1], so that signals DQS_t and DQS_c can continuously present a clear waveform between time point tcc[i] (the start point of the suffix corresponding to instruction cmd[i]) and time point tc[i+1] (the end point of the prefix corresponding to instruction cmd[i+1]), in order to combine the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1]. In contrast, in the example of Figure 3a, signals DQS_t and DQS_c do not continuously present a clear waveform between time points tcc[i] and tc[i+1]. In the example of Figure 3a, memory 20 does not combine the suffix corresponding to instruction cmd[i] with the prefix corresponding to instruction cmd[i+1]. After responding to instruction cmd[i], memory 20 will not drive line 20d for a period of time. Therefore, signals DQS_t and DQS_c will not have a clear waveform between time points tzz[i] and tz[i+1] (i.e., the shaded area).

[0046] In the example of Figure 3b, the waveform of signals DQS_t and DQS_c between time points tcc[i] and tc[i+1] due to the combination of prefix and suffix is ​​related to factors such as the form of the prefix, the form of the suffix, and the length of the time period Tcc[i]. This has been described in industry standards and will not be repeated here. In the example of Figure 3b, the explicit waveform of signals DQS_t and DQS_c between time points tcc[i] and tc[i+1] may form one or more gating edges, but these gating edges are all invalid gating edges.

[0047] As shown in Figure 3b, since the end point tdd[i] of the data string u[i] can be equal to (tb[i] + RL0 + d[i] + dd[i] + Tdq0) and the start point td[i+1] of the data string u[i+1] can be equal to (tb[i+1] + RL0 + d[i+1] + dd[i+1]), the difference between the time points tdd[i] and td[i+1] (td[i+1] – tdd[i]) can be equal to (tb[i+1] – tb[i] + d[i+1] – d[i] + dd[i+1] – dd[i] – Tdq0). Since the difference between time periods dd[i+1] and dd[i] (dd[i+1] – dd[i]) is relatively small and can be considered zero, the difference between time points tdd[i] and td[i+1] (td[i+1] – tdd[i]) can be further simplified to (Tcc[i] - Tdq0). Therefore, when time period Tcc[i] equals time period Tdq0, time points tdd[i] and td[i+1] will coincide. For ease of discussion, time period Tdq0 is defined as a time period T_min; time period T_min can be considered as a minimum interval time period.

[0048] In the example of Figure 3b, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_min, which is sufficient to make the end point tdd[i] of data string u[i] precede the start point td[i+1] of data string u[i+1]. However, when instructions cmd[i] and cmd[i+1] are closer and the time interval Tcc[i] equals the time interval T_min, the time points tdd[i] and td[i+1] will coincide. Memory 20 can seamlessly connect the data string u[i] corresponding to instruction cmd[i] and the data string u[i+1] of instruction cmd[i+1] in signal DQ, and can make the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] disappear in signals DQS_t and DQS_c, as shown in Figure 3c. In Figure 3c, memory 20 can continuously drive line 12d without interruption in response to instructions cmd[i] and cmd[i+1], so that signals DQS_t and DQS_c can continuously present a clear waveform between time point tz[i] (the start point of the prefix corresponding to instruction cmd[i]) and time point tzz[i+1] (the end point of the suffix corresponding to instruction cmd[i+1]). Between time point tc[i] (the end point of the prefix corresponding to instruction cmd[i]) and time point tcc[i+1] (the start point of the suffix corresponding to instruction cmd[i+1]), each gating edge of signals DQS_t and DQS_c is a valid gating edge and can correspond to a bit in data string u[i] or u[i+1]; that is, the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] will disappear.

[0049] Regardless of whether the suffix and prefix of the two instructions are not combined (Fig. 3a), combined (Fig. 3b), or disappear (Fig. 3c), the read gate circuit 100 of the present invention (Fig. 1) can remove invalid gating edges in signals DQS_t and DQS_c, and reflect the valid gating edges in signals DQS_t and DQS_c in signals vDQS_t and vDQS_c. As shown in Fig. 1, the read gate circuit 100 may include a delay circuit 110, an effect control circuit 120, a detection circuit 130, and a filter circuit 140. The delay circuit 110 may include one input terminal and two output terminals, respectively coupled to three nodes n4, n5, and n2. The effect control circuit 120 may include two input terminals and two output terminals, respectively coupled to nodes n5, n11, and two other nodes n1 and n6. The detection circuit 130 may include two input terminals and one output terminal, respectively coupled to nodes n1, n2, and another node n3. The filter circuit 140 may include an input terminal and an output terminal, respectively coupled to nodes n3 and n4. The delay circuit 110 may provide two signals rd_gt and rdgt_fbck at nodes n5 and n2 respectively, and the control circuit 120 may provide a signal rdgt_ref at node n1 and a signal vDQS (including signals vDQS_t and vDQS_c) at node n6. The detection circuit 130 may provide a signal s_d at node n3, and the filter circuit 140 may provide a signal s_c at node n4. Among them, the signal rdgt_ref can be regarded as a reference signal, the signal rdgt_fbck can be regarded as an internal signal, the signal rd_gt can be regarded as a gate control signal, and the signals s_d and s_c can be regarded as a detection signal and a control signal respectively.

[0050] To implement this invention, before the memory 20 operates in normal mode, the physical layer circuit 10 can first put the memory 20 into a training mode, such as the read preamble training mode in the industry standard. Continuing with FIG1, FIG4a to FIG4c illustrate the waveform timing of relevant signals when the read gate control circuit 100 operates in training mode. After putting the memory 20 into training mode, the instruction circuit 40 in the physical layer circuit 10 can issue an instruction cmd1 to the memory 20 between two time points ta1 and taa1, as shown in FIG4a. Before time point ta1, when the memory 20 has entered training mode, the memory 20 can drive line 12d to maintain signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and can drive line 12c to maintain signal DQ at a fixed level. Subsequently, in response to the instruction cmd1 from time points ta1 to taa1, memory 20 can correspondingly change the drive of lines 12c and 12d. The drive of line 12d by memory 20 can sequentially form a plurality of gating edges (edges changing from level vq0 to level vq1) in signals DQS_t and DQS_c between two time points tc1 and tcc1. The drive of line 12c by memory 20 can provide a data string u1 in signal DQ between two time points td1 and tdd1. As shown in Figure 4a, time point tcc1 can be after time point tc1, with an interval of time period Tdqs0; time point tc1 can be after another time point tbb1, with an interval of time period d1; time point tbb1 can be after yet another time point tb1, with an interval of time period RL0; time point tb1 can be the last main edge of clock CK_t before time point taa1. Time point td1 can be after time point tc1, and separated from time point tc1 by a time interval dd1; time point tdd1 can be after time point td1, and separated from time point td1 by a time interval Tdq0.

[0051] As shown in Figure 4a, corresponding to the earliest gating edge in the signal DQS_t (i.e., the gating edge at time point tc1), the control circuit 120 can change the signal rdgt_ref from one quasi-vr0 to another quasi-vr1 at a time point tr1, so as to form a main edge hr1 in the signal rdgt_ref. In one embodiment, time point tr1 can coincide with or be very close to time point tc1, and the quasi-vr0 and vr1 can represent logic 0 and logic 1, respectively. At another time point trr1 after time point tr1, the control circuit 120 can change the signal rdgt_ref from quasi-vr1 back to quasi-vr0, so as to form another reverse edge in the signal rdgt_ref. In one embodiment, the interval between time points trr1 and tr1 can be equal to a preset time period, such as period T0.

[0052] Corresponding to instruction cmd1, delay circuit 110 can change the signal rdgt_fbck from one quasi-vn0 to another quasi-vn1 at a time point tn1, so as to form a main edge hn1 in the signal rdgt_fbck. In one embodiment, time point tn1 can be after time point to1, and separated from time point to1 by a time interval dn1; time point to1 can be earlier than time point tbb1, and separated from time point tbb1 by a time interval g0. In one embodiment, the length of time interval g0 can be equal to a preset number (e.g., 4) multiplied by period T0. In one embodiment, quasi-vn0 and vn1 can represent logic 0 and logic 1, respectively. At another time point tnn1 after time point tn1, delay circuit 110 can change the signal rdgt_fbck from quasi-vn1 back to quasi-vn0, so as to form another reverse edge in the signal rdgt_fbck. In one embodiment, the interval between time points tnn1 and tn1 can be equal to a preset time period, such as period T0.

[0053] In some embodiments, the timing tn1 of the main edge hn1 can be timing tb1 plus one or more clock cycles (e.g., interface clock cycles or internal clock cycles). In some embodiments, the timing tn1 of the main edge hn1 can be located between timing tb1 and tc1. For example, the delay circuit 110 can determine the timing tn1 of the main edge hn1 based on the read delay (or time period RL0), wherein timing tn1 can be timing tbb1 minus one or more clock cycles (e.g., interface clock cycles or internal clock cycles), or timing tbb1 plus one or more clock cycles (e.g., interface clock cycles or internal clock cycles).

[0054] In the gate control circuit 100, the detection circuit 130 can detect the time difference dt1 between the main edges hn1 and hr1 (that is, the interval between time points tn1 and tr1) and reflect the corresponding detection result in the signal s_d (Figure 1). In one embodiment, when the detection circuit 130 detects the time difference dt1 and reflects the corresponding detection result in the signal s_d, the operation of the detection circuit 130 may include: counting how many periods T0 are covered in the time difference dt1 and reflecting the counting result in the signal s_d; the number Nk1 indicated in Figure 4a can represent that the detection circuit 130 counts that the time difference dt1 is covered by Nk1 periods T0. The filter circuit 140 (Figure 1) can perform signal processing (e.g., filtering) on ​​the signal s_d and reflect the result of the signal processing in the signal s_c. In training mode, memory 20 can continuously drive lines 12d and 12c after responding to instruction cmd1, maintaining signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining signal DQ at a fixed level.

[0055] As shown in Figure 4b, when instruction cmd1 ends at time point taa1 and memory 20 is still operating in training mode, instruction circuit 40 in physical layer circuit 10 can issue another instruction cmd2 to memory 20 between two time points ta2 and taa2; wherein time point ta2 can be after time point taa1. In response to instruction cmd2 at time points ta2 to taa2, memory 20 can correspondingly change the drive of lines 12c and 12d; the drive of line 12d by memory 20 can form a plurality of gating edges in signals DQS_t and DQS_c sequentially between two time points tc2 and tcc2, and the drive of line 12c by memory 20 can provide a data string u2 in signal DQ between two time points td2 and tdd2. As shown in Figure 4b, time point tcc2 can be after time point tc2, with an interval of time period Tdqs0; time point tc2 can be after another time point tbb2, with an interval of time period d2; time point tbb2 can be after yet another time point tb2, with an interval of time period RL0; time point tb2 can be the last main edge of clock CK_t before time point taa2. Time point td2 can be after time point tc2, with an interval of time period dd2; time point tdd2 can be after time point td2, with an interval of time period Tdq0.

[0056] As shown in Figure 4b, corresponding to the earliest gating edge in the signal DQS_t (i.e., the gating edge at time point tc2), the effect control circuit 120 can change the signal rdgt_ref from level vr0 to level vr1 at a time point tr2 to form a main edge hr2 in the signal rdgt_ref. In one embodiment, time point tr2 can coincide with or be very close to time point tc2. At another time point trr2 after time point tr2, the effect control circuit 120 can change the signal rdgt_ref from level vr1 back to level vr0. In one embodiment, the interval between time points trr2 and tr2 can be equal to the interval between time points trr1 and tr1.

[0057] Corresponding to instruction cmd2, delay circuit 110 can change the signal rdgt_fbck from level vn0 to level vn1 at a time point tn2, so as to form a main edge hn2 in the signal rdgt_fbck. In one embodiment, time point tn2 can be after another time point to2, and separated from time point to2 by a time interval dn2; time point to2 can be earlier than time point tbb2, and separated from time point tbb2 by a time interval g0. At another time point tnn2 after time point tn2, delay circuit 110 can change the signal rdgt_fbck from level vn1 back to level vn0, so as to form a reverse edge in the signal rdgt_fbck. In one embodiment, the interval between time points tnn2 and tn2 can be equal to the interval between time points tnn1 and tn1. The detection circuit 130 can detect the time difference dt2 between the main edges hn2 and hr2 (that is, the time difference between time points tn2 and tr2) and reflect the corresponding detection result in the signal s_d. The filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d and reflect the result of the signal processing in the signal s_c. In training mode, the memory 20 can continuously drive the lines 12d and 12c after responding to the instruction cmd2, maintaining the signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining the signal DQ at a fixed level.

[0058] In Figures 4a and 4b, time points to1 and to2 can be considered as reference time points; the interval between time points to2 and tb2 can be equal to the interval between time points to1 and tb1. That is, time points to1 and tb1 are similar and can both represent the timing of instruction cmd1; similarly, time points to2 and tb2 can both represent the timing of instruction cmd2. The main edges hr1 and hr2 formed by the control circuit 120 in the signal rdgt_ref can be considered as reference edges; the time points tr1 and tr2 of the main edges hr1 and hr2 can reflect the actual timing of the corresponding gating edges of memory 20 when responding to instructions cmd1 and cmd2 (e.g., the time point when the earliest gating edge actually occurs). On the other hand, the main edges hn1 and hn2 formed by the delay circuit 110 in the signal rdgt_fbck can be regarded as internal edges; the delay circuit 110 can estimate the expected timing of the gating edge corresponding to the memory 20 when responding to the instructions cmd1 and cmd2 (e.g., the time point at which the earliest gating edge is expected to occur), and can reflect the expected timing in the time points tn1 and tn2 of the main edges hn1 and hn2. Therefore, for the expected timing of the gating edge estimated by the delay circuit 110 for the instruction cmd1 (Fig. 4a), the time difference dt1 (Fig. 4a) between time points tn1 and tr1 can reflect the error between the expected timing of the gating edge and the actual timing of the gating edge; for the expected timing of the gating edge estimated by the delay circuit 110 for the instruction cmd2 (Fig. 4b), the time difference dt2 (Fig. 4b) between time points tn2 and tr2 can reflect the error between the expected timing of the gating edge and the actual timing of the gating edge.

[0059] In Figure 4a, the delay circuit 110 can control the length of the time period dn1 to control how much the timing point tn1 of the main edge hn1 will be delayed compared to the timing point tb1 of the instruction cmd1; similarly, in Figure 4b, the delay circuit 110 can also control the length of the time period dn2 to control how much the timing point tn2 of the main edge hn2 will be delayed compared to the timing point tb2 of the instruction cmd2. In Figure 4b, the delay circuit 110 can control the length of the time period dn2 according to the signal s_c. As previously described, in one embodiment, the detection circuit 130 has previously counted the number Nk1 in FIG. 4a and reflected the number Nk1 in the signal s_d, and the filtering circuit 140 has made the signal s_c reflect the signal s_d; therefore, in FIG. 4b, when the delay circuit 110 controls the length of the time period dn2 according to the signal s_c, the delay circuit 110 can control the length of the time period dn2 according to the number Nk1, for example, making the time period dn2 equal to the time period dn1 plus Nk1 periods T0. In this way, the time difference dt2 (FIG. 4b) between time point tn2 and time point tr2 can be significantly reduced compared to the time difference dt1 (FIG. 4a). In Figure 4a, the time difference dt1 can be greater than Nk1 cycles T0. However, after the delay circuit 110 adjusts the time interval dn2 according to the number Nk1, the time difference dt2 in Figure 4b can be less than one cycle T0. That is, the delay circuit 110 can make multiples of the time difference dt2 (e.g., the number Nk1) smaller than the time difference dt1. In other words, after only going through instructions cmd1 and cmd2, the expected timing of the gating edge estimated by the delay circuit 110 for each instruction can quickly approach the actual timing of the gating edge of the memory 20 when responding to the instruction.

[0060] As shown in Figure 4c, after instruction cmd2 ends, the physical layer circuit 10 can continue to issue one or more subsequent instructions to memory 20 in training mode, such as instruction cmd# between two time points ta# and taa#; where time point ta# can be after time point taa2. In response to instruction cmd#, memory 20 can sequentially form multiple gating edges in signals DQS_t and DQS_c between two time points tc# and tcc#, and can provide a data string u# in signal DQ between two time points td# and tdd#. Wherein, time point tcc# can be after time point tc#, and separated from time point tc# by a time interval Tdqs0; time point tc# can be after another time point tbb#, and separated from time point tbb# by a time interval d#; time point tbb# can be after yet another time point tb#, and separated from time point tb# by a time interval RL0; time point tb# can be the last main edge of clock CK_t before time point taa#. Time point td# can be after time point tc#, and separated from time point tc# by a time interval dd#; time point tdd# can be after time point td#, and separated from time point td# by a time interval Tdq0.

[0061] The earliest gating edge of the response signal DQS at time point tc#, the control circuit 120 can form a main edge hr# (the edge from level vr0 to vr1) in the signal rdgt_ref at time point tr# to reflect the actual timing of the gating edge corresponding to the memory 20 when responding to the instruction cmd#. The delay circuit 110 can estimate the expected timing of the gating edge corresponding to the memory 20 when responding to the instruction cmd# based on the signal s_c (e.g., the time point at which the earliest gating edge is expected to occur), and can form a main edge hn# (the edge from level vn0 to level vn1) in the signal rdgt_fbck at time point tn# based on the expected timing. Among them, time point tn# can be after another time point to#, and is separated from time point to# by a time interval dn#; time point to# can be earlier than time point tbb#, and is separated from time point tbb# by a time interval g0. The detection circuit 130 can detect the time difference dt# between the main edge hn# and the main edge hr#, and reflect the corresponding detection result in the signal s_d. The filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c. The signal s_c fed back to the delay circuit 110 by the detection circuit 130 and the filtering circuit 140 can be fine-tuned when the delay circuit 110 estimates the expected timing of the gating edges corresponding to other subsequent instructions (not shown) in training mode, so that the expected timing can be closer to the actual timing.

[0062] Similar to Figures 4a and 4b, in Figure 4c, time point to# can be considered a reference time point, and the main edges hr# and hn# can be considered a reference edge and an internal edge, respectively. When the delay circuit 110 estimates the expected timing of the corresponding gating edge based on the signal s_c as the instruction cmd# and forms the main edge hn# based on the expected timing, the delay circuit 110 can determine the length of the time period dn# based on the signal s_c, which also determines the position of time point tn# on the time axis. At time point tnn# after time point tn#, the delay circuit 120 can change the signal rdgt_fbck from level vn1 back to level vn0; at time point trr# after time point tr#, the control circuit 120 can change the signal rdgt_ref from level vr1 back to level vr0. The interval between time points tr# and trr# can be equal to the interval between time points tr1 and trr1, and the interval between time points tn# and tnn# can be equal to the interval between time points tn1 and tnn1. In training mode, memory 20 can continuously drive lines 12d and 12c after responding to the instruction cmd#, maintaining signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining signal DQ at a fixed level. However, when memory 20 ends the training mode (e.g., Figures 4a to 4c) and enters the normal mode (e.g., Figures 2a to 2d and 3a to 3c), memory 20 will not continuously drive lines 12d and 12c. Instead, it will drive lines 12d and 12c only when responding to instructions to give signals DQS and DQ a clear waveform. In the examples of Figures 2a to 2d and Figures 3a to 3c, when memory 20 does not drive lines 12d and 12c, signals DQS and DQ will not have a clear waveform (as shown by the shading).

[0063] In one embodiment, signal s_d may include two signals s_dr and s_df (Figure 1). Signal s_dr reflects how many periods T0 are covered in the time difference dt# between the main edges hn# and hr#, while signal s_df reflects the leading / lagging relationship between the main edges hn# and hr#. For example, in one embodiment, signal s_df can use a first logic value and a second logic value to reflect whether the main edge hn# in signal rdgt_fbck is earlier or later than the main edge hr# in signal rdgt_ref.

[0064] In one embodiment, the signal s_c provided by the filter circuit 140 may include two signals s_cr and s_cf (FIG. 1). The filter circuit 140 may also include two signal paths (not shown) to perform different signal processing on the signals s_dr and s_df in the signal s_d, thereby providing the signals s_cr and s_cf. For example, when processing the signal s_df, the filter circuit 140 can accumulate the number of times the first logic value and the second logic value appear in the signal s_df. If the number of times the first logic value appears is much greater than the number of times the second logic value appears (for example, the difference between the former and the latter is greater than a preset first threshold number), the filter circuit 140 can reflect an extension message (not shown) in the signal s_cf. After the delay circuit 110 receives this extension message from the signal s_c, when the delay circuit 110 needs to form the next main edge hn#' (not shown) in the signal rdgt_fbck for the next instruction cmd#' (not shown), the delay circuit 110 can extend the interval between the instruction cmd#' and the main edge hn#'. On the other hand, if the number of times the second logic value appears is much greater than the number of times the first logic value appears (for example, the difference between the former and the latter is greater than a preset second threshold number), the filter circuit 140 can reflect a shortening message (not shown) in the signal s_cf; after the delay circuit 110 receives this shortening message from the signal s_c, when the delay circuit 110 needs to form the main edge hn#' again in the signal rdgt_fbck in response to the instruction cmd#', the delay circuit 110 can shorten the interval between the instruction cmd#' and the main edge hn#'.

[0065] In training mode, when memory 20 responds to the instructions cmd1, cmd2 or cmd#, memory 20 will not add prefixes or suffixes to the signals DQS_t and DQS_c; that is, in training mode, the gating edges formed by memory 20 in the signals DQS_t and DQS_c are all valid gating edges, which can reflect the timing of each bit in the data strings u1, u2 and u# respectively.

[0066] After experiencing multiple instructions in training mode, delay circuit 110 can lock the main edge of signal rdgt_fbck to the corresponding main edge of signal rdgt_ref, for example, making the main edge of signal rdgt_fbck substantially aligned with the corresponding main edge of signal rdgt_ref. After locking is achieved, it means that the expected timing of the gating edge estimated by the read gate control circuit 100 for each instruction is very close to the actual timing of the gating edge of each instruction. In one embodiment, after experiencing multiple instructions, if the number of occurrences of the first logic value and the second logic value in signal s_df is not much different, and the signal value of signal s_dr remains unchanged, the read gate control circuit 100 can determine that locking has been achieved.

[0067] After the training mode is locked, the physical layer circuit 10 can enable the memory 20 to enter the normal mode for access by the processing units PU[1] to PU[M]. Continuing with Figures 1 and 2a to 2d, Figure 5 illustrates an example of a waveform timing embodiment for reading the relevant signals when the gate control circuit 100 is operating in the normal mode. As previously mentioned in Figures 2a to 2d, in response to the instruction cmd[i], the memory 20 can sequentially form multiple gating edges in signals DQS_t and DQS_c between time points tz[i] and tzz[i], and can provide the data string u[i] in signal DQ between time points td[i] and tdd[i]. Among them, the gating edge between time points tc[i] and tcc[i] is the effective gating edge.

[0068] As shown in Figure 5, corresponding to the instruction cmd[i], the delay circuit 110 in the gate control circuit 100 can change the signal rdgt_fbck from level vn0 to level vn1 at one time point tn[i] to form a main edge hn[i], and can change the signal rdgt_fbck from level vn1 back to level vn0 at another time point tnn[i]. Furthermore, corresponding to the instruction cmd[i], the delay circuit 110 can also change the signal rd_gt from one level vg0 to another level vg1 at one time point tp[i] to form an edge hp[i], and change the signal rd_gt from level vg1 back to level vg0 at another time point tpp[i] to form another edge hpp[i]. In this context, levels vg0 and vg1 can represent logic 0 and logic 1, respectively; time point tn[i] can be after time point to[i], and separated from time point to[i] by a time interval dn[i]; time point to[i] can be before time point tbb[i], and separated from time point tbb[i] by a time interval g0. Time point tnn[i] can be after time point tn[i], and the interval between time points tn[i] and tnn[i] can be equal to the interval between time points tn1 and tnn1 (Figure 4a). Time point tp[i] can be before time point tn[i], and separated from time point tn[i] by a time interval p0; time point tpp[i] can be after time point tp[i], and separated from time point tp[i] by a time interval TG0. In one embodiment, time interval p0 can be equal to a preset value multiplied by period T0, for example, a quarter of a period T0. In one embodiment, time interval TG0 can be equal to time interval Tdq0.

[0069] Similar to time points to1, to2, and to# in Figures 4a to 4c, time point to[i] in Figure 5 can be considered a reference time point; the interval between time points to[i] and tb[i] can be equal to the interval between time points to1 and tb1, so time points to[i] and tb[i] can both represent the timing of instruction cmd[i]. Similar to the main edges hn1, hn2, and hn# in Figures 4a to 4c, the main edge hn[i] in Figure 5 can be considered an internal edge. Furthermore, the edges hp[i] and hpp[i] formed by the delay circuit 110 in the signal rd_gt can be considered as a gated leading edge and a gated trailing edge, respectively.

[0070] Similar to the training modes in Figures 4a to 4c, in the normal mode of Figure 5, when memory 20 responds to instruction cmd[i] and forms multiple gating edges in signals DQS_t and DQS_c, delay circuit 110 can estimate the expected timing of the effective gating edges among these gating edges based on signal s_c, and can reflect the expected timing in the timing point tn[i] of the main edge hn[i], the timing point tp[i] of the edge hp[i], and the timing point tpp[i] of the edge hpp[i]. For example, timing point tn[i] can reflect the timing point when the earliest effective gating edge occurs in the expected range, timing point tp[i] is earlier than timing point tn[i], and can reflect a timing point between the earliest effective gating edge and the previous ineffective gating edge in the expected range; timing point tpp[i] is later than timing point tn[i], and can reflect a timing point between the latest effective gating edge and the next ineffective gating edge in the expected range.

[0071] Based on the edges hp[i] and hpp[i] of the signal rd_gt, the effect control circuit 120 can filter out one or more gated gating edges from the plurality of gating edges of the signals DQS_t and DQS_c, and can reflect the filtering results in the signals vDQS_t and vDQS_c. For example, in one embodiment, the effect control circuit 120 can select the gating edge in the signals DQS_t and DQS_c that is located between time points tp[i] and tpp[i] as the gated gating edge, and form a corresponding gating edge in the signals vDQS_t and vDQS_c in response to the selected gated gating edge (for example, changing the signals vDQS_t and vDQS_c from one quasi-vp0 to another quasi-vp1, where quasi-vp0 and vp1 can represent logic 0 and logic 1, respectively). The gate selection edges filtered by the effect control circuit 120 from signals DQS_t and DQS_c can reflect the valid selection edges in signals DQS_t and DQS_c; that is, the filtering performed by the effect control circuit 120 based on signal rd_gt can remove invalid selection edges in the prefix and suffix, and reflect the valid selection edges of signals DQS_t and DQS_c in signals vDQS_t and vDQS_c respectively. In this way, when the data circuit 50 in the physical layer circuit 10 samples the signal DQ according to the timing (selection edges) of signals vDQS_t and vDQS_c, it can correctly retrieve each bit in the data string u[i] and will not incorrectly sample the unclear parts of the waveform in signal DQ (shaded areas).

[0072] Furthermore, when the control circuit 120 selects the gated gating edge from signals DQS_t and DQS_c based on the signal rd_gt, the control circuit 120 can also respond to the earliest gated gating edge (that is, the earliest gating edge after edge hp[i], located at time point tc[i]) and change the signal rdgt_ref from level vr0 to level vr1 at a time point tr[i] to form a main edge hr[i] in the signal rdgt_ref. Similar to the main edges hr1, hr2 and hr# in Figures 4a to 4c, the main edge hr[i] in Figure 5 can be regarded as a reference edge, and the time point tr[i] when the main edge hr[i] occurs can reflect the actual time point when the earliest effective gating edge occurs.

[0073] Similar to the previous descriptions in Figures 4a to 4c, in the normal mode of Figure 5, the detection circuit 130 can detect a time difference dt[i] between time points tn[i] and tr[i], and reflect the corresponding detection result in the signal s_d; the filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c. Similar to the previous descriptions in Figures 4a to 4c, in the normal mode of Figure 5, the signal s_d can include signals s_dr and s_df (Figure 1), and the signal s_c can include signals s_cr and s_cf (Figure 1). In one embodiment, after the detection circuit 130 detects the time difference dt[i] between time points tr[i] and tn[i], the detection circuit 130 can update the signal value of signal s_dr from a previous signal value s_dr[i-1] (not shown) to a current signal value s_dr[i] (not shown), and update the signal value of signal s_df from a previous signal value s_df[i-1] (not shown) to a current signal value s_df[i] (not shown), so as to reflect the detection result of time difference dt[i] in the signal values ​​s_dr[i] and s_df[i]. In one embodiment, when the detection circuit 130 detects the time difference dt[i], the detection circuit 130 can count how many periods T0 the time difference dt[i] covers, and compare whether the main edge hn[i] is earlier or later than the main edge hr[i]. When the detection circuit 130 reflects the detection result in the signal s_d, the detection circuit 130 can reflect how many periods T0 the time difference dt[i] covers in the signal value s_dr[i], and can reflect whether the main edge hn[i] is earlier or later than the main edge hr[i] in the signal value s_df[i]. In one embodiment, when the filter circuit 140 processes the signal s_d after the signal value is updated and reflects the result of the signal processing in the signal s_c, the filter circuit 140 can update the signal value of the signal s_cr from a previous signal value s_cr[i-1] to a current signal value s_cr[i], and update the signal value of the signal s_cf from a previous signal value s_cr[i-1] to a current signal value s_cr[i], so that the result of the signal processing on the updated signal s_d is reflected in the signal values ​​s_cr[i] and s_cf[i].

[0074] In one embodiment, the operation of the detection circuit 130 and the filtering circuit 140 in training mode can be similar to their operation in normal mode. For example, in normal mode, the detection circuit 130 can reflect whether the main edge hn[i] is earlier or later than the main edge hr[i] in the signal value s_df[i] using a first logic value and a second logic value. If the signal value s_df[i] is the first logic value, the signal processing of the signal s_df by the filtering circuit 140 can make the number of occurrences of the first logic value reflected by the signal value s_cf[i] increase by one compared to the number of occurrences of the first logic value reflected by the signal value s_cf[i-1]; if the signal value s_df[i] is the second logic value, the signal processing of the signal s_df by the filtering circuit 140 can make the number of occurrences of the second logic value reflected by the signal value s_cf[i] increase by one compared to the number of occurrences of the second logic value reflected by the signal value s_cf[i-1].

[0075] The delay circuit 110 can control the length of the time interval dn[i] according to the signal s_c, thereby controlling the position of the time point tn[i] (and the time points tp[i] and tpp[i]) on the time axis. As shown in Figure 5, in one embodiment, the time interval dn[i] can include two time intervals Tn1 and Tn[i]. When the delay circuit 110 forms the main edge hn[i] in the signal rdgt_fbck, the delay circuit 110 can start from the time point to[i] and wait for the time interval Tn1 according to the previous signal value s_cr[i-1] of the signal s_cr, and wait for the time interval Tn[i] according to the previous signal value s_cf[i-1] of the signal s_cf, and form the main edge hn[i] at the time point tn[i] after the waiting ends. In one embodiment, the time interval Tn1 can be equal to one or more periods T0, while the time interval Tn[i] can be less than one period T0. In one embodiment, the time period Tn1 can be equal to the time difference dt1 in Figure 4a minus the time difference dt2 in Figure 4b. In one embodiment, the signal value s_cr[i-1] of the signal s_cr can reflect the number Nk1 (Figure 4a), and the delay circuit 110 can further include a counter 1101 (Figure 1); when the delay circuit 110 waits for the time period Tn1, the counter 1101 can count Nk1 cycles T0 passing. As previously described in Figure 4a, when the detection circuit 130 detects the time difference dt1, the detection circuit 130 can count how many cycles T0 are in the time difference dt1 and reflect the counted number Nk1 in the signal s_cr. In other words, the signal s_cr in the normal mode can be the same as the signal s_cr obtained in the training mode.

[0076] In one embodiment, the delay circuit 110 may further include a controlled delay line 1102, controlled by the signal s_cf; when the delay circuit 110 waits for a period of time Tn[i], it may be through the controlled delay line 1102 waiting for a period of time Tn[i], and the length of the period of time Tn[i] may be controlled by the signal value s_cf[i-1] of the signal s_cf. In the read gate control circuit 100, the signals s_cr and s_cf can be regarded as a coarse adjustment signal and a fine adjustment signal, respectively, the periods Tn1 and Tn[i] can be regarded as a coarse adjustment period and a fine adjustment period, respectively, and the number Nk1 can be regarded as a coarse adjustment number.

[0077] As previously described, when memory 20 responds to instructions cmd1, cmd2, or cmd# in the training mode of Figures 4a, 4b, or 4c, memory 20 can form a plurality of gating edges in the signal DQS between time points tc1 and tcc1, between time points tc2 and tcc2, or between time points tc# and tcc#, and these gating edges are all valid gating edges. On the other hand, when memory 20 responds to instruction cmd[i] in normal mode as shown in Figure 5, memory 20 can form a plurality of gating edges in signal DQS between time points tz[i] and tzz[i]. However, among these plurality of gating edges, only the gating edge between time points tc[i] and tcc[i] is a valid gating edge, and the other gating edges are invalid gating edges. That is, the gating edge between time points tz[i] and tc[i] and the gating edge between time points tcc[i] and tzz[i] are both invalid gating edges. Although memory 20 forms invalid gating edges in the prefix and / or suffix of the signal DQS in normal mode, the interval between time points tb# and tc# (and the interval between time points tb1 and tc1 and the interval between time points tb2 and tc2) in training mode can reflect the interval between time points tb[i] and tc[i] in normal mode; where time points tb1, tb2, tb#, and tb[i] can represent the timing of instructions cmd1, cmd2, cmd#, and cmd[i] respectively, and time points tc1, tc2, tc#, and tc[i] can represent the timing of valid gating edges respectively. That is to say, the interval between each instruction and its corresponding gating edge in training mode (e.g., the interval between time points tb1 and tc1, tb2 and tc2, or tb# and tc#) can reflect the interval between each instruction and its corresponding valid gating edge in normal mode (e.g., the interval between time points tb[i] and tc[i]).

[0078] When the delay circuit 110 can lock the expected timing of the corresponding gating edge to the actual timing for each instruction in the training mode (as shown in Figures 4a to 4c), it means that the delay circuit 110 can correctly estimate the interval between each instruction and the corresponding gating edge in the training mode. When the delay circuit 110 needs to estimate the expected timing of the effective gating edge corresponding to each instruction cmd[i] in the normal mode (as shown in Figure 5), the delay circuit 110 can estimate the expected timing of the effective gating edge for each instruction cmd[i] based on the locking result previously achieved in the training mode (e.g., the signal s_cr after locking), and reflect the expected timing in the time period dn[i], the main edge hn[i] and the signal rd_gt. Based on the timing of the signal rd_gt, the control circuit 120 can filter out the gated gating edge from the signal DQS to reflect the effective gating edge between time points tc[i] and tcc[i], and reflect the filtering result in the signal vDQS and the main edge hr[i]. The detection circuit 130 can detect the time difference between the main edge hn[i] and hr[i]. Through the feedback from the detection circuit 130, the filter circuit 140 to the delay circuit 110, the delay circuit 110 can be fine-tuned when estimating the expected timing of the effective gating edge for subsequent instructions, so that the expected timing of the effective gating edge can be continuously locked to the actual timing.

[0079] When memory 20 responds to instruction cmd[i] in normal mode, the actual timing of the effective gating edge will dynamically drift because the time interval d[i] between time point tbb[i] and time point tc[i] may change dynamically due to factors such as bias voltage and / or temperature drift. However, when memory 20 responds to multiple instructions sequentially in normal mode, the delay circuit 110 can continuously fine-tune its expected timing for the effective gating edge estimation through feedback from the detection circuit 130 and the filter circuit 140. Even if the actual timing of the effective gating edge drifts, the expected timing estimated by the delay circuit 110 for the effective gating edge can still be locked to the actual timing of the effective gating edge.

[0080] Continuing from Figures 1, 3b, and 3c, Figures 6a and 6b illustrate examples of waveform timing implementations for reading relevant signals when the gate control circuit 100 is operating in normal mode. As previously described in Figure 3b, in Figure 6a, when memory 20 responds to instructions cmd[i] and cmd[i+1], since the interval Tcc[i] between instructions cmd[i] and cmd[i+1] is less than the interval T_mrg[i], memory 20 can combine the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] in signals DQS_t and DQS_c, so that signals DQS_t and DQS_c can form multiple gating edges with a definite waveform between time points tz[i] and tzz[i+1]. On the other hand, since the interval Tcc[i] is greater than the interval T_min, the waveform of signal DQ between time points tdd[i] and td[i+1] will be ambiguous.

[0081] As previously described in Figure 5, in Figure 6a, corresponding to the instruction cmd[i], the delay circuit 110 can form the main edge hn[i] in the signal rdgt_fbck at time point tn[i], and can form edges hp[i] and hpp[i] in the signal rd_gt at time points tp[i] and tpp[i]. The delay circuit 110 can determine when time points tp[i], tn[i], and tpp[i] should be located based on the signal s_c. Based on the signal rd_gt, the effect control circuit 120 can filter out valid gating edges from the plurality of gating edges of signals DQS_t and DQS_c, and remove invalid gating edges. Specifically, the control circuit 120 can respond to the gating edges between time points tp[i] and tpp[i] in signals DQS_t and DQS_c, and form corresponding gating edges in signals vDQS_t and vDQS_c. The gating edges in signals vDQS_t and vDQS_c represent the valid gating edges in signals DQS_t and DQS_c. Based on the gating edges in signals vDQS_t and vDQS_c, the data circuit 50 can sample the signal DQ to retrieve each bit of the data string u[i]. Furthermore, based on the earliest gating edge after time point tp[i] in the (response) signals DQS_t and DQS_c (that is, the earliest valid gating edge formed by memory 20 in signals DQS_t and DQS_c when responding to instruction cmd[i]), the control circuit 120 can also form the main edge hr[i] in the signal rdgt_ref at time point tr[i]. The detection circuit 130 can detect the time difference dt[i] between the main edges hn[i] and hr[i] and reflect the corresponding detection result in the signal s_d; the filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d and reflect the result of the signal processing in the signal s_c.

[0082] Similarly, corresponding to the instruction cmd[i+1], the delay circuit 110 can change the signal rdgt_fbck from level vn0 to level vn1 at a time point tn[i+1] to form a main edge hn[i+1] in the signal rdgt_fbck; the delay circuit 110 can also change the signal rdgt_fbck from level vn1 back to level vn0 at another time point tnn[i+1]. Corresponding to the instruction cmd[i+1], the delay circuit 110 can also change the signal rd_gt from level vg0 to level vg1 at another time point tp[i+1], and can change the signal rd_gt from level vg1 back to level vg0 at yet another time point tpp[i+1] to form two edges hp[i+1] and hpp[i+1] in the signal rd_gt respectively. Among them, time point tn[i+1] can be after another time point to[i+1], and separated from time point to[i+1] by a time interval dn[i+1]; time point to[i+1] can be before time point tbb[i+1], and separated from time point tbb[i+1] by a time interval g0; time point tp[i+1] can be before time point tn[i+1], and separated from time point tn[i+1] by a time interval p0; time point tpp[i+1] can be after time point tp[i+1], and separated from time point tp[i+1] by a time interval TG0. For the instruction cmd[i+1], time point to[i+1] can be regarded as a reference time point, which can reflect the timing of the instruction cmd[i+1]; the time interval dn[i+1] is controlled by the signal s_c. In one embodiment, the time period dn[i+1] may include two time periods Tn1 and Tn[i+1], which are respectively controlled by the signal values ​​s_cr[i] and s_cf[i] of the signal s_c.

[0083] Based on the signal rd_gt, when memory 20 responds to the instruction cmd[i+1] and forms a plurality of gating edges in signals DQS_t and DQS_c, the control circuit 120 can filter out valid gating edges and remove invalid gating edges from these gating edges in signals DQS_t and DQS_c. For example, the control circuit 120 can respond to the gating edge in signals DQS_t and DQS_c located between time points tp[i+1] and tpp[i+1] and form corresponding gating edges in signals vDQS_t and vDQS_c. Based on the gating edges in signals vDQS_t and vDQS_c, the data circuit 50 can sample the signal DQ to retrieve each bit of the data string u[i+1]. Furthermore, based on the earliest gating edge after time point tp[i+1] in the (response) signals DQS_t and DQS_c, the effect control circuit 120 can also form a main edge hr[i+1] (the edge from level vr0 to vr1) in the signal rdgt_ref at a time point tr[i+1]. The detection circuit 130 can detect the time difference dt[i+1] between the main edges hn[i+1] and hr[i+1], and reflect the corresponding detection result in the signal s_d; the filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c.

[0084] As shown in Figure 6a, the interval between time points to[i] and tb[i] can be equal to the interval between time points to[i+1] and tb[i+1]. The interval Tcc[i] between time points tb[i] and tb[i+1] is the interval between instructions cmd[i] and cmd[i+1]. Time points tc[i] and tc[i+1] can represent the actual timing of the effective selection edge of memory 20 when responding to instructions cmd[i] and cmd[i+1], respectively. The interval between time points tc[i] and tc[i+1] can be equal to the time period (Tcc[i] + d[i+1] - d[i]). On the other hand, time points tn[i] and tn[i+1], time points tp[i] and tp[i+1], and time points tpp[i] and tpp[i+1] can represent the expected timing of the effective gating edges corresponding to instructions cmd[i] and cmd[i+1]. The interval between time points tn[i] and tn[i+1], the interval between time points tp[i] and tp[i+1], and the interval between time points tpp[i] and tpp[i+1] can be equal to the time period (Tcc[i] + dn[i+1] - dn[i]). As described above, as the instruction cmd[i+1] gets closer to the instruction cmd[i] (the shorter the time interval Tcc[i]), the timing tc[i+1] related to memory 20 will get closer to the timing tc[i], and the timing tp[i+1], tn[i+1], and tpp[i+1] related to delay circuit 110 will also get closer to the timing tp[i], tn[i], and tpp[i], respectively. In other words, the expected timing of the effective gating edge by delay circuit 110 can follow the actual timing of the effective gating edge. Even if the time interval Tcc[i] between adjacent instructions cmd[i] and cmd[i+1] changes, the control circuit 120 can still correctly filter the effective gating edge from the signals DQS_t and DQS_c based on the signal rd_gt of delay circuit 110.

[0085] In the example of Figure 6a, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is less than the time interval T_mrg[i]. Therefore, when memory 20 responds to instructions cmd[i] and cmd[i+1], it will combine the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] in signals DQS_t and DQS_c between time points tcc[i] and tc[i+1], so that signals DQS_t and DQS_c have a clear waveform between time points tcc[i] and tc[i+1], and there may be invalid gating edges. However, as shown in Figure 6a, even if memory 20 combines the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] in the example of Figure 6a, delay circuit 110 will still form edges hpp[i] and hp[i+1] in signal rd_gt; therefore, when effect control circuit 120 operates according to signal rd_gt, effect control circuit 120 can eliminate invalid gating edges that may occur between time points tcc[i] and tc[i+1]. As shown in Figure 6a, in one embodiment, effect control circuit 120 can maintain signals vDQS_t and vDQS_c at levels vp0 and vp1 respectively between time points tpp[i] and tp[i+1] of edges hpp[i] and hp[i+1], so that signals vDQS_t and vDQS_c will not have gating edges between time points tpp[i] and tp[i+1].

[0086] In the example of Figure 6b, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is equal to the time interval T_min. Therefore, when memory 20 responds to instructions cmd[i] and cmd[i+1], it will seamlessly concatenate the data strings u[i] and u[i+1] in signal DQ. It will also remove the suffix corresponding to instruction cmd[i] and the prefix corresponding to instruction cmd[i+1] in signals DQS_t and DQS_c, so that there are no invalid gating edges between time points tc[i] and tcc[i+1] in signals DQS_t and DQS_c. However, as shown in Figure 6b, if the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is equal to T_min, the time point tpp[i] of the corresponding instruction cmd[i] and the time point tp[i+1] of the corresponding instruction cmd[i+1] can coincide (or, the time point tpp[i] can be after the time point tp[i+1]). Therefore, the delay circuit 110 can cancel the edge hpp[i] of the time point tpp[i] and the edge hp[i+1] of the time point tp[i+1] in the signal rd_gt, so that the signal rd_gt can be maintained at level vg1 between the time points tp[i] and tpp[i+1]. When the control circuit 120 operates according to the signal rd_gt, it filters out the gating edges between time points tp[i] and tpp[i+1] in the signals DQS_t and DQS_c as gating edges, and reflects these filtered gating edges in the signals vDQS_t and vDQS_c. In this way, when the data circuit 50 samples the signal DQ according to the gating edges in the signals vDQS_t and vDQS_c, it can correctly retrieve the seamlessly concatenated data strings u[i] and u[i+1].

[0087] As shown in Figure 3a, if the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_mrg[i], memory 20 will not combine the suffix of instruction cmd[i] and the prefix of instruction cmd[i+1] when responding to instructions cmd[i] and cmd[i+1]. That is, memory 20 will form a complete prefix and suffix in signals DQS_t and DQS_c when responding to instruction cmd[i], and will also form a complete prefix and suffix in signals DQS_t and DQS_c when responding to instruction cmd[i+1]. The operation of delay circuit 110 and effect control circuit 120 in the example of Figure 3a can be understood from the relevant descriptions in Figures 5 and 6a. Corresponding to cmd[i] and cmd[i+1], the delay circuit 110 will form edges hp[i], hpp[i], hp[i+1] and hpp[i+1] in the signal rd_gt at time points tp[i], tpp[i], tp[i+1] and tpp[i+1] in sequence. Among them, time point tpp[i] can be before time point tp[i+1], and the interval between time points tpp[i] and tpp[i+1] will reflect (e.g., positively correlated with) the interval between time points tcc[i] and tc[i+1]. Therefore, when the effect control circuit 120 operates according to the signal rd_gt, the effect control circuit 120 can remove the suffix (time points tcc[i] to tzz[i], Figure 3a) corresponding to the instruction cmd[i] and the prefix (time points tz[i+1] to tc[i+1], Figure 3a) corresponding to the instruction cmd[i+1] based on the edges hpp[i] and hp[i+1] of the signal rd_gt. For example, the effect control circuit 120 can keep the signals vDQS_t and vDQS_c at levels vp0 and vp1 respectively between the time points tpp[i] and tp[i+1] of the edges hpp[i] and hp[i+1], so that the signals vDQS_t and vDQS_c will not have a gating edge between the time points tpp[i] and tp[i+1].

[0088] In summary, the physical layer circuitry (e.g., 10) of the present invention can access a memory (e.g., 20) and may include a read gate circuit (e.g., 100); this read gate circuit can improve read gate operation when reading the memory. In one embodiment, the read gate circuit of the present invention may include a delay circuit (e.g., 110), a control circuit (e.g., 120), and a detection circuit (e.g., 130). When the memory responds to a first instruction (e.g., cmd1) in a training mode (e.g., FIG. 4a) and forms a plurality of first gating edges (e.g., the gating edge between time points tc1 and tcc1) in a gating signal (e.g., DQS_t and DQS_c), the delay circuit can reflect the expected timing between these first gating edges in a first internal time period (e.g., dn1) and can reflect the first internal time period in an internal signal (e.g., rdgt_fbck), for example, forming a first internal edge (e.g., hn1) in the internal signal based on the first internal time period; The control circuit can reflect the actual timing of these first gating edges in a reference signal (e.g., rdgt_ref), for example, forming a first reference edge (e.g., hr1) in the reference signal based on (in response to) the earliest of these first gating edges; the detection circuit can detect the timing difference between the internal signal and the reference signal, and reflect the detected timing difference in a control signal (e.g., s_c), for example, detecting a first time difference (e.g., dt1) between the first internal edge and the first reference edge, and reflecting the first time difference in the control signal.

[0089] When the memory responds to a second instruction (e.g., cmd2) in the training mode (e.g., Figure 4b) and forms a plurality of second gating edges in the gating signal (e.g., gating edges between time points tc2 and tcc2), the delay circuit can determine a second internal time period (e.g., dn2) based on the control signal to reflect the expected timing of these second gating edges, and can reflect the second internal time period in the internal signal, for example, forming a second internal edge (e.g., hn2) in the internal signal based on the second internal time period; the control circuit can reflect the actual timing of these second gating edges in the reference signal, for example, forming a second reference edge (e.g., hr2) in the reference signal based on (responding to) the earliest of these second gating edges; the detection circuit can detect the timing difference between the internal signal and the reference signal, for example, detecting a second time difference (e.g., dt2) between the second internal edge and the second reference edge. In one embodiment, when detecting the first time difference, the detection circuit can count how many interface clock cycles (e.g., T0) are covered in the first time difference, and make a coarse adjustment number (e.g., Nk1) reflected in the control signal; when the delay circuit determines the second internal time period according to the control signal, the delay circuit can determine the length of the second internal time period according to the first internal time period and the coarse adjustment number, so that the second time difference can be much smaller than the first time difference, for example, making the second time difference a multiple of the first time difference smaller than the first time difference. In other words, the present invention can quickly (e.g., through two instructions cmd1 and cmd2) lock the expected timing of the gating edge to the actual timing of the gating edge in training mode.

[0090] When the memory responds to a third instruction (e.g., cmd[i]) in a normal mode (e.g., Figure 5) and forms multiple third gating edges (e.g., the gating edge between time points tz[i] and tzz[i]) in the gating signal (e.g., DQS_t and DQS_c) and provides a data string (e.g., u[i]) in a data signal (e.g., DQ), the delay circuit can determine a third internal time period (e.g., dn[i]) based on the control signal to reflect the expected timing of the effective gating edges among these third gating edges, and can reflect the third internal time period in the internal signal and a gate signal (e.g., rd_gt). For example, based on the third internal time period, a third internal edge (e.g., hn[i]) is formed in the internal signal, and a gate leading edge (e.g., hp[i]) and a gate trailing edge (e.g., hpp[i]) are formed in the gate signal based on the third internal time period. The control circuit can reflect the timing of the gate signal in a gate selection signal (e.g., vDQS_t and vDQS_c) and the reference signal, for example, reflecting the third selection edges located between the gate leading edge and the gate trailing edge in the gate selection signal, and forming a third reference edge (e.g., hr[i]) in the reference signal based on the earliest third selection edge located after the gate leading edge; a data circuit (e.g., 50) in the physical layer circuit can sample the data signal according to the gate selection signal to retrieve each bit of the data string, and the detection circuit can detect the timing difference between the internal signal and the reference signal, and reflect the detected timing difference in the control signal, for example, detecting a third time difference (e.g., dt[i]) between the third internal edge and the third reference edge, and reflecting the third time difference in the control signal. In one embodiment, the third internal time period may include a coarse adjustment period (e.g., Tn1) and a fine adjustment period (e.g., Tn[i]). The coarse adjustment period may be equal to the interface clock cycle multiplied by the number of coarse adjustments, and the fine adjustment period may be less than the interface clock cycle. In other words, based on the locking results in the training mode, the present invention can continuously lock the timing of the effective gated edges in the normal mode so as to correctly retrieve each bit in the data string from the data signal.

[0091] When the memory responds to a third instruction (e.g., cmd[i]) and a fourth instruction (e.g., cmd[i+1]) in the normal mode (e.g., Figures 6a and 6b) and forms multiple response gating edges (e.g., the gating edge between time points tz[i] and tzz[i+1]) in the gating signal (e.g., DQS_t and DQS_c) and provides two data strings (e.g., u[i] and u[i+1]) in the data signal, the delay circuit can determine a third internal time period (e.g., dn[i]) and a fourth internal time period (e.g., dn[i+1]) according to the control signal to reflect the expected timing of the effective gating edges in these response gating edges, and can reflect the third internal time period and the fourth internal time period in the internal signal, for example, forming a third internal edge (e.g., hn[i]) and a fourth internal edge (e.g., hn[i+1]) in the internal signal according to the third internal time period and the fourth internal time period. The delay circuit can further reflect the third internal time period and the fourth internal time period in the gate control signal. For example, if the interval between the third instruction and the fourth instruction is greater than a minimum interval time period (e.g., T_min, FIG. 6a), the delay circuit can form a third gate control leading edge (e.g., hp[i]) and a third gate control trailing edge (e.g., hpp[i], FIG. 6a) in the gate control signal according to the third internal time period, and can form a fourth gate control leading edge (e.g., hp[i+1], FIG. 6a) and a fourth gate control trailing edge (e.g., hpp[i+1]) in the gate control signal according to the fourth internal time period. If the interval between the third instruction and the fourth instruction is not greater than (e.g., equal to) the minimum interval time period, the delay circuit can form an integrated gate control leading edge (e.g., hp[i], FIG. 6b) and an integrated gate control trailing edge (e.g., hpp[i+1], FIG. 6b) in the gate control signal according to the third internal time period. The control circuit can reflect the timing of the gate signal in the gate selection signal and the reference signal. For example, it can reflect the gate selection signal in the gate selection signal in the response selection edges located between the leading edge and the trailing edge of the integrated gate. Based on the earliest response selection edge located after the leading edge of the integrated gate, a third reference edge (e.g., hr[i]) and a fourth reference edge (e.g., hr[i+1]) can be formed in the reference signal. The data circuit (e.g., 50) can be based on the gate selection. The signal samples the data signal to retrieve each bit of the two data strings. The detection circuit can detect the timing difference between the internal signal and the reference signal and make the detected timing difference reflected in the control signal. For example, it can detect a third time difference (e.g., dt[i]) between the third internal edge and the third reference edge, and detect a fourth time difference (e.g., dt[i+1]) between the fourth internal edge and the fourth reference edge and make the third time difference and the fourth time difference reflected in the control signal.In other words, regardless of whether the interval between two adjacent instructions is equal to the minimum interval time period, this invention can adaptably and correctly reflect the effective selection edge in the gate control signal.

[0092] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0093] 10: Physical layer circuits 12a to 12d: Lines 20: Memory 22: Memory controller 26: Busbar 30: Clock circuit 40: Instruction Circuit 50: Data Circuit 60: Input / output circuit 100: Read the gate control circuit 110: Delay circuit 120: Effect control circuit 130: Detection circuit 140: Filtering circuit 1000: Electronic devices 1101: Counter 1102: Controlled Delay Line cmd, DQ, DQS, DQS_t, DQS_c, rdgt_ref, rdgt_fbck, rd_gt, s_c, s_cr, s_cf, s_d, s_dr, s_df, vDQS, vDQS_t, vDQS_c: signal cmd1, cmd2, cmd#, cmd[i], cmd[i+1]: command CK_t, CK_c, ck0: Clock d1, d2, d#, d[i], d[i + 1], dd1, dd2, dd#, dd[i], dd[i + 1], dn1, dn2, dn#, dn[i], dn[i + 1], dt1, dt2, dt#, dt[i], dt[i + 1], g0, p0, RL0, Tcc[i], Tdq0, Tdqs0, TG0, T_min, T_mrg[i], Tn1, Tn[i], Tn[i + 1], Tpre[i], Tpre[i + 1], Tpst[i], Tpst[i + 1]: Time period hn1, hn2, hn#, hn[i], hn[i + 1], hr1, hr2, hr#, hr[i], hr[i + 1]: Main edge hp[i], hp[i + 1], hpp[i], hpp[i + 1]: Edge n1 to n11: Node Nk1: Number PU[1], PU[m], PU[M]: Processing unit s_cr[i - 1], s_cf[i - 1], s_cr[i], s_cf[i]: Signal value ta1, ta2, ta#, ta[i], ta[i + 1], taa1, taa2, taa#, taa[i], taa[i + 1], tb1, tb2, tb#, tb[i], tb[i + 1], tbb1, tbb2, tbb#, tbb[i], tbb[i + 1], tc1, tc2, tc#, tc[i], tc[i + 1], tcc1, tcc2, tcc#, tcc[i], tcc[i + 1], td1, td2, td#, td[i], td[i + 1], tdd1, tdd2, tdd#, tdd[i], tdd[i + 1], tn1, tn2, tn#, tn[i], tn[i + 1], tnn1, tnn2, tnn#, tnn[i], tnn[i + 1], to1, to2, to#, to[i], tp[i], tp[i + 1], tpp[i], tpp[i + 1], tr1, tr2, tr#, tr[i], tr[i + 1], trr1, trr2, trr#, trr[i], trr[i + 1], tz[i], tz[i + 1], tzz[i], tzz[i + 1]: Time point T0: Period u1, u2, u#, u[i], u[i + 1]: Data string vc0, vc1, vg0, vg1, vk0, vk1, vn0, vn1, vp0, vp1, vq0, vq1, vr0, vr1: Level

Claims

1. A physical layer circuit with improved read gating, coupled to a memory, wherein: The physical layer circuitry includes a delay circuit, a control circuit, and a detection circuit. The control circuit is coupled to the delay circuit and a selection signal. The detection circuit is coupled to the delay circuit and the control circuit. In a first mode, the physical layer circuitry transmits a first instruction to the memory, causing the memory to sequentially form a plurality of first gating edges in the selection signal in response to the first instruction. In response to the earliest of the plurality of first gating edges, the control circuit forms a first reference edge in a reference signal. Corresponding to the first instruction, the delay circuit forms a first internal edge in an internal signal. The detection circuit detects a first time difference between the first internal edge and the first reference edge, and reflects the corresponding detection result in a control signal. In the first mode, the physical layer circuitry further transmits a second instruction to the memory, causing the memory to sequentially form a plurality of second gating edges in the selection signal in response to the second instruction. In response to the earliest of the plurality of second gating edges, the control circuit further forms a second reference edge in the reference signal; and in response to the second instruction, the delay circuit further forms a second internal edge in the internal signal according to the control signal, so that a second time difference between the second internal edge and the second reference edge is less than the first time difference.

2. The physical layer circuitry as described in request item 1, wherein, When the delay circuit makes the second time difference less than the first time difference, the delay circuit makes the second time difference a multiple of the first time difference less than the first time difference.

3. The physical layer circuitry as described in request item 1, wherein: The first time difference is greater than a multiple of the interface clock cycle; and when the delay circuit makes the second time difference less than the first time difference, the delay circuit makes the second time difference less than the interface clock cycle.

4. The physical layer circuitry as described in request item 1, wherein: In a second mode, the physical layer circuit further transmits a third instruction to the memory, causing the memory to sequentially form a plurality of third gating edges in the gating signal in response to the third instruction, and to provide a third data string in a data signal in response to the third instruction; corresponding to the third instruction, the delay circuit further forms a gate leading edge and a gate trailing edge in a gate signal according to the control signal; according to the gate signal, the control circuit further filters out those located between the gate leading edge and the gate trailing edge from the plurality of third gating edges, and reflects the filtering result in a gate gating signal; the physical layer circuit further includes a data circuit; the data circuit is coupled to the control circuit; and the data circuit samples the data signal according to the gate gating signal to retrieve the third data string.

5. The physical layer circuitry as described in request item 4, wherein: In response to the third instruction, the delay circuit further forms a third internal edge in the internal signal based on the control signal; based on the filtering result, the control circuit further forms a third reference edge in the reference signal; the detection circuit further detects a third time difference between the third internal edge and the third reference edge, and reflects the corresponding detection result in the control signal; the gate leading edge is before the third internal edge; and the gate trailing edge is after the third internal edge.

6. The physical layer circuitry as described in request item 1, wherein: In a second mode, the physical layer circuit further transmits a third instruction to the memory, causing the memory to sequentially form a plurality of third gating edges in the gating signal in response to the third instruction; corresponding to the third instruction, the delay circuit further forms a third internal edge in the internal signal according to the control signal, and forms a gate leading edge in a gate signal according to the control signal; in response to the earliest one of the plurality of third gating edges occurring after the gate leading edge, the control circuit further forms a third reference edge in the reference signal; and the detection circuit further detects a third time difference between the third internal edge and the third reference edge, and reflects the corresponding detection result in the control signal.

7. The physical layer circuitry as described in request item 6, wherein: The physical layer circuit further includes a filter circuit coupled between the detection circuit and the delay circuit; and when the detection circuit detects the third time difference and reflects the corresponding detection result in the control signal, the detection circuit reflects the corresponding detection result in a detection signal, and the filter circuit filters the detection signal and reflects the result of the filtering process in the control signal.

8. The physical layer circuitry as described in request item 6, wherein: When the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit forms the third internal edge at a third internal edge time point; the third internal edge time point is after a third reference time point, and the interval between the third reference time point and the third internal edge time point includes a coarse adjustment period and a fine adjustment period; the coarse adjustment period is a multiple of an interface clock cycle; and the fine adjustment period is less than the interface clock cycle.

9. The physical layer circuitry as described in request item 8, wherein: The coarse adjustment period is essentially equal to the first time difference minus the second time difference.

10. The physical layer circuitry as described in request item 6, wherein: The control signal includes a coarse adjustment signal and a fine adjustment signal; when the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit waits for a coarse adjustment period and a fine adjustment period respectively according to the coarse adjustment signal and the fine adjustment signal, and forms the third internal edge at the third internal edge time point after the waiting ends.

11. The physical layer circuitry of request item 10, wherein: The delay circuit includes a counter; the coarse adjustment signal reflects a coarse adjustment number; and when the delay circuit waits for the coarse adjustment period, the counter counts the number of interface clock cycles that have elapsed.

12. The physical layer circuitry of request item 11, wherein: The coarse adjustment number is related to the first time difference.

13. The physical layer circuitry of request item 10, wherein: The delay circuit includes a controlled delay line; when the delay circuit waits for the fine-tuning period, the controlled delay line waits for the fine-tuning period to pass; and the length of the fine-tuning period is controlled by the fine-tuning signal.

14. The physical layer circuitry as described in request item 6, wherein: When the detection circuit detects the third time difference between the third inner edge and the third reference edge, the operation of the detection circuit includes: comparing whether the third inner edge is earlier or later than the third reference edge.

15. The physical layer circuitry of request item 1, wherein: When the detection circuit detects the first time difference between the first internal edge and the first reference edge and reflects the corresponding detection result in the control signal, the operation of the detection circuit includes: counting how many interface clock cycles the first time difference covers and reflecting the counting result in the control signal.

16. The physical layer circuitry as described in request item 1, wherein: In a second mode, the physical layer circuitry further transmits a third instruction and a fourth instruction sequentially to the memory, causing the memory to respond to the third instruction and the fourth instruction by sequentially forming a plurality of response gating edges in the gating signal, and causing the memory to also respond to the third instruction and the fourth instruction by providing a third data string and a fourth data string in a data signal respectively; if the interval between the third instruction and the fourth instruction is greater than a minimum interval period, the delay circuitry further forms a third gate leading edge, a third gate trailing edge, a fourth gate leading edge and a fourth gate trailing edge in a gate signal according to the control signal, and the control circuitry further selects one or more third gate gating edges and one or more fourth gate gating edges from the plurality of response gating edges according to the gate signal; each third gate gating edge is one of the plurality of response gating edges and is located between the third gate leading edge and the third gate trailing edge; Each of the fourth gate selection edges is one of the plurality of response selection edges and is located between the fourth gate leading edge and the fourth gate trailing edge; the physical layer circuit further includes a data circuit coupled to the control circuit; and the data circuit samples the data signal according to the one or more third gate selection edges to retrieve the third data string, and samples the data signal according to the one or more fourth gate selection edges to retrieve the fourth data string.

17. The physical layer circuitry of request item 1, wherein: In a second mode, the physical layer circuitry further transmits a third instruction and a fourth instruction sequentially to the memory, causing the memory to respond to the third instruction and the fourth instruction by sequentially forming a plurality of response gating edges in the gating signal, and causing the memory to also respond to the third instruction and the fourth instruction by providing a third data string and a fourth data string respectively in a data signal; if the interval between the third instruction and the fourth instruction is not greater than a minimum interval period, the delay circuitry further forms an integrated gate control leading edge and an integrated gate control trailing edge in a gate control signal according to the control signal, and the control circuitry further selects one or more gate control gating edges from the plurality of response gating edges according to the gate control signal; each gate control gating edge is one of the plurality of response gating edges and is located between the integrated gate control leading edge and the integrated gate control trailing edge; The physical layer circuitry further includes a data circuitry coupled to the control circuitry; and the data circuitry samples the data signal based on one or more gate selection edges to retrieve the third data string and the fourth data string.

18. An improved physical layer circuit for read gate control, coupled to a memory, wherein: The physical layer circuitry includes a delay circuit, a control circuit, and a detection circuit. The control circuit is coupled to the delay circuit and a selection signal. The detection circuit is coupled to the delay circuit and the control circuit. The physical layer circuitry transmits an instruction to the memory, causing the memory to sequentially form a plurality of gating edges in the selection signal in response to the instruction. Corresponding to the instruction, the delay circuit forms an internal edge in an internal signal. In a first mode, the control circuit forms a reference edge in a reference signal in response to the earliest of the plurality of gating edges. In a second mode, the delay circuit further forms a gate leading edge in a gate signal, and the control circuit forms the reference edge in the reference signal in response to the nearest gate leading edge among the plurality of gating edges, wherein the gate leading edge is earlier than the internal edge. The detection circuit detects a time difference between the internal edge and the reference edge and reflects the corresponding detection result in a detection signal.

19. The physical layer circuitry of request item 18, wherein: The physical layer circuitry further includes a filtering circuit coupled between the detection circuit and the delay circuit; the filtering circuit filters the detection signal to provide a control signal; and when the delay circuit forms the internal edge in the internal signal, the delay circuit determines when to form the internal edge in the internal signal based on the control signal.

20. The physical layer circuitry of request item 18, wherein: When the delay circuit forms the internal edge in the internal signal, the delay circuit waits for a coarse adjustment period and a fine adjustment period to pass, and forms the internal edge at an internal edge point after the waiting period ends; the coarse adjustment period is an integer multiple of an interface clock cycle; and the fine adjustment period is not greater than the interface clock cycle.

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