Memory device

Abstract

A memory device includes a first region and a second region. The memory device includes a bottom logic die, a memory die stack, a top die, and a redistribution layer. The bottom logic die includes a first global repair circuit in the second region and a first device layer in the first region. The memory die stack is on the bottom logic die and includes at least two mutually stacked memory dies. Each memory die includes a first local repair circuit in the second region and a second device layer in the first region. The top die is on the memory die stack and includes a second global repair circuit in the second region and a third device layer in the first region. The top die includes a top repair via disposed in the second region and connected to the second global repair circuit. The redistribution layer is on the top die and electrically connected to the top repair via.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a memory device. Prior Technology

[0002] Test interfaces for 3D stacks, such as high bandwidth memory (HBM), are typically designed into the bottom logic die. This physical architecture limits test feasibility, especially when the 3D stack (i.e., HBM) is located on an interposer during or after the 2.5D packaging process.

[0003] In 3D stacks (e.g., HBM), the bottom logic die can serve as an interface or organizer between the memory chip and the computing chip. Therefore, after the 3D stack (e.g., HBM) is mounted on an interposer, the pads and / or bumps contained in the bottom logic die cannot be directly contacted by micro / nano-scale probe tips. However, this problem may not only occur in memory stacks but also in the integration of various heterogeneous chiplets using advanced packaging technologies, which can be limiting when probing can only be performed before system assembly.

[0004] The discussion in the prior art is for background information only. The statements in the discussion of the prior art do not constitute an admission that the subject matter disclosed in the discussion of the prior art constitutes prior art to this disclosure, and no part of the discussion of the prior art shall be used as an admission that any part of this application (including the discussion of the prior art) constitutes prior art to this disclosure. Summary of the Invention

[0005] This disclosure provides a memory device in which a bottom logic die includes a first global repair circuit in a second region, and a top die includes a second global repair circuit in the second region. The bottom logic die and the top die are located on the bottom and top sides of a memory die stack, respectively, and a redistribution layer is disposed on the top die and electrically connected to the second global repair circuit. In this way, testing and repair procedures can be performed from the bottom logic die and / or from the top die, and can still be probed through the redistribution layer after system assembly, thereby improving the quality and yield of the memory device.

[0006] This disclosure provides a memory device including a first region and a second region. The memory device includes a bottom logic die, a memory die stack, a top die, and a redistribution layer. The bottom logic die includes a first global repair circuit disposed in the second region and a first device layer disposed in the first region. The memory die stack is on the bottom logic die and includes at least two mutually stacked memory dies, each memory die including a first local repair circuit disposed in the second region and a second device layer disposed in the first region. The top die is on the memory die stack and includes a second global repair circuit disposed in the second region and a third device layer disposed in the first region. The top die includes a plurality of top repair vias disposed in the second region and connected to the second global repair circuit. The redistribution layer is on the top die and electrically connected to the plurality of top repair vias.

[0007] In some embodiments, the memory device further includes a plurality of test pads on a redistribution layer, and the plurality of test pads are electrically connected to a plurality of top repair vias through the redistribution layer.

[0008] In some embodiments, the redistribution layer includes a plurality of connection pads respectively connected to a plurality of top repair vias and a plurality of wirings respectively connecting a plurality of test pads to the plurality of connection pads, wherein the size of the plurality of connection pads is smaller than the size of the plurality of test pads.

[0009] In some embodiments, the bottom logic die includes a plurality of bottom repair vias configured in the second region and connected to the first global repair circuit, wherein the diameter of one of the plurality of bottom repair vias is smaller than the diameter of one of the plurality of top repair vias.

[0010] In some embodiments, the diameter of one of the plurality of top-repair vias is larger than the diameter of the vias in each memory die that connect to the second device layer.

[0011] In some embodiments, the diameter of one of the plurality of top repair vias is larger than the diameter of the vias in each memory die connected to the first local repair circuit.

[0012] In some embodiments, one of the plurality of top repair vias has a diameter greater than 20 μm.

[0013] In some embodiments, the bottom logic die includes a plurality of bottom repair vias configured in the second region and connected to the first global repair circuit, and one of the plurality of bottom repair vias has a height less than the height of one of the plurality of top repair vias in the direction in which the memory dies are stacked.

[0014] In some embodiments, the height of one of the plurality of top-repair vias is greater than the height of the vias in each memory die connected to the second device layer in the direction.

[0015] In some embodiments, the height of one of the plurality of top repair vias is greater than the height of the vias in each memory die connected to the first local repair circuit in the direction.

[0016] In some embodiments, the height of one of the plurality of top repair vias is greater than 175 μm.

[0017] In some embodiments, the second global repair circuit is configured to receive a control signal from at least one of a plurality of test pads.

[0018] In some embodiments, the second global repair circuit includes a bidirectional buffer circuit.

[0019] In some embodiments, the second global repair circuit includes an electrostatic discharge (ESD) protection circuit connected to a bidirectional buffer circuit.

[0020] Based on the above, in the aforementioned memory device, the bottom logic die includes a first global repair circuit in the second region, and the top die includes a second global repair circuit in the second region. The bottom logic die and the top die are located on the bottom and top sides of the memory die stack, respectively, and a redistribution layer is disposed on the top die and electrically connected to the second global repair circuit. In this way, testing and repair procedures can be initiated from the bottom logic die and / or from the top die, and can still be probed through the redistribution layer after system assembly, thereby improving the quality and yield of the memory device.

[0021] To make the foregoing easier to understand, several embodiments with illustrations are described in detail below. Simple Explanation of the Diagram

[0022] The accompanying drawings are incorporated herein to provide a further understanding of the present disclosure and form part of this specification. These drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Figure 1 is a schematic cross-sectional view of a memory device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of a second global repair circuit according to an embodiment of the present disclosure. Implementation

[0023] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, it will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and apparatuses are shown schematically for the purpose of simplifying the illustrations.

[0024] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0025] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be intermediate elements present. If an element is referred to as being "directly on" or "directly connected" to another element, there are no intermediate elements present. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupled" may mean that there are other elements between two elements. "Electrical connection" as used herein may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0026] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0027] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0028] Figure 1 is a schematic cross-sectional view of a memory device according to an embodiment of the present disclosure. Figure 2 is a schematic diagram of a second global repair circuit according to an embodiment of the present disclosure.

[0029] Referring to FIG1, the memory device 10 includes a first region R1 and a second region R2, and wherein the memory device 10 includes a memory die stack 100, a bottom logic die 200, a top die 300, and a redistribution layer RDL1. In some embodiments, the first region R1 may be, for example, a cell region in which memory cells are disposed, and the second region R2 may be, for example, a repair region in which repair circuitry is disposed. In this embodiment, the memory cells and repair circuitry of the memory dies D1 to Dm are stacked and overlap each other in the vertical direction, so the first region R1 may include the same range in the vertical direction, and the second region R2 may include the same range in the vertical direction, but this disclosure is not limited thereto. In some other embodiments, when the memory dies are stacked with a horizontal offset in the vertical direction, the first region R1 and the second region R2 may include different ranges in the vertical direction. In some embodiments, the second region R2 may be, for example, adjacent to the first region R1.

[0030] Memory die stack 100 is disposed on bottom logic die 200 and includes at least two memory dies D1 to Dm stacked on top of each other, wherein each of memory dies D1 to Dm includes a device layer disposed in a first region R1 and a first local repair circuit disposed in a second region R2. For example, memory die Dj among memory dies D1 to Dm includes a device layer 102 disposed in the first region R1 and a first local repair circuit 104 disposed in the second region R2. Bottom logic die 200 includes a device layer 202 disposed in the first region R1 and a first global repair circuit 204 disposed in the second region R2.

[0031] In some embodiments, device layer 102 may include memory devices in a device region and wiring in a connection region. The device region may be a region of memory die Dj in which a memory array is disposed. The connection region may be a region of memory die Dj in which connection members such as through-silicon vias (TSVs), pads, or wiring layers / wiring patterns are disposed. For example, device layer 102 shown in FIG1 may be a wiring layer connecting a conductive member TSV1a to memory die Dj in a first region R1, but this disclosure is not limited thereto. In some embodiments, conductive member TSV1a may be a through-silicon via for transmitting signals. In some embodiments, conductive member TSV1a may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0032] In some embodiments, device layer 202 may include logic devices in a device region and wiring in a connection region. The device region may be a region of the bottom logic die 200 in which logic devices are disposed. The connection region may be a region of the bottom logic die 200 in which connection members such as through-silicon vias (TSVs), pads, or wiring layers / wiring patterns are disposed. For example, device layer 202 shown in FIG1 may be a wiring layer connecting a conductive member TSV2a to the memory die Dj in the first region R1, but this disclosure is not limited thereto. In some embodiments, conductive member TSV2a may be a through-silicon via (TSV) for transmitting signals. In some embodiments, conductive member TSV2a may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0033] In some embodiments, during the testing procedure, a first global repair circuit 204 in the bottom logic die 200 issues a series of commands to a first local repair circuit 104 to initiate a monitoring and testing sequence. A global tester in the first global repair circuit 204 transmits test patterns via signal paths (e.g., paths including wiring and conductive components TSV1a in the memory die Dj), and the first local repair circuit 104 monitors these patterns and also transmits test patterns on a bidirectional network for verification by the first global repair circuit 204. If any signal path fails to respond, it indicates a problem with the wiring constituting the signal path, and the global repair circuit then initiates a path repair operation. In some embodiments, the path repair operation may include, for example, the following steps. When a faulty (i.e., damaged) TSV is identified in memory die Dj, a pass command is transmitted from the first global repair circuit 204 to the first local repair circuit 104 in memory die Dj and to the first local repair circuit 104 in a memory die adjacent to memory die Dj (e.g., memory die Dj-1) to initiate a re-route repair action. That is, the re-route repair action is accomplished through the actions of memory die Dj and memory die Dj-1. For example, the first local repair circuit 104 in memory die Dj will take action to cut the wiring in the wiring layer connected to the damaged TSV and route the signal to a spare TSV (e.g., spare conductive component TSV_S1 in memory die Dj), while the first local repair circuit 104 in memory die Dj-1 will also take action to cut the wiring in the wiring layer connected to the damaged TSV in memory die Dj and route the signal to the spare TSV in memory die Dj.

[0034] In some embodiments, each of the memory chips D1 to Dm may include a conductive member TSV1b disposed in the second region R2 and electrically connected to the first local repair circuit 104, and the bottom logic chip 200 may include a conductive member TSV2b disposed in the second region R2 and electrically connected to the first global repair circuit 204. The conductive members TSV1b and TSV2b may each be silicon through-hole (TSV) and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0035] In some embodiments, each of the memory chips D1 to Dm may include spare conductive components TSV1_S1 and TSV1_S2 disposed in the first region R1 and spare conductive component TSV1_S3 disposed in the second region R2. In some embodiments, each spare conductive component TSV1_S1, TSV1_S2, and TSV1_S3 may be a silicon through-hole (TSV) and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W. In some embodiments, the bottom logic chip 200 may include spare conductive components TSV2_S1 and TSV2_S2 disposed in the first region R1 and spare conductive component TSV2_S3 disposed in the second region R2. In some embodiments, each of the standby conductive components TSV2_S1, TSV2_S2, and TSV2_S3 may be a silicon through-hole (TSV) and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0036] In some embodiments, each of the memory chips D1 to Dm may include a conductive member 110 electrically connecting the memory chips D1 to Dm to each other. For example, the conductive member 110 of memory chip Dj may be disposed on conductive members TSV1a, TSV1b and spare conductive members TSV1_S1, TSV1_S2, TSV1_S3 respectively, and the conductive members TSV1a, TSV1b and spare conductive members TSV1_S1, TSV1_S2, TSV1_S3 in memory chip Dj may be electrically connected to the conductive members TSV1a, TSV1b and spare conductive members TSV1_S1, TSV1_S2, TSV1_S3 in memory chip Dj-1 respectively. In some embodiments, each conductive member 110 may be a micro-bump and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN and W.

[0037] In some embodiments, the bottom logic die 200 may include conductive members 120 electrically connecting the bottom logic die 200 to the memory die Dm. For example, the conductive members 120 of the bottom logic die 200 may be respectively disposed on conductive members TSV2a, TSV2b and spare conductive members TSV2_S1, TSV2_S2, TSV2_S3, and the conductive members TSV2a, TSV2b and spare conductive members TSV2_S1, TSV2_S2, TSV2_S3 in the bottom logic die 200 may be electrically connected to the conductive members TSV1a, TSV1b and spare conductive members TSV1_S1, TSV1_S2, TSV1_S3 in the memory die Dm. In some embodiments, each conductive member 120 may be a microbump and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN and W.

[0038] A top die 300 is disposed on the memory die stack 100 and includes a device layer 302 disposed in a first region R1 and a second global repair circuit 304 disposed in a second region R2. The top die 300 is electrically connected to the memory die D1 in the memory die stack 100 via conductive members 110 disposed therebetween. For example, the conductive members 110 of the memory die D1 electrically connect the device layer 302 of the top die 300 to the conductive member TSV1a of the memory die D1 in the first region R1, and electrically connect the second global repair circuit 304 of the top die 300 to the conductive member TSV1b of the memory die D1 in the second region R2. In some embodiments, the device layer 302 may include memory devices in a device area and wiring in a connection area. The device area may be a region of the top die 300 in which a memory array is disposed. The connection area may be a region of the top die 300 in which connection members such as connection pads or wiring layers / wiring patterns are disposed. For example, the device layer 302 shown in FIG1 may be a wiring layer of the conductive component 110 connected to the memory chip D1 in the first region R1, but this disclosure is not limited thereto.

[0039] In this embodiment, the top die 300 includes a top repair via TSV3 disposed in the second region R2 and connected to the second global repair circuit 304. This allows testing and repair procedures to be initiated from the bottom logic die 200 and / or from the top die 300, and to still be probed via the redistribution layer (e.g., the redistribution layer RDL1 on the top die 300) after system assembly, thereby improving the quality and yield of the memory device 10. For example, during a testing procedure, if a series of commands from the bottom logic die 200 cannot access memory die Dj-1, this assumes that one of the wiring (e.g., a control path) in memory die Dj-1 for the first local repair circuit 104 is damaged. In this case, the second global repair circuit 304 in the top die 300 can initiate a series of commands through the top repair via TSV3, so that the first local repair circuit 104 in the memory die Dj-1 can be started from the top die 300, and the first local repair circuit 104 in the memory die Dj can be started from the bottom logic die 200, so as to complete the rerouting repair action by performing cutting and rerouting actions on the memory die Dj and the memory die Dj-1.

[0040] In some embodiments, the top repair vias TSV3 may each be a through-silicon via (TSV) and may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W. In some embodiments, the height of one of the top repair vias TSV3 may be greater than 175 μm. In some other embodiments, the height of the plurality of top repair vias TSV3 may be greater than 175 μm. In some embodiments, the bottom logic die 200 may include bottom repair vias (i.e., conductive members TSV2b) disposed in the second region R2 and connected to the first global repair circuit 204, and in the direction in which memory dies D1 to Dm are stacked, the height of one of the bottom repair vias (i.e., conductive members TSV2b) may be less than the height of one of the top repair vias TSV3. In some other embodiments, in the direction in which memory dies D1 to Dm are stacked, the height of the plurality of bottom repair vias (i.e., conductive members TSV2b) may be less than the height of the plurality of top repair vias TSV3. In some embodiments, in the stacking direction of memory dies D1 to Dm, the height of one of the top repair vias TSV3 may be greater than the height of the vias (e.g., one of conductive members TSV1a or TSV1b) of each of the memory dies D1 to Dm that connect to the device layer 102 or the first local repair circuit 104. In some embodiments, in the stacking direction of memory dies D1 to Dm, the height of a plurality of top repair vias TSV3 may be greater than the height of the vias (e.g., conductive members TSV1a or TSV1b) of each of the memory dies D1 to Dm that connect to the device layer 102 or the first local repair circuit 104.

[0041] In some embodiments, the diameter of one of the top repair vias TSV3 may be greater than 20 μm. In some other embodiments, the diameter of the plurality of top repair vias TSV3 may be greater than 20 μm. In some embodiments, the diameter of one of the bottom repair vias (e.g., one of the conductive members TSV2b) may be smaller than the diameter of one of the top repair vias TSV3. In some other embodiments, the diameter of the plurality of bottom repair vias (i.e., conductive members TSV2b) may be smaller than the diameter of the plurality of top repair vias TSV3. In some embodiments, the diameter of one of the top repair vias TSV3 may be larger than the diameter of the vias (e.g., one of the conductive members TSV1a or TSV1b) connecting each of the memory dies D1 to Dm to the device layer 102 or the first local repair circuit 104. In some other embodiments, the diameter of the plurality of top repair vias TSV3 may be larger than the diameter of the vias (e.g., conductive members TSV1a or TSV1b) connecting each of the memory dies D1 to Dm to the device layer 102 or the first local repair circuit 104.

[0042] A redistribution layer RDL1 is disposed on the top die 300 and electrically connected to the top repair via TSV3. In some embodiments, the redistribution layer RDL1 may include at least one insulating layer and at least one conductive layer alternately stacked along the direction of mutual stacking of memory dies D1 to Dm. In some embodiments, the connection pads CP1 contained in the redistribution layer RDL1 and respectively connected to the top repair via TSV3 may be redistributed such that the spacing between two adjacent contact pads at the ends of the contact test pads TP1 of the redistribution layer RDL1 may be greater than the spacing between two adjacent connection pads CP1 at the ends of the contact top repair via TSV3 of the redistribution layer RDL1. Therefore, the test pad TP1 may be formed to have a size larger than that of the connection pad CP1 (e.g., the size of the connection pad CP1 is less than 60 μm). For example, the test pad TP1 may be formed to have a size greater than 100 μm. The insulating layer may include any suitable insulating material. The conductive layer may include any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0043] Test pad TP1 may be included in memory device 10 and electrically connected to top repair via TSV3 via redistribution layer RDL1. Redistribution layer RDL1 may include connection pads CP1 respectively connected to top repair via TSV3 and wiring respectively connecting test pad TP1 to connection pads CP1. Test pad TP1, connection pad CP1, and wiring may each comprise any suitable conductive material, such as one or more metals or metal alloys including Al, AlCu, Cu, Ti, TiN, and W.

[0044] In some embodiments, the second global repair circuit 304 in the top die 300 may be configured to receive control signals from at least one test pad TP1. For example, in some embodiments, the second global repair circuit 304 may include a signal Rx buffer circuit (e.g., buffer 1 shown in FIG. 2), a bidirectional buffer circuit (e.g., buffer 2 shown in FIG. 2), and electrostatic discharge (ESD) protection circuits (e.g., ESD shown in FIG. 2) connected to the signal Rx buffer circuit and the bidirectional buffer circuit, respectively. Therefore, test control signals (e.g., signal 11 or signal 12 shown in FIG. 2) from the test pad TP1 and through the top repair via TSV3 may be transmitted to the ESD protection circuit and the signal Rx buffer circuit or the bidirectional buffer circuit before being transmitted to the control bus of the second global repair circuit 304.

[0045] In some embodiments, the top die 300 can serve as a second test / repair path for the memory logic and signal paths in memory dies D1 to Dm. For example, a control bus connected to the second global repair circuit 304 is used to activate the second global repair circuit 304 in the top die 300, via a test pad TP1, redistribution layer RDL1, top repair via TSV3, and ESD protection circuitry (e.g., electrostatic discharge (ESD) shown in FIG. 2), and signal Rx buffer circuitry (e.g., buffer 1 shown in FIG. 2) or bidirectional buffer circuitry (e.g., buffer 2 shown in FIG. 2). Next, the first local repair circuitry 104 in memory die D1 is activated from the second global repair circuit 304 in the top die 300 via the conductive member TSV1b in memory die D1. Afterwards, test and repair operations are performed on memory die D1. The above steps can be repeated on other memory dies D2 to Dm, allowing the test and repair process to be initiated from the top die 300.

[0046] In summary, in the aforementioned memory device, the bottom logic die includes a first global repair circuit in the second region, and the top die includes a second global repair circuit in the second region. The bottom logic die and the top die are located on the bottom and top sides of the memory die stack, respectively, and a redistribution layer is disposed on the top die and electrically connected to the second global repair circuit. In this way, testing and repair procedures can be initiated from the bottom logic die and / or from the top die, and can still be probed through the redistribution layer after system assembly, thereby improving the quality and yield of the memory device.

[0047] To those skilled in the art, various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the following claims and their equivalents.

[0048] 10: Memory Device 100: Memory chip stacking 102, 202, 302: Device Layer 104: First Partial Repair Circuit 110, 120, TSV1a, TSV1b, TSV2a, TSV2b: Conductive components 200: Bottom logic die 204: First Global Repair Circuit 300: Top grain 304: Second Global Repair Circuit CP1: Connecting pad D1~Dm: Memory chips Dj, Dj-1: Memory chips R1: Zone 1 R2: Second Zone RDL1: Redistribution Layer TP1: Test pad TSV1_S1, TSV1_S2, TSV1_S3, TSV2_S1, TSV2_S2, TSV2_S3: Spare conductive components TSV3: Top Repair Through Hole

Claims

1. A memory device, comprising a first region and a second region, wherein the memory device includes: The bottom logic die includes a first global repair circuit configured in the second region and a first device layer configured in the first region; A memory die stack, on the bottom logic die and including at least two memory dies stacked on top of each other, wherein each memory die includes a first local repair circuit disposed in the second region and a second device layer disposed in the first region; a top die, on the memory die stack and including a second global repair circuit disposed in the second region and a third device layer disposed in the first region, wherein the top die includes a plurality of top repair vias disposed in the second region and connected to the second global repair circuit; and a redistribution layer, on the top die and electrically connected to the plurality of top repair vias, wherein the bottom logic die includes a plurality of bottom repair vias disposed in the second region and connected to the first global repair circuit, and the diameter of one of the plurality of bottom repair vias is smaller than the diameter of one of the plurality of top repair vias.

2. The memory device as claimed in claim 1, further comprising: Multiple test pads are located on the redistribution layer and electrically connected to the multiple top repair vias via the redistribution layer.

3. The memory device as claimed in claim 2, wherein the redistribution layer includes a plurality of connection pads and a plurality of wirings, the plurality of connection pads being respectively connected to the plurality of top repair vias, the plurality of wirings respectively connecting the plurality of test pads to the plurality of connection pads, and the plurality of connection pads being smaller than the plurality of test pads.

4. The memory device as claimed in claim 3, wherein the second global repair circuit is configured to receive a control signal from at least one of the plurality of test pads.

5. The memory device as claimed in claim 1, wherein the second global repair circuit includes a bidirectional buffer circuit.

6. The memory device as claimed in claim 5, wherein the second global repair circuit includes an electrostatic discharge (ESD) protection circuit connected to the bidirectional buffer circuit.

7. The memory device as claimed in claim 1, wherein the diameter of one of the plurality of top-repair vias is larger than the diameter of the vias in each memory die connected to the second device layer.

8. The memory device as claimed in claim 1, wherein the diameter of one of the plurality of top repair vias is larger than the diameter of the vias in each memory die connected to the first local repair circuit.

9. The memory device as claimed in claim 1, wherein one of the plurality of top repair vias has a diameter greater than 20 μm.

10. A memory device comprising a first region and a second region, wherein the memory device includes: The bottom logic die includes a first global repair circuit configured in the second region and a first device layer configured in the first region; A memory die stack, on the bottom logic die and including at least two memory dies stacked on top of each other, wherein each memory die includes a first local repair circuit disposed in a second region and a second device layer disposed in the first region; a top die, on the memory die stack and including a second global repair circuit disposed in the second region and a third device layer disposed in the first region, wherein the top die includes a plurality of top repair vias disposed in the second region and connected to the second global repair circuit; and a redistribution layer, on the top die and electrically connected to the plurality of top repair vias, wherein the bottom logic die includes a plurality of bottom repair vias disposed in the second region and connected to the first global repair circuit, and the height of one of the plurality of bottom repair vias in the direction in which the memory dies are stacked on top of each other is less than the height of one of the plurality of top repair vias.

11. The memory device of claim 10, wherein the height of one of the plurality of top-repair vias is greater than the height of the vias in each memory die connected to the second device layer in the direction.

12. The memory device of claim 10, wherein the height of one of the plurality of top repair vias is greater than the height of the vias in each memory die connected to the first local repair circuit in the direction.

13. The memory device as claimed in claim 10, wherein the height of one of the plurality of top repair vias is greater than 175 μm.

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