Semiconductor package having two or more driver devices

Abstract

This invention discloses a semiconductor package comprising a lead frame, two or more low-side field-effect transistors (FETs), two or more high-side FETs, two or more metal clips, a metal block, an integrated circuit (IC) controller, and a molded package. The advantage of this invention is that it co-packages DrMOS transistors in a single package, reducing package size and lowering impedance.

Description

Technical Field

[0001] This invention generally relates to a semiconductor package. More specifically, this invention relates to a semiconductor package having two or more drivers. Prior Technology

[0002] Traditional circuits that power a central processing unit (CPU) or graphics processing unit (GPU) consist of multiple driver metal-oxide-semiconductor (DrMOS) circuits. These DrMOS circuits take up space and increase impedance.

[0003] U.S. Patent No. 11,094,617 (Xue et al.) discloses a size-reduced (from 5 mm × 6 mm to 5 mm × 5 mm) buck-boost power controller that includes at least four field-effect transistors (FETs) packaged in a single package. This invention further reduces the size to 5 mm × 4 mm by using a common Vcc pin, TMON pin, AGND pin, and PVcc pin. Summary of the Invention

[0004] This invention discloses a semiconductor package, comprising:

[0005] A lead frame comprising: a first die pad; and a second die pad;

[0006] Two or more low-side field-effect transistors (FETs), wherein each of the two or more low-side FETs is flipped and connected to the first wafer pad, each of the two or more low-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more low-side FETs, and each of the two or more low-side FETs includes a drain electrode located on the bottom surface of each of the two or more low-side FETs;

[0007] Two or more high-side FETs, wherein each of the two or more high-side FETs is connected to the second wafer pad, and each of the two or more high-side FETs includes a source electrode and a gate electrode located on the top surface of each of the two or more high-side FETs;

[0008] Two or more metal clips, wherein each of the two or more metal clips connects the drain electrode of a corresponding low-side FET of the two or more low-side FETs to the source electrode of a corresponding high-side FET of the two or more high-side FETs;

[0009] A metal block is located above the two or more metal clips, wherein each of the two or more metal clips is connected to the metal block;

[0010] An integrated circuit (IC) controller is located above the two or more metal clips; and

[0011] A molded package encapsulates the two or more low-side FETs, the two or more high-side FETs, the two or more metal clips, most of the metal block, the IC controller, and most of the lead frame.

[0012] Wherein, a first significant portion of the bottom surface of the first wafer pad is exposed from the molded package; a second significant portion of the bottom surface of the second wafer pad is exposed from the molded package; and the top surface of the metal block is exposed from the molded package.

[0013] The semiconductor package further includes multiple bonding wires;

[0014] The lead frame also includes multiple pins;

[0015] The plurality of bonding wires connect the IC controller to the plurality of pins; and

[0016] The molded package further encapsulates the plurality of bonding wires.

[0017] The first wafer pad includes two or more wafer pad portions and one or more connection portions;

[0018] Each of the one or more connection portions is located between a first corresponding wafer pad portion and a second corresponding wafer pad portion of the two or more wafer pad portions; and

[0019] Each of the one or more connection portions is top-etched such that the thickness of each of the one or more connection portions is less than the thickness of the first corresponding wafer pad portion of the two or more wafer pad portions.

[0020] The thickness of each of the one or more connection portions is 50% of the thickness of the first corresponding wafer pad portion.

[0021] Each of the one or more connecting portions includes one or more slots; and

[0022] Each of the one or more connecting portions has one or more slots filled with a molded encapsulation.

[0023] The second wafer pad includes two or more wafer pad portions and one or more connection portions:

[0024] Each of the one or more connection portions is located between a first corresponding wafer pad portion and a second corresponding wafer pad portion of the two or more wafer pad portions; and

[0025] Each of the one or more connecting portions has a groove etched on its bottom;

[0026] The groove is filled with a molded package; and

[0027] The thickness of each of the one or more connecting portions is less than the thickness of the first corresponding wafer pad portion of the two or more wafer pad portions.

[0028] The semiconductor package also includes two or more drivers;

[0029] Each of the two or more drives mentioned herein includes:

[0030] The respective low-side FETs of the two or more low-side FETs;

[0031] The corresponding high-side FETs of the two or more high-side FETs; and

[0032] The corresponding metal clips of the two or more metal clips.

[0033] Each of the two or more drivers is connected to the same Vcc pin, the same TMON pin, the same AGND pin, and the same PVcc pin.

[0034] The metal block and the IC controller are connected to the two or more metal clips via non-conductive epoxy resin.

[0035] The present invention also discloses a method for manufacturing a semiconductor package. The method includes the following steps: providing a lead frame including wafer pads; connecting transistors to the wafer pads respectively; mounting metal clips; mounting a metal block and a controller; applying bonding wires; forming a molded package; and applying a dicing process.

[0036] This invention encapsulates DrMOS within a single package to reduce package size and lower impedance. Furthermore, by using common Vcc, TMON, AGND, and PVcc pins, the size is further reduced to 5 mm × 4 mm. Simple Explanation of the Diagram

[0037] Figure 1 shows a schematic diagram of a conventional circuit that provides power to a CPU or GPU. Figure 2A shows a top perspective view of the semiconductor package in an example of the present invention, and Figure 2B shows a bottom perspective view thereon. Figure 3 shows a top perspective view of another semiconductor package in an example of the present invention. Figure 4 shows a process flow diagram for developing semiconductor packaging in an example of the present invention. Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, and 5J respectively represent perspective views of various steps in manufacturing a semiconductor package in an example of the present invention. Implementation

[0038] Figure 1 shows a schematic diagram of a circuit 100 that provides power to a CPU or GPU 110. Circuit 100 includes a first DrMOS 122, a second DrMOS 124, and a controller 130. An advantage of this invention is that the DrMOS components are co-packaged in a single package, reducing package size and impedance.

[0039] Figure 2A is a top perspective view of the semiconductor package 200 in an example of the present invention, and Figure 2B is a bottom perspective view thereon. The semiconductor package 200 includes a lead frame 220, two or more low-side field-effect transistors (FETs) 540 as shown in Figure 5C, two or more high-side FETs 550 as shown in Figure 5C, two or more metal clips 560 as shown in Figure 5E, a metal block 280, an integrated circuit (IC) controller 582 as shown in Figure 5G, and a molded package 290.

[0040] The leadframe 220 includes a first die pad 522 as shown in FIG. 5A and a second die pad 524 as shown in FIG. 5A. In one example, the top of the first die pad 522 is etched to form one or more cavities 523, which are filled with the molded package 290. In another example, the bottom of the second die pad 524 is etched to form one or more recesses, including a recess 525 as shown in FIG. 5A, which are filled with the molded package 290. In an example of the present invention, the leadframe 220 includes one or more slots 529, which are filled with the molded package 290 to facilitate a locking mechanism, thereby improving the integration of the leadframe 220 and the molded package 290.

[0041] As shown in Figure 5C, each of the two or more low-side FETs 540 is flipped and connected to the first wafer pad 522. Each of the two or more low-side FETs 540 includes a source electrode 541 and a gate electrode 543 located on the top surface of each of the two or more low-side FETs 540. Each of the two or more low-side FETs 540 includes a drain electrode 547 located on the bottom surface of each of the two or more low-side FETs 540.

[0042] Each of the two or more high-side FETs 550 is connected to a second wafer pad 524. Each of the two or more high-side FETs 550 includes a source electrode 551 and a gate electrode 553 located on the top surface of each of the two or more high-side FETs 550.

[0043] Each of the two or more metal clips 560 connects the drain electrode 547 of the corresponding low-side FET of the two or more low-side FETs 540 to the source electrode 551 of the corresponding high-side FET of the two or more high-side FETs 550.

[0044] Metal block 280 is mounted above two or more metal clips 560, optionally above two or more low-side FETs 540. Each of the two or more metal clips 560 is connected to metal block 280.

[0045] IC controller 582 is mounted above two or more metal clips 560, optionally above two or more high-side FETs 550.

[0046] The molded package 290 encapsulates two or more low-side FETs 540, two or more high-side FETs 550, two or more metal clips 560, a first majority portion of a metal block 280, an IC controller 582, and a second majority portion of a lead frame 220. In this example of the invention, the first majority portion refers to a percentage greater than 50%. The second majority portion refers to a percentage greater than 50%.

[0047] A first significant portion of the bottom surface of the first die pad 522 is exposed from the molded package 290. A second significant portion of the bottom surface of the second die pad 524 is exposed from the molded package 290. In this example of the invention, the first significant portion refers to a portion greater than 90%. The second significant portion refers to a portion greater than 90%. The top surface of the metal block 280 is exposed from the molded package 290.

[0048] In an example of the present invention, the semiconductor package 200 further includes a plurality of bonding wires 589 as shown in FIG. 5H. The lead frame 220 further includes a plurality of pins 287 as shown in FIG. 5G. The plurality of bonding wires 589 connect the IC controller 582 to the plurality of pins 287. The molded package 290 also encapsulates the plurality of bonding wires 589.

[0049] The first wafer pad includes two or more wafer pad portions 531 and one or more connection portions 533, as shown in FIG. 5A. Although only the first corresponding wafer pad portion 532 and the second corresponding wafer pad portion 534 are shown in FIG. 5A, the number of the two or more wafer pad portions 531 may vary. Each connection portion of the one or more connection portions 533 is located between the first corresponding wafer pad portion 532 and the second corresponding wafer pad portion 534 of the two or more wafer pad portions 531. Each connection portion of the one or more connection portions 533 is top-etched such that the thickness of each connection portion of the one or more connection portions 533 is less than the thickness of the first corresponding wafer pad portion 532 of the two or more wafer pad portions 531. In an example of the present invention, the thickness of each connection portion of the one or more connection portions 533 is 50% of the thickness of the first corresponding wafer pad portion 532.

[0050] Each of the one or more connection portions 533 includes one or more slots 529. The one or more slots 529 of each of the one or more connection portions 533 are filled with a molded package 290.

[0051] The second die pad 524 includes two or more die pad portions 537 and one or more connection portions 539. One or more connection portions 539 of each connection portion are located between a first corresponding die pad portion 536 and a second corresponding die pad portion 538 of the two or more die pad portions 537. A recess 525 is etched into the bottom of the one or more connection portions 539 of each connection portion. The recess 525 is filled with a molded package 290. The thickness of the one or more connection portions 539 of each connection portion is less than the thickness of the first corresponding die pad portion 536 of the two or more die pad portions 537.

[0052] The semiconductor package includes two or more drivers. In one example, the semiconductor package 200 in FIG2A includes a first driver 597 as shown in FIG5G and a second driver 599 as shown in FIG5G. In another example, the semiconductor package 300 in FIG3 includes a first driver 391, a second driver 393, a third driver 395, and a fourth driver 397. Each of the two or more drivers in the semiconductor package 200 includes two or more low-side FETs 540 of a corresponding low-side FET, two or more high-side FETs 550 of a corresponding high-side FET, and corresponding metal clips of two or more metal clips 560. Each of the two or more drivers is connected to the same Vcc pin 501, the same TMON pin 503, the same AGND pin 505, and the same PVcc pin 507 as shown in FIG5G to reduce the width of the semiconductor package 200 (from 5 mm × 5 mm to 5 mm × 4 mm).

[0053] Figure 4 shows a flowchart of a semiconductor packaging process 400 in an example of the present invention. Process 400 can begin at step 402.

[0054] In step 402, referring to FIG. 5A, a leadframe 220 is provided. The leadframe 220 includes a first die pad 522 and a second die pad 524. In one example, the top of the first die pad 522 is etched to form one or more cavities 523, which are filled with the molded package 290. In another example, the bottom of the second die pad 524 is etched to form one or more recesses, including recesses 525, which are filled with the molded package 290. In examples of this disclosure, the leadframe 220 includes one or more slots 529, which are filled with the molded package 290 to facilitate a locking mechanism, thereby improving the integration of the leadframe 220 and the molded package 290.

[0055] The first wafer pad includes two or more wafer pad portions 531 and one or more connection portions 533. Although only the first corresponding wafer pad portion 532 and the second corresponding wafer pad portion 534 are shown in FIG. 5A, the number of the two or more wafer pad portions 531 may vary. Each connection portion of the one or more connection portions 533 is located between the first corresponding wafer pad portion 532 and the second corresponding wafer pad portion 534 of the two or more wafer pad portions 531. Each connection portion of the one or more connection portions 533 is top-etched such that the thickness of each connection portion of the one or more connection portions 533 is less than the thickness of the first corresponding wafer pad portion 532 of the two or more wafer pad portions 531. In an example of the present invention, the thickness of each connection portion of the one or more connection portions 533 is 50% of the thickness of the first corresponding wafer pad portion 532.

[0056] Each of the one or more connection portions 533 includes one or more slots 529. The one or more slots 529 of each of the one or more connection portions 533 are filled with a molded package 290.

[0057] The second die pad 524 includes two or more die pad portions 537 and one or more connection portions 539. Each of the one or more connection portions 539 is located between a first corresponding die pad portion 536 and a second corresponding die pad portion 538 of the two or more die pad portions 537. Each of the one or more connection portions 539 has a bottom-etched recess 525. The recess 525 is filled with a molded package 290. The thickness of each of the one or more connection portions 539 is less than the thickness of the first corresponding die pad portion 536 of the two or more die pad portions 537. Step 402 may be followed by step 404.

[0058] In step 404, referring to Figures 5B and 5C, two or more low-side FETs 540 are connected to a first wafer pad 522 via a printed solder material layer 549, and two or more high-side FETs 550 are connected to a second wafer pad 524. Each of the two or more low-side FETs 540 shown in Figure 5C is flipped and connected to the first wafer pad 522. Each of the two or more low-side FETs 540 includes a source electrode 541 and a gate electrode 543 located on the top surface of each low-side FET. Each of the two or more low-side FETs 540 includes a drain electrode 547 located on the bottom surface of each low-side FET.

[0059] Each of the two or more high-side FETs 550 is connected to a second wafer pad 524. Each of the two or more high-side FETs 550 includes a source electrode 551 and a gate electrode 553 located on the top surface of each of the two or more high-side FETs 550. Step 404 may be followed by step 406.

[0060] In step 406, referring to Figures 5D and 5E, two or more metal clips are mounted by distributing solder material layer 559. Each of the two or more metal clips 560 connects the drain electrode 547 of a corresponding low-side FET of two or more low-side FETs 540 to the source electrode 551 of a corresponding high-side FET of two or more high-side FETs 550. Step 406 may be followed by step 408.

[0061] In step 408, referring to Figures 5F and 5G, a metal block 280 and an IC controller 582 are mounted on two or more metal clips 560 via a non-conductive epoxy resin layer 579. Optionally, the metal block 280 may be mounted above two or more low-side FETs 540. Each of the two or more metal clips 560 is connected to the metal block 280. The IC controller 582 is located above two or more high-side FETs 550. Optionally, the IC controller 582 may be connected to each of the two or more metal clips 560. Step 408 may be followed by step 410.

[0062] In step 410, referring to FIG5H, multiple bonding wires 589 are installed and connected. The multiple bonding wires 589 connect the IC controller 582 to multiple pins 287 of the lead frame 220. Step 410 may be followed by step 412.

[0063] In step 412, referring to FIG. 5I, a molded package 290 is formed. The molded package 290 encapsulates two or more low-side FETs 540, two or more high-side FETs 550, two or more metal clips 560, a majority portion of the metal block 280, the IC controller 582, and a majority portion of the lead frame 220. In one example, the molded package 290 also encapsulates a plurality of bonding wires 589. In examples of the present invention, "majority" refers to a portion greater than 50%.

[0064] A first significant portion of the bottom surface of the first die pad 522 is exposed from the molded package 290. A second significant portion of the bottom surface of the second die pad 524 is exposed from the molded package 290. In this example of the invention, the first significant portion refers to a portion greater than 90%. The second significant portion refers to a portion greater than 90%. The top surface of the metal block 280 is exposed from the molded package 290. Step 412 may be followed by step 414.

[0065] In step 414, referring to FIG5J, cutting process 209 is applied to separate semiconductor package 200 from adjacent semiconductor packages 201 and 203.

[0066] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the number of leads may vary. Other modifications can be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined in the claims.

[0067] 100: Circuit 110:CPU or GPU 122: First DrMOS 124: Second DrMOS 130: Controller 200, 201, 203: Semiconductor Packaging 209: Cutting process 220: Lead Frame 280: Metal Block 287: Pin 290: Molded Package 300: Semiconductor Packaging 391: First Driver 393: Second Driver 395: Third Drive 397: The Fourth Drive 400: Process 402, 404, 406, 408, 410, 412, 414: Steps 501: Vcc pin 503: TMON pin 505: AGND pin 507: PVcc pin 522: First chip pad 523: Cavity 524: Second chip pad 525: Groove 529: Slot 531: Wafer Pad Section 532: First corresponding wafer pad portion 533: Connection part 534: Second corresponding wafer pad portion 536: First corresponding wafer pad portion 537: Chip Pad Section 538: Second corresponding wafer pad portion 539: Connection part 540: Low-side FET 541: Source electrode 543: Gate electrode 547: Drain electrode 549: Printed solder material layer 550: High-side FET 551: Source electrode 553: Gate electrode 559: Distribute solder material layers 560: Metal Clip 579: Non-conductive epoxy resin layer 582: IC controller 589: Bond wire 597: First Driver 599: Second Driver

Claims

1. A semiconductor package, wherein, include: A lead frame comprising: a first wafer pad; and a second wafer pad; two or more low-side FETs, wherein each of the two or more low-side FETs is flipped and connected to the first wafer pad, each of the two or more low-side FETs including a source electrode and a gate electrode located on the top surface of each of the two or more low-side FETs, and each of the two or more low-side FETs including a drain electrode located on the bottom surface of each of the two or more low-side FETs; two or more high-side FETs, wherein each of the two or more high-side FETs is connected to the second wafer pad, and each of the two or more high-side FETs including a source electrode and a gate electrode located on the top surface of each of the two or more high-side FETs; and two or more metal clips, wherein each of the two or more metal clips connects the drain electrode of a corresponding low-side FET of the two or more low-side FETs to the source electrode of a corresponding high-side FET of the two or more high-side FETs. A metal block is located above the two or more metal clips, wherein each of the two or more metal clips is connected to the metal block; an IC controller is located above the two or more metal clips; and a molded package encapsulates the two or more low-side FETs, the two or more high-side FETs, the two or more metal clips, a majority of the metal block, the IC controller, and a majority of the lead frame; wherein the first wafer pad includes two or more wafer pad portions and one or more connection portions.

2. The semiconductor package as described in claim 1, wherein, A first significant portion of the bottom surface of the first wafer pad is exposed from the molded package; A second significant portion of the bottom surface of the second wafer pad is exposed from the molded package; Furthermore, the top surface of the metal block is exposed from the molded package.

3. The semiconductor package as described in claim 1, wherein, It also includes multiple bonding wires; wherein the lead frame further includes multiple pins; wherein the multiple bonding wires connect the IC controller to the multiple pins; and wherein the molded package further encapsulates the multiple bonding wires.

4. The semiconductor package of claim 1, wherein each of the one or more connection portions is located between a first corresponding wafer pad portion and a second corresponding wafer pad portion of the two or more wafer pad portions; and wherein each of the one or more connection portions is top-etched such that the thickness of each of the one or more connection portions is less than the thickness of the first corresponding wafer pad portion of the two or more wafer pad portions.

5. The semiconductor package as described in claim 4, wherein, The thickness of each of the one or more connection portions is 50% of the thickness of the first corresponding wafer pad portion.

6. The semiconductor package as described in claim 4, wherein, Each of the one or more connecting portions includes one or more slots; and the one or more slots of each of the one or more connecting portions are filled with the molded package.

7. The semiconductor package as claimed in claim 1, wherein, The second wafer pad includes two or more wafer pad portions and one or more connection portions: each of the one or more connection portions is located between a first corresponding wafer pad portion and a second corresponding wafer pad portion of the two or more wafer pad portions; and each of the one or more connection portions has a bottom etched groove; the groove is filled with the molded package; and the thickness of each of the one or more connection portions is less than the thickness of the first corresponding wafer pad portion of the two or more wafer pad portions.

8. The semiconductor package as described in claim 1, wherein, It also includes two or more drivers; wherein each of the two or more drivers includes: a corresponding low-side FET of the two or more low-side FETs; a corresponding high-side FET of the two or more high-side FETs; and a corresponding metal clip of the two or more metal clips.

9. The semiconductor package as described in claim 8, wherein, Each of the two or more drivers is connected to the same Vcc pin, the same TMON pin, the same AGND pin, and the same PVcc pin.

10. The semiconductor package as claimed in claim 1, wherein, The metal block and the IC controller are connected to the two or more metal clips via non-conductive epoxy resin.

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