Image sensor and method for forming the same

Abstract

This disclosure provides an image sensor and a method for forming the same. The image sensor includes a logic wafer, an image sensing wafer, an intermediate wafer, and conductive elements. The logic wafer includes a first interconnect structure disposed on a first substrate. The image sensing wafer includes a second substrate, an image sensing element, a transfer transistor, a source follower transistor, and a second interconnect structure. The second substrate includes a pixel region and a connection region disposed in a cell region. The image sensing element is disposed in the pixel region. The transfer transistor and the source follower transistor are respectively disposed on the pixel region. The second interconnect structure is disposed on the second substrate and electrically connected to the transfer transistor and the source follower transistor. The intermediate wafer is disposed between the image sensing wafer and the logic wafer and includes a passive element electrically connected to the source follower transistor. The conductive elements are disposed in the connection region and include conductive pads embedded in the second substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the same, and more particularly to an image sensor and a method for forming the same. Prior Technology

[0002] Image sensors are widely used in devices such as cameras, mobile phones, and automotive lenses. In recent years, compared to charge-coupled devices (CCDs), complementary metal-oxide-semiconductor (CMOS) image sensors have become increasingly advantageous due to their lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing cost. Therefore, CMOS image sensors have largely replaced CCD image sensors. Generally, CMOS image sensors can include front-side illuminated (FSI) image sensors and back-side illuminated (BSI) image sensors.

[0003] However, as electronic devices continue to evolve towards smaller size and higher performance, the current image sensors and their manufacturing yields may not be able to meet current or future needs. Summary of the Invention

[0004] This invention provides an image sensor and a method for forming the same, wherein the logic wafer, image sensing wafer, and intermediate wafer in the image sensor can be manufactured independently first, and then bonded together by stacking. In this way, the process used to form the intermediate wafer does not affect the image sensing wafer, and the passive components in the intermediate wafer can be formed in various types without considering the image sensing wafer, thereby significantly improving the stability, cost, and performance of the image sensor.

[0005] An embodiment of the present invention provides an image sensor including a logic wafer, an image sensing wafer, an intermediate wafer, and conductive elements. The logic wafer includes a first interconnect structure disposed on a first substrate. The image sensing wafer is disposed above the logic wafer and includes a second substrate, an image sensing element, a transfer transistor, a source follower transistor, and a second interconnect structure. The second substrate includes a pixel region and a connection region disposed in a cell region. The image sensing element is disposed in the pixel region. The transfer transistor and the source follower transistor are respectively disposed on the pixel region. The second interconnect structure is disposed on the second substrate and electrically connected to the transfer transistor and the source follower transistor. The intermediate wafer is disposed between the image sensing wafer and the logic wafer and includes a passive element electrically connected to the source follower transistor. The conductive element is disposed in the connection region and includes a conductive pad embedded in the second substrate.

[0006] In some embodiments, the image sensing wafer includes a color filter covering a pixel area and a microlens on the color filter, wherein the color filter and the microlens do not cover the connection area.

[0007] In some embodiments, the second substrate includes trenches in the connection region that expose conductive pads.

[0008] In some embodiments, the interposer wafer includes an interposer substrate and a back-side wiring structure. The interposer substrate includes a front surface and a back surface, and a passive component is disposed in the interposer substrate. The back-side wiring structure is disposed on the back surface and is electrically connected to the passive component and a first interconnect structure.

[0009] In some embodiments, the back-side wiring structure includes a first conductive via penetrating the intermediate substrate, the conductive element includes a second conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the second conductive via and the first conductive via.

[0010] In some embodiments, the front surface of the interposer substrate faces the logic wafer, the back surface of the interposer substrate faces the image sensing wafer, and the first conductive via includes a portion extending into the first interconnect structure.

[0011] In some embodiments, the front surface of the interposer substrate faces the image sensing wafer, the back surface of the interposer substrate faces the logic wafer, and the interposer wafer includes a front wiring structure disposed on the front surface and electrically connected to the second interconnect structure.

[0012] In some embodiments, the front wiring structure is bonded to the second interconnect structure via a hybrid bond, and the back wiring structure is bonded to the first interconnect structure via a hybrid bond.

[0013] An embodiment of the present invention provides a method for forming an image sensor, comprising the following steps: A logic wafer is provided, wherein the logic wafer includes a first interconnect structure disposed on a first substrate. An image sensing wafer is provided, wherein the image sensing wafer includes a second substrate, an image sensing element, a transfer transistor, a source follower transistor, and a second interconnect structure. The second substrate includes a pixel region and a connection region disposed in a cell region. The image sensing element is formed in the pixel region. The transfer transistor and the source follower transistor are respectively formed on the pixel region. The second interconnect structure is formed on the second substrate and electrically connected to the transfer transistor and the source follower transistor. An intermediate wafer is provided, wherein the intermediate wafer includes an intermediate substrate and a passive element. The intermediate substrate includes a front surface and a back surface. The passive element is formed in the intermediate substrate. The intermediate wafer is bonded to the logic wafer, wherein the front surface of the intermediate substrate faces the logic wafer. A back-side wiring structure is formed on the back surface of the intermediate substrate, wherein the back-side wiring structure is electrically connected to the passive element and the first interconnect structure. The image sensing wafer is bonded to the intermediate wafer, wherein the second interconnect structure is bonded to the back-side wiring structure.

[0014] In some embodiments, the method of forming an image sensor further includes forming a color filter and a microlens on the color filter on a pixel area, wherein the color filter and the microlens cover the pixel area, while the color filter and the microlens do not cover the connection area.

[0015] In some embodiments, the method of forming an image sensor further includes forming a conductive element in the connection area, wherein the conductive element includes a conductive pad embedded in a second substrate.

[0016] In some embodiments, the second substrate includes trenches in the connection region that expose conductive pads.

[0017] In some embodiments, the back-side wiring structure includes a first conductive via penetrating the intermediate substrate, the conductive element includes a second conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the second conductive via and the first conductive via.

[0018] In some embodiments, the back surface of the intermediate substrate faces the image sensing wafer, and the first conductive via includes a portion extending into the first interconnect structure.

[0019] Another embodiment of the present invention provides a method for forming an image sensor, comprising the following steps: A logic wafer is provided, wherein the logic wafer includes a first interconnect structure disposed on a first substrate. An image sensing wafer is provided, wherein the image sensing wafer includes a second substrate, an image sensing element, a transfer transistor, a source follower transistor, and a second interconnect structure. The second substrate includes a pixel region and a connection region disposed in a cell region. The image sensing element is formed in the pixel region. The transfer transistor and the source follower transistor are respectively formed on the pixel region. The second interconnect structure is formed on the second substrate and electrically connected to the transfer transistor and the source follower transistor. An intermediate wafer is provided, wherein the intermediate wafer includes an intermediate substrate, a passive element, and a front-side wiring structure. The intermediate substrate includes a front-side surface and a back-side surface. The passive element is formed in the intermediate substrate. The front-side wiring structure is formed on the front-side surface. The intermediate wafer is bonded to the image sensing wafer, wherein the front-side surface of the intermediate substrate faces the image sensing wafer, and the front-side wiring structure is electrically connected to the second interconnect structure. A back-side wiring structure is formed on the back-side surface of an intermediate substrate, wherein the back-side wiring structure is electrically connected to a passive component. A logic wafer is bonded to the intermediate wafer, wherein a first interconnect structure is bonded to the back-side wiring structure.

[0020] In some embodiments, the method of forming an image sensor further includes forming a color filter and a microlens on the color filter on a pixel area, wherein the color filter and the microlens cover the pixel area, while the color filter and the microlens do not cover the connection area.

[0021] In some embodiments, the method of forming an image sensor further includes forming a conductive element in the connection area, wherein the conductive element includes a conductive pad embedded in a second substrate.

[0022] In some embodiments, the second substrate includes trenches in the connection region that expose conductive pads.

[0023] In some embodiments, the back-side wiring structure includes a first conductive via penetrating the intermediate substrate, the conductive element includes a second conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the second conductive via and the first conductive via.

[0024] In some embodiments, the front wiring structure is joined to the second interconnect structure by a hybrid connection, and the back wiring structure is joined to the first interconnect structure by a hybrid connection.

[0025] Based on the above, in the aforementioned image sensor and its formation method, the logic wafer, image sensing wafer, and intermediate wafer in the image sensor can be manufactured independently first, and then bonded together by stacking. In this way, the process used to form the intermediate wafer does not affect the image sensing wafer, and the passive components (e.g., capacitors) in the intermediate wafer can be formed into various desired types without considering the components (e.g., image sensing elements) in the image sensing wafer, thereby significantly improving the stability, cost, and performance of the image sensor. Simple Explanation of the Diagram

[0026] Figures 1A to 1F are schematic cross-sectional views of a method for forming an image sensor according to a first embodiment of the present invention. Figures 2A to 2D are cross-sectional schematic diagrams of a method for forming an image sensor according to a second embodiment of the present invention. Figures 3A to 3C are cross-sectional schematic diagrams of passive elements according to different embodiments of the present invention. Figure 4 is a cross-sectional schematic diagram of an image sensor according to an embodiment of the present invention. Implementation

[0027] The invention is described more fully with reference to the drawings of this embodiment. However, the invention may be embodied in various different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings is enlarged for clarity. The same or similar reference numerals denote the same or similar elements, which will not be repeated in the following paragraphs.

[0028] It should be understood that when an element is referred to as being "on" or "connected" to another element, it may be directly on or connected to the other element, or there may be an intermediate element. If an element is referred to as being "directly on" or "directly connected" to another element, there is no intermediate element. As used herein, "connection" may refer to a physical and / or electrical connection, while "electrical connection" or "coupling" may mean that there are other elements between two elements. "Electrical connection" as used herein may include physical connections (e.g., wired connections) and physical disconnections (e.g., wireless connections).

[0029] As used herein, “about,” “approximately,” or “substantially” includes the average of the mentioned value and a specific value that can be determined by someone of ordinary skill in the art, within an acceptable range of deviations, taking into account the measurement under discussion and a specific number of errors associated with the measurement (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations of the value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the use of “about,” “approximately,” or “substantially” herein may be chosen based on the optical, etched, or other properties to select a more acceptable range of deviations or standard deviations, and may not require a single standard deviation to apply to all properties.

[0030] The terminology used herein is for illustrative purposes only and is not intended to limit the scope of this disclosure. In this context, the singular form includes the plural form unless the context otherwise requires.

[0031] Figures 1A to 1F are schematic cross-sectional views of a method for forming an image sensor according to a first embodiment of the present invention.

[0032] First, referring to FIG1A, a logic wafer 10 is provided. In this embodiment, the logic wafer 10 may include a first interconnect structure 110 disposed on a first substrate 100. The first substrate 100 may include a semiconductor substrate and a device layer (not shown) formed on the semiconductor substrate.

[0033] The semiconductor substrate may be, for example, a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include Si or Ge. Alloy semiconductors may include SiGe, SiGeC, etc. Compound semiconductors may include SiC, group III-V semiconductor materials, or group II-VI semiconductor materials. The semiconductor material may be doped with a first conductivity type dopant or a second conductivity type dopant complementary to the first conductivity type. For example, the first conductivity type may be P-type, and the second conductivity type may be N-type. The element layer may include logic elements.

[0034] The first interconnect structure 110 may include an insulating layer IL1 formed on a first substrate 100 and a wiring layer WL1 formed in the insulating layer IL1. The insulating layer IL1 may contain organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), poly-p-xylylene (also known as Parylene), benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials. The wiring layer WL1 may include conductive materials such as metals or metal alloys. Metals and metal alloys may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0035] Next, an interposer wafer 20 is provided. In this embodiment, the interposer wafer 20 may include an interposer substrate 200 and a passive element IPD1. The interposer substrate 200 may include a front surface and a back surface. The passive element IPD1 may be formed in the interposer substrate 200. The interposer substrate 200 may include any suitable substrate material. The passive element IPD1 may include a capacitor. For example, the passive element IPD1 may be a trench capacitor. In some embodiments, the interposer wafer 20 may not include active elements such as transistors, thus avoiding transistors and the complex circuitry for transistors occupying the area where the passive element IPD1 is formed, thereby increasing the density of the passive element IPD1.

[0036] In this embodiment, the interposer wafer 20 may include an insulating layer IL2f formed on the front surface of the interposer substrate 200. The insulating layer IL2f may comprise organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials.

[0037] Next, referring to Figures 1A and 1B, the interposer wafer 20 is bonded to the logic wafer 10. In this embodiment, the front surface of the interposer substrate 200 faces the logic wafer 10. That is, the insulating layer IL2f of the interposer wafer 20 is bonded to the first interconnect structure 110 of the logic wafer 10. In some embodiments, the interposer wafer 20 can be bonded to the logic wafer 10 by oxide-oxide bonding between the insulating layer IL1 and the insulating layer IL2f of the first interconnect structure 110. Then, a thinning process is performed on the back surface of the interposer substrate 200 so that the thickness of the interposer substrate 202 is less than the thickness of the interposer substrate 200.

[0038] Next, referring to FIG1C, a back-side wiring structure 210 is formed on the back-side surface of the intermediate substrate 202, wherein the back-side wiring structure 210 is electrically connected to the passive element IPD1 and the first interconnect structure 110. In this embodiment, the back-side wiring structure 210 may include an insulating layer IL2b and a wiring layer WL2 formed in the insulating layer IL2b.

[0039] The insulating layer IL2b may contain organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials.

[0040] Wiring layer WL2 may include a conductive via CV1 electrically connected to the passive element IPD1 and a conductive via CV2 electrically connected to the wiring layer WL1 of the first interconnect structure 110. In this embodiment, the conductive via CV2 penetrates the intermediate substrate 202 and includes a portion extending into the first interconnect structure 110. In this embodiment, wiring layer WL2 also includes a conductive layer 212 embedded in an insulating layer IL2b and electrically connected to the conductive vias CV1 and CV2, and a connection pad 214 above the conductive layer 212 and including a surface exposed by the insulating layer IL2b. In some embodiments, the connection pad 214 may be electrically connected to the conductive layer 212. In this embodiment, the conductive via CV1, conductive via CV2, conductive layer 212, and connection pad 214 may each include any suitable conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0041] Next, referring to FIG1D, an image sensing wafer 30 is provided. In this embodiment, the image sensing wafer 30 includes a second substrate 300, an image sensing element PD1, a transfer transistor TX1, a source follower transistor SF1, and a second interconnect structure 310.

[0042] The second substrate 300 may include a pixel region PR1 and a connection region CR1 disposed in a cell region. The second substrate 300 may include any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) and any other type of semiconductor layer and / or epitaxial layer associated therewith. In some embodiments, the second substrate 300 may be doped with a dopant of a first conductivity type or a dopant of a second conductivity type complementary to the first conductivity type. In some embodiments, when the second substrate 300 is doped with a dopant of a first conductivity type (e.g., P-type), the image sensing element PD1 may be doped with a dopant of a second conductivity type (e.g., N-type), but is not limited thereto.

[0043] An image sensing element PD1 may be formed in a pixel region PR1 of a second substrate 300 and may convert radiation (e.g., light) incident on the image sensing element PD1 into an electrical signal. A transfer transistor TX1 and a source follower transistor SF1 may be formed on the pixel region PR1 of the second substrate 300, respectively. In some embodiments, a transfer gate in the transfer transistor TX1 may control the movement of charge carriers between the image sensing element PD1 and a floating diffusion well FD1. In this embodiment, the floating diffusion well FD1 is formed in the second substrate 300 between the transfer transistor TX1 and the source follower transistor SF1. In some embodiments, the image sensing element PD1 and the floating diffusion well FD1 may be disposed on opposite sides of the transfer transistor TX1.

[0044] The second interconnect structure 310 may be formed on the second substrate 300 and electrically connected to the transfer transistor TX1 and the source follower transistor SF1. In some embodiments, the source follower transistor SF1 may be electrically connected to the floating diffusion well FD1 through the second interconnect structure 310. In this embodiment, the second interconnect structure 310 may include an insulating layer IL3 and a wiring layer WL3 formed in the insulating layer IL3.

[0045] The insulating layer IL3 may contain organic or inorganic materials. Organic materials may include, but are not limited to, polyimide (PI), parylene, benzocyclobutene (BCB), epoxy resin, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polymers, or other suitable organic materials. Inorganic materials may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable inorganic materials.

[0046] The wiring layer WL3 may include a conductive layer 312 electrically connected to the transfer transistor TX1 and the source follower transistor SF1, and a connection pad 314 above the conductive layer 312, including a surface exposed by the insulating layer IL3. In some embodiments, the connection pad 314 may be electrically connected to the conductive layer 312. In this embodiment, the conductive layer 312 and the connection pad 314 may each comprise any suitable conductive material such as a metal or metal alloy. The metal and metal alloy may be, for example, Cu, Al, Ti, Ta, W, Pt, Cr, Mo, or alloys thereof.

[0047] Then, referring to Figures 1D and 1E, the image sensing wafer 30 is bonded to the intermediate wafer 20, wherein the second interconnect structure 310 is bonded to the back-side wiring structure 210. In this embodiment, the image sensing wafer 30 can be bonded to the intermediate wafer 20 via hybrid bonding. For example, hybrid bonding may include metal-to-metal bonding (e.g., Cu-Cu bonding) between the connection pads 314 of the second interconnect structure 310 and the connection pads 214 of the back-side wiring structure 210, and oxide-to-oxide bonding between the insulating layer IL3 of the second interconnect structure 310 and the insulating layer IL2b of the back-side wiring structure 210. Then, a thinning process is performed on the back-side surface of the second substrate 300, such that the thickness of the second substrate 302 is less than the thickness of the second substrate 300.

[0048] Then, referring to FIG1F, a passivation layer PV1 is formed on the thinned surface of the second substrate 302. In some embodiments, the material of the passivation layer PV1 is, for example, silicon oxide, a high dielectric constant material such as aluminum oxide, tantalum pentoxide (Ta2O5), zirconium oxide (ZrO), or other suitable materials.

[0049] Subsequently, a color filter CF1 and a microlens ML1 are formed on the pixel area PR1. In this embodiment, the color filter CF1 and the microlens ML1 may cover the pixel area PR1, while the color filter CF1 and the microlens ML1 may not cover the connecting area CR1. The color filter CF1 may be formed of a material that allows radiation (e.g., light) with a specific wavelength range to pass through while blocking light with wavelengths outside the specified range. In some embodiments, the color filter CF1 may be formed of a monomer, polymer, or the like. In some embodiments, the microlens ML1 may be formed by depositing microlens material onto the color filter CF1 (e.g., by spin coating or deposition process). A microlens template (not shown) having a curved upper surface is patterned over the microlens material. The microlens template may include photoresist material exposed using a distributed exposure dose (e.g., for negative photoresist, more light is exposed at the bottom of the curvature and less light is exposed at the top of the curvature), developed, and baked to form a rounded shape. Next, the microlens ML1 is formed by selectively etching the microlens material according to the microlens template.

[0050] Then, a conductive element CE1 is formed in the connection region CR1, wherein the conductive element CE1 includes a conductive pad CP1 embedded in the second substrate 302. In some embodiments, the conductive pad CP1 may be a connection pad used to connect other external components or circuits. In this embodiment, the back-side wiring structure 210 may include a conductive via CV2 penetrating the intermediate substrate 202, and the conductive element CE1 may include a conductive via TSV1 embedded in the second substrate 302 and the second interconnect structure 310. The conductive pad CP1 can be electrically connected to the first interconnect structure 110 through the conductive via TSV1 and the conductive via CV2. That is, other external components or circuits can be connected to the logic wafer 10 through the conductive element CE1, the second interconnect structure 310, and the back-side wiring structure 210. In some embodiments, the logic wafer 10 can control other external components or circuits through the above path. In this embodiment, the second substrate 302 may include a trench TR1 in the connection region CR1 exposing the conductive pad CP1.

[0051] In this embodiment, as shown in FIG1F, the back surface of the interposer substrate 202 (e.g., the surface on which the back side wiring structure 210 is formed) can face the image sensing wafer 30, while the front surface of the interposer substrate 202 (e.g., the surface on which the insulating layer IL2f is formed) can face the logic wafer 10.

[0052] Figures 2A to 2D are schematic cross-sectional views of a method for forming an image sensor according to a second embodiment of the present invention. The method for forming an image sensor shown in Figures 2A to 2D is similar to the method for forming an image sensor shown in Figures 1A to 1F. The main difference is that, in the second embodiment, the intermediate wafer 20a is first bonded to the image sensing wafer 30, and then the structure including the intermediate wafer 20a and the image sensing wafer 30 is bonded to the logic wafer 10a. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0053] Referring to FIG2A, an interposer wafer 20a is provided. In this embodiment, the interposer wafer 20a may include an interposer substrate 200, a passive element IPD1, and a front-side wiring structure 210f. The interposer substrate 200 may include a front-side surface and a back-side surface. The passive element IPD1 may be formed in the interposer substrate 200. The front-side wiring structure 210f may be formed on the front-side surface of the interposer substrate 200. The front-side wiring structure 210f may include an insulating layer IL2f and a wiring layer WL2f formed in the insulating layer IL2f. In this embodiment, the wiring layer WL2f may include a surface exposed by the insulating layer IL2b. In some embodiments, the wiring layer WL2f may be electrically connected to the passive element IPD1.

[0054] An image sensing wafer 30 is provided. In this embodiment, the image sensing wafer 30 includes a second substrate 300, an image sensing element PD1, a transfer transistor TX1, a source follower transistor SF1, and a second interconnect structure 310. The second substrate 300 may include a pixel region PR1 and a connection region CR1 disposed in a cell region. The image sensing element PD1 may be formed in the pixel region PR1. The transfer transistor TX1 and the source follower transistor SF1 may be formed on the pixel region PR1, respectively. The second interconnect structure 310 may be formed on the second substrate 300 and electrically connected to the transfer transistor TX1 and the source follower transistor SF1.

[0055] Next, referring to Figures 2A and 2B, the interposer wafer 20a is bonded to the image sensing wafer 30. In this embodiment, the front surface of the interposer substrate 202 (e.g., the surface on which the front wiring structure 210f is formed) faces the image sensing wafer 30, and the front wiring structure 210f is electrically connected to the second interconnect structure 310. In this embodiment, the interposer wafer 20a can be bonded to the image sensing wafer 30 by a hybrid bonding method. For example, the hybrid bonding may include a metal-metal bond (e.g., Cu-Cu bond) between the wiring layer WL2f of the front wiring structure 210f and the connection pad 314 of the second interconnect structure 310, and an oxide-oxide bond between the insulating layer IL2f of the front wiring structure 210f and the insulating layer IL3 of the second interconnect structure 310. Then, a thinning process is performed on the back surface of the interposer substrate 200 so that the thickness of the interposer substrate 202 is less than the thickness of the interposer substrate 200.

[0056] Next, referring to FIG2B, a back-side wiring structure 210b is formed on the back-side surface of the intermediate substrate 202, wherein the back-side wiring structure 210b is electrically connected to the passive element IPD1. In this embodiment, the back-side wiring structure 210b may include an insulating layer IL2b and a wiring layer WL2b formed in the insulating layer IL2b.

[0057] The wiring layer WL2b may include a conductive via CV1 electrically connected to the passive component IPD1 and a conductive via CV2 electrically connected to the second interconnect structure 310. In this embodiment, the wiring layer WL2b further includes a conductive layer 212 embedded in the insulating layer IL2b and electrically connected to the conductive vias CV1 and CV2, and a connection pad 214 above the conductive layer 212 and including a surface exposed by the insulating layer IL2b. In this embodiment, the conductive via CV2 may penetrate the intermediate substrate 202 and extend into the front wiring structure 210f to contact the wiring layer WL2f. In some embodiments, the connection pad 214 may be electrically connected to the conductive layer 212.

[0058] Next, referring to FIG2C, a logic wafer 10a is provided, wherein the logic wafer 10a includes a first interconnect structure 110a disposed on a first substrate 100. In this embodiment, the first interconnect structure 110a may include an insulating layer IL1 formed on the first substrate 100 and a wiring layer WL1a formed in the insulating layer IL1. In this embodiment, the wiring layer WL1a may include a surface exposed by the insulating layer IL1.

[0059] Then, the logic wafer 10a is bonded to the intermediate wafer 20a, wherein the first interconnect structure 110a is bonded to the back-side wiring structure 210b. In this embodiment, a structure including the intermediate wafer 20a and the image sensing wafer 30 can be bonded to the logic wafer 10a. In this embodiment, the logic wafer 10a can be bonded to the intermediate wafer 20a via hybrid bonding. For example, hybrid bonding may include a metal-metal bond (e.g., Cu-Cu bond) between the wiring layer WL1a of the first interconnect structure 110a and the connection pad 214 of the back-side wiring structure 210b, and an oxide-oxide bond between the insulating layer IL1 of the first interconnect structure 110a and the insulating layer IL2b of the back-side wiring structure 210b.

[0060] Next, referring to Figures 2C and 2D, a thinning process is performed on the back surface of the second substrate 300, such that the thickness of the second substrate 302 is less than the thickness of the second substrate 300. Then, a passivation layer PV1 is formed on the thinned surface of the second substrate 302. Afterwards, a color filter CF1 and a microlens ML1 on the color filter CF1 are formed on the pixel area PR1. In this embodiment, the color filter CF1 and the microlens ML1 may cover the pixel area PR1, while the color filter CF1 and the microlens ML1 may not cover the connection area CR1.

[0061] Then, a conductive element CE1 is formed in the connection region CR1, wherein the conductive element CE1 includes a conductive pad CP1 embedded in the second substrate 302. In this embodiment, the back-side wiring structure 210b may include a conductive via CV2 penetrating the intermediate substrate 202, and the conductive element CE1 may include a conductive via TSV1 embedded in the second substrate 302 and the second interconnect structure 310. The conductive pad CP1 can be electrically connected to the first interconnect structure 110a through the conductive via TSV1 and the conductive via CV2. That is, other external components or circuits can be connected to the logic wafer 10a through the conductive element CE1, the second interconnect structure 310, and the back-side wiring structure 210b. In some embodiments, the logic wafer 10a can control other external components or circuits through the above path. In this embodiment, the second substrate 302 may include a trench TR1 in the connection region CR1 that exposes the conductive pad CP1.

[0062] Figures 3A to 3C are cross-sectional schematic diagrams of passive elements according to different embodiments of the present invention.

[0063] The passive element IPD1 in the intermediate wafers 20 and 20a can be a capacitor. In some embodiments, as shown in FIG3A, the passive element IPD1 can be a trench capacitor formed in a trench of the intermediate substrate 200. For example, the passive element IPD1 may include a lower electrode BE1 formed on the surface of the trench, a dielectric DI1 formed on the lower electrode BE1, and an upper electrode TE1 formed on the dielectric DI1. In other embodiments, as shown in FIG3B, the passive element IPD2 can also be a planar capacitor, which includes a lower electrode BE2, an upper electrode TE2, and a dielectric DI2 formed between the lower electrode BE2 and the upper electrode TE2.

[0064] The lower electrodes BE1 and BE2, and the upper electrodes TE1 and TE2, may each comprise metals such as cobalt, titanium, nickel, tungsten, or molybdenum, or metal nitrides such as titanium nitride (TiN), titanium-silicon nitride (TiSiN), titanium-aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum-silicon nitride (TaSiN), tantalum-aluminum nitride (TaAlN), tungsten nitride (WN), or combinations thereof. The dielectrics DI1 and DI2 may each comprise oxides, nitrides, oxynitrides, or high-k dielectric materials. In some exemplary embodiments, the materials of dielectric DI1 and dielectric DI2 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxide-silicon nitride-silicon oxide (ONO), high dielectric constant materials with a dielectric constant greater than 4, greater than 7, or even greater than 10, or combinations thereof. High dielectric constant materials are, for example, metal oxides. For example, the metal oxide can be a rare earth metal oxide, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), strontium bismuth tantalum oxide (SrBi2Ta2O9, SBT), or combinations thereof.

[0065] In other embodiments, as shown in FIG3C, the passive element IPD3 may also be a stacked structure. For example, the interposer wafer 20b may include an interposer substrate 200b1 and an interposer substrate 200b2, wiring structures 210b1 and 210b2 formed on the interposer substrate 200b1 and the interposer substrate 200b2, respectively, and passive elements IPD3b1 and IPD3b2 formed in the interposer substrate 200b1 and the interposer substrate 200b2, respectively. The wiring structure 210b1 may include an insulating layer IL2f1 formed on the interposer substrate 200b1 and a wiring layer WL2f1 formed in the insulating layer IL2f1. The wiring structure 210b2 may include an insulating layer IL2f2 formed on the interposer substrate 200b2 and a wiring layer WL2f2 formed in the insulating layer IL2f2.

[0066] In this embodiment, wiring structure 210b1 and wiring structure 210b2 can be joined together by a hybrid bonding method. For example, the hybrid bonding may include a metal-metal bond (e.g., Cu-Cu bond) between the wiring layer WL2f1 of wiring structure 210b1 and the wiring layer WL2f2 of wiring structure 210b2, and an oxide-oxide bond between the insulating layer IL2f1 of wiring structure 210b1 and the insulating layer IL2f2 of wiring structure 210b2.

[0067] The image sensor disclosed herein will be illustrated below with reference to FIG2D. It should be noted that although the image sensor shown in FIG2D is formed in the manner described above, it is not limited thereto.

[0068] Referring to Figure 2D, the image sensor includes a logic wafer 10a, an intermediate wafer 20a, an image sensing wafer 30, and a conductive element CE1. The logic wafer 10a includes a first interconnect structure 110a disposed on a first substrate 100. The image sensing wafer 30 is disposed above the logic wafer 10a and includes a second substrate 302, an image sensing element PD1, a transfer transistor TX1, a source follower transistor SF1, and a second interconnect structure 310. The second substrate 302 includes a pixel region PR1 and a connection region CR1 disposed in a cell region. The image sensing element PD1 is disposed in the pixel region PR1. The transfer transistor TX1 and the source follower transistor SF1 are respectively disposed on the pixel region PR1. The second interconnect structure 310 is disposed on the second substrate 302 and electrically connected to the transfer transistor TX1 and the source follower transistor SF1. Intermediate wafer 20a is disposed between image sensing wafer 30 and logic wafer 10a and includes a passive element IPD1 electrically connected to source follower transistor SF1. Conductive element CE1 is disposed in connection region CR1 and includes conductive pad CP1 embedded in second substrate 302.

[0069] In this embodiment, the image sensing wafer 30 may include a color filter CF1 covering the pixel region PR1 and a microlens ML1 on the color filter CF1. In some embodiments, the color filter CF1 and the microlens ML1 may not cover the connection region CR1. In some embodiments, the second substrate 302 includes a trench TR1 in the connection region CR1 that exposes a conductive pad CP1.

[0070] In this embodiment, the intermediate wafer 20a may include an intermediate substrate 202 and a back-side wiring structure 210b. The intermediate substrate 202 may include a front surface and a back surface, and the passive element IPD1 is disposed in the intermediate substrate 202. The back-side wiring structure 210b may be disposed on the back surface and electrically connected to the passive element IPD1 and the first interconnect structure 110a. In this embodiment, the back-side wiring structure 210b may include a conductive via CV2 penetrating the intermediate substrate 202, and the conductive element CE1 may include a conductive via TSV1 buried in the second substrate 302 and the second interconnect structure 310. The conductive pad CP1 may be electrically connected to the first interconnect structure 110a through the conductive via TSV1 and the first conductive via CV2.

[0071] In this embodiment, the front surface of the interposer substrate 202 may face the image sensing wafer 30, and the back surface of the interposer substrate 202 may face the logic wafer 10a. The interposer wafer 20a may include a front wiring structure 210f disposed on the front surface and electrically connected to the second interconnect structure 310. In some embodiments, as shown in FIG1F, the front surface of the interposer substrate 202 may face the logic wafer 10, the back surface of the interposer substrate 202 may face the image sensing wafer 30, and the conductive via CV2 may include a portion extending into the first interconnect structure 110a.

[0072] In this embodiment, the front wiring structure 210f can be connected to the second internal wiring structure 310 by a hybrid connection, and the back wiring structure 210b can be connected to the first internal wiring structure 110a by a hybrid connection.

[0073] Figure 4 is a cross-sectional schematic diagram of an image sensor according to an embodiment of the present invention. The image sensor shown in Figure 4 is similar to the image sensor shown in Figure 2D. The main difference is that the conductive element CE2 and wiring layer WL3' shown in Figure 4 are different from the conductive element CE1 and wiring layer WL3 shown in Figure 2D. Other identical or similar elements are represented by the same or similar element symbols, and will not be described again here.

[0074] Referring to Figure 4, the conductive element CE2 may include a conductive pad CP1 embedded in the second substrate 302. The wiring layer WL3' may include conductive contacts CC1, CC2, CC3, a conductive layer 312, and a connection pad 314. In this embodiment, the floating diffusion well FD1 can be connected to the source follower transistor SF1 through conductive contacts CC1, the first conductive layer 312a in the conductive layer 312, and conductive contacts CC2. In this embodiment, the source of the source follower transistor SF1 can be connected to the intermediate wafer 20a through conductive contacts CC3, the first conductive layer 312a and the second conductive layer 312b in the conductive layer 312, and the connection pad 314, and then connected to the logic wafer 10a through the wiring layer WL2f, the conductive via CV2, the conductive layer 212, and the connection pad 214 in the intermediate wafer 20a.

[0075] In summary, in the image sensor and its formation method described in the above embodiments, the logic wafer, image sensing wafer, and intermediate wafer in the image sensor can be manufactured independently first, and then bonded together by stacking. In this way, the process used to form the intermediate wafer does not affect the image sensing wafer, and the passive components (e.g., capacitors) in the intermediate wafer can be formed into various desired types without considering the components (e.g., image sensing elements) in the image sensing wafer, thereby significantly improving the stability, cost, and performance of the image sensor.

[0076] 10, 10a: Logic wafer 20, 20a, 20b: Intermediate wafers 30: Image Sensing Wafer 100: First base 110, 110a: First internal connection structure 200, 202, 200b1, 200b2: Intermediate Base 210, 210b: Backside wiring structure 210b1, 210b2: Wiring structure 210f: Front wiring structure 212, 312: Conductive layer 214, 314: Connecting pads 300, 302: Second base 310: Second internal connection structure 312a: First conductive layer 312b: Second conductive layer BE1, BE2: Lower electrode CC1, CC2, CC3: Conductive contacts CE1, CE2: Conductive elements CF1: Color Filter CP1: Conductive pad CR1: Connector CV1, CV2, TSV1: Conductive vias DI1, DI2: Dielectrics FD1: Floating Diffusion Well IL1, IL2b, IL2f, IL2f1, IL2f2, IL3: Insulating layer IPD1, IPD2, IPD3, IPD3b1, IPD3b2: Passive components ML1: Microlens PD1: Image Sensing Element PR1: Pixel area PV1: Passivation layer SF1: Source follower transistor TE1, TE2: Upper electrode TR1: Ditch TX1: Transfer transistor WL1, WL1a, WL2, WL2b, WL2f, WL2f1, WL2f2, WL3, WL3': Wiring layers

Claims

1. An image sensor, comprising: A logic wafer, including a first interconnect structure disposed on a first substrate; An image sensing wafer, disposed above the logic wafer, includes: a second substrate including a pixel region and a connection region configured in a cell region; an image sensing element disposed in the pixel region; a transfer transistor and a source follower transistor, respectively disposed on the pixel region; and a second interconnect structure disposed on the second substrate and electrically connected to the transfer transistor and the source follower transistor; and an interposer wafer, disposed between the image sensing wafer and the logic wafer, including: an interposer substrate including a front surface and a back surface opposite to each other in the vertical direction; A passive element disposed in the intermediate substrate and electrically connected to the source follower transistor; and a back-side wiring structure disposed on the back-side surface and electrically connected to the passive element and the first interconnect structure, wherein the back-side wiring structure includes an insulating layer disposed on the back-side surface and a wiring layer disposed in the insulating layer, the wiring layer including a conductive layer disposed in the insulating layer, a first conductive via disposed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the passive element, and a second conductive via disposed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the first interconnect structure; and a conductive element disposed in the connection area and including a conductive pad embedded in the second substrate, wherein the conductive element overlaps with the second conductive via in the vertical direction.

2. The image sensor as claimed in claim 1, wherein the image sensing wafer includes a color filter covering the pixel area and a microlens on the color filter, the color filter and the microlens not covering the connection area.

3. The image sensor as claimed in claim 1, wherein the second substrate includes a trench in the connection region exposing the conductive pad.

4. The image sensor as claimed in claim 1, wherein the conductive element includes a third conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the third conductive via and the second conductive via.

5. The image sensor of claim 4, wherein the front surface of the intermediate substrate faces the logic wafer, the back surface of the intermediate substrate faces the image sensing wafer, and the second conductive via includes a portion extending into the first interconnect structure.

6. The image sensor of claim 4, wherein the front surface of the intermediate substrate faces the image sensing wafer, the back surface of the intermediate substrate faces the logic wafer, and the intermediate wafer includes a front wiring structure disposed on the front surface and electrically connected to the second interconnect structure.

7. The image sensor as claimed in claim 6, wherein the front wiring structure is bonded to the second interconnect structure via a hybrid bond, and the rear wiring structure is bonded to the first interconnect structure via a hybrid bond.

8. A method for forming an image sensor, comprising: A logic wafer is provided, wherein the logic wafer includes a first interconnect structure disposed on a first substrate; An image sensing wafer is provided, wherein the image sensing wafer includes: a second substrate including a pixel region and a connection region disposed in a cell region; an image sensing element formed in the pixel region; a transfer transistor and a source follower transistor respectively formed on the pixel region; and a second interconnect structure formed on the second substrate and electrically connected to the transfer transistor and the source follower transistor; an intermediate wafer is provided, wherein the intermediate wafer includes: an intermediate substrate including a front surface and a back surface opposite to each other in a vertical direction; and a passive element formed in the intermediate substrate; bonding the intermediate wafer to the logic wafer, wherein the front surface of the intermediate substrate faces the logic wafer; forming a back-side wiring structure on the back surface of the intermediate substrate, wherein the back-side wiring structure is electrically connected to the passive element and the first interconnect structure; and bonding the image sensing wafer to the intermediate wafer, wherein the second interconnect structure is bonded to the back-side wiring structure. The back-side wiring structure includes an insulating layer formed on the back-side surface and a wiring layer formed in the insulating layer. The wiring layer includes a conductive layer formed in the insulating layer, a first conductive via formed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the passive element, and a second conductive via formed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the first interconnect structure. The second conductive via is formed in the connection area and overlaps with the conductive element formed in the connection area in the vertical direction.

9. The method as described in claim 8, further comprising: A color filter and a microlens are formed on the pixel area, wherein the color filter and the microlens cover the pixel area, while the color filter and the microlens do not cover the connection area.

10. The method as described in request item 9, wherein: The conductive element includes a conductive pad embedded in the second substrate.

11. The method of claim 10, wherein the second substrate includes a trench in the connection region exposing the conductive pad.

12. The method of claim 10, wherein the conductive element includes a third conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the third conductive via and the second conductive via.

13. The method of claim 12, wherein the back surface of the intermediate substrate faces the image sensing wafer, and the first conductive via includes a portion extending into the first interconnect structure.

14. A method for forming an image sensor, comprising: A logic wafer is provided, wherein the logic wafer includes a first interconnect structure disposed on a first substrate; An image sensing wafer is provided, wherein the image sensing wafer includes: a second substrate including a pixel region and a connection region disposed in a cell region; an image sensing element formed in the pixel region; a transfer transistor and a source follower transistor respectively formed on the pixel region; and a second interconnect structure formed on the second substrate and electrically connected to the transfer transistor and the source follower transistor; an intermediate wafer is provided, wherein the intermediate wafer includes: an intermediate substrate including a front surface and a back surface opposite to each other in a vertical direction; a passive element formed in the intermediate substrate; and a front wiring structure formed on the front surface; the intermediate wafer is bonded to the image sensing wafer, wherein the front surface of the intermediate substrate faces the image sensing wafer, and the front wiring structure is electrically connected to the second interconnect structure; A back-side wiring structure is formed on the back-side surface of the intermediate substrate, wherein the back-side wiring structure is electrically connected to the passive element; and the logic wafer is bonded to the intermediate wafer, wherein the first interconnect structure is bonded to the back-side wiring structure, wherein the back-side wiring structure includes an insulating layer formed on the back-side surface and a wiring layer formed in the insulating layer, the wiring layer including a conductive layer formed in the insulating layer, a first conductive via formed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the passive element, and a second conductive via formed in the insulating layer and passing through the intermediate substrate to electrically connect the conductive layer to the first interconnect structure, the second conductive via being formed in the connection region and overlapping with a conductive element formed in the connection region in the vertical direction.

15. The method as described in claim 14, further comprising: A color filter and a microlens are formed on the pixel area, wherein the color filter and the microlens cover the pixel area, while the color filter and the microlens do not cover the connection area.

16. The method as described in request item 15, wherein: The conductive element includes a conductive pad embedded in the second substrate.

17. The method of claim 16, wherein the second substrate includes a trench in the connection region exposing the conductive pad.

18. The method of claim 16, wherein the conductive element includes a third conductive via embedded in the second substrate and the second interconnect structure, and the conductive pad is electrically connected to the first interconnect structure through the third conductive via and the second conductive via.

19. The method of claim 18, wherein the front wiring structure is coupled to the second interconnect structure via a hybrid bonding method, and the back wiring structure is coupled to the first interconnect structure via a hybrid bonding method.

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