Imprint mold and method for patterning semiconductor substrate using the same

Abstract

An imprinting die is used to pattern a first stamped layer located above a semiconductor substrate. The imprinting die includes a first imprinting unit and a second imprinting unit. The first imprinting unit includes a first imprinted pattern having a first linewidth, used to transfer the first imprinted pattern to a portion of the first stamped layer located above a main region of the semiconductor substrate by a first imprinting step. The second imprinting unit includes a second imprinted pattern having a second linewidth, used to transfer the second imprinted pattern to another portion of the first stamped layer located above an edge region of the semiconductor substrate by a second imprinting step.

Description

Technical Field

[0001] This disclosure relates to a semiconductor manufacturing apparatus and its use, and more particularly to an embossing die for a semiconductor substrate patterning process and a method for patterning semiconductor substrates using the same. Prior Technology

[0002] Nano Imprint Lithograph (NIL) technology is a surface treatment process that transfers the microstructure shape of the surface of an imprinting die onto a stamped layer on a semiconductor substrate (e.g., a semiconductor wafer) to form an imprint texture. Subsequently, the stamped layer with the imprint texture is used as an etching mask to etch the semiconductor substrate, thereby forming an etched feature pattern on the surface of the semiconductor substrate that corresponds to the microstructure shape of the imprinting die.

[0003] However, current nanoimprint lithography techniques typically only pattern the main areas of semiconductor substrates with complete integrated circuit layouts, often neglecting edge areas that lack such layouts. This leads to uneven stress distribution between the edge areas and the main areas in subsequent semiconductor processes (e.g., chemical mechanical polishing) due to the lack of patterned structures in these areas. Consequently, the surface of the semiconductor substrate becomes uneven or even fractured, severely impacting the yield of subsequent processes.

[0004] Therefore, there is a need to provide an advanced embossing mold and a method for patterning semiconductor substrates therewith, in order to solve the problems of the prior art. Summary of the Invention

[0005] One embodiment of this specification discloses an imprinting die for patterning a first stamped layer located above a semiconductor substrate. The imprinting die includes a first imprinting unit and a second imprinting unit. The first imprinting unit includes a first imprinted pattern having a first linewidth, used to transfer the first imprinted pattern to a portion of the first stamped layer located above a main region of the semiconductor substrate via a first imprinting step. The second imprinting unit includes a second imprinted pattern having a second linewidth, used to transfer the second imprinted pattern to another portion of the first stamped layer located above an edge region of the semiconductor substrate via a second imprinting step.

[0006] Another embodiment of this specification discloses a patterning method for a semiconductor substrate, comprising the following steps: First, a semiconductor substrate including a main region and an edge region is provided. A first stamping layer is formed, covering the main region and the edge region. An imprinting die including a first imprinting unit and a second imprinting unit is provided. The first imprinting unit includes a first imprinted pattern having a first linewidth; the second imprinting unit includes a second imprinted pattern having a second linewidth. A first imprinting step is performed to transfer the first imprinted pattern to a portion of the first stamping layer located above the main region. A second imprinting step is performed to transfer the second imprinted pattern to another portion of the first stamping layer located above the edge region. An etching process is performed using the first stamping layer as an etching mask to form a main feature pattern in the main region and a dummy feature pattern in the edge region.

[0007] According to the above embodiments, this specification provides an imprinting mold and a method for patterning a semiconductor substrate using the same. The imprinting mold employs at least two imprinting units with imprinting patterns having different linewidths to pattern a stamping layer located above a semiconductor substrate (e.g., a semiconductor wafer). Subsequently, using the patterned stamping layer as a mask, the semiconductor substrate is etched to form a main feature pattern (e.g., a circuit pattern) on the main area of ​​the semiconductor substrate (e.g., a semiconductor wafer) and a virtual feature pattern (e.g., a virtual circuit pattern) on the edge area of ​​the semiconductor substrate (e.g., a semiconductor wafer). The imprinting unit with a smaller pattern linewidth has a first imprinting pattern corresponding to the main feature pattern. The imprinting unit with a larger pattern linewidth has a second imprinting pattern corresponding to the virtual feature circuit pattern.

[0008] By forming etched feature patterns on both the main and edge regions of a semiconductor substrate (e.g., a semiconductor wafer), the problem of uneven stress distribution on the semiconductor substrate during subsequent integrated circuit fabrication processes can be effectively improved, preventing surface irregularities or fractures in the semiconductor substrate. Furthermore, since the manufacturing cost of imprinting units with larger pattern linewidths is significantly lower than that of imprinting units with smaller pattern linewidths, the yield of integrated circuit fabrication processes can be greatly improved without excessively increasing process costs. Simple Explanation of the Diagram

[0009] To provide a better understanding of the above and other aspects of this specification, specific embodiments are described below in conjunction with the accompanying drawings: Figure 1 is a schematic diagram illustrating, according to an embodiment of this specification, an imprinting die for patterning a first stamping layer located above a semiconductor substrate and the structure of the patterned first stamping layer; Figure 2A is a schematic cross-sectional view of a series of process structures for forming the first imprinting unit of Figure 1, according to an embodiment of this specification. Figure 2B is a schematic cross-sectional view of a series of process structures for forming the second imprinting unit of Figure 1, according to an embodiment of this specification. Figures 3A and 3B are schematic diagrams illustrating a process structure for forming a mask pattern on a first stamping layer above a semiconductor substrate by performing multiple first stamping steps and multiple second stamping steps using a first stamping unit and a second stamping unit, respectively; and Figure 4 is a cross-sectional view illustrating a process step of patterning a semiconductor substrate using a first stamping layer as a mask, according to an embodiment of this specification. Implementation

[0010] This specification provides an embossing mold and a method for patterning semiconductor substrates using the same. This effectively improves the problem of uneven stress distribution on semiconductor substrates during integrated circuit manufacturing without excessively increasing process costs, preventing surface unevenness or breakage of the semiconductor substrate, and significantly improving the yield of integrated circuit manufacturing processes. To make the above-described embodiments and other objects, features, and advantages of this specification more apparent and understandable, several embodiments are described below in detail with reference to the accompanying drawings.

[0011] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0012] Please refer to Figure 1, which is a schematic diagram illustrating an imprinting die 100 for patterning a first stamping layer 102 located above a semiconductor substrate 101, and the structure of the patterned first stamping layer 102 (including the semiconductor substrate 101), according to an embodiment of this specification. The imprinting die 100 includes a first imprinting unit 100A and a second imprinting unit 100B. The first imprinting unit 100A includes a first imprinted pattern 100AP having a first linewidth W1, and the second imprinting unit 100B includes a second imprinted pattern 100BP having a second linewidth W2.

[0013] The first imprinting unit 100A is used to transfer the first imprinted pattern 100AP to a portion of the first stamping layer 102 located above the main region 101M of the semiconductor substrate 101 through a first imprinting step (detailed below), thereby forming a first mask pattern unit 102AM. The second imprinting unit 100B is used to transfer the second imprinted pattern 100BP to another portion of the first stamping layer 102 located above the edge region 101P of the semiconductor substrate 101 through a second imprinting step (detailed below), thereby forming a second mask pattern unit 102BM. The mask pattern 102M is then composed of multiple first mask pattern units 102AM and multiple second mask pattern units 102BM.

[0014] In some embodiments of this specification, the first embossing unit 100A of the embossing mold 100 may be a resin template with a first embossing pattern 100AP on its surface. The plasticizing material constituting the first embossing unit 100A may be, for example, polycarbonate (PC), polyethylene (PE), poly(methyl methacrylate), PMMA, polyolefin (PO), or any combination thereof.

[0015] The second embossing unit 100B can be a resin template with a second embossed pattern 100BP on its surface. The material constituting the second embossing unit 100B can be the same as or different from the material constituting the first embossing unit 100A. However, it is worth noting that the materials constituting the first embossing unit 100A and the second embossing unit 100B are not limited to this. Any material capable of forming a three-dimensional embossed pattern on its surface can be used to manufacture the first embossing unit 100A and the second embossing unit 100B.

[0016] The method for fabricating the embossing mold 100 includes forming a first embossing unit 100A and a second embossing unit 100B respectively using similar steps. Figure 2A is a schematic cross-sectional view of a series of process structures for forming the first embossing unit 100A according to an embodiment of this specification. Figure 2B is a schematic cross-sectional view of a series of process structures for forming the second embossing unit 100B according to an embodiment of this specification. The order in which the first embossing unit 100A and the second embossing unit 100B are formed is not limited, and the following fabrication process is for illustrative purposes only and is not intended to limit the embodiments of this specification.

[0017] First, as shown in Figure 2A, a first mold substrate (master) 201 is provided. In some embodiments of this specification, the first mold substrate 201 may be a crystal or sapphire substrate. Next, a patterned photoresist layer 202 is formed on the surface 201S of the first mold substrate 201, and then at least one first substrate pattern 201P is formed on the surface 201S of the first mold substrate 201 by an etching process 203.

[0018] Next, using the patterned first mold substrate 201 as a mold, a stamping step 204 is performed on the second stamping layer 205 to transfer the first base pattern 201P to the second stamping layer 205 (that is, a patterned second stamping layer 205 is formed on the surface 100AS of the resin template of the first imprinting unit 100A). For example, in this embodiment, the stamping step 204 includes making the surface 201S of the first mold substrate 201 face the upper surface 205S of the second stamping layer 205, and applying a mechanical stress to press the second stamping layer 205, thereby forming a stamping pattern 205P corresponding to the first base pattern 201P in the second stamping layer 205.

[0019] Subsequently, the second stamping layer 205, which is patterned (with stamping pattern 205P), is used as an etching mask to perform an etching process 206 on the resin template of the first imprinting unit 100A, so as to form a first imprinting pattern 100AP corresponding to the first substrate pattern 201P on the first surface 100AS of the resin template of the first imprinting unit 100A.

[0020] As shown in Figure 2B, the formation of the second imprinting unit 100B includes the following steps: first, a second mold substrate 211 is provided, and a patterned photoresist layer 212 is formed on the surface 211S of the second mold substrate 211. Then, at least one second substrate pattern 211P is formed on the surface 201S of the second mold substrate 211 by an etching process 213.

[0021] Next, using the patterned second mold substrate 211 as a mold, a stamping step 214 is performed on the second stamping layer 205 to transfer the second base pattern 211P to the third stamping layer 215 (that is, a patterned third stamping layer 215 is formed on the surface 100BS of the resin template of the second imprinting unit 100B). For example, in this embodiment, the stamping step 214 includes making the surface 211S of the second mold substrate 211 face the surface 215S of the third stamping layer 215, and simultaneously applying a mechanical stress to press the third stamping layer 215, thereby forming a stamping pattern 215P corresponding to the second base pattern 211P in the third stamping layer 215.

[0022] Subsequently, the patterned (with stamped pattern 215P) third stamping layer 215 is used as an etching mask to perform an etching process 216 on the resin template of the second imprinting unit 100B, so as to form a second imprinting pattern 100BP on the second surface 100BS of the resin template of the second imprinting unit 100B.

[0023] In this embodiment, the first imprinted pattern 100AP of the first imprinting unit 100A has a smaller first linewidth W1; the second imprinted pattern 100BP of the second imprinting unit 100B has a larger second linewidth W2. The second linewidth W2 is preferably 10 to 50 times the first linewidth W1. For example, in some embodiments of this specification, the first linewidth W1 is substantially between 10 nanometers (nm) and 200 nanometers, for example, about 100 nanometers; the second linewidth W2 is substantially between 150 micrometers (µm) and 1000 nanometers, for example, about 200 nanometers.

[0024] Furthermore, the first embossed pattern 100AP and the second embossed pattern 100BP preferably (but not limited to) have the same pattern thickness H. In other words, the cost required to manufacture the second embossed unit 100B with a larger second line width W2 under the same conditions will be much lower than the cost of manufacturing the first embossed unit 100A with a smaller first line width W1.

[0025] Please refer to Figures 3A and 3B, which are schematic diagrams illustrating a process structure in which a first mask pattern unit 102AM is formed on a first stamping layer 102 above a semiconductor substrate 101 by performing multiple first stamping steps and multiple second stamping steps using a first stamping unit 100A and a second stamping unit 100B, respectively. The first and second stamping steps shown in Figures 3A and 3B are not sequentially restricted.

[0026] In some embodiments of this specification, a first imprinting unit 100A may be used as a mold to perform a stamping step 301 on the first stamping layer 102 located above the semiconductor substrate 101. For example, in this embodiment, the stamping step 301 includes making the first imprinting pattern 100AP of the first imprinting unit 100A face a portion of the first stamping layer 102 located above the main region 101M of the semiconductor substrate 101, and applying a mechanical stress to press the first stamping layer 102, thereby forming a first mask pattern unit 102AM corresponding to the first imprinting pattern 100AP on the upper surface 102S of the first stamping layer 102.

[0027] By repeating the stamping step 301 multiple times, a plurality of first mask pattern units 102AM can be formed in other portions (positions) of the first stamping layer 102 above the main region 101M of the semiconductor substrate 101. In some other embodiments of this specification, a plurality of first imprinting units 100A can be used to form a stamping die in a specific arrangement, and stamping steps can be performed on different portions (positions) of the first stamping layer 102 above the main region 101M of the semiconductor substrate 101 to form a plurality of first mask pattern units 102AM.

[0028] Subsequently, a second imprinting unit 100B is used as a mold to perform a stamping step 302 on the first stamped layer 102 located above the semiconductor substrate 101. For example, in this embodiment, the stamping step 302 includes making the second imprinted pattern 100BP of the second imprinting unit 100B face a portion of the first stamped layer 102 located above the edge region 101P of the semiconductor substrate 101, and applying a mechanical stress to press the first stamped layer 102, thereby forming a second mask pattern unit 102BM corresponding to the second imprinted pattern 100BP on the upper surface 102S of the first stamped layer 102. In some embodiments of this specification, during the stamping step 302, the edge of the second imprinting unit 100B extends beyond the substrate edge 101G of the semiconductor substrate 101.

[0029] By repeating the stamping step 302 multiple times, a plurality of second mask pattern units 102BM can be formed in other portions (positions) of the first stamping layer 102 above the edge region 101P of the semiconductor substrate 101. In some other embodiments of this specification, a plurality of second imprinting units 100B can be used to form a stamping die in a specific arrangement, and stamping steps can be performed on different portions (positions) of the first stamping layer 102 above the edge region 101P of the semiconductor substrate 101 to form a plurality of second mask pattern units 102BM. The plurality of first mask pattern units 102AM and the plurality of second mask pattern units 102BM can form a mask pattern 102M in the first stamping layer 102.

[0030] Subsequently, the semiconductor substrate 101 is patterned using the first stamped layer 102 with the mask pattern 102M as the mask. For example, please refer to Figure 4, which is a cross-sectional view illustrating the process steps of etching process 401 on the semiconductor substrate 101 using the first stamped layer 102 with the mask pattern 102M as the etching mask according to an embodiment of this specification. In this embodiment, the etching process 401 forms a circuit pattern 101EP in the main region 101M of the semiconductor substrate 101 and a virtual feature pattern (e.g., a virtual circuit pattern 101DP) in the edge region 101P of the semiconductor substrate 101. Among them, at least a portion of the circuit pattern 101EP corresponds to the first imprinted pattern 100AP of the first imprinting unit 100A; at least a portion of the virtual circuit pattern 101DP corresponds to the second imprinted pattern 100BP of the second imprinting unit 100B.

[0031] According to the above embodiments, this specification provides an imprinting mold 100 and a method for patterning a semiconductor substrate 101 therewith. The imprinting mold 100 employs at least two imprinting units (e.g., first imprinting unit 100A and second imprinting unit 100B) with imprinting patterns (e.g., first imprinting pattern 100AP and second imprinting pattern 100BP) having different linewidths W1 and W2, respectively, to pattern a first stamping layer 102 located above a semiconductor substrate (e.g., a semiconductor wafer) 101. Subsequently, using the patterned first stamping layer 102 as a mask, an etching process 401 is performed on the semiconductor substrate (e.g., a semiconductor wafer) 101 to form a main feature pattern (e.g., a circuit pattern 101EP) on the main region 101M of the semiconductor substrate (e.g., a semiconductor wafer) 101, and a virtual feature pattern (e.g., a virtual circuit pattern 101DP) on the edge region 101P of the semiconductor substrate (e.g., a semiconductor wafer) 101. The imprinting unit 100A, which has a smaller pattern linewidth W1, has a first imprinted pattern 100AP corresponding to the circuit pattern 101EP. The imprinting unit 100B, which has a larger pattern linewidth W2, has a second imprinted pattern 100BP corresponding to the virtual circuit pattern 100DP.

[0032] By forming etched feature patterns on both the main region 101M and the edge region 101P of the semiconductor substrate (e.g., semiconductor wafer) 101, the problem of uneven stress distribution on the semiconductor substrate 101 during integrated circuit manufacturing can be effectively improved, preventing surface unevenness or breakage of the semiconductor substrate 101. Furthermore, since the manufacturing cost of the imprinting unit 100B with a larger pattern linewidth W2 is much lower than that of the imprinting unit 100A with a smaller pattern linewidth W2, the yield of integrated circuit manufacturing can be significantly improved without excessively increasing process costs.

[0033] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0034] 100: Imprinting mold 100A: First Imprinting Unit 100B: Second Imprinting Unit 100AP: First embossed pattern 100AS: Surface 100BP: Second embossed pattern 100BS: Surface 101: Semiconductor substrate 101G: Substrate Edge 101P: Edge region 101M: Main Area 101EP: Circuit Pattern 100DP: Virtual Circuit Pattern 102: First stamping layer 102AM: First Cover Pattern Unit 102BM: Second Cover Pattern Unit 102M: Curtain Pattern 102S: Upper surface 201: First mold substrate 201S: Surface 201P: First Base Pattern 204: Stamping Steps 205: Second stamping layer 205S: Top surface 205P: Stamped Pattern 206: Etching Process 211: Second mold substrate 211S: Surface 211P: Second base pattern 214: Stamping Steps 215: Third stamping layer 215S: Surface 216: Etching Process 215P: Stamped Pattern 301: Stamping Steps 302: Stamping Steps 401: Etching process H: Thickness W1: Line width W2: Line width

Claims

1. An imprinting die for patterning a first stamped layer located above a semiconductor substrate, the imprinting die comprising: a first imprinting unit including a first imprinting pattern having a first linewidth, for transferring the first imprinting pattern onto a portion of the first stamped layer located in a major region of the semiconductor substrate by a first imprinting step; and a second imprinting unit including a second imprinting pattern having a second linewidth, for transferring the second imprinting pattern onto another portion of the first stamped layer located in an edge region of the semiconductor substrate by a second imprinting step.

2. The embossing die as described in claim 1, wherein the second line width is substantially 10 to 50 times the first line width.

3. The imprinting mold as claimed in claim 1, wherein in the second imprinting step, the second imprinting unit extends beyond a substrate edge of the semiconductor substrate.

4. The embossing mold as claimed in claim 1, wherein the first embossing pattern corresponds to a major feature pattern formed on the semiconductor substrate; and the second embossing pattern includes a dummy feature pattern corresponding to a dummy feature pattern formed on the semiconductor substrate.

5. The embossing mold as claimed in claim 1, wherein the first embossed pattern and the second embossed pattern have the same pattern thickness.

6. A method for patterning a semiconductor substrate, comprising: providing a semiconductor substrate including a main region and an edge region; forming a first stamping layer covering the main region and the edge region; providing an imprinting die, comprising: a first imprinting unit including a first imprinting pattern having a first linewidth; and a second imprinting unit including a second imprinting pattern having a second linewidth; performing a first stamping step to transfer the first imprinting pattern to a portion of the first stamping layer located above the main region; performing a second stamping step to transfer the second imprinting pattern to another portion of the first stamping layer located above the edge region; and performing an etching process using the first stamping layer as an etching mask to form a main feature pattern in the main region and a virtual feature pattern in the edge region.

7. The method for patterning a semiconductor substrate as described in claim 6, wherein the second linewidth is substantially 10 to 50 times the first linewidth.

8. The method for patterning a semiconductor substrate as described in claim 6, wherein, during the second stamping step, the second imprinting unit extends beyond a substrate edge of the semiconductor substrate.

9. A method for patterning a semiconductor substrate as described in claim 6, wherein the first imprinted pattern and the second imprinted pattern have the same pattern thickness.

10. A method for patterning a semiconductor substrate as described in claim 6, wherein the step of providing the imprinting mold comprises: etching a first master substrate to form at least one first substrate pattern on a surface of the first master substrate; forming a second stamping layer on a first surface of the first imprinting unit; performing a third stamping step on the second stamping layer with the first master substrate to transfer the first substrate pattern to the second stamping layer; performing an etching process on the first imprinting unit using the second stamping layer as an etching mask to form the first imprinting pattern on the first surface; etching a second master substrate to form at least one second substrate pattern on a surface of the second master substrate; forming a third stamping layer on a second surface of the second imprinting unit; performing a fourth stamping step on the third stamping layer with the second master substrate to transfer the second substrate pattern to the third stamping layer; and performing an etching process on the second imprinting unit using the third stamping layer as an etching mask to form the second imprinting pattern on the second surface.

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