Engineered substrate structure for power and RF applications

Abstract

A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a second adhesive layer coupled to the conductive layer; and a barrier layer coupled to the second adhesive layer. The substrate further includes a silicon oxide layer coupled to the support structure, a substantially monocrystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially monocrystalline silicon layer.

Description

Technical Field

[0001] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 350,084, filed June 14, 2016, entitled "Engineering Substrate Structure for Power and RF Applications," and U.S. Provisional Patent Application No. 62 / 350,077, filed June 14, 2016, entitled "Engineering Substrate Structure and Method of Manufacturing of the Same," the disclosures of which are incorporated herein by reference in their entirety for all purposes.

[0002] This invention generally relates to engineering substrate structures. More specifically, this invention relates to methods and systems suitable for epitaxial growth processes. Prior Technology

[0003] Light-emitting diodes (LEDs) are typically epitaxially grown on a sapphire substrate. Currently, many products use LED components, including lighting, computer monitors, and other display devices.

[0004] Growing gallium nitride (GaN) LED structures on sapphire substrates is a heteroepitaxial growth process, as the substrate and epitaxial layer are composed of different materials. Due to the heteroepitaxial growth process, the epitaxial growth material exhibits various adverse effects, including reduced uniformity and decreased metrics related to the electronic / optical properties of the epitaxial layer. Therefore, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures. Summary of the Invention

[0005] This invention generally relates to engineered substrate structures. More specifically, it relates to methods and systems suitable for epitaxial growth processes. By way of example only, this invention has been applied to methods and systems for providing substrate structures suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) substantially matching that of the epitaxial layer grown thereon. These methods and techniques can be applied to a wide variety of semiconductor processing operations.

[0006] According to one embodiment of the present invention, a substrate is provided. The substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a second adhesive layer coupled to the conductive layer; and a barrier layer coupled to the second adhesive layer. The substrate further includes a silicon oxide layer coupled to the support structure, a substantially monocrystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially monocrystalline silicon layer.

[0007] According to another embodiment of the present invention, a method for manufacturing a substrate is provided. The method includes forming a support structure by means of the following steps: providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesive shell; encapsulating the first adhesive shell in a conductive shell; encapsulating the conductive shell in a second adhesive shell; and encapsulating the second adhesive shell in a barrier shell. The method further includes bonding a bonding layer to the support structure, bonding a substantial single-crystal silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantial single-crystal silicon layer, and forming an epitaxial III-V layer by epitaxial growth on the epitaxial silicon layer.

[0008] According to one specific embodiment of the present invention, an engineering substrate structure is provided. The engineering substrate structure includes a support structure, a bonding layer coupled to the support structure, a solid monocrystalline silicon layer coupled to the bonding layer, and an epitaxial monocrystalline silicon layer coupled to the solid monocrystalline silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a barrier shell coupled to the second adhesive layer.

[0009] This invention achieves numerous advantages over conventional technologies. For example, embodiments of the invention provide an engineered substrate structure that matches gallium nitride (CTE) epitaxial layers suitable for optical, electronic, and optoelectronic applications. An encapsulation layer, which forms part of the engineered substrate structure, prevents impurities present in the central portion of the substrate from diffusing into the semiconductor processing environment using the engineered substrate. Key properties associated with the substrate material, including coefficient of thermal expansion, lattice mismatch, thermal stability, and shape control, are independently designed to improve (e.g., optimize) the matching with gallium nitride epitaxial and device layers, as well as with different device architectures and performance targets. Because the substrate material layers are integrated together in conventional semiconductor manufacturing processes, process integration is simplified. These and other embodiments of the invention, along with their many advantages and features, will be described in more detail below and with reference to the accompanying drawings. Simple Explanation of the Diagram

[0010] Figure 1 is a simplified schematic diagram illustrating an engineering substrate structure according to one embodiment of the present invention.

[0011] Figure 2A shows the SIMS curve of species concentration as a function of depth for an engineering structure according to one embodiment of the present invention.

[0012] Figure 2B shows the SIMS curve of species concentration as a function of depth for an engineered structure according to one embodiment of the present invention after annealing.

[0013] Figure 2C shows the SIMS curve of species concentration as a function of depth for an engineered structure with a silicon nitride layer after annealing, according to one embodiment of the present invention.

[0014] Figure 3 is a simplified schematic diagram illustrating an engineering substrate structure according to another embodiment of the present invention.

[0015] Figure 4 is a simplified schematic diagram illustrating an engineering substrate structure according to yet another embodiment of the present invention.

[0016] Figure 5 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to one embodiment of the present invention.

[0017] Figure 6 is a simplified schematic diagram illustrating an epitaxial / engineered substrate structure for RF and power applications according to one embodiment of the present invention.

[0018] Figure 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineering substrate structure according to one embodiment of the present invention.

[0019] Figure 8 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to another embodiment of the present invention. Implementation

[0020] The embodiments of this invention relate to engineered substrate structures. More specifically, the invention relates to methods and systems suitable for epitaxial growth processes. By way of example only, the invention has been applied to methods and systems for providing substrate structures suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) substantially matching that of the epitaxial layer grown thereon. These methods and techniques can be applied to a wide variety of semiconductor processing operations.

[0021] Figure 1 is a simplified schematic diagram illustrating an engineering substrate structure according to one embodiment of the present invention. The engineering substrate 100 illustrated in Figure 1 is suitable for a wide variety of electronic and optical applications. The engineering substrate includes a core 110, which may have a CTE substantially matching the coefficient of thermal expansion (CTE) of the epitaxial material to be grown on the engineering substrate 100. The epitaxial material 130 is illustrated as optional because it is not required as a component of the engineering substrate, but it is typically grown on the engineering substrate.

[0022] For applications involving the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), which may include bonding materials such as yttrium oxide. Other materials may be used for core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), and the like.

[0023] The core thickness can be in the range of 100 μm to 1,500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which may be referred to as a shell or encapsulation shell. In one embodiment, the first adhesive layer 112 comprises a layer of tetraethyl orthosilicate (TEOS) with a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesive layer in some embodiments, according to one embodiment of the invention, other materials may be used to provide adhesion between subsequent deposited layers and underlying layers or materials (e.g., ceramics, particularly polycrystalline ceramics). For example, SiO2 or other silicon oxides (SixOy) adhere well to ceramic materials and provide a suitable surface for subsequent deposition (e.g., conductive materials). In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first adhesive layer 112 may be formed using an LPCVD process. The first adhesive layer 112 provides a surface on which subsequent layers are adhered to form elements of an engineered substrate structure.

[0024] In addition to using LPCVD processes, furnace-based processes, etc., to form the encapsulating first adhesive layer, embodiments of the present invention can use other semiconductor processes, including CVD processes or similar deposition processes. As examples, a deposition process can be used to coat a portion of the core, the core can be flipped, and the deposition process can be repeated to coat other portions of the core. Therefore, although LPCVD technology is used in some embodiments to provide a fully encapsulated structure, other film formation techniques can be used depending on the specific application.

[0025] A conductive layer 114 is formed surrounding the first adhesive layer 112. In one embodiment, the conductive layer 114 is a polycrystalline silicon shell formed around the first adhesive layer 112, because polycrystalline silicon exhibits poor adhesion to ceramic materials. In embodiments where the conductive layer is polycrystalline silicon, the thickness of the polycrystalline silicon layer can be on the order of 500-5,000 Å, for example, 2,500 Å. In some embodiments, the polycrystalline silicon layer can be formed as a shell completely surrounding the first adhesive layer 112 (e.g., a TEOS layer), thereby forming a fully encapsulated first adhesive layer, and can be formed using an LPCVD process. In other embodiments, as discussed below, a conductive material can be formed on a portion of the adhesive layer, for example, on the lower half of the substrate structure. In some embodiments, the conductive material can be formed as a fully encapsulated layer, and the conductive material on one side of the substrate structure can be subsequently removed.

[0026] In one embodiment, the conductive layer 114 may be a polycrystalline silicon layer doped to provide a highly conductive material, such as boron doping to provide a p-type polycrystalline silicon layer. In some embodiments, boron doping is performed at a concentration of 1 × 10¹⁹ cm⁻³ to 1 × 10²⁰ cm⁻³ to provide high conductivity. Other dopants with different dopant concentrations (e.g., phosphorus, arsenic, bismuth, etc., with dopant concentrations ranging from 1 × 10¹⁶ cm⁻³ to 5 × 10¹⁸ cm⁻³) can be used to provide n-type or p-type semiconductor materials suitable for the conductive layer. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0027] The presence of conductive layer 114 is useful during the process of electrostatically clamping an engineering substrate to a semiconductor processing tool (e.g., a tool with an electrostatic chuck (ESC)). After processing in the semiconductor processing tool, conductive layer 114 can be quickly released from clamping. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner commonly used for silicon wafers. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0028] A second adhesive layer 116 (e.g., a TEOS layer with a thickness on the order of 1000 Å) is formed to surround the conductive layer 114. In some embodiments, the second adhesive layer 116 completely surrounds the conductive layer 114 to form a fully encapsulated structure, and can be formed using LPCVD, CVD, or any other suitable deposition process, including the deposition of spin-coated dielectrics.

[0029] A barrier layer 118, such as a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer 118 with a thickness on the order of 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 116 to form a fully encapsulated structure and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials (including SiCN, SiON, AlN, SiC, etc.) can be used as the barrier layer. In some embodiments, the barrier layer 118 comprises several sublayers constructed to form the barrier layer. Therefore, the term barrier layer is not intended to refer to a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0030] In some embodiments, the barrier layer 118 (e.g., a silicon nitride layer) prevents elements present within the core 110 (e.g., yttrium oxide, oxygen, metallic impurities, other trace elements, etc.) from diffusing and / or escaping into the environment of a semiconductor processing chamber where an engineered substrate may be present, such as during high-temperature (e.g., 1,000 °C) epitaxial growth processes. Using the encapsulation layers described herein, ceramic materials, including polycrystalline AlN designed for non-cleanroom environments, can be used in semiconductor process flows and cleanroom environments.

[0031] Figure 2A shows a secondary ion mass spectrometry (SIMS) curve of the species concentration as a function of depth for an engineered structure according to one embodiment of the present invention. This engineered structure does not include the barrier layer 118. Referring to Figure 2A, several species present in the ceramic core (e.g., yttrium, calcium, and aluminum) are reduced to negligible concentrations in engineered layers 120 / 122. The concentrations of calcium, yttrium, and aluminum decrease by three, four, and six orders of magnitude, respectively.

[0032] Figure 2B illustrates the SIMS curve of species concentration as a function of depth for an engineered structure without a barrier layer according to one embodiment of the present invention after annealing. As discussed above, during semiconductor processing operations, such as during the epitaxial growth of GaN series layers, the engineered substrate structure provided by the embodiments of the present invention can be exposed to high temperatures (~1,100 °C) for several hours.

[0033] For the curves shown in Figure 2B, the engineered substrate structure was annealed at 1,100 °C for 4 hours. As shown in Figure 2B, calcium, yttrium, and aluminum, which were originally present in low concentrations in the freshly deposited, untreated sample, have diffused into the engineered layer to reach concentrations similar to those of the other elements.

[0034] Figure 2C illustrates the SIMS curve of species concentration as a function of depth in an engineered structure with a barrier layer according to one embodiment of the present invention after annealing. Integrating a diffusion barrier layer 118 (e.g., a silicon nitride layer) into the engineered substrate structure prevents calcium, yttrium, and aluminum from diffusing into the engineered layer during the annealing process, which would occur in the absence of the diffusion barrier layer. As illustrated in Figure 2C, after annealing, calcium, yttrium, and aluminum present in the ceramic core remain at low concentrations in the engineered layer. Therefore, using the barrier layer 118 (e.g., a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier layer, thereby preventing their release into the environment surrounding the engineered substrate. Similarly, any other impurities contained in the bulk ceramic material will also be contained by the barrier layer.

[0035] Typically, the ceramic material used to form the core 110 is calcined at temperatures in the range of 1800 °C. This process is expected to remove a large number of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds generated due to the use of yttrium oxide as a sintering agent. Subsequently, during epitaxial growth processes at much lower temperatures in the range of 800 °C to 1100 °C, the subsequent diffusion of these impurities is expected to be negligible. However, contrary to conventional expectations, the inventors have determined that even during epitaxial growth processes at temperatures much lower than the calcination temperature of the ceramic material, a large amount of elemental diffusion occurs through the layers of the engineered substrate. Therefore, embodiments of the present invention integrate a barrier layer 118 (e.g., a silicon nitride layer) to prevent background elements from diffusing outward from the polycrystalline ceramic material (e.g., AlN) into the engineered layers 120 / 122 and the epitaxial layers (e.g., optional GaN layer 130). The silicon nitride layer 118 encapsulating the underlying layers and material provides the desired barrier layer function.

[0036] As illustrated in Figure 2B, elements (including yttrium) originally present in the core 110 diffuse into and through the first TEOS layer 112, the polycrystalline silicon layer 114, and the second TEOS layer 116. However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing these elements from being released into the environment surrounding the engineered substrate, as illustrated in Figure 2C.

[0037] Referring again to Figure 1, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118 (e.g., the top surface of the barrier layer), and the bonding layer 120 is subsequently used in the bonding process of the substantially monocrystalline silicon layer 122. In some embodiments, the thickness of the bonding layer 120 may be about 1.5 μm.

[0038] The substantial single-crystal layer 122 is suitable for use as a growth layer during the epitaxial growth process to form the epitaxial material 130. In some embodiments, the epitaxial material 130 includes a GaN layer with a thickness of 2 μm to 10 μm, which can be used as one of a plurality of layers for use in optoelectronic devices, RF devices, power devices, etc. In one embodiment, the substantial single-crystal layer 122 includes a substantial single-crystal silicon layer attached to the silicon oxide layer 118 using a layer transfer process.

[0039] Figure 3 is a simplified schematic diagram illustrating an engineering substrate structure according to one embodiment of the present invention. The engineering substrate 300 illustrated in Figure 3 is suitable for a wide variety of electronic and optical applications. The engineering substrate includes a core 110, which may have a CTE substantially matching the coefficient of thermal expansion (CTE) of the epitaxial material 130 to be grown on the engineering substrate 300. The epitaxial material 130 is illustrated as optional because it is not required as a component of the engineering substrate, but it is typically grown on the engineering substrate.

[0040] For applications involving the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), the core 110 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core can be in the range of 100 μm to 1,500 μm, for example, 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which can be referred to as a shell or encapsulation shell. In this embodiment, the first adhesive layer 112 completely encapsulates the core, but this is not required by the present invention, as discussed in more detail with respect to Figure 4.

[0041] In one embodiment, the first adhesive layer 112 comprises a tetraethyl orthosilicate (TEOS) layer with a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesive layer in some embodiments, according to one embodiment of the invention, other materials can be used to provide adhesion between subsequent deposited layers and underlying layers or materials. For example, SiO2, SiON, and the like adhere well to ceramic materials and provide suitable surfaces for subsequent deposition (e.g., conductive materials). In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first adhesive layer 112 can be formed using an LPCVD process. The adhesive layer provides a surface on which subsequent layers are adhered to form elements of an engineered substrate structure.

[0042] In addition to using LPCVD processes, furnace-based processes, etc., to form the encapsulating adhesive layer, other semiconductor processes can be used according to embodiments of the present invention. As an example, a deposition process (e.g., CVD, PECVD, or similar process) can be used to coat a portion of the core, the core can be flipped, and the deposition process can be repeated to coat other portions of the core.

[0043] A conductive layer 314 is formed on at least a portion of the first adhesive layer 112. In one embodiment, the conductive layer 314 comprises polycrystalline silicon (i.e., polycrystalline silicon) formed by a deposition process on a lower portion (e.g., the lower half or back side) of the core / adhesive layer structure. In embodiments where the conductive layer is polycrystalline silicon, the thickness of the polycrystalline silicon layer can be on the order of several thousand angstroms, for example, 3,000 Å. In some embodiments, the polycrystalline silicon layer can be formed using an LPCVD process.

[0044] In one embodiment, the conductive layer 314 may be a polycrystalline silicon layer doped to provide a highly conductive material; for example, the conductive layer 314 may be doped with boron to provide a p-type polycrystalline silicon layer. In some embodiments, boron doping is used in amounts ranging from about 1 × 10¹⁹ cm⁻³ to 1 × 10²⁰ cm⁻³ to provide high conductivity. The presence of the conductive layer is useful during the electrostatic clamping of the engineered substrate to a semiconductor processing tool (e.g., a tool with an electrostatic chuck (ESC)). The conductive layer 314 can be quickly released from clamping after processing. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner consistent with conventional silicon wafers. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0045] A second adhesive layer 316 (e.g., a second TEOS layer) is formed to surround the conductive layer 314 (e.g., a polycrystalline silicon layer). The thickness of the second adhesive layer 316 is on the order of 1,000 Å. In some embodiments, the second adhesive layer 316 may completely surround the conductive layer 314 and the first adhesive layer 112 to form a fully encapsulated structure, and may be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314, for example terminating at the location illustrated in plane 317, which may be aligned with the top surface of the conductive layer 314. In this example, the top surface of the conductive layer 314 will contact a portion of the barrier layer 118. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0046] A barrier layer 118 (e.g., a silicon nitride layer) is formed surrounding the second adhesive layer 316. In some embodiments, the thickness of the barrier layer 118 is on the order of 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesive layer 316 to form a fully encapsulated structure, and can be formed using an LPCVD process.

[0047] In some embodiments, a silicon nitride barrier layer is used to prevent the diffusion and / or escaping of elements present within the core 110 (e.g., yttrium oxide, oxygen, metallic impurities, other trace elements, etc.) into the environment of a semiconductor processing chamber where an engineered substrate may be present, such as during high-temperature (e.g., 1,000 °C) epitaxial growth processes. Using the encapsulation layer described herein, ceramic materials, including polycrystalline AlN designed for non-cleanroom environments, can be used in semiconductor process flows and cleanroom environments.

[0048] Figure 4 is a simplified schematic diagram illustrating an engineering substrate structure according to another embodiment of the present invention. In the embodiment illustrated in Figure 4, a first adhesive layer 412 is formed on at least a portion of the core 110, but does not encapsulate the core 110. In this embodiment, the first adhesive layer 412 is formed on the lower surface (back side of the core 110) of the core 110 to enhance the adhesion of the subsequently formed conductive layer 414, as described more fully below. Although Figure 4 only illustrates the adhesive layer 412 on the lower surface of the core 110, it will be understood that depositing the adhesive layer material on other portions of the core will not adversely affect the performance of the engineering substrate structure, and such materials can be present in various embodiments. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0049] The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110, but is generally aligned with the first adhesive layer 412. Although the conductive layer 414 is illustrated to extend along the bottom or back side of the first adhesive layer 412 and upward along a portion of the side of the first adhesive layer 412, extension along a vertical side is not required by the invention. Therefore, embodiments may utilize deposition on one side of the substrate structure, masking on one side of the substrate structure, etc. The conductive layer 414 may be formed on a portion of one side (e.g., the bottom / back side) of the first adhesive layer 412. The conductive layer 414 provides electrical conduction on one side of the engineered substrate structure, which is advantageous in RF and high-power applications. The conductive layer may include the doped polysilicon discussed with respect to the conductive layer 114 in Figure 1.

[0050] A portion of the core 110, multiple portions of the first adhesive layer 412, and the conductive layer 414 are covered by a second adhesive layer 416 to enhance the adhesion of the barrier layer 418 to the underlying material. As discussed above, the barrier layer 418 forms an encapsulation structure to prevent diffusion from the underlying layer.

[0051] In addition to semiconductor conductive layers, in other embodiments, conductive layer 414 is a metal layer, such as 500 Å titanium or the like.

[0052] Referring again to Figure 4, depending on the implementation, one or more layers may be removed. For example, layers 412 and 414 may be removed, leaving only the single bonded shell 416 and the barrier layer 418. In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance the stress and wafer warping caused by layer 120 deposited on top of layer 418. The construction of a substrate structure with an insulating layer on the top side of core 110 (e.g., an insulating layer only between core 110 and layer 120) will provide benefits for power / RF applications where highly insulating substrates are required.

[0053] In another embodiment, the barrier layer 418 may directly encapsulate the core 110, followed by the conductive layer 414 and then the adhesive layer 416. In this embodiment, layer 120 may be deposited directly onto the adhesive layer 416 from the top side. In yet another embodiment, the adhesive layer 416 may be deposited on the core 110, followed by the barrier layer 418, then the conductive layer 414, and another adhesive layer 412.

[0054] Although some embodiments have been discussed regarding layers, the term "layer" should be understood to mean that a layer may include several sublayers constructed to form the layer of interest. Therefore, the term "layer" is not intended to refer to a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form the desired structure. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0055] Figure 5 is a simplified flowchart illustrating a method for manufacturing an engineered substrate according to one embodiment of the present invention. This method can be used to manufacture a substrate that matches one or more epitaxial layers (CTEs) grown on the substrate. Method 500 includes forming a support structure by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer to form a shell (e.g., a tetraethyl orthosilicate (TEOS) shell) (512), and encapsulating the first adhesive layer in a conductive shell (e.g., a polycrystalline silicon shell) (514). The first adhesive layer may be formed as a single layer of TEOS. The conductive shell may be formed as a single layer of polycrystalline silicon.

[0056] The method further includes encapsulating the conductive shell in a second adhesive layer (e.g., a second TEOS shell) (516), and encapsulating the second adhesive layer in a barrier shell (518). The second adhesive layer may be formed as a monolayer of TEOS. The barrier shell may be formed as a monolayer of silicon nitride.

[0057] Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (520) and bonding a solid single-crystal layer (e.g., a solid single-crystal silicon layer) to the silicon oxide layer (522). According to embodiments of the invention, other solid single-crystal layers can be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc. Bonding the bonding layer may include depositing a bonding material, followed by performing a planarization process as described herein. In the embodiments described below, the solid single-crystal layer (e.g., a solid single-crystal silicon layer) is attached to the bonding layer system using a layer transfer process, wherein the solid single-crystal layer is a single-crystal silicon layer transferred from a silicon wafer.

[0058] Referring to Figure 1, bonding layer 120 can be formed by depositing a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of approximately 1.5 μm. The thick initial oxide layer is used to fill voids and surface features present in the support structure, which may exist after the fabrication of the polycrystalline core and continue to exist during the formation of the encapsulation layer illustrated in Figure 1. The CMP process provides a generally flat surface free of voids, particles, or other features, which can then be used during the wafer transfer process to bond the substantial single-crystal layer 122 (e.g., a substantial single-crystal silicon layer) to bonding layer 120. It will be understood that bonding layer 120 need not be characterized by an atomically flat surface, but rather should provide a generally flat surface that will support the bonding substantial single-crystal layer (e.g., a substantial single-crystal silicon layer) with the desired reliability.

[0059] A layer transfer process can be used to bond the substantial single-crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a split surface. After wafer bonding, the silicon substrate can be removed together with the portion of the single-crystal silicon layer below the split surface, thereby producing the stripped single-crystal silicon layer 122 illustrated in Figure 1. The thickness of the substantial single-crystal layer 122 can be varied to meet the specifications of various applications. Furthermore, the crystal orientation of the substantial single-crystal layer 122 can be varied to meet the specifications of the application. Additionally, the doping level and distribution in the substantial single-crystal layer 122 can be varied to meet the specifications of a specific application.

[0060] The method illustrated in Figure 5 may also include smoothing the solid single-crystal layer (524). In some embodiments, the thickness and surface roughness of the solid single-crystal layer 122 can be modified to obtain high-quality epitaxial growth. Different device applications may have slightly different specifications regarding the thickness and surface smoothness of the solid single-crystal layer 122. The splitting process separates the solid single-crystal layer 122 from the bulk single-crystal silicon wafer at the peak of the implanted ion distribution. After splitting, the solid single-crystal layer 122 can be adjusted or modified in several aspects and then used as a growth surface for epitaxial growth of other materials, such as gallium nitride.

[0061] First, the transferred solid single-crystal layer 122 may contain a small amount of residual hydrogen concentration and may have some crystal damage from the fabric growth. Therefore, it may be beneficial to remove the thin, lattice-damaged portions of the transferred solid single-crystal layer 122. In some embodiments, the depth of the fabric growth can be adjusted to be greater than the desired final thickness of the solid single-crystal layer 122. The additional thickness allows for the removal of the damaged thin portions of the transferred solid single-crystal layer, leaving the undamaged portion of the desired final thickness.

[0062] Second, the overall thickness of the solid single-crystal layer 122 may need to be adjusted. Generally, it may be desirable to make the solid single-crystal layer 122 thick enough to provide a high-quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough to have high compliance. When the solid single-crystal layer 122 is relatively thin, it can be referred to as "compliant," meaning that the physical properties of the solid single-crystal layer 122 are less restricted and can mimic the physical properties of the surrounding material, with a lower tendency to generate crystal defects. The compliance of the solid single-crystal layer 122 can be inversely proportional to its thickness. Higher compliance can result in a lower defect density in the epitaxial layers grown on the template and allows for the growth of thicker epitaxial layers. In some embodiments, the thickness of the solid single-crystal layer 122 can be increased by epitaxially growing silicon on a stripped silicon layer.

[0063] Third, improving the smoothness of the substantial single-crystal layer 122 may be beneficial. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-distributed plant species, and the annealing conditions used to form the hydrogen-based splitting surface. The initial roughness resulting from layer transfer (i.e., the splitting step) can be reduced by thermal oxidation and oxide stripping, as discussed below.

[0064] In some embodiments, removing the damaged layer and adjusting the final thickness of the substantial single-crystal layer 122 can be achieved by thermally oxidizing the top portion of the silicon layer, followed by oxide layer removal using hydrogen fluoride (HF) acid. For example, a silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to produce a silicon dioxide layer approximately 420 nm thick. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be approximately 53 nm. During thermal oxidation, implanted hydrogen may migrate to the surface. Therefore, the subsequent oxide layer removal can remove some of the damage. Furthermore, thermal oxidation is typically performed at temperatures of 1000 °C or higher. The increased temperature can also repair lattice damage.

[0065] The silicon oxide layer formed on the top portion of the substantial single-crystal layer during thermal oxidation can be removed by etching with HF acid. The etching selectivity of HF acid for silicon oxide and silicon (SiO2:Si) can be adjusted by adjusting the temperature and concentration of the HF solution, as well as the stoichiometry and density of silicon oxide. Etching selectivity refers to the etching rate of one material relative to another. The selectivity of the HF solution for (SiO2:Si) can range from about 10:1 to about 100:1. A high etching selectivity can reduce the surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantial single-crystal layer 122 may still be greater than desired. For example, the surface roughness of the bulk Si (111) may have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by atomic force microscopy (AFM) scanning prior to additional treatment. In some embodiments, the surface roughness required for epitaxial growth of gallium nitride material on Si(111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm in a 30 μm × 30 μm AFM scanning area.

[0066] If the surface roughness of the solid single-crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, further surface smoothing can be performed. Several methods exist for smoothing silicon surfaces. These methods may include hydrogen annealing, laser finishing, plasma smoothing, and contact polishing (e.g., chemical mechanical polishing or CMP). These methods may involve preferentially etching high aspect ratio surface peaks. Therefore, high aspect ratio features on the surface can be removed faster than low aspect ratio features, resulting in a smoother surface.

[0067] It should be understood that the specific steps illustrated in Figure 5 provide a particular method for manufacturing an engineering substrate according to one embodiment of the present invention. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Furthermore, each step illustrated in Figure 5 may include multiple sub-steps that can be performed in various sequences suitable for individual steps. Additionally, additional steps may be added or removed depending on the specific application. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0068] Figure 6 is a simplified schematic diagram illustrating an epitaxial / engineered substrate structure for RF and power applications according to one embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing a high-quality GaN layer, and is subsequently removed from the engineered substrate structure. However, for RF and power device applications, the engineered substrate structure forms part of the completed device; as a result, the electrical, thermal, and other characteristics of the engineered substrate structure or the device formed by the engineered substrate structure are important for the specific application.

[0069] Referring to Figure 1, the monocrystalline silicon layer 122 is typically a release layer separated from the silicon substrate wafer using implantation and lift-off techniques. Typical implants are hydrogen and boron. For power and RF device applications, the electrical properties of the layers and materials in the engineered substrate structure are important. For example, some device architectures use highly insulating silicon layers with a resistivity greater than 10³ Ohm-cm to reduce or eliminate leakage through the substrate and interface layers. Other applications utilize designs including conductive silicon layers with a predetermined thickness (e.g., 1 μm) to connect the source of a device to other devices. Therefore, in these applications, it is desirable to be able to control the size and performance of the monocrystalline silicon layer. In designs where implantation and lift-off techniques are used during layer transfer, residual implanted atoms (e.g., hydrogen or boron) remain in the silicon layer, thereby altering its electrical properties. Furthermore, it is difficult to control the thickness, conductivity, and other properties of thin silicon layers by adjusting, for example, the implantation dosage. Adjusting the implantation dosage can affect conductivity, the half-width at half-maximum (FWHM) of the implantation distribution, surface roughness, the accuracy of the splitting plane position, and the implantation depth, which may affect the layer thickness.

[0070] According to embodiments of the present invention, silicon epitaxy on an engineered substrate structure is used to achieve the desired characteristics of a single-crystal silicon layer suitable for a specific device design.

[0071] Referring to Figure 6, the epitaxial / engineering substrate structure 600 includes an engineering substrate structure 610 and a silicon epitaxial layer 620 formed on the engineering substrate structure 610. The engineering substrate structure 610 may be similar to the engineering substrate structures illustrated in Figures 1, 3, and 4. Typically, after layer transfer, the substantial monocrystalline silicon layer 122 is on the order of 0.5 μm. In some processes, surface conditioning processes can be used to reduce the thickness of the monocrystalline silicon layer 122 to about 0.3 μm. To increase the thickness of the monocrystalline silicon layer to about 1 μm for fabricating, for example, reliable ohmic contacts, an epitaxial monocrystalline silicon layer 620 is grown on the substantial monocrystalline silicon layer 122 formed by the layer transfer process using an epitaxial process. Various epitaxial growth processes can be used to grow the epitaxial monocrystalline silicon layer 620, including CVD, ALD, MBE, etc. The thickness of the epitaxial single-crystal silicon layer 620 can range from about 0.1 μm to about 20 μm, for example, between 0.1 μm and 10 μm.

[0072] Figure 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineering substrate structure according to one embodiment of the present invention. As described below, the structure illustrated in Figure 7 can be referred to as a dual epitaxial structure. As illustrated in Figure 7, the engineering substrate structure 710, including an epitaxial monocrystalline silicon layer 620, has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer comprises gallium nitride (GaN).

[0073] Depending on the required functionality, the desired thickness of the III-V epitaxial layer 720 can vary considerably. In some embodiments, the thickness of the III-V epitaxial layer 720 can vary between 0.5 μm and 100 μm, for example, a thickness greater than 5 μm. The resulting breakdown voltage of a device fabricated on the III-V epitaxial layer 720 can vary depending on the thickness of the III-V epitaxial layer 720. Some embodiments provide breakdown voltages of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

[0074] To provide conductivity between certain portions of the III-V epitaxial layer 720, which may include multiple sublayers, in this example, a set of vias 724 are formed extending from the top surface of the III-V epitaxial layer 720 into the epitaxial single-crystal silicon layer 620. The vias 724 may be lined with an insulating layer (not shown) to insulate them from the III-V epitaxial layer 720. As an example, these vias can be used to connect electrodes of a diode or transistor to the underlying silicon layer by providing ohmic contacts through them, thereby mitigating charge buildup in the device.

[0075] If a III-V epitaxial layer is grown on a single-crystal silicon layer 122, obtaining such ohmic contacts through vias would be difficult because terminating the via etching within the single-crystal silicon layer 122 would be challenging: for example, reliably etching through 5 μm of GaN across the entire wafer and terminating the etching within a 0.3 μm silicon layer. Embodiments of the present invention can provide single-crystal silicon layers several micrometers thick, which is difficult using placement and stripping processes because achieving large placement depths requires high placement energy. Subsequently, the thick silicon layer enables applications such as the illustrated vias, enabling a wide variety of device designs.

[0076] In addition to increasing the thickness of the silicon "layer" by epitaxially growing a single-crystal silicon layer 620 on the single-crystal silicon layer 122, other adjustments can be made to the original properties of the single-crystal silicon layer 122, including modifications to conductivity, crystallinity, etc. For example, if a silicon layer on the order of 10 μm is needed before further epitaxial growth of a III-V layer or other materials, such a thick layer can be grown according to embodiments of the present invention.

[0077] Because the implantation process affects the properties of the monocrystalline silicon layer 122—for example, residual boron / hydrogen atoms can affect the electrical properties of silicon—in embodiments of the present invention, a portion of the monocrystalline silicon layer 122 is removed before epitaxial growth of the monocrystalline silicon layer 620. For example, the monocrystalline silicon layer 122 can be thinned to form a layer with a thickness of 0.1 μm or less, thereby removing most or all of the residual boron / hydrogen atoms. The subsequently grown monocrystalline silicon layer 620 is then used to provide a monocrystalline material whose electrical and / or other properties are substantially independent of the corresponding properties of layers formed using a layer transfer process.

[0078] In addition to increasing the thickness of the single-crystal silicon material coupled to the engineered substrate structure, the electrical properties (including conductivity) of the epitaxial single-crystal silicon layer 620 can differ from those of the single-crystal silicon layer 122. During growth, doping of the epitaxial single-crystal silicon layer 620 can produce p-type silicon by using boron doping and n-type silicon by using phosphorus doping. Undoped silicon can be grown to provide high-resistivity silicon for use in devices with insulating regions. In particular, insulating layers can be used in RF devices.

[0079] A strained epitaxial material can be generated by adjusting the lattice constant of the epitaxial single-crystal silicon layer 620 during growth to change the lattice constant of the single-crystal silicon layer 122. Besides silicon, other elements can be epitaxially grown to provide layers, including strained layers containing silicon and germanium, or the like. For example, buffer layers can be grown on the single-crystal silicon layer 122, on the epitaxial single-crystal silicon layer 620, or between layers to enhance subsequent epitaxial growth. Such buffer layers may include strained III-V layers, silicon-germanium strained layers, etc. Furthermore, buffer layers and other epitaxial layers can be graded by molar fraction, dopant, polarity, etc. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0080] In some embodiments, the strain present in the monocrystalline silicon layer 122 or the epitaxial monocrystalline silicon layer 620 can be relaxed during the growth of subsequent epitaxial layers (including III-V epitaxial layers).

[0081] Figure 8 is a simplified flowchart illustrating a method for manufacturing an engineering substrate according to another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810) and forming a first adhesive layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first adhesive layer may include a tetraethyl orthosilicate (TEOS) layer. The method further includes forming a conductive layer (814) coupled to the first adhesive layer. The conductive layer may be a polycrystalline silicon layer. The first adhesive layer may be formed as a monolayer of TEOS. The conductive layer may be formed as a monolayer of polycrystalline silicon.

[0082] The method further includes forming a second adhesive layer (816) coupled to at least a portion of the conductive layer, and forming a barrier shell (818). The second adhesive layer may be formed as a monolayer of TEOS. The barrier shell may be formed as a monolayer of silicon nitride or a series of sublayers forming the barrier shell.

[0083] Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (820) and bonding a substantial single-crystal silicon layer or a substantial single-crystal layer to the silicon oxide layer (822). The bonding of the bonding layer may include depositing a bonding material as described herein, followed by a planarization process.

[0084] A layer transfer process can be used to bond the substantial single-crystal silicon layer 122 to the bonding layer 120. In some embodiments, a silicon wafer (e.g., a silicon (111) wafer) is implanted to form a split surface. After wafer bonding, the silicon substrate can be removed together with the portion of the single-crystal silicon layer below the split surface, thereby producing the peeled single-crystal silicon layer 122 illustrated in Figure 1. The thickness of the substantial single-crystal silicon layer 122 can be varied to meet the specifications of various applications. In addition, the crystal orientation of the substantial single-crystal layer 122 can be varied to meet the specifications of the application. Furthermore, the doping level and distribution in the substantial single-crystal layer 122 can be varied to meet the specifications of a specific application. In some embodiments, the substantial single-crystal silicon layer 122 can be smoothed, as described above.

[0085] The method illustrated in Figure 8 may further include forming an epitaxial silicon layer (824) by epitaxial growth on the substantial single-crystal silicon layer, and forming an epitaxial III-V layer (826) by epitaxial growth on the epitaxial silicon layer. In some embodiments, the epitaxial III-V layer may comprise gallium nitride (GaN).

[0086] It should be understood that the specific steps illustrated in Figure 8 provide a particular method for manufacturing an engineering substrate according to another embodiment of the present invention. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the above steps in a different order. Furthermore, each step illustrated in Figure 8 may include multiple sub-steps that can be performed in various sequences suitable for a single step. Additionally, additional steps may be added or removed depending on the specific application. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0087] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or variations will be conceived by one of ordinary skill in the art in light of such examples and embodiments, and will be included within the spirit and scope of this application and the scope of the appended claims.

[0088] 100: Engineering substrate 110:core 112: First adhesive layer 114: Conductive layer 116: Second adhesive layer 118: Barrier Layer 120: Bonding layer 122: Substantial monocrystalline silicon layer 130: Epitaxial Materials 300: Engineering substrate 314: Conductive layer 316: Second adhesive layer 317: Plane 412: First adhesive layer 414: Conductive layer 416: Second adhesive layer 418: Barrier Layer 500: Methods 600: Epitaxial / Engineering Substrate Structure 610: Engineering substrate structure 620: Silicon epitaxial layer 710: Engineering substrate structure 720: III-V epitaxial layer 724: Through hole

[0089] Domestic storage information (please note in order of storage institution, date, and number) none

[0090] Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A substrate comprising: a support structure comprising: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a second adhesive layer coupled to the conductive layer; a barrier layer coupled to the second adhesive layer; a bonding layer coupled to the support structure; a substantial single-crystal layer coupled to the bonding layer, the substantial single-crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride; and an epitaxial semiconductor layer coupled to the substantial single-crystal layer.

2. The substrate as claimed in claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride.

3. The substrate as claimed in claim 1, wherein the bonding layer comprises silicon oxide.

4. The substrate as claimed in claim 1, wherein the epitaxial semiconductor layer comprises an epitaxial III-V layer.

5. The substrate as claimed in claim 4, wherein the epitaxial III-V layer comprises an epitaxial gallium nitride layer having a thickness of about 5 μm or greater.

6. The substrate as described in claim 4 further includes a plurality of vias extending from the epitaxial III-V layer into the epitaxial semiconductor layer.

7. The substrate as claimed in claim 1, wherein the epitaxial semiconductor layer comprises an epitaxial monocrystalline silicon layer, and the substrate further comprises an epitaxial III-V layer coupled to the epitaxial monocrystalline silicon layer.

8. The substrate as described in claim 1, wherein: The first adhesive layer encapsulates the polycrystalline ceramic core; the conductive layer encapsulates the first adhesive layer; and the second adhesive layer encapsulates the conductive layer.

9. The substrate as described in claim 1, further comprising forming an epitaxial silicon layer on the substantial single-crystal layer.

10. The substrate as described in claim 1, wherein: The first adhesive layer includes a first tetraethyl orthosilicate (TEOS) layer encapsulating the polycrystalline ceramic core; the conductive layer includes a polycrystalline silicon layer encapsulating the first TEOS layer; the second adhesive layer includes a second TEOS layer encapsulating the polycrystalline silicon layer; and the barrier layer includes a silicon nitride layer encapsulating the second TEOS layer.

11. The substrate as claimed in claim 1, wherein the barrier layer comprises a silicon nitride layer.

12. The substrate as claimed in claim 1, wherein the substantial single-crystal layer comprises a substantial single-crystal silicon layer.

13. The substrate as claimed in claim 1, wherein at least one of the first adhesive layer or the second adhesive layer comprises silicon oxynitride (SiON).

14. The substrate as claimed in claim 1, wherein the epitaxial semiconductor layer comprises an epitaxial monocrystalline silicon layer.

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