Plasma processing apparatus and plasma processing method

Abstract

The plasma processing apparatus disclosed in this invention includes a chamber, a substrate support, and a power supply system. The substrate support has electrodes and is configured to support a substrate within the chamber. The power supply system is electrically connected to the electrodes. The power supply system is configured to output a first pulse as a bias voltage to the electrodes during a first period, and to output a second pulse to the electrodes during a second period following the first period. The first pulse and the second pulse are voltage pulses. The voltage level of the first pulse is different from the voltage level of the second pulse.

Description

Technical Field

[0001] The exemplary embodiments of the present invention relate to a plasma treatment apparatus and a plasma treatment method. Prior Technology

[0002] A plasma processing apparatus is used for plasma processing of a substrate. The plasma processing apparatus includes a chamber and a substrate holding electrode. The substrate holding electrode is disposed in the chamber. The substrate holding electrode holds the substrate placed on its main surface. One such plasma processing apparatus is described in Japanese Patent Application Publication No. 2009-187975 (hereinafter referred to as "Patent Document 1").

[0003] The plasma processing apparatus described in Patent Document 1 further includes a high-frequency generating device and a DC (Direct Current) negative pulse generating device. The high-frequency generating device applies a high-frequency voltage to the substrate holding electrode. In the plasma processing apparatus described in Patent Document 1, the high-frequency voltage is alternately switched on and off. Furthermore, in the plasma processing apparatus described in Patent Document 1, a DC negative pulse voltage is applied to the substrate holding electrode from the DC negative pulse generating device according to the timing of the high-frequency voltage switching on and off. Summary of the Invention

[0004] This invention provides a technique for supplying ions with different energies to a substrate.

[0005] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, and a power supply system. The substrate support has electrodes and is configured to support a substrate within the chamber. The power supply system is electrically connected to the electrodes of the substrate support and is configured to apply a bias voltage to the electrodes of the substrate support in order to feed ions from plasma within the chamber onto the substrate on the substrate support. The power supply system is configured to output a first pulse to the electrodes of the substrate support during a first period as the bias voltage, and to output a second pulse to the electrodes of the substrate support during a second period following the first period. The first pulse and the second pulse are voltage pulses. The voltage level of the first pulse is different from the voltage level of the second pulse.

[0006] According to one exemplary embodiment, ions with different energies can be supplied to the substrate. Simple Explanation of the Diagram

[0007] Figure 1 is a schematic diagram of a plasma processing apparatus according to an exemplary embodiment. Figure 2 is the timing diagram of the bias voltage in the first example. Figure 3 is the timing diagram of the bias voltage in the second example. Figure 4 is the timing diagram of the bias voltage in the third example. Figure 5 is the timing diagram of the bias voltage in the fourth example. Figure 6 shows the timing diagram of the bias voltage in the fifth example. Figure 7 is a diagram illustrating a power supply system of an exemplary embodiment. Figure 8 is a diagram illustrating another exemplary embodiment of the power supply system. Figure 9 is a diagram showing the configuration of a substrate support according to another exemplary embodiment. Implementation

[0008] The following describes various exemplary embodiments.

[0009] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, and a power supply system. The substrate support has electrodes and is configured to support a substrate within the chamber. The power supply system is electrically connected to the electrodes of the substrate support and is configured to apply a bias voltage to the electrodes of the substrate support in order to feed ions from plasma within the chamber onto the substrate on the substrate support. The power supply system is configured to output a first pulse to the electrodes of the substrate support during a first period as the bias voltage, and to output a second pulse to the electrodes of the substrate support during a second period following the first period. The first pulse and the second pulse are voltage pulses. The voltage level of the first pulse is different from the voltage level of the second pulse.

[0010] In the above embodiment, the voltage level of the first pulse is different from the voltage level of the second pulse. Therefore, the energy of the ions supplied from the plasma to the substrate during the first period is different from the energy of the ions supplied from the plasma to the substrate during the second period. Thus, according to the above embodiment, it is possible to supply the substrate with ions of different energies.

[0011] In one exemplary embodiment, the second period may also be continuous with the first period. The first pulse and the second pulse may also be pulses of negative polarity voltage. The absolute value of the voltage level of the first pulse may also be less than the absolute value of the voltage level of the second pulse.

[0012] In one exemplary embodiment, the first pulse and the second pulse may also be negative voltage pulses. The absolute value of the voltage level of the first pulse may also be greater than the absolute value of the voltage level of the second pulse. The power supply system may also be configured such that the voltage output to the electrodes of the substrate support is 0 V during the period between the first and second periods.

[0013] In one exemplary embodiment, the second period may also be continuous with the first period. The first pulse and the second pulse may also be pulses of negative polarity voltage. The absolute value of the voltage level of the first pulse may also be greater than the absolute value of the voltage level of the second pulse.

[0014] In one exemplary embodiment, the power supply system may also be configured to output a third pulse to the electrodes of the substrate support during a third period following the second period. The third pulse may also be a negative voltage pulse. The absolute value of the voltage level of the third pulse may also be greater than the absolute value of the voltage level of the second pulse. The absolute value of the voltage level of the third pulse may also be the same as the absolute value of the voltage level of the first pulse.

[0015] In one exemplary embodiment, the power supply system may also be configured to output a pulse of positive voltage to the electrodes of the substrate support before the start of the first period in the subsequent period of two cycles, which respectively include a first period and a second period. According to this embodiment, when the pulse of positive voltage is output to the electrodes of the substrate support, electrons are supplied to the substrate. As a result, the amount of positive charge on the substrate is reduced.

[0016] In one exemplary embodiment, the power supply system may also be configured to intermittently output the first pulse to the electrodes of the substrate support during the first period. The power supply system may also be configured to intermittently output the second pulse to the electrodes of the substrate support during the second period.

[0017] In one exemplary embodiment, the first pulse and the second pulse may also be negative voltage pulses. The power supply system may also be configured to alternately output the first pulse and positive voltage pulses to the electrodes of the substrate support during the first period. The power supply system may also be configured to alternately output the second pulse and positive voltage pulses to the electrodes of the substrate support during the second period. According to this embodiment, when a positive voltage pulse is output to the electrodes of the substrate support, electrons are supplied to the substrate. As a result, the amount of positive charge on the substrate decreases.

[0018] In one exemplary embodiment, the power supply system may also be configured to output a positive voltage pulse to the electrodes of the substrate support during the period between the first and second periods. According to this embodiment, when the positive voltage pulse is output to the electrodes of the substrate support, electrons are supplied to the substrate. As a result, the amount of positive charge on the substrate is reduced.

[0019] In another exemplary embodiment, a plasma processing method is provided. The plasma processing method includes the step of preparing a substrate on a substrate support disposed within a chamber of a plasma processing apparatus. The substrate support includes electrodes. The plasma processing method further includes the step of outputting a first pulse from a power supply system to the electrodes of the substrate support during a first period, as a bias voltage for feeding ions from plasma within the chamber to the substrate. The plasma processing method further includes the step of outputting a second pulse from the power supply system to the electrodes of the substrate support during a second period, as a bias voltage. The first pulse and the second pulse are voltage pulses. The voltage level of the first pulse is different from the voltage level of the second pulse.

[0020] In one exemplary embodiment, the second period may also be continuous with the first period. The first pulse and the second pulse may also be pulses of negative polarity voltage. The absolute value of the voltage level of the first pulse may also be less than the absolute value of the voltage level of the second pulse.

[0021] In one exemplary embodiment, the first pulse and the second pulse may also be negative voltage pulses. The absolute value of the voltage level of the first pulse may also be greater than the absolute value of the voltage level of the second pulse. The plasma processing method may further include the step of setting the voltage output from the power supply system to the electrodes of the substrate support to 0 V during the period between the first period and the second period.

[0022] In one exemplary embodiment, the second period may also be continuous with the first period. The first pulse and the second pulse may also be pulses of negative polarity voltage. The absolute value of the voltage level of the first pulse may also be greater than the absolute value of the voltage level of the second pulse.

[0023] In one exemplary embodiment, the plasma processing method may further include the step of outputting a third pulse from the power supply system to the electrodes of the substrate support during a third period following the second period. The third pulse may also be a negative voltage pulse. The absolute value of the voltage level of the third pulse may also be greater than the absolute value of the voltage level of the second pulse. Alternatively, the absolute value of the voltage level of the third pulse may be the same as the absolute value of the voltage level of the first pulse.

[0024] In one exemplary embodiment, the plasma processing method may further include the following steps: before the start of the first period in the subsequent period of the two cycles comprising the first period and the second period, respectively, outputting a positive voltage pulse from the power supply system to the electrodes of the substrate support.

[0025] In one exemplary embodiment, the first pulse may also be intermittently output from the power supply system to the electrodes of the substrate support during the first period. Similarly, the second pulse may be intermittently output from the power supply system to the electrodes of the substrate support during the second period.

[0026] In one exemplary embodiment, the first pulse and the aforementioned second pulse may also be negative voltage pulses. The plasma processing method may further include the step of intermittently outputting positive voltage pulses from the power supply system to the electrodes of the substrate support during the first period. The positive voltage pulses may also be output alternately with the first pulse. The plasma processing method may further include the step of intermittently outputting positive voltage pulses from the power supply system to the electrodes of the substrate support during the second period. The positive voltage pulses may also be output alternately with the second pulse.

[0027] In one exemplary embodiment, the plasma processing method may further include the step of: during the period between the first period and the second period, outputting a positive voltage pulse from the power supply system to the electrodes of the substrate support.

[0028] Hereinafter, various exemplary embodiments will be described in detail with reference to the drawings. Furthermore, the same or equivalent parts will be labeled with the same symbols in each drawing.

[0029] Figure 1 is a schematic diagram illustrating an exemplary embodiment of a plasma processing apparatus. The plasma processing apparatus 1 shown in Figure 1 is a capacitively coupled plasma processing apparatus. The plasma processing apparatus 1 includes a chamber 10. The chamber 10 provides an internal space 10s therein. The central axis of the chamber 10 is axis AX, and extends along the vertical direction.

[0030] In one embodiment, the chamber 10 may also include a chamber body 12. The chamber body 12 has a generally cylindrical shape. An internal space 10s is provided within the chamber body 12. The chamber body 12 may contain, for example, aluminum. The chamber body 12 is electrically grounded. A plasma-resistant film is formed on the inner wall surface of the chamber body 12, i.e., the wall surface that divides the internal space 10s. This film may be a ceramic film formed by anodizing or by yttrium oxide.

[0031] A passage 12p is formed on the side wall of the chamber body 12. When the substrate W is transported between the internal space 10s and the outside of the chamber 10, the substrate W passes through the passage 12p. In order to open and close the passage 12p, a gate valve 12g is provided along the side wall of the chamber body 12.

[0032] The plasma processing apparatus 1 further includes a substrate support 16. The substrate support 16 is configured to support a substrate W placed thereon within the chamber 10. The substrate W has a generally disc-shaped form. The substrate support 16 can also be supported by a support body 15. The support body 15 extends upward from the bottom of the chamber body 12. The support body 15 has a generally cylindrical shape. The support body 15 is formed of an insulating material such as quartz.

[0033] The substrate support 16 has a lower electrode 18. The substrate support 16 may also have an electrostatic chuck 20. The substrate support 16 may also have an electrode plate 19. The electrode plate 19 is formed of a conductive material such as aluminum and has a generally disc-shaped form. The lower electrode 18 is disposed on the electrode plate 19. The lower electrode 18 is formed of a conductive material such as aluminum and has a generally disc-shaped form. The lower electrode 18 is electrically connected to the electrode plate 19. The central axis of the lower electrode 18 and the electrode plate 19 is substantially aligned with axis AX.

[0034] The lower electrode 18 provides a flow path 18f therein. Flow path 18f is a flow path for the heat exchange medium. The heat exchange medium is, for example, a refrigerant. A circulation device (e.g., a cooler unit) for the heat exchange medium is connected to flow path 18f. This circulation device is located outside chamber 10. The heat exchange medium from the circulation device is supplied to flow path 18f via pipe 23a. The heat exchange medium supplied to flow path 18f returns to the circulation device via pipe 23b.

[0035] An electrostatic chuck 20 is disposed on the lower electrode 18. When the substrate W is processed within the internal space for 10 seconds, it is placed on the electrostatic chuck 20 such that its center is aligned with the axis AX. The electrostatic chuck 20 is configured to hold the substrate. The electrostatic chuck 20 has a body and electrodes. The body of the electrostatic chuck 20 is formed of a dielectric material such as aluminum oxide or aluminum nitride. The body of the electrostatic chuck 20 has a generally disc-shaped form. The central axis of the electrostatic chuck 20 is approximately aligned with the axis AX.

[0036] The electrodes of the electrostatic chuck 20 are disposed within the body of the electrostatic chuck 20. The electrodes of the electrostatic chuck 20 are films formed of conductors. A DC power supply is electrically connected to the electrodes of the electrostatic chuck 20. When a DC voltage is applied to the electrodes of the electrostatic chuck 20 from the DC power supply, an electrostatic attraction is generated between the electrostatic chuck 20 and the substrate W. The substrate W is attracted to the electrostatic chuck 20 by the generated electrostatic attraction, and the electrostatic chuck 20 holds the substrate W.

[0037] The substrate support 16 can also support the edge ring ER mounted thereon. The edge ring ER has a ring shape and is formed, for example, from silicon or silicon carbide. The edge ring ER is mounted on the substrate support 16 with its central axis located on axis AX. In one embodiment, the edge ring ER can also be partially mounted on the electrostatic chuck 20. Furthermore, the substrate W is disposed on the electrostatic chuck 20 within the area surrounded by the edge ring ER.

[0038] The plasma processing apparatus 1 may further include a gas supply line 25. The gas supply line 25 supplies heat transfer gas, such as He gas, from the gas supply mechanism to the gap between the upper surface of the electrostatic chuck 20 and the back surface (lower surface) of the substrate W.

[0039] The plasma processing apparatus 1 may further include a cylindrical portion 28 and an insulating portion 29. The cylindrical portion 28 extends upward from the bottom of the chamber body 12. The cylindrical portion 28 extends along the outer periphery of the support 15. The cylindrical portion 28 is formed of a conductive material and has a generally cylindrical shape. The cylindrical portion 28 is electrically grounded. The insulating portion 29 is disposed on the cylindrical portion 28. The insulating portion 29 is formed of an insulating material. The insulating portion 29 is formed, for example, of ceramic such as quartz. The insulating portion 29 has a generally cylindrical shape. The insulating portion 29 extends along the outer periphery of the electrode plate 19, the outer periphery of the lower electrode 18, and the outer periphery of the electrostatic chuck 20.

[0040] The plasma processing apparatus 1 further includes an upper electrode 30. The upper electrode 30 is disposed above the substrate support 16. The upper electrode 30 and the member 32 together close the upper opening of the chamber body 12. The member 32 is formed of an insulating material. The upper electrode 30 is supported on the upper part of the chamber body 12 through the member 32.

[0041] The upper electrode 30 may also include a top plate 34 and a support 36. An internal space 10s is formed on the lower surface of the top plate 34. A plurality of gas ejection holes 34a are formed on the top plate 34. The plurality of gas ejection holes 34a penetrate the top plate 34 in the thickness direction (vertical direction). The top plate 34 is, for example, formed of silicon. Alternatively, the top plate 34 may have a structure formed by depositing a plasma-resistant film on the surface of an aluminum component. This film may be a ceramic film formed by anodizing or by yttrium oxide.

[0042] The support body 36 supports the top plate 34, allowing for easy installation and removal. The support body 36 is made of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support body 36. A plurality of gas holes 36b extend downward from the gas diffusion chamber 36a. The plurality of gas holes 36b are respectively connected to a plurality of gas ejection holes 34a. A gas inlet port 36c is formed in the support body 36. The gas inlet port 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas inlet port 36c.

[0043] A gas source group 40 is connected to the gas supply pipe 38 via a valve group 41, a flow controller group 42, and a valve group 43. The gas source group 40, valve group 41, flow controller group 42, and valve group 43 constitute a gas supply unit. The gas source group 40 includes a plurality of gas sources. Valve groups 41 and 43 each include a plurality of valves (e.g., on / off valves). The flow controller group 42 includes a plurality of flow controllers. The plurality of flow controllers in the flow controller group 42 are either mass flow controllers or pressure-controlled flow controllers. The plurality of gas sources in the gas source group 40 are connected to the gas supply pipe 38 via corresponding valves in valve group 41, corresponding flow controllers in flow controller group 42, and corresponding valves in valve group 43. The plasma processing apparatus 1 can individually adjust the flow rate of gas from one or more selected gas sources from the plurality of gas sources in the gas source group 40, and supply the gas to the internal space at that flow rate for 10 seconds.

[0044] A baffle member 48 may also be provided between the cylindrical portion 28 and the side wall of the chamber body 12. The baffle member 48 may be a plate-shaped component. For example, the baffle member 48 may be constructed by coating an aluminum plate with a ceramic such as yttrium oxide. A plurality of through holes are formed in the baffle member 48. Below the baffle member 48, an exhaust pipe 52 is connected to the bottom of the chamber body 12. An exhaust device 50 is connected to the exhaust pipe 52. The exhaust device 50 has a pressure controller such as an automatic pressure control valve and a vacuum pump such as a turbomolecular pump, which can reduce the pressure in the internal space within 10 seconds.

[0045] The plasma processing apparatus 1 further includes a high-frequency power supply 61. The high-frequency power supply 61 generates a first high-frequency power for plasma generation. The frequency of the first high-frequency power can be in the range of 27 to 100 MHz, for example, 40 MHz or 60 MHz. The high-frequency power supply 61 is connected to the lower electrode 18 via a matching device 61m and an electrode plate 19. The matching device 61m has a matching circuit for matching the impedance of the load side (lower electrode 18 side) of the high-frequency power supply 61 with the output impedance of the high-frequency power supply 61. Furthermore, the high-frequency power supply 61 can also be connected to the upper electrode 30 without electrical connection to the lower electrode 18, or via the matching device 61m.

[0046] The plasma processing apparatus 1 may further include a high-frequency power supply 62. The high-frequency power supply 62 generates a second high-frequency power. The frequency of the second high-frequency power is lower than the frequency of the first high-frequency power. The high-frequency power supply 62 is connected to the lower electrode 18 via a matching device 62m and an electrode plate 19. The matching device 62m has a matching circuit for matching the impedance of the load side (lower electrode 18 side) of the high-frequency power supply 62 with the output impedance of the high-frequency power supply 62. Alternatively, the plasma processing apparatus 1 may not include the high-frequency power supply 62 and the matching device 62m.

[0047] In the plasma processing apparatus 1, gas is supplied to the internal space from the gas supply unit for 10 seconds. Furthermore, by supplying high-frequency electricity, the gas is excited within the internal space for 10 seconds. As a result, plasma is generated within the internal space for 10 seconds. The substrate W is then processed using chemical species such as ions and / or free radicals from the plasma.

[0048] The plasma processing apparatus 1 further includes a power supply system 70. The power supply system 70 is electrically connected to the lower electrode 18. The power supply system 70 is configured to apply a bias voltage to the lower electrode 18 in order to feed ions from the plasma onto the substrate on the substrate support 16. The power supply system 70 can also be connected to the lower electrode 18 via a filter 70f. The filter 70f includes a filter circuit that blocks or reduces high-frequency power directed toward the power supply system 70. Further details of the power supply system 70 will be described below.

[0049] The plasma processing apparatus 1 may further include a control unit MC. The control unit MC is a computer equipped with a processor, memory, input device, and display device, which controls various parts of the plasma processing apparatus 1. Specifically, the control unit MC executes a control program stored in the memory, controlling various parts of the plasma processing apparatus 1 based on process recipe data stored in the memory. Through the control performed by the control unit MC, the process specified by the process recipe data is executed in the plasma processing apparatus 1. By utilizing the control of various parts of the plasma processing apparatus 1 by the control unit MC, various embodiments of plasma processing methods can be executed in the plasma processing apparatus 1.

[0050] The bias voltage generated by the power supply system 70 will be described below with reference to Figures 2 to 6. Figures 2 to 6 are timing diagrams of the bias voltages in Examples 1 to 5, respectively. Furthermore, the plasma processing methods of various exemplary embodiments will also be described below.

[0051] In various exemplary embodiments, the plasma processing method includes the step of preparing a substrate W on a substrate support 16. The plasma processing method is performed while the substrate W is placed on the substrate support 16.

[0052] The plasma processing method includes the step of generating plasma within chamber 10. To generate plasma, processing gas is supplied to chamber 10 from a gas supply unit. Furthermore, the pressure of the gas within chamber 10 is adjusted to a specified pressure by an exhaust device 50. Additionally, a first high-frequency power is supplied from a high-frequency power source 61. As a result, plasma is generated from the processing gas within chamber 10. Furthermore, during plasma generation, a second high-frequency power source from a high-frequency power source 62 can also be supplied to the lower electrode 18. The steps of the plasma processing method described below are performed during the generation of plasma within chamber 10.

[0053] As shown in Figures 2-6, the plasma processing method includes the step of outputting a first pulse PL1 from the power supply system 70 to the lower electrode 18 as a bias voltage during the first period P1. The first pulse PL1 is a voltage pulse. The first pulse PL1 can also be a DC voltage pulse. Furthermore, the first pulse PL1 can also have a waveform other than a rectangular wave such as a triangular wave or a pulse wave. The first pulse can also have a waveform in which the voltage value changes at its leading and trailing edges.

[0054] As shown in Figures 2-6, the plasma processing method includes the step of outputting a second pulse PL2 from the power supply system 70 to the lower electrode 18 as a bias voltage during the second period P2. The second period P2 is the period following the first period P1. The second pulse PL2 is a voltage pulse. The voltage level of the first pulse PL1 is different from the voltage level of the second pulse PL2. Furthermore, the second pulse PL2 can also be a DC voltage pulse. The second pulse PL2 can also have a waveform other than a rectangular wave, such as a triangular wave or a pulse wave. The second pulse can also have a waveform where the voltage value changes at its leading and trailing edges.

[0055] In the examples shown in Figures 2 through 6, the first pulse PL1 and the second pulse PL2 are pulses of negative polarity voltage (e.g., negative DC voltage). The voltage level difference between the voltage level of one of the pulses PL1 and PL2 (hereinafter referred to as the "H-level pulse") and the reference level (e.g., 0 V) ​​can also be 6 kV or more. The voltage level difference between the H-level pulse and the reference level can also be 10 kV or 20 kV or more. The voltage level difference between the other pulse of the first pulse PL1 and PL2 (hereinafter referred to as the "L-level pulse") and the reference level (e.g., 0 V) ​​can also be 5 kV or less.

[0056] In the plasma processing method, as shown in Figures 2-6, the cycle CY can also be repeated. The cycle CY includes a first period P1 and a second period P2. In the first and third examples shown in Figures 2-4, the frequency of the cycle CY can be between 100 kHz and 1 MHz. In the fourth and fifth examples shown in Figures 5-6, the frequency of the cycle CY can be between 0.2 Hz and 1 Hz.

[0057] In one embodiment, as shown in the first example of FIG2, the second period P2 may also be continuous with the first period P1. In this embodiment, the absolute value of the voltage level of the first pulse PL1 may also be less than the absolute value of the voltage level of the second pulse PL2.

[0058] Furthermore, in the first example shown in Figure 2, the reference level of the bias voltage is 0 V. This reference level can also have positive or negative values. In the first example, as long as the difference between the reference level and the voltage level of the first pulse PL1 is less than the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values. That is, in the first example, as long as the voltage level of the second pulse PL2 is lower than the voltage level of the first pulse PL1, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values.

[0059] In another embodiment, as shown in Example 2 of FIG3, the absolute value of the voltage level of the first pulse PL1 may also be greater than the absolute value of the voltage level of the second pulse PL2. In this embodiment, the plasma processing method may further include the step of setting the voltage output from the power supply system 70 to the lower electrode 18 to 0 V during the period PG1 between the first period P1 and the second period P2.

[0060] Furthermore, in the second example shown in Figure 3, the reference level of the bias voltage is 0 V. This reference level can also have positive or negative values. In the second example, as long as the difference between the reference level and the voltage level of the first pulse PL1 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values. That is, in the second example, as long as the voltage level of the first pulse PL1 is lower than the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values.

[0061] In another embodiment, as shown in Example 3 of FIG4, the second period P2 can also be continuous with the first period P1. In this embodiment, the absolute value of the voltage level of the first pulse PL1 can also be greater than the absolute value of the voltage level of the second pulse PL2.

[0062] In another embodiment, as shown in Example 3 of FIG4, the plasma processing method may further include the step of outputting a third pulse PL3 from the power supply system 70 to the lower electrode 18 during the third period P3 following the second period P2. The third pulse PL3 may also be a negative voltage pulse, and the absolute value of the voltage level of the third pulse PL3 may be greater than the absolute value of the voltage level of the second pulse PL2. The absolute value of the voltage level of the third pulse PL3 may also be the same as the absolute value of the voltage level of the first pulse PL1. That is, the third pulse PL3 may also be a pulse at the H level. The difference between the voltage level of the third pulse PL3 and the reference level (e.g., 0 V) ​​may also be 6 kV or more. The difference between the voltage level of the third pulse PL3 and the reference level may also be 10 kV or 20 kV or more.

[0063] Furthermore, in Example 3 shown in Figure 4, the reference level of the bias voltage is 0 V. This reference level can also have positive or negative values. In Example 3, as long as the difference between the reference level and the voltage level of the first pulse PL1 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values. That is, in Example 3, as long as the voltage level of the first pulse PL1 is lower than the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values. Also, in Example 3, as long as the difference between the reference level and the voltage level of the third pulse PL3 is greater than the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the third pulse PL3 and the second pulse PL2 can each have arbitrary values. That is, in the third example, as long as the voltage level of the third pulse PL3 is lower than the voltage level of the second pulse PL2, the voltage levels of the third pulse PL3 and the second pulse PL2 can each have arbitrary values.

[0064] In another embodiment, as shown in Examples 1 to 3 of Figures 2 to 4, the plasma processing method may further include the step of outputting a positive voltage pulse PPL. The voltage level of the voltage pulse PPL is higher than a reference level (e.g., 0 V). The voltage pulse PPL may also be a positive DC voltage pulse. The pulse PPL is output during the period PP. The period PP is the period before the start of the first period P1 in the subsequent period CY of any two consecutive periods CY. The period PP may also be the period immediately preceding the subsequent first period P1. In this case, ions with higher energy can be supplied to the substrate W during the subsequent first period P1.

[0065] In the first example shown in Figure 2, period PP is the period after period PG. In the first example shown in Figure 2, period PG is the period after the second period P2. In the first example shown in Figure 2, during period PG, the voltage output from the power supply system 70 to the lower electrode 18 is set to 0 V (i.e., reference level).

[0066] In the second example shown in Figure 3, period PP is the period after period PG2. In the second example shown in Figure 3, period PG2 is the period after the second period P2. In the second example shown in Figure 3, during period PG2, the voltage output from the power supply system 70 to the lower electrode 18 is set to 0 V.

[0067] In the third example shown in Figure 4, period PP is the period after period PG. In the third example shown in Figure 4, period PG is the period after the third period P3. In the third example shown in Figure 4, during period PG, the voltage output from the power supply system 70 to the lower electrode 18 is set to 0 V (i.e., reference level).

[0068] In another embodiment, as shown in Example 4 of FIG5 and Example 5 of FIG6, the first pulse PL1 can also be intermittently output from the power supply system 70 to the lower electrode 18 during the first period P1. The first pulse PL1 can also be periodically output from the power supply system 70 to the lower electrode 18 during the first period P1. The first pulse PL1 is output during the sub-period SP1 within the first period P1. The first pulse PL1 can also be periodically output at a frequency of 100 kHz or higher and 1 MHz or lower.

[0069] In another embodiment, as shown in Example 4 of FIG5 and Example 5 of FIG6, the second pulse PL2 can also be intermittently output from the power supply system 70 to the lower electrode 18 during the second period P2. The second pulse PL2 can also be periodically output from the power supply system 70 to the lower electrode 18 during the second period P2. The second pulse PL2 is output during the sub-period SP2 within the second period P2. The second pulse PL2 can also be periodically output at a frequency of 100 kHz or higher and 1 MHz or lower.

[0070] Furthermore, in Example 4 shown in Figure 5 and Example 5 shown in Figure 6, the absolute value of the voltage level of the first pulse PL1 is greater than the absolute value of the voltage level of the second pulse PL2. The absolute value of the voltage level of the first pulse PL1 may also be less than the absolute value of the voltage level of the second pulse PL2.

[0071] In Example 4 shown in Figure 5, the reference level of the bias voltage is 0 V. This reference level can also have positive or negative values. In Example 4, as long as the difference between the reference level and the voltage level of the first pulse PL1 is different from the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values.

[0072] In another embodiment, as shown in Example 4 of FIG5, the plasma processing method may further include the step of intermittently outputting a positive voltage pulse PPL1 from the power supply system 70 to the lower electrode 18 during the first period P1. The voltage level of the voltage pulse PPL1 is higher than the reference level (e.g., 0 V). The voltage pulse PPL1 may also be a positive DC voltage pulse. In this embodiment, the positive voltage pulse PPL1 may be output alternately with the first pulse PL1. The positive voltage pulse PPL1 is output during period SPP1. Period SPP1 may also be the period following period SPG1. Period SPG1 is the period following sub-period SP1. During period SPG1, the voltage output from the power supply system 70 to the lower electrode 18 may also be set to 0 V (i.e., the reference level). Period SPP1 may also be the period immediately preceding the subsequent sub-period SP1. In this case, ions with higher energy can be supplied to the substrate W during the subsequent sub-period SP1.

[0073] In another embodiment, as shown in Example 4 of FIG5, the plasma processing method may further include the step of intermittently outputting a positive voltage pulse PPL2 from the power supply system 70 to the lower electrode 18 during the second period P2. The voltage level of the voltage pulse PPL2 is higher than the reference level (e.g., 0 V). The voltage pulse PPL2 may also be a positive DC voltage pulse. In this embodiment, the positive voltage pulse PPL2 may be output alternately with the second pulse PL2. The positive voltage pulse PPL2 is output during period SPP2. Period SPP2 may also be the period following period SPG2. Period SPG2 is the period following sub-period SP2. During period SPG2, the voltage output from the power supply system 70 to the lower electrode 18 may also be set to 0 V (i.e., the reference level). Period SPP2 may also be the period immediately preceding the subsequent sub-period SP2. In this case, ions with higher energy can be supplied to the substrate W during the subsequent sub-period SP2.

[0074] In another embodiment, as shown in Example 5 of FIG6, the plasma processing method may further include the step of outputting a positive voltage pulse PPL1 from the power supply system 70 to the lower electrode 18 during the period SPP1 between the first period P1 and the second period P2. The voltage level of the voltage pulse PPL1 is higher than the reference level (e.g., 0 V). The voltage pulse PPL1 may also be a positive DC voltage pulse. The period SPP1 may also be the period immediately preceding the subsequent sub-period SP2. In this case, ions with higher energy can be supplied to the substrate W during the subsequent sub-period SP2.

[0075] In another embodiment, as shown in Example 5 of FIG6, the plasma processing method may further include the step of outputting a positive voltage pulse PPL2 from the power supply system 70 to the lower electrode 18 during period SPP2. The voltage level of the voltage pulse PPL2 is higher than the reference level (e.g., 0 V). The voltage pulse PPL2 may also be a positive DC voltage pulse. Period SPP2 is the period between the second period P2 and the subsequent first period P1. Period SPP2 may also be the period immediately preceding the subsequent sub-period SP1. In this case, ions with higher energy can be supplied to the substrate W during the subsequent sub-period SP1.

[0076] Furthermore, in Example 5 shown in Figure 6, the reference level of the bias voltage is 0 V. This reference level can also have positive or negative values. In Example 5, as long as the difference between the reference level and the voltage level of the first pulse PL1 is different from the difference between the reference level and the voltage level of the second pulse PL2, the voltage levels of the first pulse PL1 and the second pulse PL2 can each have arbitrary values.

[0077] In the various exemplary embodiments described above, the energy of the ions supplied from the plasma to the substrate W during the first period P1 is different from the energy of the ions supplied from the plasma to the substrate W during the second period P2. Therefore, it is possible to supply ions with different energies to the substrate W.

[0078] Furthermore, in several exemplary embodiments, a pulse of positive DC voltage is supplied to the lower electrode 18. By supplying a pulse of positive DC voltage to the lower electrode 18, electrons are supplied to the substrate W. As a result, the amount of positive charge on the substrate W is reduced.

[0079] Furthermore, when etching the film on substrate W using the bias voltages of Examples 1 to 3 to form an opening on substrate W, the deposits on substrate W can be removed and the shape of the opening adjusted during the supply of pulses at level L. Also, in this case, ions can be supplied to the bottom of a deeper opening during the supply of pulses at level H.

[0080] The bias voltages in Examples 4 and 5 can be used for etching multilayer films with different types of films. For example, the bias voltages in Examples 4 and 5 can be used for etching during the manufacture of NAND (Not AND) devices. In the manufacture of NAND devices, a multilayer film comprising alternating layers of silicon oxide and silicon nitride or polycrystalline silicon films is etched. The silicon oxide film can be etched using relatively high-energy ions, and the silicon nitride or polycrystalline silicon film can be etched using relatively low-energy ions. When using the bias voltages in Examples 4 and 5, the silicon oxide film can also be etched during the first period P1, and the silicon nitride or polycrystalline silicon film can be etched during the second period P2.

[0081] Hereinafter, several exemplary embodiments of the power supply system that can be used as the power supply system 70 of the plasma processing apparatus 1 will be described.

[0082] Figure 7 is a diagram illustrating a power supply system of an exemplary embodiment. The power supply system 70A shown in Figure 7 can be used as the power supply system 70 of the plasma processing apparatus 1. The power supply system 70A can output the bias voltages of the first to fifth examples described above. The power supply system 70A may include a DC power supply 71, a pulse unit 72, and a pulse controller PC.

[0083] DC power supply 71 is a power source that generates a negative DC voltage. The positive terminal of DC power supply 71 is grounded. DC power supply 71 can also be a variable DC power supply.

[0084] The pulse unit 72 is configured to generate a voltage pulse from a negative DC voltage from the DC power supply 71. In one embodiment, the pulse unit 72 may also include one or more switching transistors 72a, one or more switching transistors 72b, diodes 72c and 72d.

[0085] One or more switching transistors 72a are connected between the positive terminal of the DC power supply 71 and the node 721. When the pulse unit 72 includes a plurality of switching transistors 72a, these switching transistors 72a are connected in series between the positive terminal of the DC power supply 71 and the node 721.

[0086] One or more switching transistors 72b are connected between the negative terminal of the DC power supply 71 and node 721. When the pulse unit 72 includes a plurality of switching transistors 72b, these switching transistors 72b are connected in series between the negative terminal of the DC power supply 71 and node 721.

[0087] Diode 72c is connected in parallel with one or more switching transistors 72a. Diode 72c is connected between the positive terminal of DC power supply 71 and node 722. The cathode of diode 72c is connected to the positive terminal of DC power supply 71, and the anode of diode 72c is connected to node 722. Node 722 is connected to node 721.

[0088] Diode 72d is connected in parallel with one or more switching transistors 72b. Diode 72d is connected between the negative terminal of DC power supply 71 and node 722. The anode of diode 72d is connected to the negative terminal of DC power supply 71, and the cathode of diode 72d is connected to node 722.

[0089] The pulse controller PC is configured to set the output period of the voltage pulse from the pulse unit 72 by assigning a control signal to the pulse unit 72. In one embodiment, the pulse controller PC assigns pulse control signals as control signals to the control terminals of one or more switching transistors 72a and one or more switching transistors 72b.

[0090] Based on the pulse control signal from the pulse controller PC, when one or more switching transistors 72a are turned off and one or more switching transistors 72b are turned on, node 722 is grounded. As a result, the output voltage of the power supply system 70A becomes 0V (i.e., the reference voltage).

[0091] Based on the pulse control signal from the pulse controller PC, when one or more switching transistors 72a are turned on and one or more switching transistors 72b are turned off, node 722 is connected to the negative terminal of the DC power supply 71. This results in a negative voltage pulse (e.g., a negative DC voltage) being output from the power supply system 70A. The voltage level of the pulse output from node 722 is adjusted by adjusting the output voltage level of the DC power supply 71, thereby generating the aforementioned first, second, and third pulses.

[0092] In one embodiment, the power supply system 70A may further include a DC power supply 73 and a pulse unit 74. The DC power supply 73 is a power supply that generates a positive DC voltage. The negative terminal of the DC power supply 73 is grounded. The DC power supply 73 may also be a variable DC power supply.

[0093] The pulse unit 74 is configured to generate a voltage pulse from a positive DC voltage from the DC power supply 73. In one embodiment, the pulse unit 74 may also include one or more switching transistors 74a, one or more switching transistors 74b, diodes 74c and 74d.

[0094] One or more switching transistors 74a are connected between the positive terminal of the DC power supply 73 and node 741. When the pulse unit 74 includes a plurality of switching transistors 74a, these switching transistors 74a are connected in series between the positive terminal of the DC power supply 73 and node 741.

[0095] One or more switching transistors 74b are connected between the negative terminal of the DC power supply 73 and node 741. When the pulse unit 74 includes a plurality of switching transistors 74b, these switching transistors 74b are connected in series between the negative terminal of the DC power supply 73 and node 741.

[0096] Diode 74c is connected in parallel with one or more switching transistors 74a. Diode 74c is connected between the positive terminal of DC power supply 73 and node 742. The cathode of diode 74c is connected to the positive terminal of DC power supply 73, and the anode of diode 74c is connected to node 742. Node 742 is connected to node 741.

[0097] Diode 74d is connected in parallel with one or more switching transistors 74b. Diode 74d is connected between the negative terminal of DC power supply 73 and node 742. The anode of diode 74d is connected to the negative terminal of DC power supply 73, and the cathode of diode 74d is connected to node 742.

[0098] The pulse controller PC can also be configured to set the output period of the voltage pulse from the pulse unit 74 by assigning a control signal to the pulse unit 74. In one embodiment, the pulse controller PC assigns pulse control signals as control signals to the control terminals of one or more switching transistors 74a and one or more switching transistors 74b.

[0099] Based on the pulse control signal from the pulse controller PC, when one or more switching transistors 74a are turned on and one or more switching transistors 74b are turned off, node 742 is grounded. As a result, the output voltage of the power supply system 70A becomes 0V (i.e., the reference voltage).

[0100] When one or more switching transistors 74a are turned off and one or more switching transistors 74b are turned on, according to the pulse control signal from the pulse controller PC, node 742 is connected to the positive terminal of the DC power supply 73. The result is a pulse of positive voltage (e.g., positive DC voltage) output from the power supply system 70A.

[0101] Furthermore, when the power supply system 70A outputs a negative voltage pulse, one or more switching transistors 74a and one or more switching transistors 74b can be set to the on state. Also, when the power supply system 70A outputs a positive voltage pulse, one or more switching transistors 72a and one or more switching transistors 72b can be set to the on state.

[0102] In one embodiment, the pulse controller PC can also provide pulse control signals to the high-frequency power supply 61 and / or high-frequency power supply 62. The high-frequency power supply 61 can also output pulses of a first high-frequency power according to the pulse control signal. The pulses of the first high-frequency power can be output with the same phase as the pulses of the DC voltage output from the power supply system 70A, or they can be output with a different phase. The high-frequency power supply 62 can also output pulses of a second high-frequency power according to the pulse control signal. The pulses of the second high-frequency power can be output with the same phase as the pulses of the DC voltage output from the power supply system 70A, or they can be output with a different phase. Furthermore, the high-frequency power supply 61 can also output a continuous wave of the first high-frequency power. Also, the high-frequency power supply 62 can also output a continuous wave of the second high-frequency power.

[0103] Hereinafter, please refer to Figure 8. Figure 8 is a diagram showing a power supply system of another exemplary embodiment. The power supply system 70B shown in Figure 8 can be used as the power supply system 70 of the plasma processing apparatus 1. The power supply system 70B can output the bias voltage of the first to fifth examples described above. Hereinafter, the differences between the power supply system 70B and the power supply system 70A will be explained.

[0104] The pulse unit 72 of the power supply system 70B further includes a switching transistor 72e. The switching transistor 72e is connected between node 722 and node 701. Node 701 is connected to the lower electrode 18.

[0105] The switching transistor 72e switches between an on and off state based on the control signal (pulse control signal) assigned to its control terminals by the pulse controller PC. When the switching transistor 72e is in the on state, the pulse unit 72 is electrically disconnected from node 701 and lower electrode 18. When the switching transistor 72e is in the off state, the pulse unit 72 is connected to node 701 and lower electrode 18, outputting a negative voltage pulse from the pulse unit 72 to the lower electrode 18. The negative voltage pulse output from the pulse unit 72 to the lower electrode 18 is used as one of the first pulse PL1 and the second pulse PL2. When the pulse unit 72 outputs the first pulse PL1, the pulse unit 72 can also output a third pulse PL3.

[0106] The power supply system 70B further includes a DC power supply 75 and a pulse unit 76. The DC power supply 75 is a power supply that generates a negative DC voltage. The positive terminal of the DC power supply 75 is grounded. The DC power supply 75 can also be a variable DC power supply. The level of the negative DC voltage generated by the DC power supply 75 is different from the level of the negative DC voltage generated by the DC power supply 71.

[0107] The pulse unit 76 is configured to generate a voltage pulse from a negative DC voltage from the DC power supply 75. In one embodiment, the pulse unit 76 may also include one or more switching transistors 76a, 76b, diodes 76c, 76d, and 76e.

[0108] One or more switching transistors 76a are connected between the positive terminal of the DC power supply 75 and node 761. When the pulse unit 76 includes a plurality of switching transistors 76a, these switching transistors 76a are connected in series between the positive terminal of the DC power supply 75 and node 761.

[0109] One or more switching transistors 76b are connected between the negative terminal of the DC power supply 75 and node 761. When the pulse unit 76 includes a plurality of switching transistors 76b, these switching transistors 76b are connected in series between the negative terminal of the DC power supply 75 and node 761.

[0110] Diode 76c is connected in parallel with one or more switching transistors 76a. Diode 76c is connected between the positive terminal of DC power supply 75 and node 762. The cathode of diode 76c is connected to the positive terminal of DC power supply 75, and the anode of diode 76c is connected to node 762. Node 762 is connected to node 761. Node 762 is connected to node 701 via switching transistor 76e. That is, switching transistor 76e is connected between node 762 and node 701.

[0111] Diode 76d is connected in parallel with one or more switching transistors 76b. Diode 76d is connected between the negative terminal of DC power supply 75 and node 762. The anode of diode 76d is connected to the negative terminal of DC power supply 75, and the cathode of diode 76d is connected to node 762.

[0112] In the power supply system 70B, the pulse controller PC is configured to set the output period of the voltage pulse from the pulse unit 76 by assigning a control signal to the pulse unit 76. In one embodiment, the pulse controller PC assigns pulse control signals as control signals to the control terminals of one or more switching transistors 76a and one or more switching transistors 76b.

[0113] Furthermore, in the power supply system 70B, the pulse controller PC assigns pulse control signals to the control terminals of the switching transistor 76e. The switching transistor 76e switches between an on state and an off state according to the pulse control signals assigned to its control terminals by the pulse controller PC.

[0114] When the switching transistor 76e is in the ON state, the pulse unit 76 is electrically disconnected from node 701 and lower electrode 18. When the switching transistor 76e is in the OFF state, the pulse unit 76 is connected to node 701 and lower electrode 18.

[0115] Based on the pulse control signal from the pulse controller PC, when one or more switching transistors 76a are turned off and one or more switching transistors 76b are turned on, node 762 is grounded. As a result, the voltage in node 762 becomes 0 V (i.e., the reference level).

[0116] When one or more switching transistors 76a are turned on and one or more switching transistors 76b are turned off according to the pulse control signal from the pulse controller PC, node 762 is connected to the negative terminal of DC power supply 75.

[0117] When pulse unit 76 is connected to node 701 and node 762 is connected to the negative terminal of DC power supply 75, pulses of negative polarity voltage (e.g., negative DC voltage) are output from pulse unit 76. The pulse of negative polarity voltage output from pulse unit 76 to lower electrode 18 is used as the other of the first pulse PL1 and the second pulse PL2. When pulse unit 76 outputs the first pulse PL1, pulse unit 76 can also further output a third pulse PL3.

[0118] Hereinafter, please refer to FIG9. FIG9 is a diagram showing the configuration of a substrate support according to another exemplary embodiment. The substrate support 16 shown in FIG9 can be used instead of the substrate support 16 in the plasma processing apparatus 1.

[0119] The substrate support 16A has a lower electrode 18A and an electrostatic chuck 20A. The lower electrode 18A is formed of a conductive material such as aluminum and has a generally disk-shaped form. A high-frequency power supply 61 can be connected to the lower electrode 18A via a matching adapter 61m. Furthermore, as described above, the high-frequency power supply 61 can also be connected to the upper electrode 30 via the matching adapter 61m.

[0120] An electrostatic chuck 20A is disposed on the lower electrode 18A. The electrostatic chuck 20A has a dielectric portion 20d and an electrode 21a. The electrostatic chuck 20A may also have electrodes 22a and 22b. When processing the substrate W in the internal space for 10 seconds, it is placed on the electrostatic chuck 20A and held by the electrostatic chuck 20A. Furthermore, an edge ring ER is mounted on the substrate support 16A. The edge ring ER is mounted on the substrate support 16A with its central axis aligned with the axis AX. The substrate W housed within the chamber 10 is disposed on the electrostatic chuck 20A within the area surrounded by the edge ring ER.

[0121] The substrate support 16A has a first region 21 and a second region 22. In FIG. 9, the boundary between the first region 21 and the second region 22 is indicated by a dashed line. The first region 21 is the central region of the substrate support 16A. The first region 21 includes the central region of the electrostatic chuck 20A and the central region of the lower electrode 18A. The second region 22 extends radially outward along the circumferential direction relative to the first region 21. The second region 22 includes the peripheral region of the electrostatic chuck 20A and the peripheral region of the lower electrode 18A. The electrostatic chuck of the first region 21 and the electrostatic chuck of the second region 22 can also be provided by a single electrostatic chuck. That is, the electrostatic chuck of the first region 21 and the electrostatic chuck of the second region 22 can also be integrated. Furthermore, in another embodiment, the electrostatic chuck of the first region 21 and the electrostatic chuck of the second region 22 can also be different electrostatic chucks.

[0122] Region 21 is configured to support a substrate W placed thereon (i.e., on its upper surface). Region 21 is a disk-shaped region. The central axis of Region 21 is substantially aligned with axis AX. Region 21 and Region 22 share a dielectric portion 20d. The dielectric portion 20d is formed of a dielectric material such as aluminum nitride or aluminum oxide. The dielectric portion 20d has a generally disk-shaped form. In one embodiment, the thickness of the dielectric portion 20d in Region 22 is less than the thickness of the dielectric portion 20d in Region 21. The upper surface of the dielectric portion 20d in Region 22 may also be lower in the vertical direction than the upper surface of the dielectric portion 20d in Region 21.

[0123] The first region 21 has an electrode 21a (suction cup electrode). Electrode 21a is a film-shaped electrode disposed within the dielectric portion 20d in the first region 21. A DC power supply 101p is connected to electrode 21a via switch 101s. When a DC voltage from the DC power supply 101p is applied to electrode 21a, an electrostatic attraction is generated between the first region 21 and the substrate W. By means of the generated electrostatic attraction, the substrate W is attracted to the first region 21 and held by the first region 21.

[0124] The first region 21 further includes a first electrode 21c. The first electrode 21c is a film-shaped electrode disposed within the dielectric portion 20d in the first region 21. Furthermore, the electrode 21a may extend in the vertical direction closer to the upper surface of the first region 21 than the first electrode 21c.

[0125] A power supply system 81 is connected to the first electrode 21c via a filter 81f. The power supply system 81 has the same configuration as the power supply system 70, and is configured to apply the aforementioned bias voltage to the first electrode 21c. The filter 81f has the same configuration as the filter 70f.

[0126] Region 22 extends in a manner that surrounds Region 21. Region 22 is a generally annular region. The central axis of Region 22 is approximately aligned with axis AX. Region 22 is configured to support an edge ring ER placed thereon (i.e., on its upper surface). Region 22 and Region 21 share a dielectric portion 20d.

[0127] In one embodiment, the second region 22 can also retain the edge ring ER by electrostatic attraction. In this embodiment, the second region 22 may have more than one electrode (suction cup electrode). In the example shown in FIG9, the second region 22 has a pair of electrodes, namely electrode 22a and electrode 22b. Electrode 22a and electrode 22b are disposed within the dielectric portion 20d in the second region 22. Electrode 22a and electrode 22b constitute a bipolar electrode. Electrode 22a and electrode 22b are both film-like electrodes. Electrode 22a and electrode 22b may also extend at approximately the same height in the vertical direction.

[0128] A DC power supply 102p is connected to electrode 22a via switch 102s and filter 102f. Filter 102f is configured to block or attenuate high-frequency power. A DC power supply 103p is connected to electrode 22b via switch 103s and filter 103f. Filter 103f is configured to block or reduce high-frequency power.

[0129] DC power supplies 102p and 103p apply DC voltages to electrodes 22a and 22b respectively to generate an electrostatic attraction that draws the edge ring ER to the second region 22. Furthermore, the set potentials of electrodes 22a and 22b can be any of positive, negative, or 0 V. For example, the potential of electrode 22a can be set to positive, and the potential of electrode 22b can be set to negative. Also, a single DC power supply can be used to form, rather than two, the potential difference between electrodes 22a and 22b.

[0130] When a DC voltage is applied to electrodes 22a and 22b, an electrostatic attraction is generated between the second region 22 and the edge ring ER. The generated electrostatic attraction attracts the edge ring ER to the second region 22, where it is held in place.

[0131] The second region 22 further includes a second electrode 22c. The second electrode 22c is a film-like electrode. The second electrode 22c is disposed within the dielectric portion 20d in the second region 22. The second electrode 22c is separate from the first electrode 21c. Furthermore, electrodes 22a and 22b may extend in the vertical direction at a position closer to the upper surface of the second region 22 than the second electrode 22c. Furthermore, the second electrode 22c may also be disposed outside the second region 22. For example, the second electrode 22c may also be disposed below the edge ring ER, within the insulating portion 29.

[0132] A power supply system 82 is connected to the second electrode 22c via a filter 82f. The power supply system 82 has the same configuration as the power supply system 70, configured to apply the aforementioned bias voltage to the second electrode 22c. The filter 82f has the same configuration as the filter 70f. The bias voltage applied to the second electrode 22c by the power supply system 82 can be synchronized with the bias voltage applied to the first electrode 21c by the power supply system 81. The phase of the bias voltage applied to the second electrode 22c by the power supply system 82 can also be consistent with the phase of the bias voltage applied to the first electrode 21c by the power supply system 81. The bias voltage applied to the second electrode 22c by the power supply system 82 can also have a phase difference relative to the bias voltage applied to the first electrode 21c by the power supply system 81.

[0133] The second region 22 may further include a gas pipeline 22g. The gas pipeline 22g is provided for supplying heat transfer gas, such as He gas, to the gap between the second region 22 and the edge ring ER. The gas pipeline 22g is connected to the gas supply mechanism 104, which serves as the source of the heat transfer gas.

[0134] Furthermore, the power supply system 81 can also be connected to electrode 21a. In this case, the substrate support 16A may not have the first electrode 21c. Also, the power supply system 82 can be connected to at least one of electrode 22a and electrode 22b. In this case, the substrate support 16A may not have the second electrode 22c. Furthermore, the second region 22 may not have electrodes 22a and 22b. Also, the power supply system 81 can apply a bias voltage to the first electrode 21c and the second electrode 22c. In this case, the plasma processing apparatus 1 may not have the power supply system 82.

[0135] Furthermore, the electrostatic chuck 20A may also have a source electrode for supplying high-frequency power from the high-frequency power supply 61. The source electrode is disposed within the dielectric portion 20d of at least one of the first region 21 and the second region 22. When the source electrode is disposed within the dielectric portion 20d of the first region 21, it may also be disposed below the first electrode 21c, and the first electrode 21c may also be disposed below the electrode 21a. Alternatively, the source electrode may also be disposed above the first electrode 21c and below the electrode 21a. When the source electrode is disposed within the dielectric portion 20d of the second region 22, it may also be disposed below the second electrode 22c, and the second electrode 22c may also be disposed below electrodes 22a and 22b. Alternatively, the source electrode may also be disposed above the second electrode 22c and below electrodes 22a and 22b.

[0136] The above descriptions illustrate various exemplary embodiments, but the embodiments are not limited to these exemplary embodiments. Various additions, omissions, substitutions, and modifications can be made. Furthermore, elements from different embodiments can be combined to form other embodiments.

[0137] For example, power supply systems 70, 81, and 82 can each have one or more power supplies (e.g., DC power supplies) capable of outputting voltage (e.g., DC voltage) pulses instead of the configurations shown in Figures 7 and 8. These power supplies can also be variable DC power supplies. The bias voltages of the various examples described above can be generated by these power supplies.

[0138] Furthermore, the pulse controller PC may be an accessory to the high-frequency power supply 61 or the high-frequency power supply 62, rather than a power supply system 70, 81 and 82.

[0139] Furthermore, in the second example shown in Figure 3, the second pulse PL2 can also be generated by grounding node 722 after the end of the first period P1 and electrically isolating node 722 from the DC power supply 71 before the potential of node 722 becomes 0 V. To ground node 722, one or more switching transistors 72a are set to the off state, and one or more switching transistors 72b are set to the on state. To electrically isolate node 722 from the DC power supply 71, one or more switching transistors 72a and one or more switching transistors 72b are set to the on state.

[0140] Furthermore, in another embodiment, the plasma processing apparatus may be other types of plasma processing apparatus besides capacitively coupled plasma processing apparatus. Other types of plasma processing apparatus may include inductively coupled plasma processing apparatus, electron cyclotron resonance (ECR) plasma processing apparatus, or plasma processing apparatus that uses surface waves such as microwaves to generate plasma. Such other types of plasma processing apparatus may also be used in the plasma processing methods of various exemplary embodiments.

[0141] Based on the above description, it is understood that the various embodiments of the present invention described in this specification are for illustrative purposes, and various modifications can be made without departing from the scope and spirit of the invention. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and spirit are indicated by the appended claims.

[0142] 1: Plasma treatment device 10: Chamber 10s: Interior space 12: Chamber body 12g: Gate valve 12p: Pathway 15: Support 16: Substrate support 16A: Substrate Support 18: Lower electrode 18A: Lower electrode 18f:Flow path 19: Electrode plate 20: Electrostatic chuck 20A: Electrostatic Chuck 20d: Dielectric part 21: Area 1 21a: Electrode 21c: Electrode 1 22: Area 2 22a: Electrode 22b: Electrode 22c: Second electrode 22g: Gas pipeline 23a:Piping 23b:Piping 25: Gas supply pipeline 28:Tubular part 29: Insulation section 30: Upper electrode 32: Components 34: Top plate 34a: Gas ejection port 36: Support body 36a: Gas diffusion chamber 36b: Gas pore 36c: Gas inlet port 38: Gas supply pipe 40: Gas source group 41: Valve assembly 42: Flow controller group 43: Valve assembly 48: Baffle component 50: Exhaust device 52: Exhaust pipe 61: High-frequency power supply 61m: Matcher 62: High-frequency power supply 62m: Matcher 70: Power System 70A: Power System 70B: Power System 70f: Filter 71: DC power supply 72: Pulse Unit 72a: Switching transistor 72b: Switching Transistor 72c: Diode 72d: Diode 72e: Switching transistor 73: DC power supply 74: Pulse Unit 74a: Switching transistor 74b: Switching transistor 74c: Diode 74d: Diode 75: DC power supply 76: Pulse Unit 76a: Switching transistor 76b: Switching transistor 76c: Diode 76d: Diode 76e: Switching transistor 81: Power System 81f: Filter 82: Power System 82f: Filter 101p: DC power supply 101s: Switch 102f: Filter 102p: DC power supply 102s: Switch 103f: Filter 103p: DC power supply 103s: Switch 701: Node 721: Node 722: Node 741: Node 742: Node 761: Node 762: Node AX: Axis ER: Edge ring MC: Control Department PC: Pulse Controller W: substrate

Claims

1. A plasma processing apparatus comprising: a chamber; a substrate support having electrodes disposed within the chamber; and a power supply system configured to apply pulsed voltage signals to the electrodes at a plurality of cycles; wherein, Each period comprises: a sequence of first voltage pulses, each having a first voltage level and negative polarity during a first period; a sequence of second voltage pulses, each having a second voltage level and negative polarity different from the first voltage level during a second period; a third voltage pulse, having positive polarity during a third period between the first and second periods, wherein the third period is a single period between the first and second periods, and the third voltage pulse is a single voltage pulse within the third period; and a fourth voltage pulse, having positive polarity during a fourth period after the second period, and being a single voltage pulse within the fourth period.

2. The plasma processing apparatus of claim 1, wherein the power supply system is configured to periodically output the first voltage pulse at a frequency of 100 kHz or more and 1 MHz or less during the first period, and to periodically output the second voltage pulse at a frequency of 100 kHz or more and 1 MHz or less during the second period.

3. The plasma processing apparatus of claim 1, wherein the reciprocal of the duration of the aforementioned cycle, i.e. the frequency, is 0.2 Hz or more and 1 Hz or less.

4. The plasma processing apparatus of claim 1, wherein the power supply system is configured such that the absolute value of the first voltage level is set to a level that is greater than the absolute value of the second voltage level.

5. The plasma processing apparatus of claim 1, wherein the power supply system is configured such that the absolute value of the first voltage level is set to a level smaller than the absolute value of the second voltage level.

6. The plasma processing apparatus of claim 1, wherein the substrate support is configured as a support substrate; and the power supply system is configured to apply the pulsed voltage signal to the electrode in order to feed ions from the plasma in the chamber to the substrate on the substrate support.

7. A plasma processing method comprising: a step of preparing a substrate on a substrate support disposed in a chamber of a plasma processing apparatus, wherein the substrate support includes electrodes; and a step of outputting pulsed voltage signals to the electrodes from a power supply system for a plurality of cycles, wherein each cycle comprises: a sequence of first voltage pulses, each having a first voltage level and negative polarity during a first period; a sequence of second voltage pulses, each having a second voltage level and negative polarity different from the first voltage level during a second period; a third voltage pulse having positive polarity during a third period between the first and second periods, wherein the third period is a single period between the first and second periods, and the third voltage pulse is a single voltage pulse during the third period; and a fourth voltage pulse having positive polarity during a fourth period after the second period, and being a single voltage pulse during the fourth period.

8. The plasma processing method of claim 7, wherein the first voltage pulse is periodically output during the first period at a frequency of 100 kHz or more and 1 MHz or less, and the second voltage pulse is periodically output during the second period at a frequency of 100 kHz or more and 1 MHz or less.

9. The plasma processing method of claim 7, wherein the reciprocal of the duration of the aforementioned cycle, i.e. the frequency, is 0.2 Hz or more and 1 Hz or less.

10. The plasma processing method of claim 7, wherein the absolute value of the first voltage level is set to a level that is greater than the absolute value of the second voltage level.

11. The plasma processing method of claim 7, wherein the absolute value of the first voltage level is set to a level smaller than the absolute value of the second voltage level.

12. The plasma processing method of claim 7, wherein the substrate support portion is configured as a support substrate; the pulsed voltage signal is applied to the electrode in such a way that ions are fed from the plasma in the cavity to the substrate on the substrate support portion.

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