Manufacturing method of semiconductor structure

Abstract

A method for manufacturing a semiconductor structure includes the following steps: Providing a substrate. Forming a dielectric material layer on the substrate. Forming a polycrystalline silicon material layer on the dielectric material layer. Having multiple particle defects on the polycrystalline silicon material layer. Forming a hard mask layer on the polycrystalline silicon material layer. Patterning the hard mask layer, the polycrystalline silicon material layer, and the dielectric material layer to form a patterned hard mask layer, a polycrystalline silicon layer, a dielectric layer, and an opening, and forming multiple columnar defects in the opening. Forming a filling layer in the opening. The filling layer covers the multiple columnar defects. The thickness of the patterned hard mask layer is greater than the thickness of the filling layer. The top surface of the patterned hard mask layer is higher than the top surface of the filling layer. Removing the filling layer, the multiple columnar defects, and a portion of the patterned hard mask layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure that can effectively remove columnar defects. Prior Technology

[0002] In some semiconductor manufacturing processes, particle defects can occur on polycrystalline silicon layers. When patterning the polycrystalline silicon layer, these particle defects can form micromasks in the areas exposed by the patterned photoresist layer. This prevents the removal of portions of the polycrystalline silicon layer beneath the particle defects, resulting in pillar defects. Therefore, removing pillar defects remains a key ongoing research goal. Summary of the Invention

[0003] This invention provides a method for manufacturing a semiconductor structure that can effectively remove columnar defects.

[0004] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a dielectric material layer on the substrate. Forming a polycrystalline silicon material layer on the dielectric material layer. Having multiple particle defects on the polycrystalline silicon material layer. Forming a hard mask layer on the polycrystalline silicon material layer. Patterning the hard mask layer, the polycrystalline silicon material layer, and the dielectric material layer to form a patterned hard mask layer, a polycrystalline silicon layer, a dielectric layer, and an opening, wherein multiple columnar defects are formed in the opening. Forming a filling layer in the opening. The filling layer covers the multiple columnar defects. The thickness of the patterned hard mask layer is greater than the thickness of the filling layer. The top surface of the patterned hard mask layer is higher than the top surface of the filling layer. Removing the filling layer, the multiple columnar defects, and a portion of the patterned hard mask layer.

[0005] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method for forming a patterned hard mask layer may include the following steps: forming a patterned photoresist layer on the hard mask layer; using the patterned photoresist layer as a mask, removing a portion of the hard mask layer to form a patterned hard mask layer, thereby exposing a portion of the polycrystalline silicon material layer and multiple particle defects.

[0006] According to an embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the method for forming a polycrystalline silicon layer, a dielectric layer, and a plurality of columnar defects may include the following steps: Using a patterned hard mask layer and a plurality of particle defects exposed by the patterned hard mask layer as a mask, a portion of the polycrystalline silicon material layer and a portion of the dielectric material layer are removed to form a polycrystalline silicon layer, a dielectric layer, and a plurality of columnar defects. The positions of the columnar defects may correspond to the positions of the particle defects exposed by the patterned hard mask layer.

[0007] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, during the removal of a portion of the polycrystalline silicon material layer and a portion of the dielectric material layer, the patterned photoresist layer can be consumed and removed.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, during the removal of a portion of the polycrystalline silicon material layer and a portion of the dielectric material layer, multiple particle defects exposed by the patterned hard mask layer can be consumed and removed.

[0009] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the method for removing the fill layer, multiple columnar defects, and partially patterned hard mask layer may include the following steps: performing a non-selective etching process to remove the fill layer, multiple columnar defects, and partially patterned hard mask layer.

[0010] According to one embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: forming an isolation structure in a substrate. The isolation structure may be located below a polycrystalline silicon layer. Removing a portion of the isolation structure, thereby forming a recess below the polycrystalline silicon layer.

[0011] According to an embodiment of the present invention, in the above-described semiconductor structure manufacturing method, the columnar defect may include a dielectric material portion and a polysilicon material portion. The dielectric material portion is located on a substrate. The polysilicon material portion is located on the dielectric material portion. The method for removing the fill layer, multiple columnar defects, a partially patterned hard mask layer, and a partially isolated structure may include the following steps: Performing a first no-selectivity etching process to remove a portion of the fill layer, the polysilicon material portion, and the partially patterned hard mask layer, and exposing the dielectric material portion. Performing an isotropic etching process to remove a portion of the fill layer, a portion of the dielectric material portion, a portion of the patterned hard mask layer, and a portion of the isolated structure, thereby forming a depression. Performing a second no-selectivity etching process to remove the fill layer, the dielectric material portion, and the partially patterned hard mask layer.

[0012] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following steps: After removing the filler layer and multiple columnar defects, the patterned hard mask layer is removed.

[0013] According to an embodiment of the present invention, in the above-described method for manufacturing the semiconductor structure, the material of the polycrystalline silicon material layer is, for example, doped polycrystalline silicon.

[0014] Based on the above, in the semiconductor structure manufacturing method proposed in this invention, a filling layer covering multiple columnar defects is formed in the opening. Since the thickness of the patterned hard mask layer is greater than the thickness of the filling layer, and the top surface of the patterned hard mask layer is higher than the top surface of the filling layer, the columnar defects can be effectively removed during the removal of the filling layer, multiple columnar defects, and part of the patterned hard mask layer.

[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings for detailed explanation. Simple Explanation of the Diagram

[0016] Figures 1A to 1I are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention. Figures 2A to 2C are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention. Implementation

[0017] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation.

[0018] Figures 1A to 1I are cross-sectional views of the manufacturing process of semiconductor structures according to some embodiments of the present invention.

[0019] Referring to Figure 1A, a substrate 100 is provided. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, although not shown in the figure, the substrate may have desired doped regions (e.g., well regions).

[0020] In some embodiments, an isolation structure 102 may be formed in the substrate 100. In some embodiments, the isolation structure 102 is, for example, a shallow trench isolation (STI) structure. In some embodiments, the material of the isolation structure 102 is, for example, silicon oxide. In some embodiments, the isolation structure 102 may be formed by a shallow trench isolation structure process.

[0021] Furthermore, a dielectric material layer 104 is formed on the substrate 100. In some embodiments, the material of the dielectric material layer 104 is, for example, silicon oxide. In some embodiments, the method for forming the dielectric material layer 104 is, for example, thermal oxidation.

[0022] Next, a polycrystalline silicon material layer 106 is formed on the dielectric material layer 104. In some embodiments, the polycrystalline silicon material layer 106 may be formed on the isolation structure 102. The polycrystalline silicon material layer 106 has a plurality of particle defects D1. In some embodiments, the particle defects D1 may be particles unexpectedly generated during the manufacturing process. In some embodiments, the material of the polycrystalline silicon material layer 106 is, for example, doped polycrystalline silicon. In some embodiments, the method for forming the polycrystalline silicon material layer 106 is, for example, chemical vapor deposition.

[0023] Then, a hard mask layer 108 is formed on the polycrystalline silicon material layer 106. In some embodiments, the material of the hard mask layer 108 is, for example, amorphous carbon or spin-on carbon (SOC). In some embodiments, the hard mask layer 108 is formed by, for example, chemical vapor deposition or spin coating.

[0024] Referring to Figure 1B, a patterned photoresist layer 110 can be formed on the rigid mask layer 108. In some embodiments, the patterned photoresist layer 110 can be formed by a photolithography process.

[0025] Referring to Figure 1C, a patterned photoresist layer 110 can be used as a mask to remove part of the hard mask layer 108, thereby forming a patterned hard mask layer 108a and exposing part of the polycrystalline silicon material layer 106 and multiple particle defects D1. In some embodiments, the method for removing part of the hard mask layer 108 is, for example, anisotropic etching, such as dry etching.

[0026] Referring to Figure 1D, a patterned hard mask layer 108a and a plurality of particle defects D1 exposed by the patterned hard mask layer 108a can be used as a mask to remove a portion of the polycrystalline silicon material layer 106 and a portion of the dielectric material layer 104, thereby forming a polycrystalline silicon layer 106a, a dielectric layer 104a, and a plurality of columnar defects D2. The position of the columnar defects D2 may correspond to the position of the particle defects D1 exposed by the patterned hard mask layer 108a. In some embodiments, the isolation structure 102 may be located below the polycrystalline silicon layer 106a. In some embodiments, during the removal of a portion of the polycrystalline silicon material layer 106 and a portion of the dielectric material layer 104, the patterned photoresist layer 110 may be consumed and removed. In some embodiments, during the removal of a portion of the polycrystalline silicon material layer 106 and a portion of the dielectric material layer 104, the plurality of particle defects D1 exposed by the patterned hard mask layer 108a may be consumed and removed. In some embodiments, the method for removing a portion of the polycrystalline silicon material layer 106 and a portion of the dielectric material layer 104 is, for example, an anisotropic etching method, such as dry etching.

[0027] Using the above method, the hard mask layer 108, the polycrystalline silicon material layer 106, and the dielectric material layer 104 can be patterned to form a patterned hard mask layer 108a, a polycrystalline silicon layer 106a, a dielectric layer 104a, and an opening OP1, and a plurality of columnar defects D2 are formed in the opening OP1. In some embodiments, the opening OP1 may expose a portion of the substrate 100. In some embodiments, the columnar defects D2 may be columnar. In some embodiments, the columnar defects D2 may include a dielectric material portion P1 and a polycrystalline silicon material portion P2. The dielectric material portion P1 is located on the substrate 100. The polycrystalline silicon material portion P2 is located on the dielectric material portion P1.

[0028] Referring to Figure 1E, a filling layer 112 is formed in the opening OP1. The filling layer 112 covers a plurality of columnar defects D2. The thickness T1 of the patterned hard mask layer 108a is greater than the thickness T2 of the filling layer 112. The top surface S1 of the patterned hard mask layer 108a is higher than the top surface S2 of the filling layer 112. In some embodiments, the material of the filling layer 112 is, for example, an organic dielectric layer (ODL) or spin-coated carbon (SOC). In some embodiments, the filling layer 112 is formed by, for example, spin coating.

[0029] Referring to Figure 1F, a first non-selective etching process can be performed to remove a portion of the filler layer 112, the polycrystalline silicon material portion P2, and a portion of the patterned hard mask layer 108a, exposing the dielectric material portion P1. In this embodiment, a "non-selective etching process" refers to an etching process that has substantially the same etching rate for all layers to be etched. In some embodiments, the first non-selective etching process may be a dry etching process.

[0030] Referring to Figure 1G, an isotropic etching process can be performed to remove a portion of the filler layer 112, a portion of the dielectric material portion P1, a portion of the patterned hard mask layer 108a, and a portion of the isolation structure 102, thereby forming a recess R1. This allows for the removal of a portion of the isolation structure 102, resulting in a recess R1 formed beneath the polysilicon layer 106a. In some embodiments, the isotropic etching process can be a wet etching process or a dry etching process.

[0031] Referring to Figure 1H, a second non-selective etching process can be performed to remove the filler layer 112, the dielectric material portion P1, and the partially patterned hard mask layer 108a. In some embodiments, the second non-selective etching process can be a dry etching process. By the above method, the filler layer 112, the plurality of columnar defects D2, and the partially patterned hard mask layer 108a can be removed.

[0032] Referring to Figure 1I, after removing the filler layer 112 and the plurality of columnar defects D2, the patterned hard mask layer 108a can be removed. In some embodiments, the removal method of the patterned hard mask layer 108a is, for example, the ashing method.

[0033] As can be seen from the above embodiments, in the manufacturing method of semiconductor structure 10, a filling layer 112 covering multiple columnar defects D2 is formed in the opening OP1. Since the thickness T1 of the patterned hard mask layer 108a is greater than the thickness T2 of the filling layer 112, and the top surface S1 of the patterned hard mask layer 108a is higher than the top surface S2 of the filling layer 112, the columnar defects D2 can be effectively removed during the removal of the filling layer 112, the multiple columnar defects D2, and part of the patterned hard mask layer 108a.

[0034] Figures 2A to 2C are cross-sectional views of the manufacturing process of semiconductor structures according to other embodiments of the present invention.

[0035] Please refer to Figure 2A, which provides the structure shown in Figure 1E. Furthermore, detailed descriptions of each component in Figure 2A can be found in the description of Figure 1E, and will not be repeated here.

[0036] Referring to Figure 2B, a non-selective etching process can be performed to remove the filler layer 112, multiple columnar defects D2, and partially patterned hard mask layer 108a. In some embodiments, the non-selective etching process can be a dry etching process.

[0037] Referring to Figure 2C, after removing the filler layer 112 and the plurality of columnar defects D2, the patterned hard mask layer 108a can be removed. In some embodiments, the method for removing the patterned hard mask layer 108a is, for example, ashing.

[0038] As can be seen from the above embodiments, in the manufacturing method of semiconductor structure 20, a filling layer 112 covering multiple columnar defects D2 is formed in the opening OP1. Since the thickness T1 of the patterned hard mask layer 108a is greater than the thickness T2 of the filling layer 112, and the top surface S1 of the patterned hard mask layer 108a is higher than the top surface S2 of the filling layer 112, the columnar defects D2 can be effectively removed during the removal of the filling layer 112, the multiple columnar defects D2, and part of the patterned hard mask layer 108a.

[0039] In summary, the method for manufacturing the semiconductor structure in the above embodiments includes the following steps: A substrate is provided. A dielectric material layer is formed on the substrate. A polycrystalline silicon material layer is formed on the dielectric material layer. The polycrystalline silicon material layer has multiple particle defects. A hard mask layer is formed on the polycrystalline silicon material layer. The hard mask layer, the polycrystalline silicon material layer, and the dielectric material layer are patterned to form a patterned hard mask layer, a polycrystalline silicon layer, a dielectric layer, and an opening, and multiple columnar defects are formed in the opening. A filling layer is formed in the opening. The filling layer covers the multiple columnar defects. The thickness of the patterned hard mask layer is greater than the thickness of the filling layer. The top surface of the patterned hard mask layer is higher than the top surface of the filling layer. The filling layer, the multiple columnar defects, and a portion of the patterned hard mask layer are removed. Because the thickness of the patterned hard mask layer is greater than the thickness of the filling layer, and the top surface of the patterned hard mask layer is higher than the top surface of the filling layer, the columnar defects can be effectively removed during the removal of the filling layer, the multiple columnar defects, and a portion of the patterned hard mask layer.

[0040] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0041] 10,20: Semiconductor Structure 100: Base 102: Isolation Structure 104: Dielectric material layer 104a: Dielectric layer 106: Polycrystalline silicon material layer 106a: Polycrystalline silicon layer 108: Rigid Coverage Layer 108a: Patterned rigid mask layer 110: Patterned photoresist layer 112: Fill layer D1: Particle defects D2: Columnar defect OP1: Opening P1: Dielectric Materials Department P2: Polycrystalline Silicon Materials Department R1: Depression S1, S2: Top surface T1, T2: Thickness

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide a base; A dielectric material layer is formed on the substrate; A polycrystalline silicon material layer is formed on the dielectric material layer, wherein the polycrystalline silicon material layer has multiple particle defects; a hard mask layer is formed on the polycrystalline silicon material layer; the hard mask layer, the polycrystalline silicon material layer, and the dielectric material layer are patterned to form a patterned hard mask layer, a polycrystalline silicon layer, a dielectric layer, and an opening, and multiple columnar defects are formed in the opening; a filling layer is formed in the opening, wherein the filling layer covers the multiple columnar defects, the thickness of the patterned hard mask layer is greater than the thickness of the filling layer, and the top surface of the patterned hard mask layer is higher than the top surface of the filling layer; and the filling layer, the multiple columnar defects, and a portion of the patterned hard mask layer are removed.

2. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for forming the patterned hard mask layer includes: A patterned photoresist layer is formed on the rigid mask layer; And by using the patterned photoresist layer as a mask, a portion of the hard mask layer is removed to form the patterned hard mask layer, and a portion of the polycrystalline silicon material layer and the plurality of particle defects are exposed.

3. A method for manufacturing a semiconductor structure as claimed in claim 2, wherein the method for forming the polycrystalline silicon layer, the dielectric layer, and the plurality of columnar defects comprises: Using the patterned hard mask layer and the plurality of particle defects exposed by the patterned hard mask layer as a mask, a portion of the polycrystalline silicon material layer and a portion of the dielectric material layer are removed to form the polycrystalline silicon layer, the dielectric layer and the plurality of columnar defects, wherein the position of the columnar defects corresponds to the position of the particle defects exposed by the patterned hard mask layer.

4. A method for manufacturing a semiconductor structure as claimed in claim 3, wherein the patterned photoresist layer is consumed and removed during the removal of a portion of the polysilicon material layer and a portion of the dielectric material layer.

5. A method of manufacturing a semiconductor structure as claimed in claim 3, wherein during the removal of portions of the polycrystalline silicon material layer and portions of the dielectric material layer, a plurality of the particle defects exposed by the patterned hard mask layer are consumed and removed.

6. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the method for removing the filler layer, the plurality of columnar defects, and a portion of the patterned hard mask layer comprises: A non-selective etching process is performed to remove the filler layer, the plurality of columnar defects, and a portion of the patterned hard mask layer.

7. The method for manufacturing a semiconductor structure as described in claim 1 further includes: An isolation structure is formed in the substrate, wherein the isolation structure is located below the polycrystalline silicon layer; And remove part of the isolation structure to form a recess beneath the polycrystalline silicon layer.

8. A method for manufacturing a semiconductor structure as claimed in claim 7, wherein the columnar defect comprises a dielectric material portion and a polycrystalline silicon material portion, the dielectric material portion being located on the substrate, the polycrystalline silicon material portion being located on the dielectric material portion, and a method for removing the filling layer, the plurality of the columnar defects, a portion of the patterned hard mask layer, and a portion of the isolation structure comprising: A first non-selective etching process is performed to remove a portion of the filler layer, the polysilicon material portion, and a portion of the patterned hard mask layer, and to expose the dielectric material portion. An isotropic etching process is performed to remove a portion of the filler layer, a portion of the dielectric material portion, a portion of the patterned hard mask layer, and a portion of the isolation structure, thereby forming the recess; And a second non-selective etching process is performed to remove the filler layer, the dielectric material portion and a portion of the patterned hard mask layer.

9. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: After removing the filler layer and the plurality of columnar defects, the patterned hard mask layer is removed.

10. A method for manufacturing a semiconductor structure as claimed in claim 1, wherein the material of the polycrystalline silicon material layer comprises doped polycrystalline silicon.

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