Semiconductor device and method of manufacturing a semiconductor device

Abstract

In one example, a semiconductor device includes: a substrate assembly comprising: a first substrate; a first device located on a top surface of the first substrate; and a first encapsulation located on the top surface of the first substrate and forming a boundary of a side surface of the first device. The semiconductor device further includes conductive pillars located on the first substrate and within a first molding compound, wherein the conductive pillars include a non-conductive pillar core and a conductive pillar shell on the pillar core.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Prior Technology

[0002] Existing semiconductor packaging and methods for forming semiconductor packages have shortcomings, such as excessive cost, reduced reliability, relatively low performance, or excessively large package size. Further limitations and disadvantages of such methods will become apparent to those skilled in the art by comparing conventional and traditional methods with this disclosure and by referring to the accompanying drawings. Summary of the Invention

[0003] One embodiment of the present invention is a semiconductor device comprising: a substrate assembly including: a first substrate; a first device located on a top surface of the first substrate; a first encapsulation located on the top surface of the first substrate and forming a boundary of a side surface of the first device; and a conductive pillar located on the first substrate and in a first molding compound; wherein the conductive pillar includes a non-conductive pillar core and a conductive pillar shell on the pillar core.

[0004] In one embodiment of the semiconductor device of the present invention, the top end of the conductive pillar shell is exposed from the encapsulation; and the top end of the conductive core is covered by the top end of the conductive pillar shell.

[0005] In one embodiment of the semiconductor device described in this invention, the first substrate includes a pad coupled to the shell and the core.

[0006] In one embodiment of the semiconductor device described in this invention, the height of the conductive pillar is from about 110 micrometers to about 350 micrometers.

[0007] The semiconductor device of one embodiment of the present invention further includes a bottom filler located between the first device and the top surface of the first substrate.

[0008] In one embodiment of the semiconductor device described in this invention, the first device or the second device includes an active device, a passive device, a semiconductor die, or a semiconductor package.

[0009] The semiconductor device of one embodiment of the present invention further includes: a top assembly comprising: a second substrate; a second device located on a top surface of the second substrate; a second encapsulation located on the top surface of the second substrate and forming a boundary of a side surface of the second device; and an interconnect located on a bottom surface of the second substrate; wherein the interconnect couples the second substrate to the top end of the conductive pillar.

[0010] The semiconductor device of one embodiment of the present invention further includes: an interface layer located between the top assembly and the substrate assembly, the interface layer forming the boundary of the interconnects of the top assembly.

[0011] In one embodiment of the semiconductor device of the present invention, the top end of the encapsulation is substantially coplanar with the top end of the conductive pillar; and the top end of the conductive pillar extends further from the top surface of the first substrate than the top end of the first device.

[0012] In one embodiment of the semiconductor device of the present invention, the top end of the encapsulation is substantially coplanar with the top end of the conductive pillar and the top end of the first device.

[0013] In one embodiment of the semiconductor device of the present invention, the width of the core is greater than the thickness of the shell; the width of the core is from about 50 micrometers to about 200 micrometers; and the thickness of the shell is from about 10 micrometers to about 50 micrometers.

[0014] Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: providing a core of non-conductive material on a top surface of a first substrate; providing a shell on the core to form a conductive pillar; placing a first device on the top surface of the first substrate; and providing a first encapsulation on the top surface of the first substrate that contacts a side surface of the first device and the conductive pillar.

[0015] In another embodiment of the method of the present invention, setting the pillar includes: setting a non-conductive material on the top surface of the first substrate; removing a portion of the non-conductive material to define the pillar; and the pillar being in direct contact with the pad of the first substrate.

[0016] Another embodiment of the method further includes: placing a top assembly on the top surface of the first encapsulation, wherein the top assembly includes a second substrate and a second device on the second substrate, and wherein the conductive post electrically couples the second device to the first substrate.

[0017] Another embodiment of the method of the present invention further includes setting a seed layer on the core before setting the shell.

[0018] Another embodiment of the method of the present invention further includes, before setting the pillar shell, setting a photoresist on the top surface of the substrate and removing a portion of the photoresist to define the pillar core.

[0019] In another embodiment of the method described in this invention, setting the cylindrical shell includes sputtering or plating.

[0020] Another aspect of the present invention is a method for manufacturing a semiconductor device, the method comprising: disposing a redistribution layer substrate on a carrier, wherein the redistribution layer substrate includes a dielectric structure and a redistribution structure in the dielectric structure; disposing a non-conductive material on a top surface of the redistribution layer substrate; removing a portion of the non-conductive material to form a core; disposing a core shell on the core to form a conductive pillar electrically coupled to the redistribution structure; placing a device for contacting the redistribution structure on the redistribution layer substrate; disposing an encapsulation on the top surface of the redistribution layer substrate that contacts a side surface of the device; and removing the carrier and disposing an interconnect on a bottom surface of the redistribution layer substrate electrically coupled to the redistribution structure.

[0021] Another embodiment of the method of the present invention further includes providing a bottom filler between the device and the top surface of the redistribution layer substrate.

[0022] Another embodiment of the method of the present invention further includes providing an additional redistribution layer substrate on the top surface of the encapsulation, which contacts the redistribution structure via the conductive pillars. Simple Explanation of the Diagram

[0023] [Figure 1] shows a cross-sectional view of an example semiconductor device.

[0024] Figures 2A through 2L show cross-sectional views of an example method for manufacturing an example semiconductor device. Implementation

[0025] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are not limiting.

[0026] The accompanying drawings illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the content of this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0027] The term "or" means any one or more items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0028] Various elements may be described using terms such as "first," "second," etc., and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element discussed herein may be referred to as the second element.

[0029] Unless otherwise specified, the term "coupled" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, then element A can be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements.

[0030] In one example, a semiconductor device includes: a substrate assembly comprising: a first substrate; a first device located on a top surface of the first substrate; and a first encapsulation located on the top surface of the first substrate and forming a boundary of a side surface of the first device. The semiconductor device further includes conductive pillars located on the first substrate and within a first molding compound, wherein the conductive pillars include a non-conductive pillar core and a conductive pillar shell on the pillar core.

[0031] In another example, a method for manufacturing a semiconductor device includes: disposing a core of non-conductive material on a top surface of a first substrate; disposing a shell on the core to form a conductive pillar; placing a first device on the top surface of the first substrate; and disposing a first encapsulation on the top surface of the first substrate that contacts a side surface of the first device and the conductive pillar.

[0032] In another example, a method for manufacturing a semiconductor device includes: disposing a redistribution layer (RDL) substrate on a carrier, wherein the RDL substrate includes a dielectric structure and a redistribution structure in the dielectric structure; disposing a non-conductive material on a top surface of the RDL substrate; removing a portion of the non-conductive material to form a core; disposing a shell on the core to form a conductive pillar electrically coupled to the redistribution structure; placing a device for contacting the redistribution structure on the RDL substrate; disposing an encapsulation on the top surface of the RDL substrate that contacts a side surface of the device; and removing the carrier and disposing an interconnect on a bottom surface of the RDL substrate electrically coupled to the redistribution structure.

[0033] This disclosure contains other examples. Such examples may exist in the accompanying drawings, requests, and / or specifications of this disclosure.

[0034] Figure 1 shows a cross-sectional view of an example semiconductor device 10. In the example shown in Figure 1, the semiconductor device 10 may include a substrate assembly 100, a top assembly 200 positioned on the substrate assembly 100, and an interface layer 300 interposed between the substrate assembly 100 and the top assembly 200.

[0035] The substrate assembly 100 may include a substrate 110, an electronic device 120, conductive pillars 130, an encapsulation 140, and an external interconnect 150. The substrate 110 may include a redistribution structure 111 and a dielectric structure 112. The redistribution structure 111 may be electrically connected to the electronic device 120 and the external interconnect 150. Additionally, the substrate 110 may further include a pad 113 formed on the top surface of the substrate 110 and electrically connected to the redistribution structure 111. The pad 113 may be part of the redistribution structure 111. The redistribution structure 111 and the dielectric structure 112 may respectively represent one or more conductive and dielectric layers that can be alternately stacked to define one or more conductive and dielectric layers of the substrate 110. Each conductive layer of the redistribution structure 111 may include one or more conductive patterns, traces, and / or vias, along which signals, currents, or voltages may be carried or redistributed across the substrate 110. Additionally, one or more portions of the conductive layer of the redistribution structure 111 may have or may form one or more sublayers made of one or more conductive materials stacked on top of each other. Interconnects 121 may be formed on the bottom surface of the electronic device 120 and these interconnects may couple the electronic device 120 to the substrate 110. An interface layer 122 may be positioned between the electronic device 120 and the substrate 110 and this interface layer may encapsulate the interconnects 121. Conductive pillars 130 may include a pillar core 131 and a pillar shell 132. Conductive pillars 130 may be positioned on the top surface of the substrate 110 to laterally displace the electronic device 120 and may provide electrical connection between the substrate 110 and the top assembly 200. Encapsulation 140 may encapsulate the electronic device 120, the conductive pillars 130, and the top surface of the substrate 110. External interconnects 150 may be formed on the bottom surface of the substrate 110 to couple the semiconductor device 10 to external devices or components, such as printed circuit boards.

[0036] The top assembly 200 may include a substrate 210, an electronic device 220, an encapsulation 230, and an interconnect 240. The substrate 210 may include a redistribution structure 211 and a dielectric structure 212 similar to the redistribution structure 111 and dielectric structure 112 described above. The redistribution structure 211 may be electrically connected to the electronic device 220 and the interconnect 240. The electronic device 220 may be formed on the substrate 210. An interconnect 221 may be formed on the bottom surface of the electronic device 220, and the interconnect may couple the electronic device 220 to the substrate 210. The encapsulation 230 may encapsulate the electronic device 220 and the top surface of the substrate 210.

[0037] Substrates 110 and 210, conductive pillars 130, encapsulants 140, 230 and 300, and interconnects 150 and 240 may be referred to as semiconductor packages or packages. Semiconductor packages prevent electronic devices 120 and 220 from being exposed to external factors and / or the environment. Additionally, semiconductor packages can provide electrical connections between external components (not shown) and electronic devices 120 and 220.

[0038] Figures 2A to 2L show cross-sectional views of an example method for manufacturing semiconductor device 10. Specifically, Figures 2B to 2G show partially enlarged plan views of the manufacturing process in portion "P" shown in Figure 2A.

[0039] Figure 2A shows a cross-sectional view of a semiconductor device 10 in an early manufacturing stage. In the example shown in Figure 2A, substrate 110 may include a redistribution structure 111, a dielectric structure 112, and a pad 113. Substrate 110 may include, for example, a printed circuit board with a core, a coreless substrate (e.g., a stacked substrate built layer by layer on a carrier and lacking a core such as a glass fiber layer, a silicon-less integrated module (SLIM) interposer, or a silicon wafer integrated fan-out technology (SWIFT) interposer), a lead frame, a microlead frame, a semiconductor die, an interposer (e.g., a silicon or glass interposer), etc.

[0040] In some instances, the redistribution structure 111 may include, or be referred to as, a conductive layer, a metal layer, a wiring layer, or a circuit pattern. The redistribution structure 111 may include, for example, conductive materials such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or palladium (Pd). Additionally, the redistribution structure 111 may be formed using, for example, sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The thickness of the layers in the redistribution structure 111 may range from about 2 micrometers to about 10 micrometers. The redistribution structure 111 may have a multilayer structure. The redistribution structure 111 may be exposed at the top surface of the substrate 110 for electrical connection to the electronic device 120 and / or the conductive pillars 130. Additionally, the redistribution structure 111 may be exposed at the bottom surface of the substrate 110 for electrical connection to the interconnects 150.

[0041] In some instances, the dielectric structure 112 may include, or be referred to as, a dielectric layer, a passivation layer, an insulating layer, or a protective layer. In some instances, the dielectric structure 112 may include, for example, oxide layers, nitride layers, and electrically insulating materials such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, or epoxy resin. Alternatively, the dielectric structure 112 may be formed using, for example, thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), sheet lamination, or vapor deposition. The thickness of the layers in the dielectric structure 112 can range from about 4 micrometers to about 12 micrometers. In some instances, the dielectric structure 112 can prevent the redistributed structure 111 from being exposed to external factors and / or the environment.

[0042] In some instances, pad 113 may include, or be referred to as, solder ring or under-bump metallization (UBM). Pad 113 may contain, for example, a conductive material such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or palladium (Pd). Pad 113 may be formed using, for example, sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). Additionally, the width of pad 113 may be formed to be wider than the width of conductive pillar 130. The width of pad 113 may range from about 60 micrometers to about 250 micrometers. Additionally, the thickness of pad 113 may range from about 2 micrometers to about 10 micrometers. Pad 113 may be formed on a redistribution structure 111 exposed on the top surface of substrate 110 and may be electrically connected to the redistribution structure 111.

[0043] In some instances, substrate 110 may be a redistribution layer ("RDL") substrate. The RDL substrate may include (a) one or more conductive redistribution layers and one or more dielectric layers that may be formed layer-by-layer on an electronic device to which the RDL substrate is to be electrically coupled, or (b) one or more conductive redistribution layers and one or more dielectric layers that may be formed layer-by-layer on a carrier that has been completely or at least partially removed after the electronic device and the RDL substrate have been coupled together. The RDL substrate may be fabricated layer-by-layer on a circular wafer as a wafer-level substrate using wafer-level processes, and / or on a rectangular or square panel carrier as a panel-level substrate using panel-level processes. The RDL substrate may be formed using an additive stacking process that may include one or more dielectric layers that are alternately stacked with one or more conductive layers defining corresponding conductive redistribution patterns or traces, the conductive redistribution patterns or traces being configured to collectively (a) fan out of the electronic device's footprint, and / or (b) fan in into the electronic device's footprint. A plating process, such as electroplating or electroless plating, may be used to form the conductive patterns. The conductive patterns may include conductive materials, such as copper or other platingable metals. The location of conductive patterns can be created using photolithography processes, such as photolithography, and photoresist materials used to form photomasks. The dielectric layer of an RDL substrate can be patterned using photolithography processes that may include photomasks through which light is exposed to desired features of the photopattern, such as vias in the dielectric layer. The dielectric layer can be made of photodeterminable organic dielectric materials, such as polyimide (PI), phenylcyclobutene (BCB), or polybenzoxazole (PBO). Such dielectric materials can be spin-coated or otherwise coated in liquid form, rather than attached as a pre-formed film. To allow for the proper formation of desired photodeterminable features, such photodeterminable dielectric materials may omit structural reinforcing agents or may be filler-free, free from lines, fabrics, or other particles that could interfere with light from the photopatterning process. In some instances, this filler-free characteristic of filler-free dielectric materials can allow for a reduction in the thickness of the resulting dielectric layer. Although the light-defined dielectric material described above can be an organic material, in other instances, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers can include silicon nitride (Si3N4), silicon oxide (SiO2), and / or SiON. These one or more inorganic dielectric layers can be formed by growing the inorganic dielectric layer using an oxidation or nitridation process instead of using a light-defined organic dielectric material. Such inorganic dielectric layers can be filler-free, without wires, fabrics, or other different inorganic particles. In some instances, the RDL substrate can omit a permanent core structure or carrier, for example, comprising dielectric materials including bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates. Other substrates in this disclosure may also include RDL substrates.

[0044] In some instances, substrate 110 may be a pre-formed substrate. The pre-formed substrate can be manufactured prior to attachment to an electronic device and may include dielectric layers situated between respective conductive layers. The conductive layers may include copper and can be formed using an electroplating process. The dielectric layers may be relatively thick, non-photodefineable layers that can be attached in the form of a pre-formed film rather than a liquid, and may contain resins with fillers such as wires, fabrics, and / or other inorganic particles for rigid and / or structural support. Because the dielectric layer is non-photodefineable, features such as through-holes or openings can be formed using drilling or lasers. In some instances, the dielectric layer may include a prepreg material or an Ajinomoto Buildup Film (ABF). The pre-formed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other instances, the pre-formed substrate may be a coreless substrate omitting the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier that is removed after the formation of the dielectric and conductive layers and before attachment to an electronic device. The pre-formed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate. Such pre-formed substrates can be formed using a semi-additive process or a modified semi-additive process. Other substrates described in this disclosure may also include pre-formed substrates.

[0045] Figure 2B shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2B, a non-conductive material 131' can be formed on the top surface of the substrate 110. In some examples, the non-conductive material 131' may be referred to as an insulating layer or a dielectric layer. The insulating layer 131' may comprise, for example, electrically insulating materials such as polymers, polyimide (PI), phenylcyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resins, epoxy resins, silicone, dry film layers, dry film photosensitive dielectrics (PDM), dry film polymer dielectrics, or acrylate polymers. Alternatively, the insulating layer 131' can be formed using, for example, spin coating, spraying, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), sheet lamination, or vapor deposition. The insulating layer 131' can be formed as a pad 113 covering the top surface of the substrate 110.

[0046] Figure 2C presents a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2C, the core 131 can be formed by removing a portion of the insulating layer 131'. For example, the core 131 can be formed by providing a mask pattern on a portion of the insulating layer 131' where a conductive pillar 130 is to be formed, and etching the insulating layer 131' from a portion where no mask pattern is formed. The core 131 can be formed on a pad 113 and its width can be less than the width of the pad 113. The height of the core 131 can be in the range of about 100 micrometers to about 300 micrometers. Additionally, the width of the core 131 can be in the range of about 50 micrometers to about 200 micrometers. The core 131 can be positioned toward the edge of the substrate 110 to allow easy placement of the electronic device 120 on the inside of the substrate 110.

[0047] Figure 2D shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2D, a seed layer 132a can be formed on the top surface of the substrate 110 and the surface of the core 131. The seed layer 132a can contain, for example, a conductive material such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or titanium (Ti). Alternatively, the seed layer 132a can be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma vapor deposition, electroless plating, or electroplating. In some examples, PVD can be referred to as sputtering. The seed layer 132a can be deposited thinly on the substrate 110, the pad 113, and the core 131. The thickness of the seed layer 132a can range from about 50 nanometers to about 200 nanometers. As explained below, the seed layer 132a can be configured to facilitate the process of forming the shell 132 in the form of a conductive outer shell on the insulating material of the core 131.

[0048] Figure 2E shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2E, a photoresist 135 can be formed on the substrate 110 and a portion of the photoresist 135 can be removed, thereby exposing the core 131 and the pad 113. For example, the photoresist 135 can be coated on the substrate 110 and / or the seed layer 132a, and a portion of the photoresist 135 can be removed by exposure and development, thereby exposing the core 131 and the pad 113.

[0049] Figure 2F shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2F, a shell 132 can be formed on the exposed seed layer 132a. The shell 132 can be formed to cover the core 131 and the pad 113. The shell 132 can contain, for example, a conductive material such as gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Alternatively, the shell 132 can be formed using, for example, sputtering, electroless plating, electroplating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD). The thickness of the shell 132 can range from about 10 micrometers to about 50 micrometers. The shell 132 covers the core 131 and is electrically connected to the pad 113.

[0050] Figures 2G and 2H show cross-sectional views of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2G, a portion of the photoresist 135 and the seed layer 132a located below the photoresist 135 is removed, which can be achieved, for example, by dry etching or wet etching. Thus, a conductive pillar 130 comprising a core 131, a seed layer 132a, and a shell 132 can be completed. The height of the conductive pillar 130 can be equal to or greater than the height of the electronic device 120. For example, the height of the conductive pillar 130 can range from about 110 micrometers to about 350 micrometers. Since the core 131 located within the conductive pillar 130 is made of an insulating material, manufacturing costs and / or manufacturing time can be reduced. For example, if the conductive pillar needed to be made only of a conductive material such as metal, the time and / or cost required to plate such a metal would be higher. However, in the example of Figure 2G, the conductive post 130 contains a core 131 therein, and forming the core 131 with an insulating layer 131' (Figure 2B) is faster and cheaper than having the same corresponding core volume metallized. Because the conductive post 130 includes a conductive shell 132 formed on the surface of the core 131, the conductive post can function much like a conventional conductive post. In the example shown in Figure 2H, the conductive post 130 can be formed at or near the edge of the substrate 110. The conductive post 130 can provide an electrical connection path between the base assembly 100 and the top assembly 200.

[0051] Figure 2I shows a cross-sectional view of a semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2I, an electronic device 120 can be attached to the top of a substrate 110. In some examples, the electronic device 120 may include a semiconductor die or a semiconductor package having one or more dies. The semiconductor die 120 may include, for example, a semiconductor material such as silicon (Si). The semiconductor die 120 may include passive electronic circuitry (not shown) or active electronic circuitry such as transistors. In some examples, the semiconductor die 120 may include, for example, circuitry such as a digital signal processor (DSP), a microprocessor, a network processor, a power management processor, an audio processor, a radio frequency (RF) circuit, a wireless baseband system-on-a-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC). The semiconductor die 120 may include interconnects 121 and molding material 122 or molding compound or underfill. In some examples, the interconnects 121 may include conductive balls such as solder balls, conductive pillars such as copper pillars, and / or conductive posts having solder caps formed on the copper pillars. Interconnect 121 may be formed on the bottom surface of semiconductor die 120 and may be electrically connected to the redistribution structure 111 of substrate 110. Molding material 122 may be formed between semiconductor die 120 and substrate 110. In some instances, molding material 122 may be referred to as molding compound or underfill. Underfill 122 may include epoxy resin, thermoplastic material, thermosetting material, polyimide, polyurethane, polymer material, filled epoxy resin, filled thermoplastic material, filled thermosetting material, filled polyimide, filled polyurethane, filled polymer material, flux underfill, etc.

[0052] In the example shown in Figure 2I, the semiconductor die 120 can be attached to the top of the substrate 110 by electrically connecting the interconnect 121 to the redistribution structure 111 of the substrate 110. The semiconductor die 120 can be electrically connected to the redistribution structure 111 using, for example, a batch reflow process, a thermal compression process, or a laser bonding process. The underfill 122 can be formed by inserting an underfill material between the semiconductor die 120 and the substrate 110 and then curing it.

[0053] Figure 2J shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2J, encapsulant 140 may encapsulate semiconductor die 120 and conductive pillar 130. Encapsulant 140 may encapsulate semiconductor die 120 and conductive pillar 130 on substrate 110. In some examples, encapsulant 140 may include various encapsulation or molding materials, including, for example, resins, polymeric materials, pillared polymers, epoxy resins, pillared epoxy resins, pillared epoxy acrylates, silicone resins, combinations thereof, or equivalents thereof. Additionally, encapsulant 140 may be formed using any of a variety of processes, including, for example, compression molding, liquid phase encapsulant molding, vacuum lamination, paste printing, or film-assisted molding. In some examples, bottom filler 122 may be part of encapsulant 140, rather than applied before or separately from encapsulant 140. Encapsulation 140 can protect semiconductor die 120 and conductive pillar 130 from the influence of the external environment. In this way, a substrate assembly 100 comprising substrate 110, semiconductor die 120, conductive pillar 130 and encapsulation 140 can be completed. In some embodiments, substrate assembly 100 may include interconnects 150 formed beneath substrate 110.

[0054] Figure 2K shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2K, a top assembly 200 can be attached to the top of a substrate assembly 100. The top assembly 200 may include a substrate 210, an electronic device 220, an encapsulation 230, and an interconnect 240. The substrate 210 may include a redistribution structure 211 and a dielectric structure 212. The top assembly 200 can be an assembly with various structures or elements, and is therefore not limited to the structure shown. The different elements of the top assembly 200 may be formed similarly to or in a similar manner to the corresponding elements of the substrate assembly 100 as described above. For example, the substrate 210, redistribution structure 211, dielectric structure 212, electronic device 220, and / or encapsulation 230 of the top assembly 200 may be similar to the substrate 110, redistribution structure 111, dielectric structure 112, electronic device 120, and / or encapsulation 140 of the substrate assembly 100, respectively.

[0055] Figure 2K illustrates a substrate 210 formed as a pre-formed substrate before being attached to the base assembly 100 using interconnects 240. However, it is possible that substrate 210 could alternatively be formed directly on top of the base assembly 100 (on the envelope 140 and / or the electronic device 120 and coupled to the pillar 130), rather than a pre-formed redistribution structure to which it is then attached using interconnects 240. Electronic device 220 and envelope 230 can then be attached and formed on substrate 210. In other examples, a redistribution structure similar to redistribution structure 110 or 120 can be formed directly on the base assembly 100 on the envelope 140 and / or the electronic device 120, and said redistribution structure is coupled to the pillar 130, to which the top assembly 200 can then be attached.

[0056] Figure 2L shows a cross-sectional view of the semiconductor device 10 in a later manufacturing stage. In the example shown in Figure 2L, an interface layer 300 may be formed between the substrate assembly 100 and the top assembly 200, and interconnects 150 may be formed on the bottom surface of the substrate assembly 100. In other examples, the interconnects 150 may be formed prior to the top assembly 200 being attached to the substrate assembly 100.

[0057] In some instances, the interface layer 300 may be referred to as a bottom filler. The bottom filler 300 may include epoxy resin, thermoplastic material, thermosetting material, polyimide, polyurethane, polymer material, filled epoxy resin, filled thermoplastic material, filled thermosetting material, filled polyimide, filled polyurethane, filled polymer material, fluxed bottom filler, etc. For example, the bottom filler 300 can be formed by injecting a liquid-phase bottom filler or a gel-type bottom filler between the substrate assembly 100 and the top assembly 200, followed by curing. The bottom filler 300 can enhance the mechanical coupling strength between the substrate assembly 100 and the top assembly 200 while protecting the interconnect 240.

[0058] Interconnect 150 can be electrically connected to the redistribution structure 111 of the substrate 110 of the substrate assembly 100. In some instances, interconnect 150 may include conductive balls such as solder balls, conductive pillars such as copper pillars, and / or conductive posts having solder caps formed on the copper pillars. Interconnect 150 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. Interconnect 150 can be formed using, for example, ball drop processes, screen printing processes, or electroplating processes. The thickness of interconnect 150 can range from about 50 micrometers to about 350 micrometers. Interconnect 150 can provide electrical connections between the semiconductor device 10 and external components or devices (not shown).

[0059] This disclosure includes references to certain examples; however, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather encompasses all examples falling within the scope of the appended claims.

[0060] 10: Semiconductor devices 100: Base assembly 110:Substrate 111: Redistributed Structure 112: Dielectric Structure 113: Padding 120: Electronic devices 121: Interconnector 122: Interface layer / Molding material / Bottom filler 130: Conductive column / column 131: Core 131': Non-conductive material / insulating layer 132: Columnar shell 132a: Seed layer 135: Optical Obscuration 140: Encapsulation 150: External interconnects / interconnects 200: Top Assembly 210:Substrate 211: Redistributed Structure 212: Dielectric Structure 220: Electronic devices 221: Interconnectors 230: Encapsulation 240: Interconnector 300: Interface layer / Encapsulation material / Bottom filler P: Part

Claims

1. A semiconductor device comprising: The first substrate includes a first dielectric structure and a first conductive layer; An electronic device located on the top side of the first substrate and coupled to the first conductive layer; an internal interconnect coupled to the first conductive layer, wherein the internal interconnect comprises a first material and a second material different from the first material; An encapsulation located on the top side of the first substrate; and a second substrate including a second dielectric structure and a second conductive layer, wherein the second substrate is located on the encapsulation and the electronic device, and the internal interconnect is coupled to the second conductive layer; wherein the encapsulation is located between the electronic device and the internal interconnect; and wherein the encapsulation contacts the lateral side of the electronic device and the lateral side of the internal interconnect.

2. The semiconductor device as claimed in claim 1, comprising: A conductive material is located on the bottom side of the second substrate; The conductive material is coupled to the top of the second conductive layer and the internal interconnect.

3. The semiconductor device as claimed in claim 1, comprising: A conductive material is located on the top side of the first substrate; The conductive material is coupled to the bottom of the first conductive layer and the internal interconnect.

4. The semiconductor device as claimed in claim 1, wherein: The first substrate includes a pad located on the top side of the first substrate; and the internal interconnect is coupled to the pad.

5. The semiconductor device as claimed in claim 4, wherein: The internal interconnects are contained within the space occupied by the liner.

6. The semiconductor device as claimed in claim 1, wherein: The first material is inside the second material.

7. The semiconductor device as claimed in claim 1, wherein: The internal interconnects are located within the encapsulation and outside the electronic device.

8. A semiconductor device comprising: The first substrate includes a first dielectric structure and a first conductive layer; An electronic device located on the top side of the first substrate and coupled to the first conductive layer; an interconnect structure coupled to the first conductive layer, wherein the interconnect structure includes an internal material and an external material different from the internal material; An encapsulation located on the top side of the first substrate; and a second substrate including a second dielectric structure and a second conductive layer, wherein the second substrate is located on the encapsulation and the electronic device, and the interconnect structure is coupled to the second conductive layer; wherein the encapsulation is located between the electronic device and the interconnect structure; and wherein the encapsulation contacts the lateral side of the electronic device and the lateral side of the interconnect structure.

9. The semiconductor device as claimed in claim 8, comprising: A conductive material is located on the bottom side of the second substrate; The conductive material is coupled to the top of the second conductive layer and the interconnect structure.

10. The semiconductor device as claimed in claim 8, comprising: A conductive material is located on the top side of the first substrate; The conductive material is coupled to the bottom of the first conductive layer and the interconnect structure.

11. The semiconductor device as claimed in claim 8, wherein: The first substrate includes a pad located on the top side of the first substrate; and the interconnect structure is coupled to the pad.

12. The semiconductor device as claimed in claim 11, wherein: The interconnect structure is contained within the space occupied by the liner.

13. The semiconductor device as claimed in claim 8, wherein: The interconnect structure is located within the encapsulation and outside the electronic device.

14. A method for manufacturing a semiconductor device, comprising: A first substrate is provided, which includes a first dielectric structure and a first conductive layer; An internal interconnect coupled to the first conductive layer is provided, wherein the internal interconnect includes a first material and a second material different from the first material; an electronic device is provided located on the top side of the first substrate and coupled to the first conductive layer; an encapsulation is provided on the top side of the first substrate. A second substrate is provided, comprising a second dielectric structure and a second conductive layer, wherein the second substrate is located above the encapsulation and the electronic device, and the internal interconnect is coupled to the second conductive layer; wherein the encapsulation is located between the electronic device and the internal interconnect; and wherein the encapsulation contacts the lateral side of the electronic device and the lateral side of the internal interconnect.

15. The method as described in claim 14, comprising: A conductive material is located on the bottom side of the second substrate; The conductive material is coupled to the top of the second conductive layer and the internal interconnect.

16. The method as described in claim 14, comprising: A conductive material is located on the top side of the first substrate; The conductive material is coupled to the bottom of the first conductive layer and the internal interconnect.

17. The method as described in request item 14, wherein: The first substrate includes a pad located on the top side of the first substrate; and the internal interconnect is coupled to the pad.

18. The method as described in request item 17, wherein: The internal interconnects are contained within the space occupied by the liner.

19. The method as described in request item 14, wherein: The first material is inside the second material.

20. The method as described in request item 14, wherein: The internal interconnects are located within the encapsulation and outside the electronic device.

Images